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Merge branch 'x86/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux...
[linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <[email protected]>
5 * Please ALWAYS copy [email protected]
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
5f173107 63 board_ahci_yes_fbs,
1da177e4 64
441577ef
TH		 65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
83f2b963
TH		 67 board_ahci_mcp77,
68 board_ahci_mcp89,
441577ef
TH		 69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 78 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 79};
80
2dcb407e 81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
bd17243a
SH		 82static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
029cfd6b
TH		 93static struct ata_port_operations ahci_vt8251_ops = {
94 .inherits = &ahci_ops,
a1efdaba 95 .hardreset = ahci_vt8251_hardreset,
029cfd6b 96};
edc93052 97
029cfd6b
TH		 98static struct ata_port_operations ahci_p5wdh_ops = {
99 .inherits = &ahci_ops,
a1efdaba 100 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 101};
102
bd17243a
SH		 103static struct ata_port_operations ahci_sb600_ops = {
104 .inherits = &ahci_ops,
105 .softreset = ahci_sb600_softreset,
106 .pmp_softreset = ahci_sb600_softreset,
107};
108
417a1a6d
TH		 109#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
110
98ac62de 111static const struct ata_port_info ahci_port_info[] = {
441577ef 112 /* by features */
4da646b7 113 [board_ahci] =
1da177e4 114 {
1188c0d8 115 .flags = AHCI_FLAG_COMMON,
14bdef98 116 .pio_mask = ATA_PIO4,
469248ab 117 .udma_mask = ATA_UDMA6,
1da177e4
LT		 118 .port_ops = &ahci_ops,
119 },
441577ef 120 [board_ahci_ign_iferr] =
bf2af2a2 121 {
441577ef 122 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 123 .flags = AHCI_FLAG_COMMON,
14bdef98 124 .pio_mask = ATA_PIO4,
469248ab 125 .udma_mask = ATA_UDMA6,
441577ef 126 .port_ops = &ahci_ops,
bf2af2a2 127 },
441577ef 128 [board_ahci_nosntf] =
41669553 129 {
441577ef 130 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 131 .flags = AHCI_FLAG_COMMON,
14bdef98 132 .pio_mask = ATA_PIO4,
469248ab 133 .udma_mask = ATA_UDMA6,
41669553
TH		 134 .port_ops = &ahci_ops,
135 },
5f173107
TH		 136 [board_ahci_yes_fbs] =
137 {
138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
441577ef
TH		 144 /* by chipsets */
145 [board_ahci_mcp65] =
55a61604 146 {
83f2b963
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_mcp77] =
155 {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
162 [board_ahci_mcp89] =
163 {
164 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 165 .flags = AHCI_FLAG_COMMON,
14bdef98 166 .pio_mask = ATA_PIO4,
469248ab 167 .udma_mask = ATA_UDMA6,
441577ef 168 .port_ops = &ahci_ops,
55a61604 169 },
4da646b7 170 [board_ahci_mv] =
cd70c266 171 {
417a1a6d 172 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 173 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
cd70c266 174 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 175 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
14bdef98 176 .pio_mask = ATA_PIO4,
cd70c266
JG		 177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
441577ef 180 [board_ahci_sb600] =
e39fc8c9 181 {
441577ef
TH		 182 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
183 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
184 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 185 .flags = AHCI_FLAG_COMMON,
14bdef98 186 .pio_mask = ATA_PIO4,
e39fc8c9 187 .udma_mask = ATA_UDMA6,
bd17243a 188 .port_ops = &ahci_sb600_ops,
e39fc8c9 189 },
441577ef 190 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 191 {
441577ef 192 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
441577ef 196 .port_ops = &ahci_sb600_ops,
aa431dd3 197 },
441577ef 198 [board_ahci_vt8251] =
1b677afd 199 {
441577ef 200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 201 .flags = AHCI_FLAG_COMMON,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
441577ef 204 .port_ops = &ahci_vt8251_ops,
1b677afd 205 },
1da177e4
LT		 206};
207
3b7d697d 208static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 209 /* Intel */
54bb3a94
JG		 210 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
211 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
212 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
213 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
214 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 215 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 216 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
217 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 220 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 221 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 222 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
224 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
236 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 237 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
238 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 239 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 240 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 241 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 242 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 244 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 245 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 246 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 247 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 248 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 249 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 250 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 256 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
257 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
258 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
fe7fa31a 259
e34bb370
TH		 260 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
261 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
262 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 263
264 /* ATI */
c65ec1c2 265 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 266 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
267 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
268 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
269 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
270 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 272
e2dd90b1 273 /* AMD */
5deab536 274 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 275 /* AMD is using RAID class only for ahci controllers */
276 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
277 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
278
fe7fa31a 279 /* VIA */
54bb3a94 280 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 281 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 282
283 /* NVIDIA */
e297d99e
TH		 284 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
285 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
286 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
287 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
288 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 292 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
293 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
294 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
295 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
296 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
305 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
306 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
307 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
321 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
322 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
323 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
324 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
333 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
334 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
335 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
345 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
346 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
347 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
357 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
358 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
359 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
360 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 368
95916edd 369 /* SiS */
20e2de4a
TH		 370 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
371 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
372 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 373
cd70c266
JG		 374 /* Marvell */
375 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 376 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107
TH		 377 { PCI_DEVICE(0x1b4b, 0x9123),
378 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
cd70c266 379
c77a036b
MN		 380 /* Promise */
381 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
382
415ae2b5
JG		 383 /* Generic, PCI class code for AHCI */
384 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 385 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 386
1da177e4
LT		 387 { } /* terminate list */
388};
389
390
391static struct pci_driver ahci_pci_driver = {
392 .name = DRV_NAME,
393 .id_table = ahci_pci_tbl,
394 .probe = ahci_init_one,
24dc5f33 395 .remove = ata_pci_remove_one,
438ac6d5 396#ifdef CONFIG_PM
c1332875 397 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 398 .resume = ahci_pci_device_resume,
399#endif
400};
1da177e4 401
365cfa1e
AV		 402#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
403static int marvell_enable;
404#else
405static int marvell_enable = 1;
406#endif
407module_param(marvell_enable, int, 0644);
408MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 409
1da177e4 410
365cfa1e
AV		 411static void ahci_pci_save_initial_config(struct pci_dev *pdev,
412 struct ahci_host_priv *hpriv)
413{
414 unsigned int force_port_map = 0;
415 unsigned int mask_port_map = 0;
67846b30 416
365cfa1e
AV		 417 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
418 dev_info(&pdev->dev, "JMB361 has only one port\n");
419 force_port_map = 1;
1da177e4
LT		 420 }
421
365cfa1e
AV		 422 /*
423 * Temporary Marvell 6145 hack: PATA port presence
424 * is asserted through the standard AHCI port
425 * presence register, as bit 4 (counting from 0)
d28f87aa 426 */
365cfa1e
AV		 427 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
428 if (pdev->device == 0x6121)
429 mask_port_map = 0x3;
430 else
431 mask_port_map = 0xf;
432 dev_info(&pdev->dev,
433 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
434 }
1da177e4 435
365cfa1e
AV		 436 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
437 mask_port_map);
1da177e4
LT		 438}
439
365cfa1e 440static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 441{
365cfa1e 442 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 443
365cfa1e 444 ahci_reset_controller(host);
1da177e4 445
365cfa1e
AV		 446 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
447 struct ahci_host_priv *hpriv = host->private_data;
448 u16 tmp16;
d6ef3153 449
365cfa1e
AV		 450 /* configure PCS */
451 pci_read_config_word(pdev, 0x92, &tmp16);
452 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
453 tmp16 |= hpriv->port_map;
454 pci_write_config_word(pdev, 0x92, tmp16);
455 }
d6ef3153
SH		 456 }
457
1da177e4
LT		 458 return 0;
459}
460
365cfa1e 461static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 462{
365cfa1e
AV		 463 struct ahci_host_priv *hpriv = host->private_data;
464 struct pci_dev *pdev = to_pci_dev(host->dev);
465 void __iomem *port_mmio;
78cd52d0 466 u32 tmp;
365cfa1e 467 int mv;
78cd52d0 468
365cfa1e
AV		 469 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
470 if (pdev->device == 0x6121)
471 mv = 2;
472 else
473 mv = 4;
474 port_mmio = __ahci_port_base(host, mv);
78cd52d0 475
365cfa1e 476 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 477
365cfa1e
AV		 478 /* clear port IRQ */
479 tmp = readl(port_mmio + PORT_IRQ_STAT);
480 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
481 if (tmp)
482 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 483 }
484
365cfa1e 485 ahci_init_controller(host);
edc93052
TH		 486}
487
365cfa1e 488static int ahci_sb600_check_ready(struct ata_link *link)
78cd52d0 489{
365cfa1e
AV		 490 void __iomem *port_mmio = ahci_port_base(link->ap);
491 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
492 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
493
494 /*
495 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
496 * which can save timeout delay.
497 */
498 if (irq_status & PORT_IRQ_BAD_PMP)
499 return -EIO;
78cd52d0 500
365cfa1e 501 return ata_check_ready(status);
78cd52d0
TH		 502}
503
365cfa1e
AV		 504static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
505 unsigned long deadline)
d6ef3153 506{
365cfa1e 507 struct ata_port *ap = link->ap;
d6ef3153 508 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 509 int pmp = sata_srst_pmp(link);
d6ef3153 510 int rc;
365cfa1e 511 u32 irq_sts;
d6ef3153 512
365cfa1e 513 DPRINTK("ENTER\n");
d6ef3153 514
365cfa1e
AV		 515 rc = ahci_do_softreset(link, class, pmp, deadline,
516 ahci_sb600_check_ready);
d6ef3153 517
365cfa1e
AV		 518 /*
519 * Soft reset fails on some ATI chips with IPMS set when PMP
520 * is enabled but SATA HDD/ODD is connected to SATA port,
521 * do soft reset again to port 0.
522 */
523 if (rc == -EIO) {
524 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
525 if (irq_sts & PORT_IRQ_BAD_PMP) {
526 ata_link_printk(link, KERN_WARNING,
527 "applying SB600 PMP SRST workaround "
528 "and retrying\n");
529 rc = ahci_do_softreset(link, class, 0, deadline,
530 ahci_check_ready);
531 }
532 }
d6ef3153 533
365cfa1e 534 return rc;
d6ef3153
SH		 535}
536
365cfa1e
AV		 537static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
538 unsigned long deadline)
d6ef3153 539{
365cfa1e
AV		 540 struct ata_port *ap = link->ap;
541 bool online;
d6ef3153
SH		 542 int rc;
543
365cfa1e 544 DPRINTK("ENTER\n");
d6ef3153 545
365cfa1e 546 ahci_stop_engine(ap);
d6ef3153 547
365cfa1e
AV		 548 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
549 deadline, &online, NULL);
d6ef3153
SH		 550
551 ahci_start_engine(ap);
d6ef3153 552
365cfa1e 553 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 554
365cfa1e
AV		 555 /* vt8251 doesn't clear BSY on signature FIS reception,
556 * request follow-up softreset.
557 */
558 return online ? -EAGAIN : rc;
7d50b60b
TH		 559}
560
365cfa1e
AV		 561static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
562 unsigned long deadline)
7d50b60b 563{
365cfa1e 564 struct ata_port *ap = link->ap;
1c954a4d 565 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 566 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
567 struct ata_taskfile tf;
568 bool online;
569 int rc;
7d50b60b 570
365cfa1e 571 ahci_stop_engine(ap);
028a2596 572
365cfa1e
AV		 573 /* clear D2H reception area to properly wait for D2H FIS */
574 ata_tf_init(link->device, &tf);
575 tf.command = 0x80;
576 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 577
365cfa1e
AV		 578 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
579 deadline, &online, NULL);
028a2596 580
365cfa1e 581 ahci_start_engine(ap);
c1332875 582
365cfa1e
AV		 583 /* The pseudo configuration device on SIMG4726 attached to
584 * ASUS P5W-DH Deluxe doesn't send signature FIS after
585 * hardreset if no device is attached to the first downstream
586 * port && the pseudo device locks up on SRST w/ PMP==0. To
587 * work around this, wait for !BSY only briefly. If BSY isn't
588 * cleared, perform CLO and proceed to IDENTIFY (achieved by
589 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
590 *
591 * Wait for two seconds. Devices attached to downstream port
592 * which can't process the following IDENTIFY after this will
593 * have to be reset again. For most cases, this should
594 * suffice while making probing snappish enough.
595 */
596 if (online) {
597 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
598 ahci_check_ready);
599 if (rc)
600 ahci_kick_engine(ap);
c1332875 601 }
c1332875
TH		 602 return rc;
603}
604
365cfa1e 605#ifdef CONFIG_PM
c1332875
TH		 606static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
607{
cca3974e 608 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 609 struct ahci_host_priv *hpriv = host->private_data;
d8993349 610 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 611 u32 ctl;
612
9b10ae86
TH		 613 if (mesg.event & PM_EVENT_SUSPEND &&
614 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
615 dev_printk(KERN_ERR, &pdev->dev,
616 "BIOS update required for suspend/resume\n");
617 return -EIO;
618 }
619
3a2d5b70 620 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 621 /* AHCI spec rev1.1 section 8.3.3:
622 * Software must disable interrupts prior to requesting a
623 * transition of the HBA to D3 state.
624 */
625 ctl = readl(mmio + HOST_CTL);
626 ctl &= ~HOST_IRQ_EN;
627 writel(ctl, mmio + HOST_CTL);
628 readl(mmio + HOST_CTL); /* flush */
629 }
630
631 return ata_pci_device_suspend(pdev, mesg);
632}
633
634static int ahci_pci_device_resume(struct pci_dev *pdev)
635{
cca3974e 636 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 637 int rc;
638
553c4aa6
TH		 639 rc = ata_pci_device_do_resume(pdev);
640 if (rc)
641 return rc;
c1332875
TH		 642
643 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 644 rc = ahci_pci_reset_controller(host);
c1332875
TH		 645 if (rc)
646 return rc;
647
781d6550 648 ahci_pci_init_controller(host);
c1332875
TH		 649 }
650
cca3974e 651 ata_host_resume(host);
c1332875
TH		 652
653 return 0;
654}
438ac6d5 655#endif
c1332875 656
4447d351 657static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 658{
1da177e4 659 int rc;
1da177e4 660
1da177e4 661 if (using_dac &&
6a35528a
YH		 662 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
663 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 664 if (rc) {
284901a9 665 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 666 if (rc) {
a9524a76
JG		 667 dev_printk(KERN_ERR, &pdev->dev,
668 "64-bit DMA enable failed\n");
1da177e4
LT		 669 return rc;
670 }
671 }
1da177e4 672 } else {
284901a9 673 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 674 if (rc) {
a9524a76
JG		 675 dev_printk(KERN_ERR, &pdev->dev,
676 "32-bit DMA enable failed\n");
1da177e4
LT		 677 return rc;
678 }
284901a9 679 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 680 if (rc) {
a9524a76
JG		 681 dev_printk(KERN_ERR, &pdev->dev,
682 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 683 return rc;
684 }
685 }
1da177e4
LT		 686 return 0;
687}
688
439fcaec
AV		 689static void ahci_pci_print_info(struct ata_host *host)
690{
691 struct pci_dev *pdev = to_pci_dev(host->dev);
692 u16 cc;
693 const char *scc_s;
694
695 pci_read_config_word(pdev, 0x0a, &cc);
696 if (cc == PCI_CLASS_STORAGE_IDE)
697 scc_s = "IDE";
698 else if (cc == PCI_CLASS_STORAGE_SATA)
699 scc_s = "SATA";
700 else if (cc == PCI_CLASS_STORAGE_RAID)
701 scc_s = "RAID";
702 else
703 scc_s = "unknown";
704
705 ahci_print_info(host, scc_s);
706}
707
edc93052
TH		 708/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
709 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
710 * support PMP and the 4726 either directly exports the device
711 * attached to the first downstream port or acts as a hardware storage
712 * controller and emulate a single ATA device (can be RAID 0/1 or some
713 * other configuration).
714 *
715 * When there's no device attached to the first downstream port of the
716 * 4726, "Config Disk" appears, which is a pseudo ATA device to
717 * configure the 4726. However, ATA emulation of the device is very
718 * lame. It doesn't send signature D2H Reg FIS after the initial
719 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
720 *
721 * The following function works around the problem by always using
722 * hardreset on the port and not depending on receiving signature FIS
723 * afterward. If signature FIS isn't received soon, ATA class is
724 * assumed without follow-up softreset.
725 */
726static void ahci_p5wdh_workaround(struct ata_host *host)
727{
728 static struct dmi_system_id sysids[] = {
729 {
730 .ident = "P5W DH Deluxe",
731 .matches = {
732 DMI_MATCH(DMI_SYS_VENDOR,
733 "ASUSTEK COMPUTER INC"),
734 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
735 },
736 },
737 { }
738 };
739 struct pci_dev *pdev = to_pci_dev(host->dev);
740
741 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
742 dmi_check_system(sysids)) {
743 struct ata_port *ap = host->ports[1];
744
745 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
746 "Deluxe on-board SIMG4726 workaround\n");
747
748 ap->ops = &ahci_p5wdh_ops;
749 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
750 }
751}
752
2fcad9d2
TH		 753/* only some SB600 ahci controllers can do 64bit DMA */
754static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 755{
756 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 757 /*
758 * The oldest version known to be broken is 0901 and
759 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 760 * Enable 64bit DMA on 1501 and anything newer.
761 *
03d783bf
TH		 762 * Please read bko#9412 for more info.
763 */
58a09b38
SH		 764 {
765 .ident = "ASUS M2A-VM",
766 .matches = {
767 DMI_MATCH(DMI_BOARD_VENDOR,
768 "ASUSTeK Computer INC."),
769 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
770 },
03d783bf 771 .driver_data = "20071026", /* yyyymmdd */
58a09b38 772 },
e65cc194
MN		 773 /*
774 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
775 * support 64bit DMA.
776 *
777 * BIOS versions earlier than 1.5 had the Manufacturer DMI
778 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
779 * This spelling mistake was fixed in BIOS version 1.5, so
780 * 1.5 and later have the Manufacturer as
781 * "MICRO-STAR INTERNATIONAL CO.,LTD".
782 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
783 *
784 * BIOS versions earlier than 1.9 had a Board Product Name
785 * DMI field of "MS-7376". This was changed to be
786 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
787 * match on DMI_BOARD_NAME of "MS-7376".
788 */
789 {
790 .ident = "MSI K9A2 Platinum",
791 .matches = {
792 DMI_MATCH(DMI_BOARD_VENDOR,
793 "MICRO-STAR INTER"),
794 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
795 },
796 },
58a09b38
SH		 797 { }
798 };
03d783bf 799 const struct dmi_system_id *match;
2fcad9d2
TH		 800 int year, month, date;
801 char buf[9];
58a09b38 802
03d783bf 803 match = dmi_first_match(sysids);
58a09b38 804 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 805 !match)
58a09b38
SH		 806 return false;
807
e65cc194
MN		 808 if (!match->driver_data)
809 goto enable_64bit;
810
2fcad9d2
TH		 811 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
812 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 813
e65cc194
MN		 814 if (strcmp(buf, match->driver_data) >= 0)
815 goto enable_64bit;
816 else {
03d783bf
TH		 817 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
818 "forcing 32bit DMA, update BIOS\n", match->ident);
2fcad9d2
TH		 819 return false;
820 }
e65cc194
MN		 821
822enable_64bit:
823 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
824 match->ident);
825 return true;
58a09b38
SH		 826}
827
1fd68434
RW		 828static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
829{
830 static const struct dmi_system_id broken_systems[] = {
831 {
832 .ident = "HP Compaq nx6310",
833 .matches = {
834 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
835 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
836 },
837 /* PCI slot number of the controller */
838 .driver_data = (void *)0x1FUL,
839 },
d2f9c061
MR		 840 {
841 .ident = "HP Compaq 6720s",
842 .matches = {
843 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
844 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
845 },
846 /* PCI slot number of the controller */
847 .driver_data = (void *)0x1FUL,
848 },
1fd68434
RW		 849
850 { } /* terminate list */
851 };
852 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
853
854 if (dmi) {
855 unsigned long slot = (unsigned long)dmi->driver_data;
856 /* apply the quirk only to on-board controllers */
857 return slot == PCI_SLOT(pdev->devfn);
858 }
859
860 return false;
861}
862
9b10ae86
TH		 863static bool ahci_broken_suspend(struct pci_dev *pdev)
864{
865 static const struct dmi_system_id sysids[] = {
866 /*
867 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
868 * to the harddisk doesn't become online after
869 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 870 *
871 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
872 *
873 * Use dates instead of versions to match as HP is
874 * apparently recycling both product and version
875 * strings.
876 *
877 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 878 */
879 {
880 .ident = "dv4",
881 .matches = {
882 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
883 DMI_MATCH(DMI_PRODUCT_NAME,
884 "HP Pavilion dv4 Notebook PC"),
885 },
9deb3431 886 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 887 },
888 {
889 .ident = "dv5",
890 .matches = {
891 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
892 DMI_MATCH(DMI_PRODUCT_NAME,
893 "HP Pavilion dv5 Notebook PC"),
894 },
9deb3431 895 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 896 },
897 {
898 .ident = "dv6",
899 .matches = {
900 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
901 DMI_MATCH(DMI_PRODUCT_NAME,
902 "HP Pavilion dv6 Notebook PC"),
903 },
9deb3431 904 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 905 },
906 {
907 .ident = "HDX18",
908 .matches = {
909 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
910 DMI_MATCH(DMI_PRODUCT_NAME,
911 "HP HDX18 Notebook PC"),
912 },
9deb3431 913 .driver_data = "20090430", /* F.23 */
9b10ae86 914 },
cedc9bf9
TH		 915 /*
916 * Acer eMachines G725 has the same problem. BIOS
917 * V1.03 is known to be broken. V3.04 is known to
918 * work. Inbetween, there are V1.06, V2.06 and V3.03
919 * that we don't have much idea about. For now,
920 * blacklist anything older than V3.04.
9deb3431
TH		 921 *
922 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 923 */
924 {
925 .ident = "G725",
926 .matches = {
927 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
928 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
929 },
9deb3431 930 .driver_data = "20091216", /* V3.04 */
cedc9bf9 931 },
9b10ae86
TH		 932 { } /* terminate list */
933 };
934 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 935 int year, month, date;
936 char buf[9];
9b10ae86
TH		 937
938 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
939 return false;
940
9deb3431
TH		 941 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
942 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 943
9deb3431 944 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 945}
946
5594639a
TH		 947static bool ahci_broken_online(struct pci_dev *pdev)
948{
949#define ENCODE_BUSDEVFN(bus, slot, func) \
950 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
951 static const struct dmi_system_id sysids[] = {
952 /*
953 * There are several gigabyte boards which use
954 * SIMG5723s configured as hardware RAID. Certain
955 * 5723 firmware revisions shipped there keep the link
956 * online but fail to answer properly to SRST or
957 * IDENTIFY when no device is attached downstream
958 * causing libata to retry quite a few times leading
959 * to excessive detection delay.
960 *
961 * As these firmwares respond to the second reset try
962 * with invalid device signature, considering unknown
963 * sig as offline works around the problem acceptably.
964 */
965 {
966 .ident = "EP45-DQ6",
967 .matches = {
968 DMI_MATCH(DMI_BOARD_VENDOR,
969 "Gigabyte Technology Co., Ltd."),
970 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
971 },
972 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
973 },
974 {
975 .ident = "EP45-DS5",
976 .matches = {
977 DMI_MATCH(DMI_BOARD_VENDOR,
978 "Gigabyte Technology Co., Ltd."),
979 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
980 },
981 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
982 },
983 { } /* terminate list */
984 };
985#undef ENCODE_BUSDEVFN
986 const struct dmi_system_id *dmi = dmi_first_match(sysids);
987 unsigned int val;
988
989 if (!dmi)
990 return false;
991
992 val = (unsigned long)dmi->driver_data;
993
994 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
995}
996
8e513217 997#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 998static void ahci_gtf_filter_workaround(struct ata_host *host)
999{
1000 static const struct dmi_system_id sysids[] = {
1001 /*
1002 * Aspire 3810T issues a bunch of SATA enable commands
1003 * via _GTF including an invalid one and one which is
1004 * rejected by the device. Among the successful ones
1005 * is FPDMA non-zero offset enable which when enabled
1006 * only on the drive side leads to NCQ command
1007 * failures. Filter it out.
1008 */
1009 {
1010 .ident = "Aspire 3810T",
1011 .matches = {
1012 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1013 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1014 },
1015 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1016 },
1017 { }
1018 };
1019 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1020 unsigned int filter;
1021 int i;
1022
1023 if (!dmi)
1024 return;
1025
1026 filter = (unsigned long)dmi->driver_data;
1027 dev_printk(KERN_INFO, host->dev,
1028 "applying extra ACPI _GTF filter 0x%x for %s\n",
1029 filter, dmi->ident);
1030
1031 for (i = 0; i < host->n_ports; i++) {
1032 struct ata_port *ap = host->ports[i];
1033 struct ata_link *link;
1034 struct ata_device *dev;
1035
1036 ata_for_each_link(link, ap, EDGE)
1037 ata_for_each_dev(dev, link, ALL)
1038 dev->gtf_filter |= filter;
1039 }
1040}
8e513217
MT		 1041#else
1042static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1043{}
1044#endif
f80ae7e4 1045
24dc5f33 1046static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1047{
1048 static int printed_version;
e297d99e
TH		 1049 unsigned int board_id = ent->driver_data;
1050 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1051 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1052 struct device *dev = &pdev->dev;
1da177e4 1053 struct ahci_host_priv *hpriv;
4447d351 1054 struct ata_host *host;
837f5f8f 1055 int n_ports, i, rc;
1da177e4
LT		 1056
1057 VPRINTK("ENTER\n");
1058
b429dd59 1059 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1060
1da177e4 1061 if (!printed_version++)
a9524a76 1062 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1063
5b66c829
AC		 1064 /* The AHCI driver can only drive the SATA ports, the PATA driver
1065 can drive them all so if both drivers are selected make sure
1066 AHCI stays out of the way */
1067 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1068 return -ENODEV;
1069
c6353b45
TH		 1070 /*
1071 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1072 * ahci, use ata_generic instead.
1073 */
1074 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1075 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1076 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1077 pdev->subsystem_device == 0xcb89)
1078 return -ENODEV;
1079
7a02267e
MN		 1080 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1081 * At the moment, we can only use the AHCI mode. Let the users know
1082 * that for SAS drives they're out of luck.
1083 */
1084 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1085 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1086 "can only drive SATA devices with this driver\n");
1087
4447d351 1088 /* acquire resources */
24dc5f33 1089 rc = pcim_enable_device(pdev);
1da177e4
LT		 1090 if (rc)
1091 return rc;
1092
dea55137
TH		 1093 /* AHCI controllers often implement SFF compatible interface.
1094 * Grab all PCI BARs just in case.
1095 */
1096 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1097 if (rc == -EBUSY)
24dc5f33 1098 pcim_pin_device(pdev);
0d5ff566 1099 if (rc)
24dc5f33 1100 return rc;
1da177e4 1101
c4f7792c
TH		 1102 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1103 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1104 u8 map;
1105
1106 /* ICH6s share the same PCI ID for both piix and ahci
1107 * modes. Enabling ahci mode while MAP indicates
1108 * combined mode is a bad idea. Yield to ata_piix.
1109 */
1110 pci_read_config_byte(pdev, ICH_MAP, &map);
1111 if (map & 0x3) {
1112 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1113 "combined mode, can't enable AHCI mode\n");
1114 return -ENODEV;
1115 }
1116 }
1117
24dc5f33
TH		 1118 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1119 if (!hpriv)
1120 return -ENOMEM;
417a1a6d
TH		 1121 hpriv->flags |= (unsigned long)pi.private_data;
1122
e297d99e
TH		 1123 /* MCP65 revision A1 and A2 can't do MSI */
1124 if (board_id == board_ahci_mcp65 &&
1125 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1126 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1127
e427fe04
SH		 1128 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1129 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1130 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1131
2fcad9d2
TH		 1132 /* only some SB600s can do 64bit DMA */
1133 if (ahci_sb600_enable_64bit(pdev))
1134 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1135
31b239ad
TH		 1136 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1137 pci_intx(pdev, 1);
1da177e4 1138
d8993349
AV		 1139 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1140
4447d351 1141 /* save initial config */
394d6e53 1142 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1143
4447d351 1144 /* prepare host */
453d3131
RH		 1145 if (hpriv->cap & HOST_CAP_NCQ) {
1146 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1147 /*
1148 * Auto-activate optimization is supposed to be
1149 * supported on all AHCI controllers indicating NCQ
1150 * capability, but it seems to be broken on some
1151 * chipsets including NVIDIAs.
1152 */
1153 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1154 pi.flags |= ATA_FLAG_FPDMA_AA;
1155 }
1da177e4 1156
7d50b60b
TH		 1157 if (hpriv->cap & HOST_CAP_PMP)
1158 pi.flags |= ATA_FLAG_PMP;
1159
0cbb0e77 1160 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1161
1fd68434
RW		 1162 if (ahci_broken_system_poweroff(pdev)) {
1163 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1164 dev_info(&pdev->dev,
1165 "quirky BIOS, skipping spindown on poweroff\n");
1166 }
1167
9b10ae86
TH		 1168 if (ahci_broken_suspend(pdev)) {
1169 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1170 dev_printk(KERN_WARNING, &pdev->dev,
1171 "BIOS update required for suspend/resume\n");
1172 }
1173
5594639a
TH		 1174 if (ahci_broken_online(pdev)) {
1175 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1176 dev_info(&pdev->dev,
1177 "online status unreliable, applying workaround\n");
1178 }
1179
837f5f8f
TH		 1180 /* CAP.NP sometimes indicate the index of the last enabled
1181 * port, at other times, that of the last possible port, so
1182 * determining the maximum port number requires looking at
1183 * both CAP.NP and port_map.
1184 */
1185 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1186
1187 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1188 if (!host)
1189 return -ENOMEM;
4447d351
TH		 1190 host->private_data = hpriv;
1191
f3d7f23f 1192 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1193 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1194 else
1195 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1196
18f7ba4c
KCA		 1197 if (pi.flags & ATA_FLAG_EM)
1198 ahci_reset_em(host);
1199
4447d351 1200 for (i = 0; i < host->n_ports; i++) {
dab632e8 1201 struct ata_port *ap = host->ports[i];
4447d351 1202
cbcdd875
TH		 1203 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1204 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1205 0x100 + ap->port_no * 0x80, "port");
1206
31556594
KCA		 1207 /* set initial link pm policy */
1208 ap->pm_policy = NOT_AVAILABLE;
1209
18f7ba4c
KCA		 1210 /* set enclosure management message type */
1211 if (ap->flags & ATA_FLAG_EM)
008dbd61 1212 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1213
1214
dab632e8 1215 /* disabled/not-implemented port */
350756f6 1216 if (!(hpriv->port_map & (1 << i)))
dab632e8 1217 ap->ops = &ata_dummy_port_ops;
4447d351 1218 }
d447df14 1219
edc93052
TH		 1220 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1221 ahci_p5wdh_workaround(host);
1222
f80ae7e4
TH		 1223 /* apply gtf filter quirk */
1224 ahci_gtf_filter_workaround(host);
1225
4447d351
TH		 1226 /* initialize adapter */
1227 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1228 if (rc)
24dc5f33 1229 return rc;
1da177e4 1230
3303040d 1231 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1232 if (rc)
1233 return rc;
1da177e4 1234
781d6550 1235 ahci_pci_init_controller(host);
439fcaec 1236 ahci_pci_print_info(host);
1da177e4 1237
4447d351
TH		 1238 pci_set_master(pdev);
1239 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1240 &ahci_sht);
907f4678 1241}
1da177e4
LT		 1242
1243static int __init ahci_init(void)
1244{
b7887196 1245 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1246}
1247
1da177e4
LT		 1248static void __exit ahci_exit(void)
1249{
1250 pci_unregister_driver(&ahci_pci_driver);
1251}
1252
1253
1254MODULE_AUTHOR("Jeff Garzik");
1255MODULE_DESCRIPTION("AHCI SATA low-level driver");
1256MODULE_LICENSE("GPL");
1257MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1258MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1259
1260module_init(ahci_init);
1261module_exit(ahci_exit);
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