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iwlwifi: Thermal Throttling debugfs function
[linux.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
CommitLineData
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1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
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4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
759ef89f 25 * Intel Linux Wireless <[email protected]>
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26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
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30#include <linux/kernel.h>
31#include <linux/module.h>
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32#include <linux/init.h>
33#include <linux/pci.h>
34#include <linux/dma-mapping.h>
35#include <linux/delay.h>
36#include <linux/skbuff.h>
37#include <linux/netdevice.h>
38#include <linux/wireless.h>
39#include <linux/firmware.h>
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40#include <linux/etherdevice.h>
41#include <linux/if_arp.h>
42
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43#include <net/mac80211.h>
44
45#include <asm/div64.h>
46
a3139c59
SO
47#define DRV_NAME "iwlagn"
48
6bc913bd 49#include "iwl-eeprom.h"
3e0d4cb1 50#include "iwl-dev.h"
fee1247a 51#include "iwl-core.h"
3395f6e9 52#include "iwl-io.h"
b481de9c 53#include "iwl-helpers.h"
6974e363 54#include "iwl-sta.h"
f0832f13 55#include "iwl-calib.h"
b481de9c 56
416e1438 57
b481de9c
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58/******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
b481de9c
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64/*
65 * module name, copyright, version, etc.
b481de9c 66 */
d783b061 67#define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
b481de9c 68
0a6857e7 69#ifdef CONFIG_IWLWIFI_DEBUG
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70#define VD "d"
71#else
72#define VD
73#endif
74
80bc5393 75#ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
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76#define VS "s"
77#else
78#define VS
79#endif
80
df48c323 81#define DRV_VERSION IWLWIFI_VERSION VD VS
b481de9c 82
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83
84MODULE_DESCRIPTION(DRV_DESCRIPTION);
85MODULE_VERSION(DRV_VERSION);
a7b75207 86MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
b481de9c 87MODULE_LICENSE("GPL");
4fc22b21 88MODULE_ALIAS("iwl4965");
b481de9c 89
b481de9c 90/*************** STATION TABLE MANAGEMENT ****
9fbab516 91 * mac80211 should be examined to determine if sta_info is duplicating
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92 * the functionality provided here
93 */
94
95/**************************************************************/
96
b481de9c 97/**
5b9f8cd3 98 * iwl_commit_rxon - commit staging_rxon to hardware
b481de9c 99 *
01ebd063 100 * The RXON command in staging_rxon is committed to the hardware and
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101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
e0158e61 105int iwl_commit_rxon(struct iwl_priv *priv)
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106{
107 /* cast away the const for active_rxon in this function */
c1adf9fb 108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
43d59b32
EG
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
b481de9c 112
fee1247a 113 if (!iwl_is_alive(priv))
43d59b32 114 return -EBUSY;
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115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
a326a5d0
EG
118 /* allow CTS-to-self if possible. this is relevant only for
119 * 5000, but will not damage 4965 */
120 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
b481de9c 121
8ccde88a 122 ret = iwl_check_rxon_cmd(priv);
43d59b32 123 if (ret) {
15b1687c 124 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
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125 return -EINVAL;
126 }
127
128 /* If we don't need to send a full RXON, we can use
5b9f8cd3 129 * iwl_rxon_assoc_cmd which is used to reconfigure filter
b481de9c 130 * and other flags for the current radio configuration. */
54559703 131 if (!iwl_full_rxon_required(priv)) {
43d59b32
EG
132 ret = iwl_send_rxon_assoc(priv);
133 if (ret) {
15b1687c 134 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
43d59b32 135 return ret;
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136 }
137
138 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
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139 return 0;
140 }
141
142 /* station table will be cleared */
143 priv->assoc_station_added = 0;
144
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145 /* If we are currently associated and the new config requires
146 * an RXON_ASSOC and the new config wants the associated mask enabled,
147 * we must clear the associated from the active configuration
148 * before we apply the new config */
43d59b32 149 if (iwl_is_associated(priv) && new_assoc) {
e1623446 150 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
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151 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
152
43d59b32 153 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 154 sizeof(struct iwl_rxon_cmd),
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155 &priv->active_rxon);
156
157 /* If the mask clearing failed then we set
158 * active_rxon back to what it was previously */
43d59b32 159 if (ret) {
b481de9c 160 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
15b1687c 161 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
43d59b32 162 return ret;
b481de9c 163 }
b481de9c
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164 }
165
e1623446 166 IWL_DEBUG_INFO(priv, "Sending RXON\n"
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167 "* with%s RXON_FILTER_ASSOC_MSK\n"
168 "* channel = %d\n"
e174961c 169 "* bssid = %pM\n",
43d59b32 170 (new_assoc ? "" : "out"),
b481de9c 171 le16_to_cpu(priv->staging_rxon.channel),
e174961c 172 priv->staging_rxon.bssid_addr);
b481de9c 173
90e8e424 174 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
43d59b32
EG
175
176 /* Apply the new configuration
177 * RXON unassoc clears the station table in uCode, send it before
178 * we add the bcast station. If assoc bit is set, we will send RXON
179 * after having added the bcast and bssid station.
180 */
181 if (!new_assoc) {
182 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
c1adf9fb 183 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
43d59b32 184 if (ret) {
15b1687c 185 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
186 return ret;
187 }
188 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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189 }
190
c587de0b 191 iwl_clear_stations_table(priv);
556f8db7 192
19cc1087 193 priv->start_calib = 0;
b481de9c 194
b481de9c 195 /* Add the broadcast address so we can send broadcast frames */
4f40e4d9 196 if (iwl_rxon_add_station(priv, iwl_bcast_addr, 0) ==
43d59b32 197 IWL_INVALID_STATION) {
15b1687c 198 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
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199 return -EIO;
200 }
201
202 /* If we have set the ASSOC_MSK and we are in BSS mode then
203 * add the IWL_AP_ID to the station rate table */
9185159d 204 if (new_assoc) {
05c914fe 205 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
9185159d
TW
206 ret = iwl_rxon_add_station(priv,
207 priv->active_rxon.bssid_addr, 1);
208 if (ret == IWL_INVALID_STATION) {
15b1687c
WT
209 IWL_ERR(priv,
210 "Error adding AP address for TX.\n");
9185159d
TW
211 return -EIO;
212 }
213 priv->assoc_station_added = 1;
214 if (priv->default_wep_key &&
215 iwl_send_static_wepkey_cmd(priv, 0))
15b1687c
WT
216 IWL_ERR(priv,
217 "Could not send WEP static key.\n");
b481de9c 218 }
43d59b32
EG
219
220 /* Apply the new configuration
221 * RXON assoc doesn't clear the station table in uCode,
222 */
223 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
224 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
225 if (ret) {
15b1687c 226 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
43d59b32
EG
227 return ret;
228 }
229 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
b481de9c
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230 }
231
36da7d70
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232 iwl_init_sensitivity(priv);
233
234 /* If we issue a new RXON command which required a tune then we must
235 * send a new TXPOWER command or we won't be able to Tx any frames */
236 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
237 if (ret) {
15b1687c 238 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
36da7d70
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239 return ret;
240 }
241
b481de9c
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242 return 0;
243}
244
5b9f8cd3 245void iwl_update_chain_flags(struct iwl_priv *priv)
5da4b55f
MA
246{
247
45823531
AK
248 if (priv->cfg->ops->hcmd->set_rxon_chain)
249 priv->cfg->ops->hcmd->set_rxon_chain(priv);
e0158e61 250 iwlcore_commit_rxon(priv);
5da4b55f
MA
251}
252
fcab423d 253static void iwl_clear_free_frames(struct iwl_priv *priv)
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254{
255 struct list_head *element;
256
e1623446 257 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
b481de9c
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258 priv->frames_count);
259
260 while (!list_empty(&priv->free_frames)) {
261 element = priv->free_frames.next;
262 list_del(element);
fcab423d 263 kfree(list_entry(element, struct iwl_frame, list));
b481de9c
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264 priv->frames_count--;
265 }
266
267 if (priv->frames_count) {
39aadf8c 268 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
b481de9c
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269 priv->frames_count);
270 priv->frames_count = 0;
271 }
272}
273
fcab423d 274static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
b481de9c 275{
fcab423d 276 struct iwl_frame *frame;
b481de9c
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277 struct list_head *element;
278 if (list_empty(&priv->free_frames)) {
279 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
280 if (!frame) {
15b1687c 281 IWL_ERR(priv, "Could not allocate frame!\n");
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282 return NULL;
283 }
284
285 priv->frames_count++;
286 return frame;
287 }
288
289 element = priv->free_frames.next;
290 list_del(element);
fcab423d 291 return list_entry(element, struct iwl_frame, list);
b481de9c
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292}
293
fcab423d 294static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
b481de9c
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295{
296 memset(frame, 0, sizeof(*frame));
297 list_add(&frame->list, &priv->free_frames);
298}
299
4bf64efd
TW
300static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
301 struct ieee80211_hdr *hdr,
73ec1cc2 302 int left)
b481de9c 303{
3109ece1 304 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
05c914fe
JB
305 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
306 (priv->iw_mode != NL80211_IFTYPE_AP)))
b481de9c
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307 return 0;
308
309 if (priv->ibss_beacon->len > left)
310 return 0;
311
312 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
313
314 return priv->ibss_beacon->len;
315}
316
5b9f8cd3 317static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
4bf64efd
TW
318 struct iwl_frame *frame, u8 rate)
319{
320 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
321 unsigned int frame_size;
322
323 tx_beacon_cmd = &frame->u.beacon;
324 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
325
326 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
327 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
328
329 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
4bf64efd
TW
330 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
331
332 BUG_ON(frame_size > MAX_MPDU_SIZE);
333 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
334
335 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
336 tx_beacon_cmd->tx.rate_n_flags =
337 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
338 else
339 tx_beacon_cmd->tx.rate_n_flags =
340 iwl_hw_set_rate_n_flags(rate, 0);
341
342 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
343 TX_CMD_FLG_TSF_MSK |
344 TX_CMD_FLG_STA_RATE_MSK;
345
346 return sizeof(*tx_beacon_cmd) + frame_size;
347}
5b9f8cd3 348static int iwl_send_beacon_cmd(struct iwl_priv *priv)
b481de9c 349{
fcab423d 350 struct iwl_frame *frame;
b481de9c
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351 unsigned int frame_size;
352 int rc;
353 u8 rate;
354
fcab423d 355 frame = iwl_get_free_frame(priv);
b481de9c
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356
357 if (!frame) {
15b1687c 358 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
b481de9c
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359 "command.\n");
360 return -ENOMEM;
361 }
362
5b9f8cd3 363 rate = iwl_rate_get_lowest_plcp(priv);
b481de9c 364
5b9f8cd3 365 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
b481de9c 366
857485c0 367 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
b481de9c
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368 &frame->u.cmd[0]);
369
fcab423d 370 iwl_free_frame(priv, frame);
b481de9c
ZY
371
372 return rc;
373}
374
7aaa1d79
SO
375static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
376{
377 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
378
379 dma_addr_t addr = get_unaligned_le32(&tb->lo);
380 if (sizeof(dma_addr_t) > sizeof(u32))
381 addr |=
382 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
383
384 return addr;
385}
386
387static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
388{
389 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
390
391 return le16_to_cpu(tb->hi_n_len) >> 4;
392}
393
394static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
395 dma_addr_t addr, u16 len)
396{
397 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
398 u16 hi_n_len = len << 4;
399
400 put_unaligned_le32(addr, &tb->lo);
401 if (sizeof(dma_addr_t) > sizeof(u32))
402 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
403
404 tb->hi_n_len = cpu_to_le16(hi_n_len);
405
406 tfd->num_tbs = idx + 1;
407}
408
409static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
410{
411 return tfd->num_tbs & 0x1f;
412}
413
414/**
415 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
416 * @priv - driver private data
417 * @txq - tx queue
418 *
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
421 */
422void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
423{
59606ffa 424 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
7aaa1d79
SO
425 struct iwl_tfd *tfd;
426 struct pci_dev *dev = priv->pci_dev;
427 int index = txq->q.read_ptr;
428 int i;
429 int num_tbs;
430
431 tfd = &tfd_tmp[index];
432
433 /* Sanity check on number of chunks */
434 num_tbs = iwl_tfd_get_num_tbs(tfd);
435
436 if (num_tbs >= IWL_NUM_OF_TBS) {
437 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
438 /* @todo issue fatal error, it is quite serious situation */
439 return;
440 }
441
442 /* Unmap tx_cmd */
443 if (num_tbs)
444 pci_unmap_single(dev,
445 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
446 pci_unmap_len(&txq->cmd[index]->meta, len),
96891cee 447 PCI_DMA_BIDIRECTIONAL);
7aaa1d79
SO
448
449 /* Unmap chunks, if any. */
450 for (i = 1; i < num_tbs; i++) {
451 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
452 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
453
454 if (txq->txb) {
455 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
456 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
457 }
458 }
459}
460
461int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
462 struct iwl_tx_queue *txq,
463 dma_addr_t addr, u16 len,
464 u8 reset, u8 pad)
465{
466 struct iwl_queue *q;
59606ffa 467 struct iwl_tfd *tfd, *tfd_tmp;
7aaa1d79
SO
468 u32 num_tbs;
469
470 q = &txq->q;
59606ffa
SO
471 tfd_tmp = (struct iwl_tfd *)txq->tfds;
472 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO
473
474 if (reset)
475 memset(tfd, 0, sizeof(*tfd));
476
477 num_tbs = iwl_tfd_get_num_tbs(tfd);
478
479 /* Each TFD can point to a maximum 20 Tx buffers */
480 if (num_tbs >= IWL_NUM_OF_TBS) {
481 IWL_ERR(priv, "Error can not send more than %d chunks\n",
482 IWL_NUM_OF_TBS);
483 return -EINVAL;
484 }
485
486 BUG_ON(addr & ~DMA_BIT_MASK(36));
487 if (unlikely(addr & ~IWL_TX_DMA_MASK))
488 IWL_ERR(priv, "Unaligned address = %llx\n",
489 (unsigned long long)addr);
490
491 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
492
493 return 0;
494}
495
a8e74e27
SO
496/*
497 * Tell nic where to find circular buffer of Tx Frame Descriptors for
498 * given Tx queue, and enable the DMA channel used for that queue.
499 *
500 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
501 * channels supported in hardware.
502 */
503int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq)
505{
a8e74e27
SO
506 int txq_id = txq->q.id;
507
a8e74e27
SO
508 /* Circular buffer (TFD queue in DRAM) physical base address */
509 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
510 txq->q.dma_addr >> 8);
511
a8e74e27
SO
512 return 0;
513}
514
b481de9c
ZY
515/******************************************************************************
516 *
517 * Generic RX handler implementations
518 *
519 ******************************************************************************/
885ba202
TW
520static void iwl_rx_reply_alive(struct iwl_priv *priv,
521 struct iwl_rx_mem_buffer *rxb)
b481de9c 522{
db11d634 523 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
885ba202 524 struct iwl_alive_resp *palive;
b481de9c
ZY
525 struct delayed_work *pwork;
526
527 palive = &pkt->u.alive_frame;
528
e1623446 529 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
b481de9c
ZY
530 "0x%01X 0x%01X\n",
531 palive->is_valid, palive->ver_type,
532 palive->ver_subtype);
533
534 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
e1623446 535 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
34a66de6
WYG
536 set_bit(STATUS_INIT_UCODE_ALIVE, &priv->status);
537 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
538 memcpy(&priv->card_alive_init,
539 &pkt->u.alive_frame,
885ba202 540 sizeof(struct iwl_init_alive_resp));
b481de9c
ZY
541 pwork = &priv->init_alive_start;
542 } else {
e1623446 543 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
34a66de6
WYG
544 set_bit(STATUS_RT_UCODE_ALIVE, &priv->status);
545 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 546 memcpy(&priv->card_alive, &pkt->u.alive_frame,
885ba202 547 sizeof(struct iwl_alive_resp));
b481de9c
ZY
548 pwork = &priv->alive_start;
549 }
550
551 /* We delay the ALIVE response by 5ms to
552 * give the HW RF Kill time to activate... */
553 if (palive->is_valid == UCODE_VALID_OK)
554 queue_delayed_work(priv->workqueue, pwork,
555 msecs_to_jiffies(5));
556 else
39aadf8c 557 IWL_WARN(priv, "uCode did not respond OK.\n");
b481de9c
ZY
558}
559
5b9f8cd3 560static void iwl_bg_beacon_update(struct work_struct *work)
b481de9c 561{
c79dd5b5
TW
562 struct iwl_priv *priv =
563 container_of(work, struct iwl_priv, beacon_update);
b481de9c
ZY
564 struct sk_buff *beacon;
565
566 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
e039fa4a 567 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
b481de9c
ZY
568
569 if (!beacon) {
15b1687c 570 IWL_ERR(priv, "update beacon failed\n");
b481de9c
ZY
571 return;
572 }
573
574 mutex_lock(&priv->mutex);
575 /* new beacon skb is allocated every time; dispose previous.*/
576 if (priv->ibss_beacon)
577 dev_kfree_skb(priv->ibss_beacon);
578
579 priv->ibss_beacon = beacon;
580 mutex_unlock(&priv->mutex);
581
5b9f8cd3 582 iwl_send_beacon_cmd(priv);
b481de9c
ZY
583}
584
4e39317d 585/**
5b9f8cd3 586 * iwl_bg_statistics_periodic - Timer callback to queue statistics
4e39317d
EG
587 *
588 * This callback is provided in order to send a statistics request.
589 *
590 * This timer function is continually reset to execute within
591 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
592 * was received. We need to ensure we receive the statistics in order
593 * to update the temperature used for calibrating the TXPOWER.
594 */
5b9f8cd3 595static void iwl_bg_statistics_periodic(unsigned long data)
4e39317d
EG
596{
597 struct iwl_priv *priv = (struct iwl_priv *)data;
598
599 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
600 return;
601
61780ee3
MA
602 /* dont send host command if rf-kill is on */
603 if (!iwl_is_ready_rf(priv))
604 return;
605
4e39317d
EG
606 iwl_send_statistics_request(priv, CMD_ASYNC);
607}
608
5b9f8cd3 609static void iwl_rx_beacon_notif(struct iwl_priv *priv,
a55360e4 610 struct iwl_rx_mem_buffer *rxb)
b481de9c 611{
0a6857e7 612#ifdef CONFIG_IWLWIFI_DEBUG
db11d634 613 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2aa6ab86
TW
614 struct iwl4965_beacon_notif *beacon =
615 (struct iwl4965_beacon_notif *)pkt->u.raw;
e7d326ac 616 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
b481de9c 617
e1623446 618 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
b481de9c 619 "tsf %d %d rate %d\n",
25a6572c 620 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
b481de9c
ZY
621 beacon->beacon_notify_hdr.failure_frame,
622 le32_to_cpu(beacon->ibss_mgr_status),
623 le32_to_cpu(beacon->high_tsf),
624 le32_to_cpu(beacon->low_tsf), rate);
625#endif
626
05c914fe 627 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
b481de9c
ZY
628 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
629 queue_work(priv->workqueue, &priv->beacon_update);
630}
631
b481de9c
ZY
632/* Handle notification from uCode that card's power state is changing
633 * due to software, hardware, or critical temperature RFKILL */
5b9f8cd3 634static void iwl_rx_card_state_notif(struct iwl_priv *priv,
a55360e4 635 struct iwl_rx_mem_buffer *rxb)
b481de9c 636{
db11d634 637 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
638 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
639 unsigned long status = priv->status;
640
e1623446 641 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
b481de9c
ZY
642 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
643 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
644
645 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
646 RF_CARD_DISABLED)) {
647
3395f6e9 648 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
b481de9c
ZY
649 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
650
a8b50a0a
MA
651 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
652 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c
ZY
653
654 if (!(flags & RXON_CARD_DISABLED)) {
3395f6e9 655 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c 656 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
a8b50a0a 657 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
b481de9c 658 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
b481de9c 659 }
39b73fb1
WYG
660 if (flags & RF_CARD_DISABLED)
661 iwl_tt_enter_ct_kill(priv);
b481de9c 662 }
39b73fb1
WYG
663 if (!(flags & RF_CARD_DISABLED))
664 iwl_tt_exit_ct_kill(priv);
b481de9c
ZY
665
666 if (flags & HW_CARD_DISABLED)
667 set_bit(STATUS_RF_KILL_HW, &priv->status);
668 else
669 clear_bit(STATUS_RF_KILL_HW, &priv->status);
670
671
b481de9c 672 if (!(flags & RXON_CARD_DISABLED))
2a421b91 673 iwl_scan_cancel(priv);
b481de9c
ZY
674
675 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
a60e77e5
JB
676 test_bit(STATUS_RF_KILL_HW, &priv->status)))
677 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
678 test_bit(STATUS_RF_KILL_HW, &priv->status));
b481de9c
ZY
679 else
680 wake_up_interruptible(&priv->wait_command_queue);
681}
682
5b9f8cd3 683int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
e2e3c57b 684{
e2e3c57b 685 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 686 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
e2e3c57b
TW
687 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
688 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
689 ~APMG_PS_CTRL_MSK_PWR_SRC);
690 } else {
691 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
692 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
693 ~APMG_PS_CTRL_MSK_PWR_SRC);
694 }
695
a8b50a0a 696 return 0;
e2e3c57b
TW
697}
698
b481de9c 699/**
5b9f8cd3 700 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
b481de9c
ZY
701 *
702 * Setup the RX handlers for each of the reply types sent from the uCode
703 * to the host.
704 *
705 * This function chains into the hardware specific files for them to setup
706 * any hardware specific handlers as well.
707 */
653fa4a0 708static void iwl_setup_rx_handlers(struct iwl_priv *priv)
b481de9c 709{
885ba202 710 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
5b9f8cd3
EG
711 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
712 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
5b9f8cd3 713 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
b481de9c 714 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
5b9f8cd3
EG
715 iwl_rx_pm_debug_statistics_notif;
716 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
b481de9c 717
9fbab516
BC
718 /*
719 * The same handler is used for both the REPLY to a discrete
720 * statistics request from the host as well as for the periodic
721 * statistics notifications (after received beacons) from the uCode.
b481de9c 722 */
8f91aecb
EG
723 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
724 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
2a421b91 725
21c339bf 726 iwl_setup_spectrum_handlers(priv);
2a421b91
TW
727 iwl_setup_rx_scan_handlers(priv);
728
37a44211 729 /* status change handler */
5b9f8cd3 730 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
b481de9c 731
c1354754
TW
732 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
733 iwl_rx_missed_beacon_notif;
37a44211 734 /* Rx handlers */
1781a07f
EG
735 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
736 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
653fa4a0
EG
737 /* block ack */
738 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
9fbab516 739 /* Set up hardware specific Rx handlers */
d4789efe 740 priv->cfg->ops->lib->rx_handler_setup(priv);
b481de9c
ZY
741}
742
b481de9c 743/**
a55360e4 744 * iwl_rx_handle - Main entry function for receiving responses from uCode
b481de9c
ZY
745 *
746 * Uses the priv->rx_handlers callback function array to invoke
747 * the appropriate handlers, including command responses,
748 * frame-received notifications, and other notifications.
749 */
a55360e4 750void iwl_rx_handle(struct iwl_priv *priv)
b481de9c 751{
a55360e4 752 struct iwl_rx_mem_buffer *rxb;
db11d634 753 struct iwl_rx_packet *pkt;
a55360e4 754 struct iwl_rx_queue *rxq = &priv->rxq;
b481de9c
ZY
755 u32 r, i;
756 int reclaim;
757 unsigned long flags;
5c0eef96 758 u8 fill_rx = 0;
d68ab680 759 u32 count = 8;
4752c93c 760 int total_empty;
b481de9c 761
6440adb5
BC
762 /* uCode's read index (stored in shared DRAM) indicates the last Rx
763 * buffer that the driver may process (last buffer filled by ucode). */
8d86422a 764 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
b481de9c
ZY
765 i = rxq->read;
766
767 /* Rx interrupt, but nothing sent from uCode */
768 if (i == r)
e1623446 769 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
b481de9c 770
4752c93c
MA
771 /* calculate total frames need to be restock after handling RX */
772 total_empty = r - priv->rxq.write_actual;
773 if (total_empty < 0)
774 total_empty += RX_QUEUE_SIZE;
775
776 if (total_empty > (RX_QUEUE_SIZE / 2))
5c0eef96
MA
777 fill_rx = 1;
778
b481de9c
ZY
779 while (i != r) {
780 rxb = rxq->queue[i];
781
9fbab516 782 /* If an RXB doesn't have a Rx queue slot associated with it,
b481de9c
ZY
783 * then a bug has been introduced in the queue refilling
784 * routines -- catch it here */
785 BUG_ON(rxb == NULL);
786
787 rxq->queue[i] = NULL;
788
df833b1d
RC
789 pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
790 priv->hw_params.rx_buf_size + 256,
791 PCI_DMA_FROMDEVICE);
db11d634 792 pkt = (struct iwl_rx_packet *)rxb->skb->data;
b481de9c
ZY
793
794 /* Reclaim a command buffer only if this packet is a response
795 * to a (driver-originated) command.
796 * If the packet (e.g. Rx frame) originated from uCode,
797 * there is no command buffer to reclaim.
798 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
799 * but apparently a few don't get set; catch them here. */
800 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
801 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
857485c0 802 (pkt->hdr.cmd != REPLY_RX) &&
7dddaf1a 803 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
cfe01709 804 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
b481de9c
ZY
805 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
806 (pkt->hdr.cmd != REPLY_TX);
807
808 /* Based on type of command response or notification,
809 * handle those that need handling via function in
5b9f8cd3 810 * rx_handlers table. See iwl_setup_rx_handlers() */
b481de9c 811 if (priv->rx_handlers[pkt->hdr.cmd]) {
e1623446 812 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
f3d67999 813 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
b481de9c 814 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
a83b9141 815 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
b481de9c
ZY
816 } else {
817 /* No handling needed */
e1623446 818 IWL_DEBUG_RX(priv,
b481de9c
ZY
819 "r %d i %d No handler needed for %s, 0x%02x\n",
820 r, i, get_cmd_string(pkt->hdr.cmd),
821 pkt->hdr.cmd);
822 }
823
824 if (reclaim) {
9fbab516 825 /* Invoke any callbacks, transfer the skb to caller, and
857485c0 826 * fire off the (possibly) blocking iwl_send_cmd()
b481de9c
ZY
827 * as we reclaim the driver command queue */
828 if (rxb && rxb->skb)
17b88929 829 iwl_tx_cmd_complete(priv, rxb);
b481de9c 830 else
39aadf8c 831 IWL_WARN(priv, "Claim null rxb?\n");
b481de9c
ZY
832 }
833
834 /* For now we just don't re-use anything. We can tweak this
835 * later to try and re-use notification packets and SKBs that
836 * fail to Rx correctly */
837 if (rxb->skb != NULL) {
838 priv->alloc_rxb_skb--;
839 dev_kfree_skb_any(rxb->skb);
840 rxb->skb = NULL;
841 }
842
b481de9c
ZY
843 spin_lock_irqsave(&rxq->lock, flags);
844 list_add_tail(&rxb->list, &priv->rxq.rx_used);
845 spin_unlock_irqrestore(&rxq->lock, flags);
846 i = (i + 1) & RX_QUEUE_MASK;
5c0eef96
MA
847 /* If there are a lot of unused frames,
848 * restock the Rx queue so ucode wont assert. */
849 if (fill_rx) {
850 count++;
851 if (count >= 8) {
852 priv->rxq.read = i;
4752c93c 853 iwl_rx_replenish_now(priv);
5c0eef96
MA
854 count = 0;
855 }
856 }
b481de9c
ZY
857 }
858
859 /* Backtrack one entry */
860 priv->rxq.read = i;
4752c93c
MA
861 if (fill_rx)
862 iwl_rx_replenish_now(priv);
863 else
864 iwl_rx_queue_restock(priv);
a55360e4 865}
a55360e4 866
0359facc
MA
867/* call this function to flush any scheduled tasklet */
868static inline void iwl_synchronize_irq(struct iwl_priv *priv)
869{
a96a27f9 870 /* wait to make sure we flush pending tasklet*/
0359facc
MA
871 synchronize_irq(priv->pci_dev->irq);
872 tasklet_kill(&priv->irq_tasklet);
873}
874
ef850d7c 875static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
b481de9c
ZY
876{
877 u32 inta, handled = 0;
878 u32 inta_fh;
879 unsigned long flags;
0a6857e7 880#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
881 u32 inta_mask;
882#endif
883
884 spin_lock_irqsave(&priv->lock, flags);
885
886 /* Ack/clear/reset pending uCode interrupts.
887 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
888 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
3395f6e9
TW
889 inta = iwl_read32(priv, CSR_INT);
890 iwl_write32(priv, CSR_INT, inta);
b481de9c
ZY
891
892 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
893 * Any new interrupts that happen after this, either while we're
894 * in this tasklet, or later, will show up in next ISR/tasklet. */
3395f6e9
TW
895 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
896 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
b481de9c 897
0a6857e7 898#ifdef CONFIG_IWLWIFI_DEBUG
a562a9dd 899 if (iwl_debug_level & IWL_DL_ISR) {
9fbab516 900 /* just for debug */
3395f6e9 901 inta_mask = iwl_read32(priv, CSR_INT_MASK);
e1623446 902 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
b481de9c
ZY
903 inta, inta_mask, inta_fh);
904 }
905#endif
906
907 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
908 * atomic, make sure that inta covers all the interrupts that
909 * we've discovered, even if FH interrupt came in just after
910 * reading CSR_INT. */
6f83eaa1 911 if (inta_fh & CSR49_FH_INT_RX_MASK)
b481de9c 912 inta |= CSR_INT_BIT_FH_RX;
6f83eaa1 913 if (inta_fh & CSR49_FH_INT_TX_MASK)
b481de9c
ZY
914 inta |= CSR_INT_BIT_FH_TX;
915
916 /* Now service all interrupt bits discovered above. */
917 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 918 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
b481de9c
ZY
919
920 /* Tell the device to stop sending interrupts */
5b9f8cd3 921 iwl_disable_interrupts(priv);
b481de9c 922
a83b9141 923 priv->isr_stats.hw++;
5b9f8cd3 924 iwl_irq_handle_error(priv);
b481de9c
ZY
925
926 handled |= CSR_INT_BIT_HW_ERR;
927
928 spin_unlock_irqrestore(&priv->lock, flags);
929
930 return;
931 }
932
0a6857e7 933#ifdef CONFIG_IWLWIFI_DEBUG
a562a9dd 934 if (iwl_debug_level & (IWL_DL_ISR)) {
b481de9c 935 /* NIC fires this, but we don't use it, redundant with WAKEUP */
a83b9141 936 if (inta & CSR_INT_BIT_SCD) {
e1623446 937 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
25c03d8e 938 "the frame/frames.\n");
a83b9141
WYG
939 priv->isr_stats.sch++;
940 }
b481de9c
ZY
941
942 /* Alive notification via Rx interrupt will do the real work */
a83b9141 943 if (inta & CSR_INT_BIT_ALIVE) {
e1623446 944 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
a83b9141
WYG
945 priv->isr_stats.alive++;
946 }
b481de9c
ZY
947 }
948#endif
949 /* Safely ignore these bits for debug checks below */
25c03d8e 950 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
b481de9c 951
9fbab516 952 /* HW RF KILL switch toggled */
b481de9c
ZY
953 if (inta & CSR_INT_BIT_RF_KILL) {
954 int hw_rf_kill = 0;
3395f6e9 955 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
b481de9c
ZY
956 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
957 hw_rf_kill = 1;
958
4c423a2b 959 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
c3056065 960 hw_rf_kill ? "disable radio" : "enable radio");
b481de9c 961
a83b9141
WYG
962 priv->isr_stats.rfkill++;
963
a9efa652 964 /* driver only loads ucode once setting the interface up.
6cd0b1cb
HS
965 * the driver allows loading the ucode even if the radio
966 * is killed. Hence update the killswitch state here. The
967 * rfkill handler will care about restarting if needed.
a9efa652 968 */
6cd0b1cb
HS
969 if (!test_bit(STATUS_ALIVE, &priv->status)) {
970 if (hw_rf_kill)
971 set_bit(STATUS_RF_KILL_HW, &priv->status);
972 else
973 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 974 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
edb34228 975 }
b481de9c
ZY
976
977 handled |= CSR_INT_BIT_RF_KILL;
978 }
979
9fbab516 980 /* Chip got too hot and stopped itself */
b481de9c 981 if (inta & CSR_INT_BIT_CT_KILL) {
15b1687c 982 IWL_ERR(priv, "Microcode CT kill error detected.\n");
a83b9141 983 priv->isr_stats.ctkill++;
b481de9c
ZY
984 handled |= CSR_INT_BIT_CT_KILL;
985 }
986
987 /* Error detected by uCode */
988 if (inta & CSR_INT_BIT_SW_ERR) {
15b1687c
WT
989 IWL_ERR(priv, "Microcode SW error detected. "
990 " Restarting 0x%X.\n", inta);
a83b9141
WYG
991 priv->isr_stats.sw++;
992 priv->isr_stats.sw_err = inta;
5b9f8cd3 993 iwl_irq_handle_error(priv);
b481de9c
ZY
994 handled |= CSR_INT_BIT_SW_ERR;
995 }
996
997 /* uCode wakes up after power-down sleep */
998 if (inta & CSR_INT_BIT_WAKEUP) {
e1623446 999 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
a55360e4 1000 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
babcebfa
TW
1001 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1002 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1003 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1004 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1005 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1006 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
b481de9c 1007
a83b9141
WYG
1008 priv->isr_stats.wakeup++;
1009
b481de9c
ZY
1010 handled |= CSR_INT_BIT_WAKEUP;
1011 }
1012
1013 /* All uCode command responses, including Tx command responses,
1014 * Rx "responses" (frame-received notification), and other
1015 * notifications from uCode come through here*/
1016 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
a55360e4 1017 iwl_rx_handle(priv);
a83b9141 1018 priv->isr_stats.rx++;
b481de9c
ZY
1019 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1020 }
1021
1022 if (inta & CSR_INT_BIT_FH_TX) {
e1623446 1023 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
a83b9141 1024 priv->isr_stats.tx++;
b481de9c 1025 handled |= CSR_INT_BIT_FH_TX;
dbb983b7
RR
1026 /* FH finished to write, send event */
1027 priv->ucode_write_complete = 1;
1028 wake_up_interruptible(&priv->wait_command_queue);
b481de9c
ZY
1029 }
1030
a83b9141 1031 if (inta & ~handled) {
15b1687c 1032 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
a83b9141
WYG
1033 priv->isr_stats.unhandled++;
1034 }
b481de9c 1035
40cefda9 1036 if (inta & ~(priv->inta_mask)) {
39aadf8c 1037 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1038 inta & ~priv->inta_mask);
39aadf8c 1039 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
b481de9c
ZY
1040 }
1041
1042 /* Re-enable all interrupts */
0359facc
MA
1043 /* only Re-enable if diabled by irq */
1044 if (test_bit(STATUS_INT_ENABLED, &priv->status))
5b9f8cd3 1045 iwl_enable_interrupts(priv);
b481de9c 1046
0a6857e7 1047#ifdef CONFIG_IWLWIFI_DEBUG
a562a9dd 1048 if (iwl_debug_level & (IWL_DL_ISR)) {
3395f6e9
TW
1049 inta = iwl_read32(priv, CSR_INT);
1050 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1051 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
e1623446 1052 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
b481de9c
ZY
1053 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1054 }
1055#endif
1056 spin_unlock_irqrestore(&priv->lock, flags);
1057}
1058
ef850d7c
MA
1059/* tasklet for iwlagn interrupt */
1060static void iwl_irq_tasklet(struct iwl_priv *priv)
1061{
1062 u32 inta = 0;
1063 u32 handled = 0;
1064 unsigned long flags;
1065#ifdef CONFIG_IWLWIFI_DEBUG
1066 u32 inta_mask;
1067#endif
1068
1069 spin_lock_irqsave(&priv->lock, flags);
1070
1071 /* Ack/clear/reset pending uCode interrupts.
1072 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1073 */
1074 iwl_write32(priv, CSR_INT, priv->inta);
1075
1076 inta = priv->inta;
1077
1078#ifdef CONFIG_IWLWIFI_DEBUG
a562a9dd 1079 if (iwl_debug_level & IWL_DL_ISR) {
ef850d7c
MA
1080 /* just for debug */
1081 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1082 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1083 inta, inta_mask);
1084 }
1085#endif
1086 /* saved interrupt in inta variable now we can reset priv->inta */
1087 priv->inta = 0;
1088
1089 /* Now service all interrupt bits discovered above. */
1090 if (inta & CSR_INT_BIT_HW_ERR) {
58dba728 1091 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
ef850d7c
MA
1092
1093 /* Tell the device to stop sending interrupts */
1094 iwl_disable_interrupts(priv);
1095
1096 priv->isr_stats.hw++;
1097 iwl_irq_handle_error(priv);
1098
1099 handled |= CSR_INT_BIT_HW_ERR;
1100
1101 spin_unlock_irqrestore(&priv->lock, flags);
1102
1103 return;
1104 }
1105
1106#ifdef CONFIG_IWLWIFI_DEBUG
a562a9dd 1107 if (iwl_debug_level & (IWL_DL_ISR)) {
ef850d7c
MA
1108 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1109 if (inta & CSR_INT_BIT_SCD) {
1110 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1111 "the frame/frames.\n");
1112 priv->isr_stats.sch++;
1113 }
1114
1115 /* Alive notification via Rx interrupt will do the real work */
1116 if (inta & CSR_INT_BIT_ALIVE) {
1117 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1118 priv->isr_stats.alive++;
1119 }
1120 }
1121#endif
1122 /* Safely ignore these bits for debug checks below */
1123 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1124
1125 /* HW RF KILL switch toggled */
1126 if (inta & CSR_INT_BIT_RF_KILL) {
1127 int hw_rf_kill = 0;
1128 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1129 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1130 hw_rf_kill = 1;
1131
4c423a2b 1132 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
ef850d7c
MA
1133 hw_rf_kill ? "disable radio" : "enable radio");
1134
1135 priv->isr_stats.rfkill++;
1136
1137 /* driver only loads ucode once setting the interface up.
1138 * the driver allows loading the ucode even if the radio
1139 * is killed. Hence update the killswitch state here. The
1140 * rfkill handler will care about restarting if needed.
1141 */
1142 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1143 if (hw_rf_kill)
1144 set_bit(STATUS_RF_KILL_HW, &priv->status);
1145 else
1146 clear_bit(STATUS_RF_KILL_HW, &priv->status);
a60e77e5 1147 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
ef850d7c
MA
1148 }
1149
1150 handled |= CSR_INT_BIT_RF_KILL;
1151 }
1152
1153 /* Chip got too hot and stopped itself */
1154 if (inta & CSR_INT_BIT_CT_KILL) {
1155 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1156 priv->isr_stats.ctkill++;
1157 handled |= CSR_INT_BIT_CT_KILL;
1158 }
1159
1160 /* Error detected by uCode */
1161 if (inta & CSR_INT_BIT_SW_ERR) {
1162 IWL_ERR(priv, "Microcode SW error detected. "
1163 " Restarting 0x%X.\n", inta);
1164 priv->isr_stats.sw++;
1165 priv->isr_stats.sw_err = inta;
1166 iwl_irq_handle_error(priv);
1167 handled |= CSR_INT_BIT_SW_ERR;
1168 }
1169
1170 /* uCode wakes up after power-down sleep */
1171 if (inta & CSR_INT_BIT_WAKEUP) {
1172 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1173 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1174 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1175 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1176 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1177 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1178 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1179 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1180
1181 priv->isr_stats.wakeup++;
1182
1183 handled |= CSR_INT_BIT_WAKEUP;
1184 }
1185
1186 /* All uCode command responses, including Tx command responses,
1187 * Rx "responses" (frame-received notification), and other
1188 * notifications from uCode come through here*/
40cefda9
MA
1189 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1190 CSR_INT_BIT_RX_PERIODIC)) {
ef850d7c 1191 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
40cefda9
MA
1192 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1193 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1194 iwl_write32(priv, CSR_FH_INT_STATUS,
1195 CSR49_FH_INT_RX_MASK);
1196 }
1197 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1198 handled |= CSR_INT_BIT_RX_PERIODIC;
1199 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1200 }
1201 /* Sending RX interrupt require many steps to be done in the
1202 * the device:
1203 * 1- write interrupt to current index in ICT table.
1204 * 2- dma RX frame.
1205 * 3- update RX shared data to indicate last write index.
1206 * 4- send interrupt.
1207 * This could lead to RX race, driver could receive RX interrupt
1208 * but the shared data changes does not reflect this.
1209 * this could lead to RX race, RX periodic will solve this race
1210 */
1211 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1212 CSR_INT_PERIODIC_DIS);
ef850d7c 1213 iwl_rx_handle(priv);
40cefda9
MA
1214 /* Only set RX periodic if real RX is received. */
1215 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1216 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1217 CSR_INT_PERIODIC_ENA);
1218
ef850d7c 1219 priv->isr_stats.rx++;
ef850d7c
MA
1220 }
1221
1222 if (inta & CSR_INT_BIT_FH_TX) {
1223 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1224 IWL_DEBUG_ISR(priv, "Tx interrupt\n");
1225 priv->isr_stats.tx++;
1226 handled |= CSR_INT_BIT_FH_TX;
1227 /* FH finished to write, send event */
1228 priv->ucode_write_complete = 1;
1229 wake_up_interruptible(&priv->wait_command_queue);
1230 }
1231
1232 if (inta & ~handled) {
1233 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1234 priv->isr_stats.unhandled++;
1235 }
1236
40cefda9 1237 if (inta & ~(priv->inta_mask)) {
ef850d7c 1238 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
40cefda9 1239 inta & ~priv->inta_mask);
ef850d7c
MA
1240 }
1241
1242
1243 /* Re-enable all interrupts */
1244 /* only Re-enable if diabled by irq */
1245 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1246 iwl_enable_interrupts(priv);
1247
1248 spin_unlock_irqrestore(&priv->lock, flags);
1249
1250}
1251
a83b9141 1252
b481de9c
ZY
1253/******************************************************************************
1254 *
1255 * uCode download functions
1256 *
1257 ******************************************************************************/
1258
5b9f8cd3 1259static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
b481de9c 1260{
98c92211
TW
1261 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1262 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1263 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1264 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1265 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1266 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c
ZY
1267}
1268
5b9f8cd3 1269static void iwl_nic_start(struct iwl_priv *priv)
edcdf8b2
RR
1270{
1271 /* Remove all resets to allow NIC to operate */
1272 iwl_write32(priv, CSR_RESET, 0);
1273}
1274
1275
b481de9c 1276/**
5b9f8cd3 1277 * iwl_read_ucode - Read uCode images from disk file.
b481de9c
ZY
1278 *
1279 * Copy into buffers for card to fetch via bus-mastering
1280 */
5b9f8cd3 1281static int iwl_read_ucode(struct iwl_priv *priv)
b481de9c 1282{
cc0f555d 1283 struct iwl_ucode_header *ucode;
a0987a8d 1284 int ret = -EINVAL, index;
b481de9c 1285 const struct firmware *ucode_raw;
a0987a8d
RC
1286 const char *name_pre = priv->cfg->fw_name_pre;
1287 const unsigned int api_max = priv->cfg->ucode_api_max;
1288 const unsigned int api_min = priv->cfg->ucode_api_min;
1289 char buf[25];
b481de9c
ZY
1290 u8 *src;
1291 size_t len;
cc0f555d
JS
1292 u32 api_ver, build;
1293 u32 inst_size, data_size, init_size, init_data_size, boot_size;
b481de9c
ZY
1294
1295 /* Ask kernel firmware_class module to get the boot firmware off disk.
1296 * request_firmware() is synchronous, file is in memory on return. */
a0987a8d
RC
1297 for (index = api_max; index >= api_min; index--) {
1298 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1299 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1300 if (ret < 0) {
15b1687c 1301 IWL_ERR(priv, "%s firmware file req failed: %d\n",
a0987a8d
RC
1302 buf, ret);
1303 if (ret == -ENOENT)
1304 continue;
1305 else
1306 goto error;
1307 } else {
1308 if (index < api_max)
15b1687c
WT
1309 IWL_ERR(priv, "Loaded firmware %s, "
1310 "which is deprecated. "
1311 "Please use API v%u instead.\n",
a0987a8d 1312 buf, api_max);
15b1687c 1313
e1623446 1314 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
a0987a8d
RC
1315 buf, ucode_raw->size);
1316 break;
1317 }
b481de9c
ZY
1318 }
1319
a0987a8d
RC
1320 if (ret < 0)
1321 goto error;
b481de9c 1322
cc0f555d
JS
1323 /* Make sure that we got at least the v1 header! */
1324 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
15b1687c 1325 IWL_ERR(priv, "File size way too small!\n");
90e759d1 1326 ret = -EINVAL;
b481de9c
ZY
1327 goto err_release;
1328 }
1329
1330 /* Data from ucode file: header followed by uCode images */
cc0f555d 1331 ucode = (struct iwl_ucode_header *)ucode_raw->data;
b481de9c 1332
c02b3acd 1333 priv->ucode_ver = le32_to_cpu(ucode->ver);
a0987a8d 1334 api_ver = IWL_UCODE_API(priv->ucode_ver);
cc0f555d
JS
1335 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1336 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1337 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1338 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1339 init_data_size =
1340 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1341 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1342 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
b481de9c 1343
a0987a8d
RC
1344 /* api_ver should match the api version forming part of the
1345 * firmware filename ... but we don't check for that and only rely
877d0310 1346 * on the API version read from firmware header from here on forward */
a0987a8d
RC
1347
1348 if (api_ver < api_min || api_ver > api_max) {
15b1687c 1349 IWL_ERR(priv, "Driver unable to support your firmware API. "
a0987a8d
RC
1350 "Driver supports v%u, firmware is v%u.\n",
1351 api_max, api_ver);
1352 priv->ucode_ver = 0;
1353 ret = -EINVAL;
1354 goto err_release;
1355 }
1356 if (api_ver != api_max)
978785a3 1357 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
a0987a8d
RC
1358 "got v%u. New firmware can be obtained "
1359 "from http://www.intellinuxwireless.org.\n",
1360 api_max, api_ver);
1361
978785a3
TW
1362 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1363 IWL_UCODE_MAJOR(priv->ucode_ver),
1364 IWL_UCODE_MINOR(priv->ucode_ver),
1365 IWL_UCODE_API(priv->ucode_ver),
1366 IWL_UCODE_SERIAL(priv->ucode_ver));
a0987a8d 1367
cc0f555d
JS
1368 if (build)
1369 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1370
e1623446 1371 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
a0987a8d 1372 priv->ucode_ver);
e1623446 1373 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
b481de9c 1374 inst_size);
e1623446 1375 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
b481de9c 1376 data_size);
e1623446 1377 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
b481de9c 1378 init_size);
e1623446 1379 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
b481de9c 1380 init_data_size);
e1623446 1381 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
b481de9c
ZY
1382 boot_size);
1383
1384 /* Verify size of file vs. image size info in file's header */
cc0f555d
JS
1385 if (ucode_raw->size !=
1386 priv->cfg->ops->ucode->get_header_size(api_ver) +
b481de9c
ZY
1387 inst_size + data_size + init_size +
1388 init_data_size + boot_size) {
1389
cc0f555d
JS
1390 IWL_DEBUG_INFO(priv,
1391 "uCode file size %d does not match expected size\n",
1392 (int)ucode_raw->size);
90e759d1 1393 ret = -EINVAL;
b481de9c
ZY
1394 goto err_release;
1395 }
1396
1397 /* Verify that uCode images will fit in card's SRAM */
099b40b7 1398 if (inst_size > priv->hw_params.max_inst_size) {
e1623446 1399 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
90e759d1
TW
1400 inst_size);
1401 ret = -EINVAL;
b481de9c
ZY
1402 goto err_release;
1403 }
1404
099b40b7 1405 if (data_size > priv->hw_params.max_data_size) {
e1623446 1406 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
90e759d1
TW
1407 data_size);
1408 ret = -EINVAL;
b481de9c
ZY
1409 goto err_release;
1410 }
099b40b7 1411 if (init_size > priv->hw_params.max_inst_size) {
e1623446
TW
1412 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1413 init_size);
90e759d1 1414 ret = -EINVAL;
b481de9c
ZY
1415 goto err_release;
1416 }
099b40b7 1417 if (init_data_size > priv->hw_params.max_data_size) {
e1623446 1418 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
90e759d1
TW
1419 init_data_size);
1420 ret = -EINVAL;
b481de9c
ZY
1421 goto err_release;
1422 }
099b40b7 1423 if (boot_size > priv->hw_params.max_bsm_size) {
e1623446
TW
1424 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1425 boot_size);
90e759d1 1426 ret = -EINVAL;
b481de9c
ZY
1427 goto err_release;
1428 }
1429
1430 /* Allocate ucode buffers for card's bus-master loading ... */
1431
1432 /* Runtime instructions and 2 copies of data:
1433 * 1) unmodified from disk
1434 * 2) backup cache for save/restore during power-downs */
1435 priv->ucode_code.len = inst_size;
98c92211 1436 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
b481de9c
ZY
1437
1438 priv->ucode_data.len = data_size;
98c92211 1439 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
b481de9c
ZY
1440
1441 priv->ucode_data_backup.len = data_size;
98c92211 1442 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
b481de9c 1443
1f304e4e
ZY
1444 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1445 !priv->ucode_data_backup.v_addr)
1446 goto err_pci_alloc;
1447
b481de9c 1448 /* Initialization instructions and data */
90e759d1
TW
1449 if (init_size && init_data_size) {
1450 priv->ucode_init.len = init_size;
98c92211 1451 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
90e759d1
TW
1452
1453 priv->ucode_init_data.len = init_data_size;
98c92211 1454 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
90e759d1
TW
1455
1456 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1457 goto err_pci_alloc;
1458 }
b481de9c
ZY
1459
1460 /* Bootstrap (instructions only, no data) */
90e759d1
TW
1461 if (boot_size) {
1462 priv->ucode_boot.len = boot_size;
98c92211 1463 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
b481de9c 1464
90e759d1
TW
1465 if (!priv->ucode_boot.v_addr)
1466 goto err_pci_alloc;
1467 }
b481de9c
ZY
1468
1469 /* Copy images into buffers for card's bus-master reads ... */
1470
1471 /* Runtime instructions (first block of data in file) */
cc0f555d 1472 len = inst_size;
e1623446 1473 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
b481de9c 1474 memcpy(priv->ucode_code.v_addr, src, len);
cc0f555d
JS
1475 src += len;
1476
e1623446 1477 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
b481de9c
ZY
1478 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1479
1480 /* Runtime data (2nd block)
5b9f8cd3 1481 * NOTE: Copy into backup buffer will be done in iwl_up() */
cc0f555d 1482 len = data_size;
e1623446 1483 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
b481de9c
ZY
1484 memcpy(priv->ucode_data.v_addr, src, len);
1485 memcpy(priv->ucode_data_backup.v_addr, src, len);
cc0f555d 1486 src += len;
b481de9c
ZY
1487
1488 /* Initialization instructions (3rd block) */
1489 if (init_size) {
cc0f555d 1490 len = init_size;
e1623446 1491 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
90e759d1 1492 len);
b481de9c 1493 memcpy(priv->ucode_init.v_addr, src, len);
cc0f555d 1494 src += len;
b481de9c
ZY
1495 }
1496
1497 /* Initialization data (4th block) */
1498 if (init_data_size) {
cc0f555d 1499 len = init_data_size;
e1623446 1500 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
90e759d1 1501 len);
b481de9c 1502 memcpy(priv->ucode_init_data.v_addr, src, len);
cc0f555d 1503 src += len;
b481de9c
ZY
1504 }
1505
1506 /* Bootstrap instructions (5th block) */
cc0f555d 1507 len = boot_size;
e1623446 1508 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
b481de9c
ZY
1509 memcpy(priv->ucode_boot.v_addr, src, len);
1510
1511 /* We have our copies now, allow OS release its copies */
1512 release_firmware(ucode_raw);
1513 return 0;
1514
1515 err_pci_alloc:
15b1687c 1516 IWL_ERR(priv, "failed to allocate pci memory\n");
90e759d1 1517 ret = -ENOMEM;
5b9f8cd3 1518 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
1519
1520 err_release:
1521 release_firmware(ucode_raw);
1522
1523 error:
90e759d1 1524 return ret;
b481de9c
ZY
1525}
1526
b481de9c 1527/**
4a4a9e81 1528 * iwl_alive_start - called after REPLY_ALIVE notification received
b481de9c 1529 * from protocol/runtime uCode (initialization uCode's
4a4a9e81 1530 * Alive gets handled by iwl_init_alive_start()).
b481de9c 1531 */
4a4a9e81 1532static void iwl_alive_start(struct iwl_priv *priv)
b481de9c 1533{
57aab75a 1534 int ret = 0;
b481de9c 1535
e1623446 1536 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
b481de9c
ZY
1537
1538 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1539 /* We had an error bringing up the hardware, so take it
1540 * all the way back down so we can try again */
e1623446 1541 IWL_DEBUG_INFO(priv, "Alive failed.\n");
b481de9c
ZY
1542 goto restart;
1543 }
1544
1545 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1546 * This is a paranoid check, because we would not have gotten the
1547 * "runtime" alive if code weren't properly loaded. */
b0692f2f 1548 if (iwl_verify_ucode(priv)) {
b481de9c
ZY
1549 /* Runtime instruction load was bad;
1550 * take it all the way back down so we can try again */
e1623446 1551 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
b481de9c
ZY
1552 goto restart;
1553 }
1554
c587de0b 1555 iwl_clear_stations_table(priv);
57aab75a
TW
1556 ret = priv->cfg->ops->lib->alive_notify(priv);
1557 if (ret) {
39aadf8c
WT
1558 IWL_WARN(priv,
1559 "Could not complete ALIVE transition [ntf]: %d\n", ret);
b481de9c
ZY
1560 goto restart;
1561 }
1562
5b9f8cd3 1563 /* After the ALIVE response, we can send host commands to the uCode */
b481de9c
ZY
1564 set_bit(STATUS_ALIVE, &priv->status);
1565
fee1247a 1566 if (iwl_is_rfkill(priv))
b481de9c
ZY
1567 return;
1568
36d6825b 1569 ieee80211_wake_queues(priv->hw);
b481de9c
ZY
1570
1571 priv->active_rate = priv->rates_mask;
1572 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1573
3109ece1 1574 if (iwl_is_associated(priv)) {
c1adf9fb
GG
1575 struct iwl_rxon_cmd *active_rxon =
1576 (struct iwl_rxon_cmd *)&priv->active_rxon;
019fb97d
MA
1577 /* apply any changes in staging */
1578 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
b481de9c
ZY
1579 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1580 } else {
1581 /* Initialize our rx_config data */
5b9f8cd3 1582 iwl_connection_init_rx_config(priv, priv->iw_mode);
45823531
AK
1583
1584 if (priv->cfg->ops->hcmd->set_rxon_chain)
1585 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1586
b481de9c
ZY
1587 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1588 }
1589
9fbab516 1590 /* Configure Bluetooth device coexistence support */
5b9f8cd3 1591 iwl_send_bt_config(priv);
b481de9c 1592
4a4a9e81
TW
1593 iwl_reset_run_time_calib(priv);
1594
b481de9c 1595 /* Configure the adapter for unassociated operation */
e0158e61 1596 iwlcore_commit_rxon(priv);
b481de9c
ZY
1597
1598 /* At this point, the NIC is initialized and operational */
47f4a587 1599 iwl_rf_kill_ct_config(priv);
5a66926a 1600
fe00b5a5
RC
1601 iwl_leds_register(priv);
1602
e1623446 1603 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
a9f46786 1604 set_bit(STATUS_READY, &priv->status);
5a66926a 1605 wake_up_interruptible(&priv->wait_command_queue);
b481de9c 1606
58d0f361 1607 iwl_power_update_mode(priv, 1);
c46fbefa 1608
ada17513
MA
1609 /* reassociate for ADHOC mode */
1610 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1611 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1612 priv->vif);
1613 if (beacon)
1614 iwl_mac_beacon_update(priv->hw, beacon);
1615 }
1616
1617
c46fbefa 1618 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
5b9f8cd3 1619 iwl_set_mode(priv, priv->iw_mode);
c46fbefa 1620
b481de9c
ZY
1621 return;
1622
1623 restart:
1624 queue_work(priv->workqueue, &priv->restart);
1625}
1626
4e39317d 1627static void iwl_cancel_deferred_work(struct iwl_priv *priv);
b481de9c 1628
5b9f8cd3 1629static void __iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1630{
1631 unsigned long flags;
1632 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c 1633
e1623446 1634 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
b481de9c 1635
b481de9c
ZY
1636 if (!exit_pending)
1637 set_bit(STATUS_EXIT_PENDING, &priv->status);
1638
ab53d8af
MA
1639 iwl_leds_unregister(priv);
1640
c587de0b 1641 iwl_clear_stations_table(priv);
b481de9c
ZY
1642
1643 /* Unblock any waiting calls */
1644 wake_up_interruptible_all(&priv->wait_command_queue);
1645
b481de9c
ZY
1646 /* Wipe out the EXIT_PENDING status bit if we are not actually
1647 * exiting the module */
1648 if (!exit_pending)
1649 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1650
1651 /* stop and reset the on-board processor */
3395f6e9 1652 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
b481de9c
ZY
1653
1654 /* tell the device to stop sending interrupts */
0359facc 1655 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 1656 iwl_disable_interrupts(priv);
0359facc
MA
1657 spin_unlock_irqrestore(&priv->lock, flags);
1658 iwl_synchronize_irq(priv);
b481de9c
ZY
1659
1660 if (priv->mac80211_registered)
1661 ieee80211_stop_queues(priv->hw);
1662
5b9f8cd3 1663 /* If we have not previously called iwl_init() then
a60e77e5 1664 * clear all bits but the RF Kill bit and return */
fee1247a 1665 if (!iwl_is_init(priv)) {
b481de9c
ZY
1666 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1667 STATUS_RF_KILL_HW |
9788864e
RC
1668 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1669 STATUS_GEO_CONFIGURED |
052ec3f1
MA
1670 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1671 STATUS_EXIT_PENDING;
b481de9c
ZY
1672 goto exit;
1673 }
1674
6da3a13e 1675 /* ...otherwise clear out all the status bits but the RF Kill
a60e77e5 1676 * bit and continue taking the NIC down. */
b481de9c
ZY
1677 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1678 STATUS_RF_KILL_HW |
9788864e
RC
1679 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1680 STATUS_GEO_CONFIGURED |
b481de9c 1681 test_bit(STATUS_FW_ERROR, &priv->status) <<
052ec3f1
MA
1682 STATUS_FW_ERROR |
1683 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1684 STATUS_EXIT_PENDING;
b481de9c 1685
ef850d7c
MA
1686 /* device going down, Stop using ICT table */
1687 iwl_disable_ict(priv);
b481de9c 1688 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1689 iwl_clear_bit(priv, CSR_GP_CNTRL,
9fbab516 1690 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
b481de9c
ZY
1691 spin_unlock_irqrestore(&priv->lock, flags);
1692
da1bc453 1693 iwl_txq_ctx_stop(priv);
b3bbacb7 1694 iwl_rxq_stop(priv);
b481de9c 1695
a8b50a0a
MA
1696 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1697 APMG_CLK_VAL_DMA_CLK_RQT);
b481de9c
ZY
1698
1699 udelay(5);
1700
7f066108 1701 /* FIXME: apm_ops.suspend(priv) */
6da3a13e 1702 if (exit_pending)
d535311e
GG
1703 priv->cfg->ops->lib->apm_ops.stop(priv);
1704 else
1705 priv->cfg->ops->lib->apm_ops.reset(priv);
b481de9c 1706 exit:
885ba202 1707 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
b481de9c
ZY
1708
1709 if (priv->ibss_beacon)
1710 dev_kfree_skb(priv->ibss_beacon);
1711 priv->ibss_beacon = NULL;
1712
1713 /* clear out any free frames */
fcab423d 1714 iwl_clear_free_frames(priv);
b481de9c
ZY
1715}
1716
5b9f8cd3 1717static void iwl_down(struct iwl_priv *priv)
b481de9c
ZY
1718{
1719 mutex_lock(&priv->mutex);
5b9f8cd3 1720 __iwl_down(priv);
b481de9c 1721 mutex_unlock(&priv->mutex);
b24d22b1 1722
4e39317d 1723 iwl_cancel_deferred_work(priv);
b481de9c
ZY
1724}
1725
086ed117
MA
1726#define HW_READY_TIMEOUT (50)
1727
1728static int iwl_set_hw_ready(struct iwl_priv *priv)
1729{
1730 int ret = 0;
1731
1732 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1733 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1734
1735 /* See if we got it */
1736 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1737 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1738 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1739 HW_READY_TIMEOUT);
1740 if (ret != -ETIMEDOUT)
1741 priv->hw_ready = true;
1742 else
1743 priv->hw_ready = false;
1744
1745 IWL_DEBUG_INFO(priv, "hardware %s\n",
1746 (priv->hw_ready == 1) ? "ready" : "not ready");
1747 return ret;
1748}
1749
1750static int iwl_prepare_card_hw(struct iwl_priv *priv)
1751{
1752 int ret = 0;
1753
1754 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1755
3354a0f6
MA
1756 ret = iwl_set_hw_ready(priv);
1757 if (priv->hw_ready)
1758 return ret;
1759
1760 /* If HW is not ready, prepare the conditions to check again */
086ed117
MA
1761 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1762 CSR_HW_IF_CONFIG_REG_PREPARE);
1763
1764 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1765 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1766 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1767
3354a0f6 1768 /* HW should be ready by now, check again. */
086ed117
MA
1769 if (ret != -ETIMEDOUT)
1770 iwl_set_hw_ready(priv);
1771
1772 return ret;
1773}
1774
b481de9c
ZY
1775#define MAX_HW_RESTARTS 5
1776
5b9f8cd3 1777static int __iwl_up(struct iwl_priv *priv)
b481de9c 1778{
57aab75a
TW
1779 int i;
1780 int ret;
34a66de6 1781 unsigned long status;
b481de9c
ZY
1782
1783 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
39aadf8c 1784 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
b481de9c
ZY
1785 return -EIO;
1786 }
1787
e903fbd4 1788 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
15b1687c 1789 IWL_ERR(priv, "ucode not available for device bringup\n");
e903fbd4
RC
1790 return -EIO;
1791 }
1792
086ed117
MA
1793 iwl_prepare_card_hw(priv);
1794
1795 if (!priv->hw_ready) {
1796 IWL_WARN(priv, "Exit HW not ready\n");
1797 return -EIO;
1798 }
1799
e655b9f0 1800 /* If platform's RF_KILL switch is NOT set to KILL */
c1842d61 1801 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
e655b9f0 1802 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1803 else
e655b9f0 1804 set_bit(STATUS_RF_KILL_HW, &priv->status);
3bff19c2 1805
c1842d61 1806 if (iwl_is_rfkill(priv)) {
a60e77e5
JB
1807 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
1808
5b9f8cd3 1809 iwl_enable_interrupts(priv);
a60e77e5 1810 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
c1842d61 1811 return 0;
b481de9c
ZY
1812 }
1813
3395f6e9 1814 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
b481de9c 1815
1053d35f 1816 ret = iwl_hw_nic_init(priv);
57aab75a 1817 if (ret) {
15b1687c 1818 IWL_ERR(priv, "Unable to init nic\n");
57aab75a 1819 return ret;
b481de9c
ZY
1820 }
1821
1822 /* make sure rfkill handshake bits are cleared */
3395f6e9
TW
1823 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1824 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY
1825 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1826
1827 /* clear (again), then enable host interrupts */
3395f6e9 1828 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
5b9f8cd3 1829 iwl_enable_interrupts(priv);
b481de9c
ZY
1830
1831 /* really make sure rfkill handshake bits are cleared */
3395f6e9
TW
1832 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1833 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
b481de9c
ZY
1834
1835 /* Copy original ucode data image from disk into backup cache.
1836 * This will be used to initialize the on-board processor's
1837 * data SRAM for a clean start when the runtime program first loads. */
1838 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
5a66926a 1839 priv->ucode_data.len);
b481de9c 1840
b481de9c
ZY
1841 for (i = 0; i < MAX_HW_RESTARTS; i++) {
1842
c587de0b 1843 iwl_clear_stations_table(priv);
b481de9c
ZY
1844
1845 /* load bootstrap state machine,
1846 * load bootstrap program into processor's memory,
1847 * prepare to load the "initialize" uCode */
57aab75a 1848 ret = priv->cfg->ops->lib->load_ucode(priv);
b481de9c 1849
57aab75a 1850 if (ret) {
15b1687c
WT
1851 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
1852 ret);
b481de9c
ZY
1853 continue;
1854 }
1855
1856 /* start card; "initialize" will load runtime ucode */
5b9f8cd3 1857 iwl_nic_start(priv);
b481de9c 1858
34a66de6
WYG
1859 /* Just finish download Init or Runtime uCode image to device
1860 * now we wait here for uCode send REPLY_ALIVE notification
1861 * to indicate uCode is ready.
1862 * 1) For Init uCode image, all iwlagn devices should wait here
1863 * on STATUS_INIT_UCODE_ALIVE status bit; if timeout before
1864 * receive the REPLY_ALIVE notification, go back and try to
1865 * download the Init uCode image again.
1866 * 2) For Runtime uCode image, all iwlagn devices except 4965
1867 * wait here on STATUS_RT_UCODE_ALIVE status bit; if
1868 * timeout before receive the REPLY_ALIVE notification, go back
1869 * and download the Runtime uCode image again.
1870 * 3) For 4965 Runtime uCode, it will not go through this path,
1871 * need to wait for STATUS_RT_UCODE_ALIVE status bit in
1872 * iwl4965_init_alive_start() function; if timeout, need to
1873 * restart and download Init uCode image.
1874 */
1875 if (priv->ucode_type == UCODE_INIT)
1876 status = STATUS_INIT_UCODE_ALIVE;
1877 else
1878 status = STATUS_RT_UCODE_ALIVE;
1879 if (test_bit(status, &priv->status)) {
1880 IWL_WARN(priv,
1881 "%s uCode already alive? "
1882 "Waiting for alive anyway\n",
1883 (status == STATUS_INIT_UCODE_ALIVE)
1884 ? "INIT" : "Runtime");
1885 clear_bit(status, &priv->status);
1886 }
1887 ret = wait_event_interruptible_timeout(
1888 priv->wait_command_queue,
1889 test_bit(status, &priv->status),
1890 UCODE_ALIVE_TIMEOUT);
1891 if (!ret) {
1892 if (!test_bit(status, &priv->status)) {
1893 priv->ucode_type =
1894 (status == STATUS_INIT_UCODE_ALIVE)
1895 ? UCODE_NONE : UCODE_INIT;
1896 IWL_ERR(priv,
1897 "%s timeout after %dms\n",
1898 (status == STATUS_INIT_UCODE_ALIVE)
1899 ? "INIT" : "Runtime",
1900 jiffies_to_msecs(UCODE_ALIVE_TIMEOUT));
1901 continue;
1902 }
1903 }
e1623446 1904 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
b481de9c
ZY
1905
1906 return 0;
1907 }
1908
1909 set_bit(STATUS_EXIT_PENDING, &priv->status);
5b9f8cd3 1910 __iwl_down(priv);
64e72c3e 1911 clear_bit(STATUS_EXIT_PENDING, &priv->status);
b481de9c
ZY
1912
1913 /* tried to restart and config the device for as long as our
1914 * patience could withstand */
15b1687c 1915 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
b481de9c
ZY
1916 return -EIO;
1917}
1918
1919
1920/*****************************************************************************
1921 *
1922 * Workqueue callbacks
1923 *
1924 *****************************************************************************/
1925
4a4a9e81 1926static void iwl_bg_init_alive_start(struct work_struct *data)
b481de9c 1927{
c79dd5b5
TW
1928 struct iwl_priv *priv =
1929 container_of(data, struct iwl_priv, init_alive_start.work);
b481de9c
ZY
1930
1931 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1932 return;
1933
1934 mutex_lock(&priv->mutex);
f3ccc08c 1935 priv->cfg->ops->lib->init_alive_start(priv);
b481de9c
ZY
1936 mutex_unlock(&priv->mutex);
1937}
1938
4a4a9e81 1939static void iwl_bg_alive_start(struct work_struct *data)
b481de9c 1940{
c79dd5b5
TW
1941 struct iwl_priv *priv =
1942 container_of(data, struct iwl_priv, alive_start.work);
b481de9c
ZY
1943
1944 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1945 return;
1946
258c44a0
MA
1947 /* enable dram interrupt */
1948 iwl_reset_ict(priv);
1949
b481de9c 1950 mutex_lock(&priv->mutex);
4a4a9e81 1951 iwl_alive_start(priv);
b481de9c
ZY
1952 mutex_unlock(&priv->mutex);
1953}
1954
16e727e8
EG
1955static void iwl_bg_run_time_calib_work(struct work_struct *work)
1956{
1957 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1958 run_time_calib_work);
1959
1960 mutex_lock(&priv->mutex);
1961
1962 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1963 test_bit(STATUS_SCANNING, &priv->status)) {
1964 mutex_unlock(&priv->mutex);
1965 return;
1966 }
1967
1968 if (priv->start_calib) {
1969 iwl_chain_noise_calibration(priv, &priv->statistics);
1970
1971 iwl_sensitivity_calibration(priv, &priv->statistics);
1972 }
1973
1974 mutex_unlock(&priv->mutex);
1975 return;
1976}
1977
5b9f8cd3 1978static void iwl_bg_up(struct work_struct *data)
b481de9c 1979{
c79dd5b5 1980 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
b481de9c
ZY
1981
1982 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1983 return;
1984
1985 mutex_lock(&priv->mutex);
5b9f8cd3 1986 __iwl_up(priv);
b481de9c
ZY
1987 mutex_unlock(&priv->mutex);
1988}
1989
5b9f8cd3 1990static void iwl_bg_restart(struct work_struct *data)
b481de9c 1991{
c79dd5b5 1992 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
b481de9c
ZY
1993
1994 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1995 return;
1996
19cc1087
JB
1997 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
1998 mutex_lock(&priv->mutex);
1999 priv->vif = NULL;
2000 priv->is_open = 0;
2001 mutex_unlock(&priv->mutex);
2002 iwl_down(priv);
2003 ieee80211_restart_hw(priv->hw);
2004 } else {
2005 iwl_down(priv);
2006 queue_work(priv->workqueue, &priv->up);
2007 }
b481de9c
ZY
2008}
2009
5b9f8cd3 2010static void iwl_bg_rx_replenish(struct work_struct *data)
b481de9c 2011{
c79dd5b5
TW
2012 struct iwl_priv *priv =
2013 container_of(data, struct iwl_priv, rx_replenish);
b481de9c
ZY
2014
2015 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2016 return;
2017
2018 mutex_lock(&priv->mutex);
a55360e4 2019 iwl_rx_replenish(priv);
b481de9c
ZY
2020 mutex_unlock(&priv->mutex);
2021}
2022
7878a5a4
MA
2023#define IWL_DELAY_NEXT_SCAN (HZ*2)
2024
5bbe233b 2025void iwl_post_associate(struct iwl_priv *priv)
b481de9c 2026{
b481de9c 2027 struct ieee80211_conf *conf = NULL;
857485c0 2028 int ret = 0;
1ff50bda 2029 unsigned long flags;
b481de9c 2030
05c914fe 2031 if (priv->iw_mode == NL80211_IFTYPE_AP) {
15b1687c 2032 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
b481de9c
ZY
2033 return;
2034 }
2035
e1623446 2036 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
e174961c 2037 priv->assoc_id, priv->active_rxon.bssid_addr);
b481de9c
ZY
2038
2039
2040 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2041 return;
2042
b481de9c 2043
508e32e1 2044 if (!priv->vif || !priv->is_open)
948c171c 2045 return;
508e32e1 2046
2a421b91 2047 iwl_scan_cancel_timeout(priv, 200);
052c4b9f 2048
b481de9c
ZY
2049 conf = ieee80211_get_hw_conf(priv->hw);
2050
2051 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2052 iwlcore_commit_rxon(priv);
b481de9c 2053
3195c1f3 2054 iwl_setup_rxon_timing(priv);
857485c0 2055 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2056 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2057 if (ret)
39aadf8c 2058 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2059 "Attempting to continue.\n");
2060
2061 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2062
42eb7c64 2063 iwl_set_rxon_ht(priv, &priv->current_ht_config);
4f85f5b3 2064
45823531
AK
2065 if (priv->cfg->ops->hcmd->set_rxon_chain)
2066 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2067
b481de9c
ZY
2068 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2069
e1623446 2070 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
b481de9c
ZY
2071 priv->assoc_id, priv->beacon_int);
2072
2073 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2074 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2075 else
2076 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2077
2078 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2079 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2080 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2081 else
2082 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2083
05c914fe 2084 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2085 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2086
2087 }
2088
e0158e61 2089 iwlcore_commit_rxon(priv);
b481de9c
ZY
2090
2091 switch (priv->iw_mode) {
05c914fe 2092 case NL80211_IFTYPE_STATION:
b481de9c
ZY
2093 break;
2094
05c914fe 2095 case NL80211_IFTYPE_ADHOC:
b481de9c 2096
c46fbefa
AK
2097 /* assume default assoc id */
2098 priv->assoc_id = 1;
b481de9c 2099
4f40e4d9 2100 iwl_rxon_add_station(priv, priv->bssid, 0);
5b9f8cd3 2101 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2102
2103 break;
2104
2105 default:
15b1687c 2106 IWL_ERR(priv, "%s Should not be called in %d mode\n",
3ac7f146 2107 __func__, priv->iw_mode);
b481de9c
ZY
2108 break;
2109 }
2110
05c914fe 2111 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2112 priv->assoc_station_added = 1;
2113
1ff50bda
EG
2114 spin_lock_irqsave(&priv->lock, flags);
2115 iwl_activate_qos(priv, 0);
2116 spin_unlock_irqrestore(&priv->lock, flags);
292ae174 2117
04816448
GE
2118 /* the chain noise calibration will enabled PM upon completion
2119 * If chain noise has already been run, then we need to enable
2120 * power management here */
2121 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
7af2c460 2122 iwl_power_update_mode(priv, 0);
c90a74ba
EG
2123
2124 /* Enable Rx differential gain and sensitivity calibrations */
2125 iwl_chain_noise_reset(priv);
2126 priv->start_calib = 1;
2127
508e32e1
RC
2128}
2129
b481de9c
ZY
2130/*****************************************************************************
2131 *
2132 * mac80211 entry point functions
2133 *
2134 *****************************************************************************/
2135
154b25ce 2136#define UCODE_READY_TIMEOUT (4 * HZ)
5a66926a 2137
5b9f8cd3 2138static int iwl_mac_start(struct ieee80211_hw *hw)
b481de9c 2139{
c79dd5b5 2140 struct iwl_priv *priv = hw->priv;
5a66926a 2141 int ret;
b481de9c 2142
e1623446 2143 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c
ZY
2144
2145 /* we should be verifying the device is ready to be opened */
2146 mutex_lock(&priv->mutex);
2147
5a66926a
ZY
2148 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2149 * ucode filename and max sizes are card-specific. */
b481de9c 2150
5a66926a 2151 if (!priv->ucode_code.len) {
5b9f8cd3 2152 ret = iwl_read_ucode(priv);
5a66926a 2153 if (ret) {
15b1687c 2154 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
5a66926a 2155 mutex_unlock(&priv->mutex);
6cd0b1cb 2156 return ret;
5a66926a
ZY
2157 }
2158 }
b481de9c 2159
5b9f8cd3 2160 ret = __iwl_up(priv);
5a66926a 2161
b481de9c 2162 mutex_unlock(&priv->mutex);
5a66926a 2163
e655b9f0 2164 if (ret)
6cd0b1cb 2165 return ret;
e655b9f0 2166
c1842d61
TW
2167 if (iwl_is_rfkill(priv))
2168 goto out;
2169
e1623446 2170 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
e655b9f0 2171
fe9b6b72 2172 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
5a66926a 2173 * mac80211 will not be run successfully. */
154b25ce
EG
2174 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2175 test_bit(STATUS_READY, &priv->status),
2176 UCODE_READY_TIMEOUT);
2177 if (!ret) {
2178 if (!test_bit(STATUS_READY, &priv->status)) {
15b1687c 2179 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
154b25ce 2180 jiffies_to_msecs(UCODE_READY_TIMEOUT));
6cd0b1cb 2181 return -ETIMEDOUT;
5a66926a 2182 }
fe9b6b72 2183 }
0a078ffa 2184
c1842d61 2185out:
0a078ffa 2186 priv->is_open = 1;
e1623446 2187 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2188 return 0;
2189}
2190
5b9f8cd3 2191static void iwl_mac_stop(struct ieee80211_hw *hw)
b481de9c 2192{
c79dd5b5 2193 struct iwl_priv *priv = hw->priv;
b481de9c 2194
e1623446 2195 IWL_DEBUG_MAC80211(priv, "enter\n");
948c171c 2196
19cc1087 2197 if (!priv->is_open)
e655b9f0 2198 return;
e655b9f0 2199
b481de9c 2200 priv->is_open = 0;
5a66926a 2201
fee1247a 2202 if (iwl_is_ready_rf(priv)) {
e655b9f0
ZY
2203 /* stop mac, cancel any scan request and clear
2204 * RXON_FILTER_ASSOC_MSK BIT
2205 */
5a66926a 2206 mutex_lock(&priv->mutex);
2a421b91 2207 iwl_scan_cancel_timeout(priv, 100);
fde3571f 2208 mutex_unlock(&priv->mutex);
fde3571f
MA
2209 }
2210
5b9f8cd3 2211 iwl_down(priv);
5a66926a
ZY
2212
2213 flush_workqueue(priv->workqueue);
6cd0b1cb
HS
2214
2215 /* enable interrupts again in order to receive rfkill changes */
2216 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2217 iwl_enable_interrupts(priv);
948c171c 2218
e1623446 2219 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2220}
2221
5b9f8cd3 2222static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
b481de9c 2223{
c79dd5b5 2224 struct iwl_priv *priv = hw->priv;
b481de9c 2225
e1623446 2226 IWL_DEBUG_MACDUMP(priv, "enter\n");
b481de9c 2227
e1623446 2228 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
e039fa4a 2229 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
b481de9c 2230
e039fa4a 2231 if (iwl_tx_skb(priv, skb))
b481de9c
ZY
2232 dev_kfree_skb_any(skb);
2233
e1623446 2234 IWL_DEBUG_MACDUMP(priv, "leave\n");
637f8837 2235 return NETDEV_TX_OK;
b481de9c
ZY
2236}
2237
60690a6a 2238void iwl_config_ap(struct iwl_priv *priv)
b481de9c 2239{
857485c0 2240 int ret = 0;
1ff50bda 2241 unsigned long flags;
b481de9c 2242
d986bcd1 2243 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
b481de9c
ZY
2244 return;
2245
2246 /* The following should be done only at AP bring up */
3195c1f3 2247 if (!iwl_is_associated(priv)) {
b481de9c
ZY
2248
2249 /* RXON - unassoc (to set timing command) */
2250 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
e0158e61 2251 iwlcore_commit_rxon(priv);
b481de9c
ZY
2252
2253 /* RXON Timing */
3195c1f3 2254 iwl_setup_rxon_timing(priv);
857485c0 2255 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
b481de9c 2256 sizeof(priv->rxon_timing), &priv->rxon_timing);
857485c0 2257 if (ret)
39aadf8c 2258 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
b481de9c
ZY
2259 "Attempting to continue.\n");
2260
45823531
AK
2261 if (priv->cfg->ops->hcmd->set_rxon_chain)
2262 priv->cfg->ops->hcmd->set_rxon_chain(priv);
b481de9c
ZY
2263
2264 /* FIXME: what should be the assoc_id for AP? */
2265 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2266 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2267 priv->staging_rxon.flags |=
2268 RXON_FLG_SHORT_PREAMBLE_MSK;
2269 else
2270 priv->staging_rxon.flags &=
2271 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2272
2273 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2274 if (priv->assoc_capability &
2275 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2276 priv->staging_rxon.flags |=
2277 RXON_FLG_SHORT_SLOT_MSK;
2278 else
2279 priv->staging_rxon.flags &=
2280 ~RXON_FLG_SHORT_SLOT_MSK;
2281
05c914fe 2282 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
b481de9c
ZY
2283 priv->staging_rxon.flags &=
2284 ~RXON_FLG_SHORT_SLOT_MSK;
2285 }
2286 /* restore RXON assoc */
2287 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
e0158e61 2288 iwlcore_commit_rxon(priv);
1ff50bda
EG
2289 spin_lock_irqsave(&priv->lock, flags);
2290 iwl_activate_qos(priv, 1);
2291 spin_unlock_irqrestore(&priv->lock, flags);
4f40e4d9 2292 iwl_rxon_add_station(priv, iwl_bcast_addr, 0);
e1493deb 2293 }
5b9f8cd3 2294 iwl_send_beacon_cmd(priv);
b481de9c
ZY
2295
2296 /* FIXME - we need to add code here to detect a totally new
2297 * configuration, reset the AP, unassoc, rxon timing, assoc,
2298 * clear sta table, add BCAST sta... */
2299}
2300
5b9f8cd3 2301static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
ab885f8c
EG
2302 struct ieee80211_key_conf *keyconf, const u8 *addr,
2303 u32 iv32, u16 *phase1key)
2304{
ab885f8c 2305
9f58671e 2306 struct iwl_priv *priv = hw->priv;
e1623446 2307 IWL_DEBUG_MAC80211(priv, "enter\n");
ab885f8c 2308
9f58671e 2309 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
ab885f8c 2310
e1623446 2311 IWL_DEBUG_MAC80211(priv, "leave\n");
ab885f8c
EG
2312}
2313
5b9f8cd3 2314static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB
2315 struct ieee80211_vif *vif,
2316 struct ieee80211_sta *sta,
b481de9c
ZY
2317 struct ieee80211_key_conf *key)
2318{
c79dd5b5 2319 struct iwl_priv *priv = hw->priv;
42986796
WT
2320 const u8 *addr;
2321 int ret;
2322 u8 sta_id;
2323 bool is_default_wep_key = false;
b481de9c 2324
e1623446 2325 IWL_DEBUG_MAC80211(priv, "enter\n");
b481de9c 2326
90e8e424 2327 if (priv->cfg->mod_params->sw_crypto) {
e1623446 2328 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
b481de9c
ZY
2329 return -EOPNOTSUPP;
2330 }
42986796 2331 addr = sta ? sta->addr : iwl_bcast_addr;
c587de0b 2332 sta_id = iwl_find_station(priv, addr);
6974e363 2333 if (sta_id == IWL_INVALID_STATION) {
e1623446 2334 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
e174961c 2335 addr);
6974e363 2336 return -EINVAL;
b481de9c 2337
deb09c43 2338 }
b481de9c 2339
6974e363 2340 mutex_lock(&priv->mutex);
2a421b91 2341 iwl_scan_cancel_timeout(priv, 100);
6974e363
EG
2342 mutex_unlock(&priv->mutex);
2343
2344 /* If we are getting WEP group key and we didn't receive any key mapping
2345 * so far, we are in legacy wep mode (group key only), otherwise we are
2346 * in 1X mode.
2347 * In legacy wep mode, we use another host command to the uCode */
5425e490 2348 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
05c914fe 2349 priv->iw_mode != NL80211_IFTYPE_AP) {
6974e363
EG
2350 if (cmd == SET_KEY)
2351 is_default_wep_key = !priv->key_mapping_key;
2352 else
ccc038ab
EG
2353 is_default_wep_key =
2354 (key->hw_key_idx == HW_KEY_DEFAULT);
6974e363 2355 }
052c4b9f 2356
b481de9c 2357 switch (cmd) {
deb09c43 2358 case SET_KEY:
6974e363
EG
2359 if (is_default_wep_key)
2360 ret = iwl_set_default_wep_key(priv, key);
deb09c43 2361 else
7480513f 2362 ret = iwl_set_dynamic_key(priv, key, sta_id);
deb09c43 2363
e1623446 2364 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
b481de9c
ZY
2365 break;
2366 case DISABLE_KEY:
6974e363
EG
2367 if (is_default_wep_key)
2368 ret = iwl_remove_default_wep_key(priv, key);
deb09c43 2369 else
3ec47732 2370 ret = iwl_remove_dynamic_key(priv, key, sta_id);
deb09c43 2371
e1623446 2372 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
b481de9c
ZY
2373 break;
2374 default:
deb09c43 2375 ret = -EINVAL;
b481de9c
ZY
2376 }
2377
e1623446 2378 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c 2379
deb09c43 2380 return ret;
b481de9c
ZY
2381}
2382
5b9f8cd3 2383static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
d783b061 2384 enum ieee80211_ampdu_mlme_action action,
17741cdc 2385 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
d783b061
TW
2386{
2387 struct iwl_priv *priv = hw->priv;
5c2207c6 2388 int ret;
d783b061 2389
e1623446 2390 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
e174961c 2391 sta->addr, tid);
d783b061
TW
2392
2393 if (!(priv->cfg->sku & IWL_SKU_N))
2394 return -EACCES;
2395
2396 switch (action) {
2397 case IEEE80211_AMPDU_RX_START:
e1623446 2398 IWL_DEBUG_HT(priv, "start Rx\n");
9f58671e 2399 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
d783b061 2400 case IEEE80211_AMPDU_RX_STOP:
e1623446 2401 IWL_DEBUG_HT(priv, "stop Rx\n");
5c2207c6
WYG
2402 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2403 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2404 return 0;
2405 else
2406 return ret;
d783b061 2407 case IEEE80211_AMPDU_TX_START:
e1623446 2408 IWL_DEBUG_HT(priv, "start Tx\n");
17741cdc 2409 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
d783b061 2410 case IEEE80211_AMPDU_TX_STOP:
e1623446 2411 IWL_DEBUG_HT(priv, "stop Tx\n");
5c2207c6
WYG
2412 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2413 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2414 return 0;
2415 else
2416 return ret;
d783b061 2417 default:
e1623446 2418 IWL_DEBUG_HT(priv, "unknown\n");
d783b061
TW
2419 return -EINVAL;
2420 break;
2421 }
2422 return 0;
2423}
9f58671e 2424
5b9f8cd3 2425static int iwl_mac_get_stats(struct ieee80211_hw *hw,
b481de9c
ZY
2426 struct ieee80211_low_level_stats *stats)
2427{
bf403db8
EK
2428 struct iwl_priv *priv = hw->priv;
2429
2430 priv = hw->priv;
e1623446
TW
2431 IWL_DEBUG_MAC80211(priv, "enter\n");
2432 IWL_DEBUG_MAC80211(priv, "leave\n");
b481de9c
ZY
2433
2434 return 0;
2435}
2436
b481de9c
ZY
2437/*****************************************************************************
2438 *
2439 * sysfs attributes
2440 *
2441 *****************************************************************************/
2442
0a6857e7 2443#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2444
2445/*
2446 * The following adds a new attribute to the sysfs representation
c3a739fa 2447 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
b481de9c
ZY
2448 * used for controlling the debug level.
2449 *
2450 * See the level definitions in iwl for details.
a562a9dd
RC
2451 *
2452 * FIXME This file can be deprecated as the module parameter is
2453 * writable and users can thus also change the debug level
2454 * using the /sys/module/iwl3945/parameters/debug file.
b481de9c
ZY
2455 */
2456
8cf769c6
EK
2457static ssize_t show_debug_level(struct device *d,
2458 struct device_attribute *attr, char *buf)
b481de9c 2459{
a562a9dd 2460 return sprintf(buf, "0x%08X\n", iwl_debug_level);
b481de9c 2461}
8cf769c6
EK
2462static ssize_t store_debug_level(struct device *d,
2463 struct device_attribute *attr,
b481de9c
ZY
2464 const char *buf, size_t count)
2465{
928841b1 2466 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2467 unsigned long val;
2468 int ret;
b481de9c 2469
9257746f
TW
2470 ret = strict_strtoul(buf, 0, &val);
2471 if (ret)
978785a3 2472 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
b481de9c 2473 else
a562a9dd 2474 iwl_debug_level = val;
b481de9c
ZY
2475
2476 return strnlen(buf, count);
2477}
2478
8cf769c6
EK
2479static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2480 show_debug_level, store_debug_level);
2481
b481de9c 2482
0a6857e7 2483#endif /* CONFIG_IWLWIFI_DEBUG */
b481de9c 2484
b481de9c 2485
bc6f59bc
TW
2486static ssize_t show_version(struct device *d,
2487 struct device_attribute *attr, char *buf)
2488{
928841b1 2489 struct iwl_priv *priv = dev_get_drvdata(d);
885ba202 2490 struct iwl_alive_resp *palive = &priv->card_alive;
f236a265
TW
2491 ssize_t pos = 0;
2492 u16 eeprom_ver;
bc6f59bc
TW
2493
2494 if (palive->is_valid)
f236a265
TW
2495 pos += sprintf(buf + pos,
2496 "fw version: 0x%01X.0x%01X.0x%01X.0x%01X\n"
2497 "fw type: 0x%01X 0x%01X\n",
bc6f59bc
TW
2498 palive->ucode_major, palive->ucode_minor,
2499 palive->sw_rev[0], palive->sw_rev[1],
2500 palive->ver_type, palive->ver_subtype);
bc6f59bc 2501 else
f236a265
TW
2502 pos += sprintf(buf + pos, "fw not loaded\n");
2503
2504 if (priv->eeprom) {
2505 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
0848e297
WYG
2506 pos += sprintf(buf + pos, "NVM Type: %s, version: 0x%x\n",
2507 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
2508 ? "OTP" : "EEPROM", eeprom_ver);
2509
f236a265
TW
2510 } else {
2511 pos += sprintf(buf + pos, "EEPROM not initialzed\n");
2512 }
2513
2514 return pos;
bc6f59bc
TW
2515}
2516
2517static DEVICE_ATTR(version, S_IWUSR | S_IRUGO, show_version, NULL);
2518
b481de9c
ZY
2519static ssize_t show_temperature(struct device *d,
2520 struct device_attribute *attr, char *buf)
2521{
928841b1 2522 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c 2523
fee1247a 2524 if (!iwl_is_alive(priv))
b481de9c
ZY
2525 return -EAGAIN;
2526
91dbc5bd 2527 return sprintf(buf, "%d\n", priv->temperature);
b481de9c
ZY
2528}
2529
2530static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2531
b481de9c
ZY
2532static ssize_t show_tx_power(struct device *d,
2533 struct device_attribute *attr, char *buf)
2534{
928841b1 2535 struct iwl_priv *priv = dev_get_drvdata(d);
91f39e8e
JS
2536
2537 if (!iwl_is_ready_rf(priv))
2538 return sprintf(buf, "off\n");
2539 else
2540 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
b481de9c
ZY
2541}
2542
2543static ssize_t store_tx_power(struct device *d,
2544 struct device_attribute *attr,
2545 const char *buf, size_t count)
2546{
928841b1 2547 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2548 unsigned long val;
2549 int ret;
b481de9c 2550
9257746f
TW
2551 ret = strict_strtoul(buf, 10, &val);
2552 if (ret)
978785a3 2553 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
b481de9c 2554 else
630fe9b6 2555 iwl_set_tx_power(priv, val, false);
b481de9c
ZY
2556
2557 return count;
2558}
2559
2560static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2561
2562static ssize_t show_flags(struct device *d,
2563 struct device_attribute *attr, char *buf)
2564{
928841b1 2565 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2566
2567 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2568}
2569
2570static ssize_t store_flags(struct device *d,
2571 struct device_attribute *attr,
2572 const char *buf, size_t count)
2573{
928841b1 2574 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2575 unsigned long val;
2576 u32 flags;
2577 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2578 if (ret)
9257746f
TW
2579 return ret;
2580 flags = (u32)val;
b481de9c
ZY
2581
2582 mutex_lock(&priv->mutex);
2583 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2584 /* Cancel any currently running scans... */
2a421b91 2585 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2586 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2587 else {
e1623446 2588 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
b481de9c 2589 priv->staging_rxon.flags = cpu_to_le32(flags);
e0158e61 2590 iwlcore_commit_rxon(priv);
b481de9c
ZY
2591 }
2592 }
2593 mutex_unlock(&priv->mutex);
2594
2595 return count;
2596}
2597
2598static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2599
2600static ssize_t show_filter_flags(struct device *d,
2601 struct device_attribute *attr, char *buf)
2602{
928841b1 2603 struct iwl_priv *priv = dev_get_drvdata(d);
b481de9c
ZY
2604
2605 return sprintf(buf, "0x%04X\n",
2606 le32_to_cpu(priv->active_rxon.filter_flags));
2607}
2608
2609static ssize_t store_filter_flags(struct device *d,
2610 struct device_attribute *attr,
2611 const char *buf, size_t count)
2612{
928841b1 2613 struct iwl_priv *priv = dev_get_drvdata(d);
9257746f
TW
2614 unsigned long val;
2615 u32 filter_flags;
2616 int ret = strict_strtoul(buf, 0, &val);
926f0b2e 2617 if (ret)
9257746f
TW
2618 return ret;
2619 filter_flags = (u32)val;
b481de9c
ZY
2620
2621 mutex_lock(&priv->mutex);
2622 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2623 /* Cancel any currently running scans... */
2a421b91 2624 if (iwl_scan_cancel_timeout(priv, 100))
39aadf8c 2625 IWL_WARN(priv, "Could not cancel scan.\n");
b481de9c 2626 else {
e1623446 2627 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
b481de9c
ZY
2628 "0x%04X\n", filter_flags);
2629 priv->staging_rxon.filter_flags =
2630 cpu_to_le32(filter_flags);
e0158e61 2631 iwlcore_commit_rxon(priv);
b481de9c
ZY
2632 }
2633 }
2634 mutex_unlock(&priv->mutex);
2635
2636 return count;
2637}
2638
2639static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2640 store_filter_flags);
2641
b481de9c
ZY
2642static ssize_t store_power_level(struct device *d,
2643 struct device_attribute *attr,
2644 const char *buf, size_t count)
2645{
c79dd5b5 2646 struct iwl_priv *priv = dev_get_drvdata(d);
298df1f6 2647 int ret;
9257746f
TW
2648 unsigned long mode;
2649
b481de9c 2650
b481de9c
ZY
2651 mutex_lock(&priv->mutex);
2652
9257746f 2653 ret = strict_strtoul(buf, 10, &mode);
926f0b2e 2654 if (ret)
9257746f
TW
2655 goto out;
2656
298df1f6
EK
2657 ret = iwl_power_set_user_mode(priv, mode);
2658 if (ret) {
e1623446 2659 IWL_DEBUG_MAC80211(priv, "failed setting power mode.\n");
5da4b55f 2660 goto out;
b481de9c 2661 }
298df1f6 2662 ret = count;
b481de9c
ZY
2663
2664 out:
2665 mutex_unlock(&priv->mutex);
298df1f6 2666 return ret;
b481de9c
ZY
2667}
2668
b481de9c
ZY
2669static ssize_t show_power_level(struct device *d,
2670 struct device_attribute *attr, char *buf)
2671{
c79dd5b5 2672 struct iwl_priv *priv = dev_get_drvdata(d);
5da4b55f 2673 int level = priv->power_data.power_mode;
b481de9c
ZY
2674 char *p = buf;
2675
872ed190 2676 p += sprintf(p, "%d\n", level);
3ac7f146 2677 return p - buf + 1;
b481de9c
ZY
2678}
2679
2680static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
2681 store_power_level);
2682
b481de9c
ZY
2683
2684static ssize_t show_statistics(struct device *d,
2685 struct device_attribute *attr, char *buf)
2686{
c79dd5b5 2687 struct iwl_priv *priv = dev_get_drvdata(d);
8f91aecb 2688 u32 size = sizeof(struct iwl_notif_statistics);
b481de9c 2689 u32 len = 0, ofs = 0;
3ac7f146 2690 u8 *data = (u8 *)&priv->statistics;
b481de9c
ZY
2691 int rc = 0;
2692
fee1247a 2693 if (!iwl_is_alive(priv))
b481de9c
ZY
2694 return -EAGAIN;
2695
2696 mutex_lock(&priv->mutex);
49ea8596 2697 rc = iwl_send_statistics_request(priv, 0);
b481de9c
ZY
2698 mutex_unlock(&priv->mutex);
2699
2700 if (rc) {
2701 len = sprintf(buf,
2702 "Error sending statistics request: 0x%08X\n", rc);
2703 return len;
2704 }
2705
2706 while (size && (PAGE_SIZE - len)) {
2707 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2708 PAGE_SIZE - len, 1);
2709 len = strlen(buf);
2710 if (PAGE_SIZE - len)
2711 buf[len++] = '\n';
2712
2713 ofs += 16;
2714 size -= min(size, 16U);
2715 }
2716
2717 return len;
2718}
2719
2720static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2721
b481de9c 2722
b481de9c
ZY
2723/*****************************************************************************
2724 *
2725 * driver setup and teardown
2726 *
2727 *****************************************************************************/
2728
4e39317d 2729static void iwl_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2730{
d21050c7 2731 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
b481de9c
ZY
2732
2733 init_waitqueue_head(&priv->wait_command_queue);
2734
5b9f8cd3
EG
2735 INIT_WORK(&priv->up, iwl_bg_up);
2736 INIT_WORK(&priv->restart, iwl_bg_restart);
2737 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
5b9f8cd3 2738 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
16e727e8 2739 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
4a4a9e81
TW
2740 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2741 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2a421b91 2742
2a421b91 2743 iwl_setup_scan_deferred_work(priv);
bb8c093b 2744
4e39317d
EG
2745 if (priv->cfg->ops->lib->setup_deferred_work)
2746 priv->cfg->ops->lib->setup_deferred_work(priv);
2747
2748 init_timer(&priv->statistics_periodic);
2749 priv->statistics_periodic.data = (unsigned long)priv;
5b9f8cd3 2750 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
b481de9c 2751
ef850d7c
MA
2752 if (!priv->cfg->use_isr_legacy)
2753 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2754 iwl_irq_tasklet, (unsigned long)priv);
2755 else
2756 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2757 iwl_irq_tasklet_legacy, (unsigned long)priv);
b481de9c
ZY
2758}
2759
4e39317d 2760static void iwl_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2761{
4e39317d
EG
2762 if (priv->cfg->ops->lib->cancel_deferred_work)
2763 priv->cfg->ops->lib->cancel_deferred_work(priv);
b481de9c 2764
3ae6a054 2765 cancel_delayed_work_sync(&priv->init_alive_start);
b481de9c
ZY
2766 cancel_delayed_work(&priv->scan_check);
2767 cancel_delayed_work(&priv->alive_start);
b481de9c 2768 cancel_work_sync(&priv->beacon_update);
4e39317d 2769 del_timer_sync(&priv->statistics_periodic);
b481de9c
ZY
2770}
2771
5b9f8cd3 2772static struct attribute *iwl_sysfs_entries[] = {
b481de9c
ZY
2773 &dev_attr_flags.attr,
2774 &dev_attr_filter_flags.attr,
b481de9c 2775 &dev_attr_power_level.attr,
b481de9c 2776 &dev_attr_statistics.attr,
b481de9c 2777 &dev_attr_temperature.attr,
b481de9c 2778 &dev_attr_tx_power.attr,
8cf769c6
EK
2779#ifdef CONFIG_IWLWIFI_DEBUG
2780 &dev_attr_debug_level.attr,
2781#endif
bc6f59bc 2782 &dev_attr_version.attr,
b481de9c
ZY
2783 NULL
2784};
2785
5b9f8cd3 2786static struct attribute_group iwl_attribute_group = {
b481de9c 2787 .name = NULL, /* put in device directory */
5b9f8cd3 2788 .attrs = iwl_sysfs_entries,
b481de9c
ZY
2789};
2790
5b9f8cd3
EG
2791static struct ieee80211_ops iwl_hw_ops = {
2792 .tx = iwl_mac_tx,
2793 .start = iwl_mac_start,
2794 .stop = iwl_mac_stop,
2795 .add_interface = iwl_mac_add_interface,
2796 .remove_interface = iwl_mac_remove_interface,
2797 .config = iwl_mac_config,
5b9f8cd3
EG
2798 .configure_filter = iwl_configure_filter,
2799 .set_key = iwl_mac_set_key,
2800 .update_tkip_key = iwl_mac_update_tkip_key,
2801 .get_stats = iwl_mac_get_stats,
2802 .get_tx_stats = iwl_mac_get_tx_stats,
2803 .conf_tx = iwl_mac_conf_tx,
2804 .reset_tsf = iwl_mac_reset_tsf,
2805 .bss_info_changed = iwl_bss_info_changed,
2806 .ampdu_action = iwl_mac_ampdu_action,
cb43dc25 2807 .hw_scan = iwl_mac_hw_scan
b481de9c
ZY
2808};
2809
5b9f8cd3 2810static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
b481de9c
ZY
2811{
2812 int err = 0;
c79dd5b5 2813 struct iwl_priv *priv;
b481de9c 2814 struct ieee80211_hw *hw;
82b9a121 2815 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
0359facc 2816 unsigned long flags;
6cd0b1cb 2817 u16 pci_cmd;
b481de9c 2818
316c30d9
AK
2819 /************************
2820 * 1. Allocating HW data
2821 ************************/
2822
6440adb5
BC
2823 /* Disabling hardware scan means that mac80211 will perform scans
2824 * "the hard way", rather than using device's scan. */
1ea87396 2825 if (cfg->mod_params->disable_hw_scan) {
a562a9dd 2826 if (iwl_debug_level & IWL_DL_INFO)
bf403db8
EK
2827 dev_printk(KERN_DEBUG, &(pdev->dev),
2828 "Disabling hw_scan\n");
5b9f8cd3 2829 iwl_hw_ops.hw_scan = NULL;
b481de9c
ZY
2830 }
2831
5b9f8cd3 2832 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
1d0a082d 2833 if (!hw) {
b481de9c
ZY
2834 err = -ENOMEM;
2835 goto out;
2836 }
1d0a082d
AK
2837 priv = hw->priv;
2838 /* At this point both hw and priv are allocated. */
2839
b481de9c
ZY
2840 SET_IEEE80211_DEV(hw, &pdev->dev);
2841
e1623446 2842 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
82b9a121 2843 priv->cfg = cfg;
b481de9c 2844 priv->pci_dev = pdev;
40cefda9 2845 priv->inta_mask = CSR_INI_SET_MASK;
316c30d9 2846
0a6857e7 2847#ifdef CONFIG_IWLWIFI_DEBUG
b481de9c
ZY
2848 atomic_set(&priv->restrict_refcnt, 0);
2849#endif
b481de9c 2850
316c30d9
AK
2851 /**************************
2852 * 2. Initializing PCI bus
2853 **************************/
2854 if (pci_enable_device(pdev)) {
2855 err = -ENODEV;
2856 goto out_ieee80211_free_hw;
2857 }
2858
2859 pci_set_master(pdev);
2860
093d874c 2861 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
316c30d9 2862 if (!err)
093d874c 2863 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
cc2a8ea8 2864 if (err) {
093d874c 2865 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2866 if (!err)
093d874c 2867 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
cc2a8ea8 2868 /* both attempts failed: */
316c30d9 2869 if (err) {
978785a3 2870 IWL_WARN(priv, "No suitable DMA available.\n");
316c30d9 2871 goto out_pci_disable_device;
cc2a8ea8 2872 }
316c30d9
AK
2873 }
2874
2875 err = pci_request_regions(pdev, DRV_NAME);
2876 if (err)
2877 goto out_pci_disable_device;
2878
2879 pci_set_drvdata(pdev, priv);
2880
316c30d9
AK
2881
2882 /***********************
2883 * 3. Read REV register
2884 ***********************/
2885 priv->hw_base = pci_iomap(pdev, 0, 0);
2886 if (!priv->hw_base) {
2887 err = -ENODEV;
2888 goto out_pci_release_regions;
2889 }
2890
e1623446 2891 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
316c30d9 2892 (unsigned long long) pci_resource_len(pdev, 0));
e1623446 2893 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
316c30d9 2894
a8b50a0a
MA
2895 /* this spin lock will be used in apm_ops.init and EEPROM access
2896 * we should init now
2897 */
2898 spin_lock_init(&priv->reg_lock);
b661c819 2899 iwl_hw_detect(priv);
978785a3 2900 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
b661c819 2901 priv->cfg->name, priv->hw_rev);
316c30d9 2902
e7b63581
TW
2903 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2904 * PCI Tx retries from interfering with C3 CPU state */
2905 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2906
086ed117
MA
2907 iwl_prepare_card_hw(priv);
2908 if (!priv->hw_ready) {
2909 IWL_WARN(priv, "Failed, HW not ready\n");
2910 goto out_iounmap;
2911 }
2912
91238714
TW
2913 /* amp init */
2914 err = priv->cfg->ops->lib->apm_ops.init(priv);
316c30d9 2915 if (err < 0) {
808ff697 2916 IWL_ERR(priv, "Failed to init APMG\n");
316c30d9
AK
2917 goto out_iounmap;
2918 }
91238714
TW
2919 /*****************
2920 * 4. Read EEPROM
2921 *****************/
316c30d9
AK
2922 /* Read the EEPROM */
2923 err = iwl_eeprom_init(priv);
2924 if (err) {
15b1687c 2925 IWL_ERR(priv, "Unable to init EEPROM\n");
316c30d9
AK
2926 goto out_iounmap;
2927 }
8614f360
TW
2928 err = iwl_eeprom_check_version(priv);
2929 if (err)
c8f16138 2930 goto out_free_eeprom;
8614f360 2931
02883017 2932 /* extract MAC Address */
316c30d9 2933 iwl_eeprom_get_mac(priv, priv->mac_addr);
e1623446 2934 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
316c30d9
AK
2935 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
2936
2937 /************************
2938 * 5. Setup HW constants
2939 ************************/
da154e30 2940 if (iwl_set_hw_params(priv)) {
15b1687c 2941 IWL_ERR(priv, "failed to set hw parameters\n");
073d3f5f 2942 goto out_free_eeprom;
316c30d9
AK
2943 }
2944
2945 /*******************
6ba87956 2946 * 6. Setup priv
316c30d9 2947 *******************/
b481de9c 2948
6ba87956 2949 err = iwl_init_drv(priv);
bf85ea4f 2950 if (err)
399f4900 2951 goto out_free_eeprom;
bf85ea4f 2952 /* At this point both hw and priv are initialized. */
316c30d9 2953
316c30d9 2954 /********************
09f9bf79 2955 * 7. Setup services
316c30d9 2956 ********************/
0359facc 2957 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 2958 iwl_disable_interrupts(priv);
0359facc 2959 spin_unlock_irqrestore(&priv->lock, flags);
316c30d9 2960
6cd0b1cb
HS
2961 pci_enable_msi(priv->pci_dev);
2962
ef850d7c
MA
2963 iwl_alloc_isr_ict(priv);
2964 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
2965 IRQF_SHARED, DRV_NAME, priv);
6cd0b1cb
HS
2966 if (err) {
2967 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
2968 goto out_disable_msi;
2969 }
5b9f8cd3 2970 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
316c30d9 2971 if (err) {
15b1687c 2972 IWL_ERR(priv, "failed to create sysfs device attributes\n");
795cc0ad 2973 goto out_free_irq;
316c30d9
AK
2974 }
2975
4e39317d 2976 iwl_setup_deferred_work(priv);
653fa4a0 2977 iwl_setup_rx_handlers(priv);
316c30d9 2978
6ba87956 2979 /**********************************
09f9bf79 2980 * 8. Setup and register mac80211
6ba87956
TW
2981 **********************************/
2982
6cd0b1cb
HS
2983 /* enable interrupts if needed: hw bug w/a */
2984 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
2985 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2986 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2987 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
2988 }
2989
2990 iwl_enable_interrupts(priv);
2991
6ba87956
TW
2992 err = iwl_setup_mac(priv);
2993 if (err)
2994 goto out_remove_sysfs;
2995
2996 err = iwl_dbgfs_register(priv, DRV_NAME);
2997 if (err)
a75fbe8d 2998 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
6ba87956 2999
6cd0b1cb
HS
3000 /* If platform's RF_KILL switch is NOT set to KILL */
3001 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3002 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3003 else
3004 set_bit(STATUS_RF_KILL_HW, &priv->status);
6ba87956 3005
a60e77e5
JB
3006 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3007 test_bit(STATUS_RF_KILL_HW, &priv->status));
6cd0b1cb 3008
58d0f361 3009 iwl_power_initialize(priv);
39b73fb1 3010 iwl_tt_initialize(priv);
b481de9c
ZY
3011 return 0;
3012
316c30d9 3013 out_remove_sysfs:
c8f16138
RC
3014 destroy_workqueue(priv->workqueue);
3015 priv->workqueue = NULL;
5b9f8cd3 3016 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
795cc0ad
HS
3017 out_free_irq:
3018 free_irq(priv->pci_dev->irq, priv);
ef850d7c 3019 iwl_free_isr_ict(priv);
6cd0b1cb
HS
3020 out_disable_msi:
3021 pci_disable_msi(priv->pci_dev);
6ba87956 3022 iwl_uninit_drv(priv);
073d3f5f
TW
3023 out_free_eeprom:
3024 iwl_eeprom_free(priv);
b481de9c
ZY
3025 out_iounmap:
3026 pci_iounmap(pdev, priv->hw_base);
3027 out_pci_release_regions:
316c30d9 3028 pci_set_drvdata(pdev, NULL);
623d563e 3029 pci_release_regions(pdev);
b481de9c
ZY
3030 out_pci_disable_device:
3031 pci_disable_device(pdev);
b481de9c
ZY
3032 out_ieee80211_free_hw:
3033 ieee80211_free_hw(priv->hw);
3034 out:
3035 return err;
3036}
3037
5b9f8cd3 3038static void __devexit iwl_pci_remove(struct pci_dev *pdev)
b481de9c 3039{
c79dd5b5 3040 struct iwl_priv *priv = pci_get_drvdata(pdev);
0359facc 3041 unsigned long flags;
b481de9c
ZY
3042
3043 if (!priv)
3044 return;
3045
e1623446 3046 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
b481de9c 3047
67249625 3048 iwl_dbgfs_unregister(priv);
5b9f8cd3 3049 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
67249625 3050
5b9f8cd3
EG
3051 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3052 * to be called and iwl_down since we are removing the device
0b124c31
GG
3053 * we need to set STATUS_EXIT_PENDING bit.
3054 */
3055 set_bit(STATUS_EXIT_PENDING, &priv->status);
c4f55232
RR
3056 if (priv->mac80211_registered) {
3057 ieee80211_unregister_hw(priv->hw);
3058 priv->mac80211_registered = 0;
0b124c31 3059 } else {
5b9f8cd3 3060 iwl_down(priv);
c4f55232
RR
3061 }
3062
39b73fb1
WYG
3063 iwl_tt_exit(priv);
3064
0359facc
MA
3065 /* make sure we flush any pending irq or
3066 * tasklet for the driver
3067 */
3068 spin_lock_irqsave(&priv->lock, flags);
5b9f8cd3 3069 iwl_disable_interrupts(priv);
0359facc
MA
3070 spin_unlock_irqrestore(&priv->lock, flags);
3071
3072 iwl_synchronize_irq(priv);
3073
5b9f8cd3 3074 iwl_dealloc_ucode_pci(priv);
b481de9c
ZY
3075
3076 if (priv->rxq.bd)
a55360e4 3077 iwl_rx_queue_free(priv, &priv->rxq);
1053d35f 3078 iwl_hw_txq_ctx_free(priv);
b481de9c 3079
c587de0b 3080 iwl_clear_stations_table(priv);
073d3f5f 3081 iwl_eeprom_free(priv);
b481de9c 3082
b481de9c 3083
948c171c
MA
3084 /*netif_stop_queue(dev); */
3085 flush_workqueue(priv->workqueue);
3086
5b9f8cd3 3087 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
b481de9c
ZY
3088 * priv->workqueue... so we can't take down the workqueue
3089 * until now... */
3090 destroy_workqueue(priv->workqueue);
3091 priv->workqueue = NULL;
3092
6cd0b1cb
HS
3093 free_irq(priv->pci_dev->irq, priv);
3094 pci_disable_msi(priv->pci_dev);
b481de9c
ZY
3095 pci_iounmap(pdev, priv->hw_base);
3096 pci_release_regions(pdev);
3097 pci_disable_device(pdev);
3098 pci_set_drvdata(pdev, NULL);
3099
6ba87956 3100 iwl_uninit_drv(priv);
b481de9c 3101
ef850d7c
MA
3102 iwl_free_isr_ict(priv);
3103
b481de9c
ZY
3104 if (priv->ibss_beacon)
3105 dev_kfree_skb(priv->ibss_beacon);
3106
3107 ieee80211_free_hw(priv->hw);
3108}
3109
b481de9c
ZY
3110
3111/*****************************************************************************
3112 *
3113 * driver and module entry point
3114 *
3115 *****************************************************************************/
3116
fed9017e
RR
3117/* Hardware specific file defines the PCI IDs table for that hardware module */
3118static struct pci_device_id iwl_hw_card_ids[] = {
4fc22b21 3119#ifdef CONFIG_IWL4965
fed9017e
RR
3120 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3121 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
4fc22b21 3122#endif /* CONFIG_IWL4965 */
5a6a256e 3123#ifdef CONFIG_IWL5000
47408639
EK
3124 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3125 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3126 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3127 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3128 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3129 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
5a6a256e 3130 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
47408639
EK
3131 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3132 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3133 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
e96a8495
TW
3134/* 5350 WiFi/WiMax */
3135 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3136 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3137 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
7100e924
TW
3138/* 5150 Wifi/WiMax */
3139 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3140 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
e1228374
JS
3141/* 6000/6050 Series */
3142 {IWL_PCI_DEVICE(0x0082, 0x1102, iwl6000_2ag_cfg)},
3143 {IWL_PCI_DEVICE(0x0085, 0x1112, iwl6000_2ag_cfg)},
3144 {IWL_PCI_DEVICE(0x0082, 0x1122, iwl6000_2ag_cfg)},
3145 {IWL_PCI_DEVICE(0x422B, PCI_ANY_ID, iwl6000_3agn_cfg)},
542cc793 3146 {IWL_PCI_DEVICE(0x422C, PCI_ANY_ID, iwl6000_2agn_cfg)},
e1228374 3147 {IWL_PCI_DEVICE(0x4238, PCI_ANY_ID, iwl6000_3agn_cfg)},
542cc793 3148 {IWL_PCI_DEVICE(0x4239, PCI_ANY_ID, iwl6000_2agn_cfg)},
e1228374
JS
3149 {IWL_PCI_DEVICE(0x0082, PCI_ANY_ID, iwl6000_2agn_cfg)},
3150 {IWL_PCI_DEVICE(0x0085, PCI_ANY_ID, iwl6000_3agn_cfg)},
3151 {IWL_PCI_DEVICE(0x0086, PCI_ANY_ID, iwl6050_3agn_cfg)},
3152 {IWL_PCI_DEVICE(0x0087, PCI_ANY_ID, iwl6050_2agn_cfg)},
3153 {IWL_PCI_DEVICE(0x0088, PCI_ANY_ID, iwl6050_3agn_cfg)},
3154 {IWL_PCI_DEVICE(0x0089, PCI_ANY_ID, iwl6050_2agn_cfg)},
77dcb6a9
JS
3155/* 1000 Series WiFi */
3156 {IWL_PCI_DEVICE(0x0083, PCI_ANY_ID, iwl1000_bgn_cfg)},
3157 {IWL_PCI_DEVICE(0x0084, PCI_ANY_ID, iwl1000_bgn_cfg)},
5a6a256e 3158#endif /* CONFIG_IWL5000 */
7100e924 3159
fed9017e
RR
3160 {0}
3161};
3162MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3163
3164static struct pci_driver iwl_driver = {
b481de9c 3165 .name = DRV_NAME,
fed9017e 3166 .id_table = iwl_hw_card_ids,
5b9f8cd3
EG
3167 .probe = iwl_pci_probe,
3168 .remove = __devexit_p(iwl_pci_remove),
b481de9c 3169#ifdef CONFIG_PM
5b9f8cd3
EG
3170 .suspend = iwl_pci_suspend,
3171 .resume = iwl_pci_resume,
b481de9c
ZY
3172#endif
3173};
3174
5b9f8cd3 3175static int __init iwl_init(void)
b481de9c
ZY
3176{
3177
3178 int ret;
3179 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3180 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
897e1cf2 3181
e227ceac 3182 ret = iwlagn_rate_control_register();
897e1cf2 3183 if (ret) {
a3139c59
SO
3184 printk(KERN_ERR DRV_NAME
3185 "Unable to register rate control algorithm: %d\n", ret);
897e1cf2
RC
3186 return ret;
3187 }
3188
fed9017e 3189 ret = pci_register_driver(&iwl_driver);
b481de9c 3190 if (ret) {
a3139c59 3191 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
897e1cf2 3192 goto error_register;
b481de9c 3193 }
b481de9c
ZY
3194
3195 return ret;
897e1cf2 3196
897e1cf2 3197error_register:
e227ceac 3198 iwlagn_rate_control_unregister();
897e1cf2 3199 return ret;
b481de9c
ZY
3200}
3201
5b9f8cd3 3202static void __exit iwl_exit(void)
b481de9c 3203{
fed9017e 3204 pci_unregister_driver(&iwl_driver);
e227ceac 3205 iwlagn_rate_control_unregister();
b481de9c
ZY
3206}
3207
5b9f8cd3
EG
3208module_exit(iwl_exit);
3209module_init(iwl_init);
a562a9dd
RC
3210
3211#ifdef CONFIG_IWLWIFI_DEBUG
3212module_param_named(debug50, iwl_debug_level, uint, 0444);
3213MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
3214module_param_named(debug, iwl_debug_level, uint, 0644);
3215MODULE_PARM_DESC(debug, "debug output mask");
3216#endif
3217
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