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ARM: dts: imx35: add iim module to imx35.dtsi
[linux.git] / arch / arm / boot / dts / imx6ul.dtsi
CommitLineData
a5fcccbc
FL		 1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6ul-clock.h>
10#include <dt-bindings/gpio/gpio.h>
89435fea 11#include <dt-bindings/input/input.h>
a5fcccbc
FL		 12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "imx6ul-pinfunc.h"
14#include "skeleton.dtsi"
15
16/ {
17 aliases {
01f3dc7d
FD		 18 ethernet0 = &fec1;
19 ethernet1 = &fec2;
a5fcccbc
FL		 20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 gpio4 = &gpio5;
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
37 serial6 = &uart7;
38 serial7 = &uart8;
fb3239ff
FE		 39 sai1 = &sai1;
40 sai2 = &sai2;
41 sai3 = &sai3;
a5fcccbc
FL		 42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &ecspi3;
45 spi3 = &ecspi4;
46 usbphy0 = &usbphy1;
47 usbphy1 = &usbphy2;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: cpu@0 {
55 compatible = "arm,cortex-a7";
56 device_type = "cpu";
57 reg = <0>;
58 clock-latency = <61036>; /* two CLK32 periods */
59 operating-points = <
60 /* kHz uV */
f7084446
FE		 61 528000 1175000
62 396000 1025000
63 198000 950000
a5fcccbc
FL		 64 >;
65 fsl,soc-operating-points = <
66 /* KHz uV */
f7084446
FE		 67 528000 1175000
68 396000 1175000
69 198000 1175000
a5fcccbc
FL		 70 >;
71 clocks = <&clks IMX6UL_CLK_ARM>,
72 <&clks IMX6UL_CLK_PLL2_BUS>,
73 <&clks IMX6UL_CLK_PLL2_PFD2>,
74 <&clks IMX6UL_CA7_SECONDARY_SEL>,
75 <&clks IMX6UL_CLK_STEP>,
76 <&clks IMX6UL_CLK_PLL1_SW>,
77 <&clks IMX6UL_CLK_PLL1_SYS>,
78 <&clks IMX6UL_PLL1_BYPASS>,
79 <&clks IMX6UL_CLK_PLL1>,
80 <&clks IMX6UL_PLL1_BYPASS_SRC>,
81 <&clks IMX6UL_CLK_OSC>;
82 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
83 "secondary_sel", "step", "pll1_sw",
84 "pll1_sys", "pll1_bypass", "pll1",
85 "pll1_bypass_src", "osc";
86 arm-supply = <&reg_arm>;
87 soc-supply = <&reg_soc>;
88 };
89 };
90
91 intc: interrupt-controller@00a01000 {
92 compatible = "arm,cortex-a7-gic";
93 #interrupt-cells = <3>;
94 interrupt-controller;
95 reg = <0x00a01000 0x1000>,
96 <0x00a02000 0x1000>,
97 <0x00a04000 0x2000>,
98 <0x00a06000 0x2000>;
99 };
100
101 ckil: clock-cli {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <32768>;
105 clock-output-names = "ckil";
106 };
107
108 osc: clock-osc {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <24000000>;
112 clock-output-names = "osc";
113 };
114
115 ipp_di0: clock-di0 {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <0>;
119 clock-output-names = "ipp_di0";
120 };
121
122 ipp_di1: clock-di1 {
123 compatible = "fixed-clock";
124 #clock-cells = <0>;
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
127 };
128
129 soc {
130 #address-cells = <1>;
131 #size-cells = <1>;
132 compatible = "simple-bus";
18619ff5 133 interrupt-parent = <&gpc>;
a5fcccbc
FL		 134 ranges;
135
136 pmu {
137 compatible = "arm,cortex-a7-pmu";
138 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
139 status = "disabled";
140 };
141
322d09d6
AH		 142 ocram: sram@00900000 {
143 compatible = "mmio-sram";
144 reg = <0x00900000 0x20000>;
145 };
146
7d1cd297
LW		 147 dma_apbh: dma-apbh@01804000 {
148 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
149 reg = <0x01804000 0x2000>;
150 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
151 <0 13 IRQ_TYPE_LEVEL_HIGH>,
152 <0 13 IRQ_TYPE_LEVEL_HIGH>,
153 <0 13 IRQ_TYPE_LEVEL_HIGH>;
154 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
155 #dma-cells = <1>;
156 dma-channels = <4>;
157 clocks = <&clks IMX6UL_CLK_APBHDMA>;
158 };
159
160 gpmi: gpmi-nand@01806000 {
161 compatible = "fsl,imx6q-gpmi-nand";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
165 reg-names = "gpmi-nand", "bch";
166 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
167 interrupt-names = "bch";
168 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
169 <&clks IMX6UL_CLK_GPMI_APB>,
170 <&clks IMX6UL_CLK_GPMI_BCH>,
171 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
172 <&clks IMX6UL_CLK_PER_BCH>;
173 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
174 "gpmi_bch_apb", "per1_bch";
175 dmas = <&dma_apbh 0>;
176 dma-names = "rx-tx";
177 status = "disabled";
178 };
179
a5fcccbc
FL		 180 aips1: aips-bus@02000000 {
181 compatible = "fsl,aips-bus", "simple-bus";
182 #address-cells = <1>;
183 #size-cells = <1>;
184 reg = <0x02000000 0x100000>;
185 ranges;
186
187 spba-bus@02000000 {
188 compatible = "fsl,spba-bus", "simple-bus";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 reg = <0x02000000 0x40000>;
192 ranges;
193
194 ecspi1: ecspi@02008000 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
198 reg = <0x02008000 0x4000>;
199 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clks IMX6UL_CLK_ECSPI1>,
201 <&clks IMX6UL_CLK_ECSPI1>;
202 clock-names = "ipg", "per";
203 status = "disabled";
204 };
205
206 ecspi2: ecspi@0200c000 {
207 #address-cells = <1>;
208 #size-cells = <0>;
209 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
210 reg = <0x0200c000 0x4000>;
211 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&clks IMX6UL_CLK_ECSPI2>,
213 <&clks IMX6UL_CLK_ECSPI2>;
214 clock-names = "ipg", "per";
215 status = "disabled";
216 };
217
218 ecspi3: ecspi@02010000 {
219 #address-cells = <1>;
220 #size-cells = <0>;
221 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
222 reg = <0x02010000 0x4000>;
223 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6UL_CLK_ECSPI3>,
225 <&clks IMX6UL_CLK_ECSPI3>;
226 clock-names = "ipg", "per";
227 status = "disabled";
228 };
229
230 ecspi4: ecspi@02014000 {
231 #address-cells = <1>;
232 #size-cells = <0>;
233 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
234 reg = <0x02014000 0x4000>;
235 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&clks IMX6UL_CLK_ECSPI4>,
237 <&clks IMX6UL_CLK_ECSPI4>;
238 clock-names = "ipg", "per";
239 status = "disabled";
240 };
241
242 uart7: serial@02018000 {
243 compatible = "fsl,imx6ul-uart",
244 "fsl,imx6q-uart";
245 reg = <0x02018000 0x4000>;
246 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
248 <&clks IMX6UL_CLK_UART7_SERIAL>;
249 clock-names = "ipg", "per";
250 status = "disabled";
251 };
252
253 uart1: serial@02020000 {
254 compatible = "fsl,imx6ul-uart",
255 "fsl,imx6q-uart";
256 reg = <0x02020000 0x4000>;
257 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
259 <&clks IMX6UL_CLK_UART1_SERIAL>;
260 clock-names = "ipg", "per";
261 status = "disabled";
262 };
263
264 uart8: serial@02024000 {
265 compatible = "fsl,imx6ul-uart",
266 "fsl,imx6q-uart";
267 reg = <0x02024000 0x4000>;
268 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
270 <&clks IMX6UL_CLK_UART8_SERIAL>;
271 clock-names = "ipg", "per";
272 status = "disabled";
273 };
36e2edf6
LW		 274
275 sai1: sai@02028000 {
276 #sound-dai-cells = <0>;
277 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
278 reg = <0x02028000 0x4000>;
279 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
281 <&clks IMX6UL_CLK_SAI1>,
282 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
283 clock-names = "bus", "mclk1", "mclk2", "mclk3";
284 dmas = <&sdma 35 24 0>,
285 <&sdma 36 24 0>;
286 dma-names = "rx", "tx";
287 status = "disabled";
288 };
289
290 sai2: sai@0202c000 {
291 #sound-dai-cells = <0>;
292 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
293 reg = <0x0202c000 0x4000>;
294 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
296 <&clks IMX6UL_CLK_SAI2>,
297 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
298 clock-names = "bus", "mclk1", "mclk2", "mclk3";
299 dmas = <&sdma 37 24 0>,
300 <&sdma 38 24 0>;
301 dma-names = "rx", "tx";
302 status = "disabled";
303 };
304
305 sai3: sai@02030000 {
306 #sound-dai-cells = <0>;
307 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
308 reg = <0x02030000 0x4000>;
309 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
311 <&clks IMX6UL_CLK_SAI3>,
312 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
313 clock-names = "bus", "mclk1", "mclk2", "mclk3";
314 dmas = <&sdma 39 24 0>,
315 <&sdma 40 24 0>;
316 dma-names = "rx", "tx";
317 status = "disabled";
318 };
a5fcccbc
FL		 319 };
320
302e01b2
LW		 321 tsc: tsc@02040000 {
322 compatible = "fsl,imx6ul-tsc";
323 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
324 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&clks IMX6UL_CLK_IPG>,
327 <&clks IMX6UL_CLK_ADC2>;
328 clock-names = "tsc", "adc";
329 status = "disabled";
330 };
331
b9901fe8
LW		 332 pwm1: pwm@02080000 {
333 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
334 reg = <0x02080000 0x4000>;
335 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&clks IMX6UL_CLK_PWM1>,
337 <&clks IMX6UL_CLK_PWM1>;
338 clock-names = "ipg", "per";
339 #pwm-cells = <2>;
340 status = "disabled";
341 };
342
343 pwm2: pwm@02084000 {
344 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
345 reg = <0x02084000 0x4000>;
346 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clks IMX6UL_CLK_PWM2>,
348 <&clks IMX6UL_CLK_PWM2>;
349 clock-names = "ipg", "per";
350 #pwm-cells = <2>;
351 status = "disabled";
352 };
353
354 pwm3: pwm@02088000 {
355 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
356 reg = <0x02088000 0x4000>;
357 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&clks IMX6UL_CLK_PWM3>,
359 <&clks IMX6UL_CLK_PWM3>;
360 clock-names = "ipg", "per";
361 #pwm-cells = <2>;
362 status = "disabled";
363 };
364
365 pwm4: pwm@0208c000 {
366 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
367 reg = <0x0208c000 0x4000>;
368 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks IMX6UL_CLK_PWM4>,
370 <&clks IMX6UL_CLK_PWM4>;
371 clock-names = "ipg", "per";
372 #pwm-cells = <2>;
373 status = "disabled";
374 };
375
c4aac1b1
LW		 376 can1: flexcan@02090000 {
377 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
378 reg = <0x02090000 0x4000>;
379 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
381 <&clks IMX6UL_CLK_CAN1_SERIAL>;
382 clock-names = "ipg", "per";
383 status = "disabled";
384 };
385
386 can2: flexcan@02094000 {
387 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
388 reg = <0x02094000 0x4000>;
389 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
391 <&clks IMX6UL_CLK_CAN2_SERIAL>;
392 clock-names = "ipg", "per";
393 status = "disabled";
394 };
395
a5fcccbc
FL		 396 gpt1: gpt@02098000 {
397 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
398 reg = <0x02098000 0x4000>;
399 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
401 <&clks IMX6UL_CLK_GPT1_SERIAL>;
402 clock-names = "ipg", "per";
403 };
404
405 gpio1: gpio@0209c000 {
406 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
407 reg = <0x0209c000 0x4000>;
408 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
410 gpio-controller;
411 #gpio-cells = <2>;
412 interrupt-controller;
413 #interrupt-cells = <2>;
414 };
415
416 gpio2: gpio@020a0000 {
417 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
418 reg = <0x020a0000 0x4000>;
419 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
421 gpio-controller;
422 #gpio-cells = <2>;
423 interrupt-controller;
424 #interrupt-cells = <2>;
425 };
426
427 gpio3: gpio@020a4000 {
428 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
429 reg = <0x020a4000 0x4000>;
430 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
432 gpio-controller;
433 #gpio-cells = <2>;
434 interrupt-controller;
435 #interrupt-cells = <2>;
436 };
437
438 gpio4: gpio@020a8000 {
439 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
440 reg = <0x020a8000 0x4000>;
441 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
443 gpio-controller;
444 #gpio-cells = <2>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
447 };
448
449 gpio5: gpio@020ac000 {
450 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
451 reg = <0x020ac000 0x4000>;
452 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
454 gpio-controller;
455 #gpio-cells = <2>;
456 interrupt-controller;
457 #interrupt-cells = <2>;
458 };
459
01f3dc7d
FD		 460 fec2: ethernet@020b4000 {
461 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
462 reg = <0x020b4000 0x4000>;
463 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&clks IMX6UL_CLK_ENET>,
466 <&clks IMX6UL_CLK_ENET_AHB>,
467 <&clks IMX6UL_CLK_ENET_PTP>,
468 <&clks IMX6UL_CLK_ENET2_REF_125M>,
469 <&clks IMX6UL_CLK_ENET2_REF_125M>;
470 clock-names = "ipg", "ahb", "ptp",
471 "enet_clk_ref", "enet_out";
472 fsl,num-tx-queues=<1>;
473 fsl,num-rx-queues=<1>;
474 status = "disabled";
475 };
476
ea1c1752
LW		 477 kpp: kpp@020b8000 {
478 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
479 reg = <0x020b8000 0x4000>;
480 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clks IMX6UL_CLK_KPP>;
482 status = "disabled";
483 };
484
a5fcccbc
FL		 485 wdog1: wdog@020bc000 {
486 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
487 reg = <0x020bc000 0x4000>;
488 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&clks IMX6UL_CLK_WDOG1>;
490 };
491
492 wdog2: wdog@020c0000 {
493 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
494 reg = <0x020c0000 0x4000>;
495 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clks IMX6UL_CLK_WDOG2>;
497 status = "disabled";
498 };
499
500 clks: ccm@020c4000 {
501 compatible = "fsl,imx6ul-ccm";
502 reg = <0x020c4000 0x4000>;
503 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
505 #clock-cells = <1>;
506 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
507 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
508 };
509
510 anatop: anatop@020c8000 {
511 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
512 "syscon", "simple-bus";
513 reg = <0x020c8000 0x1000>;
514 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
517
298701ec 518 reg_3p0: regulator-3p0 {
a5fcccbc
FL		 519 compatible = "fsl,anatop-regulator";
520 regulator-name = "vdd3p0";
521 regulator-min-microvolt = <2625000>;
522 regulator-max-microvolt = <3400000>;
523 anatop-reg-offset = <0x120>;
524 anatop-vol-bit-shift = <8>;
525 anatop-vol-bit-width = <5>;
526 anatop-min-bit-val = <0>;
527 anatop-min-voltage = <2625000>;
528 anatop-max-voltage = <3400000>;
529 anatop-enable-bit = <0>;
530 };
531
298701ec 532 reg_arm: regulator-vddcore {
a5fcccbc
FL		 533 compatible = "fsl,anatop-regulator";
534 regulator-name = "cpu";
535 regulator-min-microvolt = <725000>;
536 regulator-max-microvolt = <1450000>;
537 regulator-always-on;
538 anatop-reg-offset = <0x140>;
539 anatop-vol-bit-shift = <0>;
540 anatop-vol-bit-width = <5>;
541 anatop-delay-reg-offset = <0x170>;
542 anatop-delay-bit-shift = <24>;
543 anatop-delay-bit-width = <2>;
544 anatop-min-bit-val = <1>;
545 anatop-min-voltage = <725000>;
546 anatop-max-voltage = <1450000>;
547 };
548
298701ec 549 reg_soc: regulator-vddsoc {
a5fcccbc
FL		 550 compatible = "fsl,anatop-regulator";
551 regulator-name = "vddsoc";
552 regulator-min-microvolt = <725000>;
553 regulator-max-microvolt = <1450000>;
554 regulator-always-on;
555 anatop-reg-offset = <0x140>;
556 anatop-vol-bit-shift = <18>;
557 anatop-vol-bit-width = <5>;
558 anatop-delay-reg-offset = <0x170>;
559 anatop-delay-bit-shift = <28>;
560 anatop-delay-bit-width = <2>;
561 anatop-min-bit-val = <1>;
562 anatop-min-voltage = <725000>;
563 anatop-max-voltage = <1450000>;
564 };
565 };
566
567 usbphy1: usbphy@020c9000 {
568 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
569 reg = <0x020c9000 0x1000>;
570 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&clks IMX6UL_CLK_USBPHY1>;
572 phy-3p0-supply = <&reg_3p0>;
573 fsl,anatop = <&anatop>;
574 };
575
576 usbphy2: usbphy@020ca000 {
577 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
578 reg = <0x020ca000 0x1000>;
579 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&clks IMX6UL_CLK_USBPHY2>;
581 phy-3p0-supply = <&reg_3p0>;
582 fsl,anatop = <&anatop>;
583 };
584
5b032872
AH		 585 snvs: snvs@020cc000 {
586 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
587 reg = <0x020cc000 0x4000>;
588
589 snvs_rtc: snvs-rtc-lp {
590 compatible = "fsl,sec-v4.0-mon-rtc-lp";
591 regmap = <&snvs>;
592 offset = <0x34>;
593 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
595 };
36032575 596
ab0a05d8
AH		 597 snvs_poweroff: snvs-poweroff {
598 compatible = "syscon-poweroff";
599 regmap = <&snvs>;
600 offset = <0x38>;
601 mask = <0x60>;
602 status = "disabled";
603 };
604
36032575
AH		 605 snvs_pwrkey: snvs-powerkey {
606 compatible = "fsl,sec-v4.0-pwrkey";
607 regmap = <&snvs>;
608 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
609 linux,keycode = <KEY_POWER>;
610 wakeup-source;
611 };
5b032872
AH		 612 };
613
a5fcccbc
FL		 614 epit1: epit@020d0000 {
615 reg = <0x020d0000 0x4000>;
616 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
617 };
618
619 epit2: epit@020d4000 {
620 reg = <0x020d4000 0x4000>;
621 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
622 };
623
624 src: src@020d8000 {
625 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
626 reg = <0x020d8000 0x4000>;
627 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
629 #reset-cells = <1>;
630 };
631
632 gpc: gpc@020dc000 {
633 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
634 reg = <0x020dc000 0x4000>;
18619ff5
AH		 635 interrupt-controller;
636 #interrupt-cells = <3>;
a5fcccbc 637 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
18619ff5 638 interrupt-parent = <&intc>;
a5fcccbc
FL		 639 };
640
641 iomuxc: iomuxc@020e0000 {
642 compatible = "fsl,imx6ul-iomuxc";
643 reg = <0x020e0000 0x4000>;
644 };
645
646 gpr: iomuxc-gpr@020e4000 {
0f39c504
AH		 647 compatible = "fsl,imx6ul-iomuxc-gpr",
648 "fsl,imx6q-iomuxc-gpr", "syscon";
a5fcccbc
FL		 649 reg = <0x020e4000 0x4000>;
650 };
651
652 gpt2: gpt@020e8000 {
653 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
654 reg = <0x020e8000 0x4000>;
655 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
d97ca99f
LW		 656 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
657 <&clks IMX6UL_CLK_GPT2_SERIAL>;
a5fcccbc
FL		 658 clock-names = "ipg", "per";
659 };
660
76758c6a
LW		 661 sdma: sdma@020ec000 {
662 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
663 "fsl,imx35-sdma";
664 reg = <0x020ec000 0x4000>;
665 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clks IMX6UL_CLK_SDMA>,
667 <&clks IMX6UL_CLK_SDMA>;
668 clock-names = "ipg", "ahb";
669 #dma-cells = <3>;
670 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
671 };
672
a5fcccbc
FL		 673 pwm5: pwm@020f0000 {
674 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
675 reg = <0x020f0000 0x4000>;
676 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 677 clocks = <&clks IMX6UL_CLK_PWM5>,
678 <&clks IMX6UL_CLK_PWM5>;
a5fcccbc
FL		 679 clock-names = "ipg", "per";
680 #pwm-cells = <2>;
dd135095 681 status = "disabled";
a5fcccbc
FL		 682 };
683
684 pwm6: pwm@020f4000 {
685 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
686 reg = <0x020f4000 0x4000>;
687 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 688 clocks = <&clks IMX6UL_CLK_PWM6>,
689 <&clks IMX6UL_CLK_PWM6>;
a5fcccbc
FL		 690 clock-names = "ipg", "per";
691 #pwm-cells = <2>;
dd135095 692 status = "disabled";
a5fcccbc
FL		 693 };
694
695 pwm7: pwm@020f8000 {
696 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
697 reg = <0x020f8000 0x4000>;
698 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 699 clocks = <&clks IMX6UL_CLK_PWM7>,
700 <&clks IMX6UL_CLK_PWM7>;
a5fcccbc
FL		 701 clock-names = "ipg", "per";
702 #pwm-cells = <2>;
dd135095 703 status = "disabled";
a5fcccbc
FL		 704 };
705
706 pwm8: pwm@020fc000 {
707 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
708 reg = <0x020fc000 0x4000>;
709 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
c530d23a
LW		 710 clocks = <&clks IMX6UL_CLK_PWM8>,
711 <&clks IMX6UL_CLK_PWM8>;
a5fcccbc
FL		 712 clock-names = "ipg", "per";
713 #pwm-cells = <2>;
dd135095 714 status = "disabled";
a5fcccbc
FL		 715 };
716 };
717
718 aips2: aips-bus@02100000 {
719 compatible = "fsl,aips-bus", "simple-bus";
720 #address-cells = <1>;
721 #size-cells = <1>;
722 reg = <0x02100000 0x100000>;
723 ranges;
724
cad2cb69
FL		 725 usbotg1: usb@02184000 {
726 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
727 reg = <0x02184000 0x200>;
728 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&clks IMX6UL_CLK_USBOH3>;
730 fsl,usbphy = <&usbphy1>;
731 fsl,usbmisc = <&usbmisc 0>;
732 fsl,anatop = <&anatop>;
9493bf54 733 ahb-burst-config = <0x0>;
2b1a40e8
PC		 734 tx-burst-size-dword = <0x10>;
735 rx-burst-size-dword = <0x10>;
cad2cb69
FL		 736 status = "disabled";
737 };
738
739 usbotg2: usb@02184200 {
740 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
741 reg = <0x02184200 0x200>;
742 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clks IMX6UL_CLK_USBOH3>;
744 fsl,usbphy = <&usbphy2>;
745 fsl,usbmisc = <&usbmisc 1>;
9493bf54 746 ahb-burst-config = <0x0>;
2b1a40e8
PC		 747 tx-burst-size-dword = <0x10>;
748 rx-burst-size-dword = <0x10>;
cad2cb69
FL		 749 status = "disabled";
750 };
751
752 usbmisc: usbmisc@02184800 {
753 #index-cells = <1>;
754 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
755 reg = <0x02184800 0x200>;
756 };
757
01f3dc7d
FD		 758 fec1: ethernet@02188000 {
759 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
760 reg = <0x02188000 0x4000>;
761 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&clks IMX6UL_CLK_ENET>,
764 <&clks IMX6UL_CLK_ENET_AHB>,
765 <&clks IMX6UL_CLK_ENET_PTP>,
766 <&clks IMX6UL_CLK_ENET_REF>,
767 <&clks IMX6UL_CLK_ENET_REF>;
768 clock-names = "ipg", "ahb", "ptp",
769 "enet_clk_ref", "enet_out";
770 fsl,num-tx-queues=<1>;
771 fsl,num-rx-queues=<1>;
772 status = "disabled";
773 };
774
a5fcccbc
FL		 775 usdhc1: usdhc@02190000 {
776 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
777 reg = <0x02190000 0x4000>;
778 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clks IMX6UL_CLK_USDHC1>,
780 <&clks IMX6UL_CLK_USDHC1>,
781 <&clks IMX6UL_CLK_USDHC1>;
782 clock-names = "ipg", "ahb", "per";
783 bus-width = <4>;
784 status = "disabled";
785 };
786
787 usdhc2: usdhc@02194000 {
788 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
789 reg = <0x02194000 0x4000>;
790 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&clks IMX6UL_CLK_USDHC2>,
792 <&clks IMX6UL_CLK_USDHC2>,
793 <&clks IMX6UL_CLK_USDHC2>;
794 clock-names = "ipg", "ahb", "per";
795 bus-width = <4>;
796 status = "disabled";
797 };
798
aab8ec0c
FE		 799 adc1: adc@02198000 {
800 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
801 reg = <0x02198000 0x4000>;
802 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clks IMX6UL_CLK_ADC1>;
804 num-channels = <2>;
805 clock-names = "adc";
806 fsl,adck-max-frequency = <30000000>, <40000000>,
807 <20000000>;
808 status = "disabled";
809 };
810
a5fcccbc
FL		 811 i2c1: i2c@021a0000 {
812 #address-cells = <1>;
813 #size-cells = <0>;
814 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
815 reg = <0x021a0000 0x4000>;
816 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&clks IMX6UL_CLK_I2C1>;
818 status = "disabled";
819 };
820
821 i2c2: i2c@021a4000 {
822 #address-cells = <1>;
823 #size-cells = <0>;
824 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
825 reg = <0x021a4000 0x4000>;
826 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&clks IMX6UL_CLK_I2C2>;
828 status = "disabled";
829 };
830
831 i2c3: i2c@021a8000 {
832 #address-cells = <1>;
833 #size-cells = <0>;
834 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
835 reg = <0x021a8000 0x4000>;
836 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
837 clocks = <&clks IMX6UL_CLK_I2C3>;
838 status = "disabled";
839 };
840
51a37443
AH		 841 mmdc: mmdc@021b0000 {
842 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
843 reg = <0x021b0000 0x4000>;
844 };
845
6fe01eb7
LW		 846 lcdif: lcdif@021c8000 {
847 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
848 reg = <0x021c8000 0x4000>;
849 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
851 <&clks IMX6UL_CLK_LCDIF_APB>,
852 <&clks IMX6UL_CLK_DUMMY>;
853 clock-names = "pix", "axi", "disp_axi";
854 status = "disabled";
855 };
856
5ff807a5
FL		 857 qspi: qspi@021e0000 {
858 #address-cells = <1>;
859 #size-cells = <0>;
860 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
861 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
862 reg-names = "QuadSPI", "QuadSPI-memory";
863 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
864 clocks = <&clks IMX6UL_CLK_QSPI>,
865 <&clks IMX6UL_CLK_QSPI>;
866 clock-names = "qspi_en", "qspi";
867 status = "disabled";
868 };
869
a5fcccbc
FL		 870 uart2: serial@021e8000 {
871 compatible = "fsl,imx6ul-uart",
872 "fsl,imx6q-uart";
873 reg = <0x021e8000 0x4000>;
874 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
876 <&clks IMX6UL_CLK_UART2_SERIAL>;
877 clock-names = "ipg", "per";
878 status = "disabled";
879 };
880
881 uart3: serial@021ec000 {
882 compatible = "fsl,imx6ul-uart",
883 "fsl,imx6q-uart";
884 reg = <0x021ec000 0x4000>;
885 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
887 <&clks IMX6UL_CLK_UART3_SERIAL>;
888 clock-names = "ipg", "per";
889 status = "disabled";
890 };
891
892 uart4: serial@021f0000 {
893 compatible = "fsl,imx6ul-uart",
894 "fsl,imx6q-uart";
895 reg = <0x021f0000 0x4000>;
896 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
898 <&clks IMX6UL_CLK_UART4_SERIAL>;
899 clock-names = "ipg", "per";
900 status = "disabled";
901 };
902
903 uart5: serial@021f4000 {
904 compatible = "fsl,imx6ul-uart",
905 "fsl,imx6q-uart";
906 reg = <0x021f4000 0x4000>;
907 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
909 <&clks IMX6UL_CLK_UART5_SERIAL>;
910 clock-names = "ipg", "per";
911 status = "disabled";
912 };
913
914 i2c4: i2c@021f8000 {
915 #address-cells = <1>;
916 #size-cells = <0>;
917 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
918 reg = <0x021f8000 0x4000>;
919 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
920 clocks = <&clks IMX6UL_CLK_I2C4>;
921 status = "disabled";
922 };
923
924 uart6: serial@021fc000 {
925 compatible = "fsl,imx6ul-uart",
926 "fsl,imx6q-uart";
927 reg = <0x021fc000 0x4000>;
928 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
930 <&clks IMX6UL_CLK_UART6_SERIAL>;
931 clock-names = "ipg", "per";
932 status = "disabled";
933 };
934 };
935 };
936};
Empty description
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