[linux.git] / arch / arm / boot / dts / imx6ul.dtsi

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6ul-pinfunc.h"
#include "skeleton.dtsi"

/ {
	aliases {
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		serial6 = &uart7;
		serial7 = &uart8;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
		usbphy0 = &usbphy1;
		usbphy1 = &usbphy2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			clock-latency = <61036>; /* two CLK32 periods */
			operating-points = <
				/* kHz	uV */
				528000	1250000
				396000	1150000
				198000	1150000
			>;
			fsl,soc-operating-points = <
				/* KHz	uV */
				528000	1250000
				396000	1150000
				198000	1150000
			>;
			clocks = <&clks IMX6UL_CLK_ARM>,
				 <&clks IMX6UL_CLK_PLL2_BUS>,
				 <&clks IMX6UL_CLK_PLL2_PFD2>,
				 <&clks IMX6UL_CA7_SECONDARY_SEL>,
				 <&clks IMX6UL_CLK_STEP>,
				 <&clks IMX6UL_CLK_PLL1_SW>,
				 <&clks IMX6UL_CLK_PLL1_SYS>,
				 <&clks IMX6UL_PLL1_BYPASS>,
				 <&clks IMX6UL_CLK_PLL1>,
				 <&clks IMX6UL_PLL1_BYPASS_SRC>,
				 <&clks IMX6UL_CLK_OSC>;
			clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
				      "secondary_sel", "step", "pll1_sw",
				      "pll1_sys", "pll1_bypass", "pll1",
				      "pll1_bypass_src", "osc";
			arm-supply = <&reg_arm>;
			soc-supply = <&reg_soc>;
		};
	};

	intc: interrupt-controller@00a01000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00a01000 0x1000>,
		      <0x00a02000 0x1000>,
		      <0x00a04000 0x2000>,
		      <0x00a06000 0x2000>;
	};

	ckil: clock-cli {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ckil";
	};

	osc: clock-osc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc";
	};

	ipp_di0: clock-di0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "ipp_di0";
	};

	ipp_di1: clock-di1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "ipp_di1";
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		aips1: aips-bus@02000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba-bus@02000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				ecspi1: ecspi@02008000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ECSPI1>,
						 <&clks IMX6UL_CLK_ECSPI1>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi2: ecspi@0200c000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ECSPI2>,
						 <&clks IMX6UL_CLK_ECSPI2>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi3: ecspi@02010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ECSPI3>,
						 <&clks IMX6UL_CLK_ECSPI3>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi4: ecspi@02014000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_ECSPI4>,
						 <&clks IMX6UL_CLK_ECSPI4>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart7: serial@02018000 {
					compatible = "fsl,imx6ul-uart",
						     "fsl,imx6q-uart";
					reg = <0x02018000 0x4000>;
					interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_UART7_IPG>,
						 <&clks IMX6UL_CLK_UART7_SERIAL>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart1: serial@02020000 {
					compatible = "fsl,imx6ul-uart",
						     "fsl,imx6q-uart";
					reg = <0x02020000 0x4000>;
					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_UART1_IPG>,
						 <&clks IMX6UL_CLK_UART1_SERIAL>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart8: serial@02024000 {
					compatible = "fsl,imx6ul-uart",
						     "fsl,imx6q-uart";
					reg = <0x02024000 0x4000>;
					interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6UL_CLK_UART8_IPG>,
						 <&clks IMX6UL_CLK_UART8_SERIAL>;
					clock-names = "ipg", "per";
					status = "disabled";
				};
			};

			gpt1: gpt@02098000 {
				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
				reg = <0x02098000 0x4000>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
					 <&clks IMX6UL_CLK_GPT1_SERIAL>;
				clock-names = "ipg", "per";
			};

			gpio1: gpio@0209c000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x0209c000 0x4000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio@020a0000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a0000 0x4000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio@020a4000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a4000 0x4000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio4: gpio@020a8000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020a8000 0x4000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio5: gpio@020ac000 {
				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
				reg = <0x020ac000 0x4000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};

			fec2: ethernet@020b4000 {
				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
				reg = <0x020b4000 0x4000>;
				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_ENET>,
					 <&clks IMX6UL_CLK_ENET_AHB>,
					 <&clks IMX6UL_CLK_ENET_PTP>,
					 <&clks IMX6UL_CLK_ENET2_REF_125M>,
					 <&clks IMX6UL_CLK_ENET2_REF_125M>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				fsl,num-tx-queues=<1>;
				fsl,num-rx-queues=<1>;
				status = "disabled";
			};

			wdog1: wdog@020bc000 {
				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
				reg = <0x020bc000 0x4000>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_WDOG1>;
			};

			wdog2: wdog@020c0000 {
				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
				reg = <0x020c0000 0x4000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_WDOG2>;
				status = "disabled";
			};

			clks: ccm@020c4000 {
				compatible = "fsl,imx6ul-ccm";
				reg = <0x020c4000 0x4000>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
			};

			anatop: anatop@020c8000 {
				compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
					     "syscon", "simple-bus";
				reg = <0x020c8000 0x1000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

				reg_3p0: regulator-3p0@120 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd3p0";
					regulator-min-microvolt = <2625000>;
					regulator-max-microvolt = <3400000>;
					anatop-reg-offset = <0x120>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2625000>;
					anatop-max-voltage = <3400000>;
					anatop-enable-bit = <0>;
				};

				reg_arm: regulator-vddcore@140 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "cpu";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <0>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <24>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_soc: regulator-vddsoc@140 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddsoc";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <18>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <28>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};
			};

			usbphy1: usbphy@020c9000 {
				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
				reg = <0x020c9000 0x1000>;
				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USBPHY1>;
				phy-3p0-supply = <&reg_3p0>;
				fsl,anatop = <&anatop>;
			};

			usbphy2: usbphy@020ca000 {
				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
				reg = <0x020ca000 0x1000>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USBPHY2>;
				phy-3p0-supply = <&reg_3p0>;
				fsl,anatop = <&anatop>;
			};

			epit1: epit@020d0000 {
				reg = <0x020d0000 0x4000>;
				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			epit2: epit@020d4000 {
				reg = <0x020d4000 0x4000>;
				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			};

			src: src@020d8000 {
				compatible = "fsl,imx6ul-src", "fsl,imx51-src";
				reg = <0x020d8000 0x4000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@020dc000 {
				compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
				reg = <0x020dc000 0x4000>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			};

			iomuxc: iomuxc@020e0000 {
				compatible = "fsl,imx6ul-iomuxc";
				reg = <0x020e0000 0x4000>;
			};

			gpr: iomuxc-gpr@020e4000 {
				compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
				reg = <0x020e4000 0x4000>;
			};

			gpt2: gpt@020e8000 {
				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
				reg = <0x020e8000 0x4000>;
				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
			};

			pwm5: pwm@020f0000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f0000 0x4000>;
				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm6: pwm@020f4000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f4000 0x4000>;
				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm7: pwm@020f8000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020f8000 0x4000>;
				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm8: pwm@020fc000 {
				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
				reg = <0x020fc000 0x4000>;
				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_DUMMY>,
					 <&clks IMX6UL_CLK_DUMMY>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};
		};

		aips2: aips-bus@02100000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02100000 0x100000>;
			ranges;

			usbotg1: usb@02184000 {
				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
				reg = <0x02184000 0x200>;
				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy1>;
				fsl,usbmisc = <&usbmisc 0>;
				fsl,anatop = <&anatop>;
				status = "disabled";
			};

			usbotg2: usb@02184200 {
				compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
				reg = <0x02184200 0x200>;
				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USBOH3>;
				fsl,usbphy = <&usbphy2>;
				fsl,usbmisc = <&usbmisc 1>;
				status = "disabled";
			};

			usbmisc: usbmisc@02184800 {
				#index-cells = <1>;
				compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x02184800 0x200>;
			};

			fec1: ethernet@02188000 {
				compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
				reg = <0x02188000 0x4000>;
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_ENET>,
					 <&clks IMX6UL_CLK_ENET_AHB>,
					 <&clks IMX6UL_CLK_ENET_PTP>,
					 <&clks IMX6UL_CLK_ENET_REF>,
					 <&clks IMX6UL_CLK_ENET_REF>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				fsl,num-tx-queues=<1>;
				fsl,num-rx-queues=<1>;
				status = "disabled";
			};

			usdhc1: usdhc@02190000 {
				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
				reg = <0x02190000 0x4000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USDHC1>,
					 <&clks IMX6UL_CLK_USDHC1>,
					 <&clks IMX6UL_CLK_USDHC1>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: usdhc@02194000 {
				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
				reg = <0x02194000 0x4000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_USDHC2>,
					 <&clks IMX6UL_CLK_USDHC2>,
					 <&clks IMX6UL_CLK_USDHC2>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			i2c1: i2c@021a0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a0000 0x4000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_I2C1>;
				status = "disabled";
			};

			i2c2: i2c@021a4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a4000 0x4000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_I2C2>;
				status = "disabled";
			};

			i2c3: i2c@021a8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021a8000 0x4000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_I2C3>;
				status = "disabled";
			};

			qspi: qspi@021e0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_QSPI>,
					 <&clks IMX6UL_CLK_QSPI>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			uart2: serial@021e8000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021e8000 0x4000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART2_IPG>,
					 <&clks IMX6UL_CLK_UART2_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart3: serial@021ec000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021ec000 0x4000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART3_IPG>,
					 <&clks IMX6UL_CLK_UART3_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart4: serial@021f0000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021f0000 0x4000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART4_IPG>,
					 <&clks IMX6UL_CLK_UART4_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart5: serial@021f4000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021f4000 0x4000>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART5_IPG>,
					 <&clks IMX6UL_CLK_UART5_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			i2c4: i2c@021f8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
				reg = <0x021f8000 0x4000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_I2C4>;
				status = "disabled";
			};

			uart6: serial@021fc000 {
				compatible = "fsl,imx6ul-uart",
					     "fsl,imx6q-uart";
				reg = <0x021fc000 0x4000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6UL_CLK_UART6_IPG>,
					 <&clks IMX6UL_CLK_UART6_SERIAL>;
				clock-names = "ipg", "per";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
a5fcccbc FL	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <dt-bindings/clock/imx6ul-clock.h>
	10	#include <dt-bindings/gpio/gpio.h>
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12	#include "imx6ul-pinfunc.h"
	13	#include "skeleton.dtsi"
	14
	15	/ {
	16	aliases {
01f3dc7d FD	17	ethernet0 = &fec1;
01f3dc7d FD	18	ethernet1 = &fec2;
a5fcccbc FL	19	gpio0 = &gpio1;
	20	gpio1 = &gpio2;
	21	gpio2 = &gpio3;
	22	gpio3 = &gpio4;
	23	gpio4 = &gpio5;
	24	i2c0 = &i2c1;
	25	i2c1 = &i2c2;
	26	i2c2 = &i2c3;
	27	i2c3 = &i2c4;
	28	mmc0 = &usdhc1;
	29	mmc1 = &usdhc2;
	30	serial0 = &uart1;
	31	serial1 = &uart2;
	32	serial2 = &uart3;
	33	serial3 = &uart4;
	34	serial4 = &uart5;
	35	serial5 = &uart6;
	36	serial6 = &uart7;
	37	serial7 = &uart8;
	38	spi0 = &ecspi1;
	39	spi1 = &ecspi2;
	40	spi2 = &ecspi3;
	41	spi3 = &ecspi4;
	42	usbphy0 = &usbphy1;
	43	usbphy1 = &usbphy2;
	44	};
	45
	46	cpus {
	47	#address-cells = <1>;
	48	#size-cells = <0>;
	49
	50	cpu0: cpu@0 {
	51	compatible = "arm,cortex-a7";
	52	device_type = "cpu";
	53	reg = <0>;
	54	clock-latency = <61036>; /* two CLK32 periods */
	55	operating-points = <
	56	/* kHz uV */
	57	528000 1250000
	58	396000 1150000
	59	198000 1150000
	60	>;
	61	fsl,soc-operating-points = <
	62	/* KHz uV */
	63	528000 1250000
	64	396000 1150000
	65	198000 1150000
	66	>;
	67	clocks = <&clks IMX6UL_CLK_ARM>,
	68	<&clks IMX6UL_CLK_PLL2_BUS>,
	69	<&clks IMX6UL_CLK_PLL2_PFD2>,
	70	<&clks IMX6UL_CA7_SECONDARY_SEL>,
	71	<&clks IMX6UL_CLK_STEP>,
	72	<&clks IMX6UL_CLK_PLL1_SW>,
	73	<&clks IMX6UL_CLK_PLL1_SYS>,
	74	<&clks IMX6UL_PLL1_BYPASS>,
	75	<&clks IMX6UL_CLK_PLL1>,
	76	<&clks IMX6UL_PLL1_BYPASS_SRC>,
	77	<&clks IMX6UL_CLK_OSC>;
	78	clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
	79	"secondary_sel", "step", "pll1_sw",
	80	"pll1_sys", "pll1_bypass", "pll1",
	81	"pll1_bypass_src", "osc";
	82	arm-supply = <&reg_arm>;
83	soc-supply = <&reg_soc>;
84	};
85	};
86
87	intc: interrupt-controller@00a01000 {
88	compatible = "arm,cortex-a7-gic";
89	#interrupt-cells = <3>;
90	interrupt-controller;
91	reg = <0x00a01000 0x1000>,
92	<0x00a02000 0x1000>,
93	<0x00a04000 0x2000>,
94	<0x00a06000 0x2000>;
95	};
96
97	ckil: clock-cli {
98	compatible = "fixed-clock";
99	#clock-cells = <0>;
100	clock-frequency = <32768>;
101	clock-output-names = "ckil";
102	};
103
104	osc: clock-osc {
105	compatible = "fixed-clock";
106	#clock-cells = <0>;
107	clock-frequency = <24000000>;
108	clock-output-names = "osc";
109	};
110
111	ipp_di0: clock-di0 {
112	compatible = "fixed-clock";
113	#clock-cells = <0>;
114	clock-frequency = <0>;
115	clock-output-names = "ipp_di0";
116	};
117
118	ipp_di1: clock-di1 {
119	compatible = "fixed-clock";
120	#clock-cells = <0>;
121	clock-frequency = <0>;
122	clock-output-names = "ipp_di1";
123	};
124
125	soc {
126	#address-cells = <1>;
127	#size-cells = <1>;
128	compatible = "simple-bus";
129	interrupt-parent = <&intc>;
130	ranges;
131
132	pmu {
133	compatible = "arm,cortex-a7-pmu";
134	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
135	status = "disabled";
136	};
137
138	aips1: aips-bus@02000000 {
139	compatible = "fsl,aips-bus", "simple-bus";
140	#address-cells = <1>;
141	#size-cells = <1>;
142	reg = <0x02000000 0x100000>;
143	ranges;
144
145	spba-bus@02000000 {
146	compatible = "fsl,spba-bus", "simple-bus";
147	#address-cells = <1>;
148	#size-cells = <1>;
149	reg = <0x02000000 0x40000>;
150	ranges;
151
152	ecspi1: ecspi@02008000 {
153	#address-cells = <1>;
154	#size-cells = <0>;
155	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
156	reg = <0x02008000 0x4000>;
157	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
158	clocks = <&clks IMX6UL_CLK_ECSPI1>,
159	<&clks IMX6UL_CLK_ECSPI1>;
160	clock-names = "ipg", "per";
161	status = "disabled";
162	};
163
164	ecspi2: ecspi@0200c000 {
165	#address-cells = <1>;
166	#size-cells = <0>;
167	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
168	reg = <0x0200c000 0x4000>;
169	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
170	clocks = <&clks IMX6UL_CLK_ECSPI2>,
171	<&clks IMX6UL_CLK_ECSPI2>;
172	clock-names = "ipg", "per";
173	status = "disabled";
174	};
175
176	ecspi3: ecspi@02010000 {
177	#address-cells = <1>;
178	#size-cells = <0>;
179	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
180	reg = <0x02010000 0x4000>;
181	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
182	clocks = <&clks IMX6UL_CLK_ECSPI3>,
183	<&clks IMX6UL_CLK_ECSPI3>;
184	clock-names = "ipg", "per";
185	status = "disabled";
186	};
187
188	ecspi4: ecspi@02014000 {
189	#address-cells = <1>;
190	#size-cells = <0>;
191	compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
192	reg = <0x02014000 0x4000>;
193	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
194	clocks = <&clks IMX6UL_CLK_ECSPI4>,
195	<&clks IMX6UL_CLK_ECSPI4>;
196	clock-names = "ipg", "per";
197	status = "disabled";
198	};
199
200	uart7: serial@02018000 {
201	compatible = "fsl,imx6ul-uart",
202	"fsl,imx6q-uart";
203	reg = <0x02018000 0x4000>;
204	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
205	clocks = <&clks IMX6UL_CLK_UART7_IPG>,
206	<&clks IMX6UL_CLK_UART7_SERIAL>;
207	clock-names = "ipg", "per";
208	status = "disabled";
209	};
210
211	uart1: serial@02020000 {
212	compatible = "fsl,imx6ul-uart",
213	"fsl,imx6q-uart";
214	reg = <0x02020000 0x4000>;
215	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
216	clocks = <&clks IMX6UL_CLK_UART1_IPG>,
217	<&clks IMX6UL_CLK_UART1_SERIAL>;
218	clock-names = "ipg", "per";
219	status = "disabled";
220	};
221
222	uart8: serial@02024000 {
223	compatible = "fsl,imx6ul-uart",
224	"fsl,imx6q-uart";
225	reg = <0x02024000 0x4000>;
226	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
227	clocks = <&clks IMX6UL_CLK_UART8_IPG>,
228	<&clks IMX6UL_CLK_UART8_SERIAL>;
229	clock-names = "ipg", "per";
230	status = "disabled";
231	};
232	};
233
234	gpt1: gpt@02098000 {
235	compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
236	reg = <0x02098000 0x4000>;
237	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
238	clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
239	<&clks IMX6UL_CLK_GPT1_SERIAL>;
240	clock-names = "ipg", "per";
241	};
242
243	gpio1: gpio@0209c000 {
244	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
245	reg = <0x0209c000 0x4000>;
246	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
247	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
248	gpio-controller;
249	#gpio-cells = <2>;
250	interrupt-controller;
251	#interrupt-cells = <2>;
252	};
253
254	gpio2: gpio@020a0000 {
255	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
256	reg = <0x020a0000 0x4000>;
257	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
258	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
259	gpio-controller;
260	#gpio-cells = <2>;
261	interrupt-controller;
262	#interrupt-cells = <2>;
263	};
264
265	gpio3: gpio@020a4000 {
266	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
267	reg = <0x020a4000 0x4000>;
268	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
269	<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
270	gpio-controller;
271	#gpio-cells = <2>;
272	interrupt-controller;
273	#interrupt-cells = <2>;
274	};
275
276	gpio4: gpio@020a8000 {
277	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
278	reg = <0x020a8000 0x4000>;
279	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
280	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
281	gpio-controller;
282	#gpio-cells = <2>;
283	interrupt-controller;
284	#interrupt-cells = <2>;
285	};
286
287	gpio5: gpio@020ac000 {
288	compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
289	reg = <0x020ac000 0x4000>;
290	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
291	<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
292	gpio-controller;
293	#gpio-cells = <2>;
294	interrupt-controller;
295	#interrupt-cells = <2>;
296	};
297
01f3dc7d FD	298	fec2: ethernet@020b4000 {
	299	compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
	300	reg = <0x020b4000 0x4000>;
	301	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
	302	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
	303	clocks = <&clks IMX6UL_CLK_ENET>,
	304	<&clks IMX6UL_CLK_ENET_AHB>,
	305	<&clks IMX6UL_CLK_ENET_PTP>,
	306	<&clks IMX6UL_CLK_ENET2_REF_125M>,
	307	<&clks IMX6UL_CLK_ENET2_REF_125M>;
	308	clock-names = "ipg", "ahb", "ptp",
	309	"enet_clk_ref", "enet_out";
	310	fsl,num-tx-queues=<1>;
	311	fsl,num-rx-queues=<1>;
	312	status = "disabled";
	313	};
	314
a5fcccbc FL	315	wdog1: wdog@020bc000 {
	316	compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
	317	reg = <0x020bc000 0x4000>;
	318	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
	319	clocks = <&clks IMX6UL_CLK_WDOG1>;
	320	};
	321
	322	wdog2: wdog@020c0000 {
	323	compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
	324	reg = <0x020c0000 0x4000>;
	325	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	326	clocks = <&clks IMX6UL_CLK_WDOG2>;
	327	status = "disabled";
	328	};
	329
	330	clks: ccm@020c4000 {
	331	compatible = "fsl,imx6ul-ccm";
	332	reg = <0x020c4000 0x4000>;
	333	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	334	<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	335	#clock-cells = <1>;
	336	clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
	337	clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
	338	};
	339
	340	anatop: anatop@020c8000 {
	341	compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
	342	"syscon", "simple-bus";
	343	reg = <0x020c8000 0x1000>;
	344	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	345	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	346	<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
	347
	348	reg_3p0: regulator-3p0@120 {
	349	compatible = "fsl,anatop-regulator";
	350	regulator-name = "vdd3p0";
	351	regulator-min-microvolt = <2625000>;
	352	regulator-max-microvolt = <3400000>;
	353	anatop-reg-offset = <0x120>;
	354	anatop-vol-bit-shift = <8>;
	355	anatop-vol-bit-width = <5>;
	356	anatop-min-bit-val = <0>;
	357	anatop-min-voltage = <2625000>;
	358	anatop-max-voltage = <3400000>;
	359	anatop-enable-bit = <0>;
	360	};
	361
	362	reg_arm: regulator-vddcore@140 {
	363	compatible = "fsl,anatop-regulator";
	364	regulator-name = "cpu";
	365	regulator-min-microvolt = <725000>;
	366	regulator-max-microvolt = <1450000>;
	367	regulator-always-on;
	368	anatop-reg-offset = <0x140>;
	369	anatop-vol-bit-shift = <0>;
	370	anatop-vol-bit-width = <5>;
	371	anatop-delay-reg-offset = <0x170>;
	372	anatop-delay-bit-shift = <24>;
	373	anatop-delay-bit-width = <2>;
	374	anatop-min-bit-val = <1>;
	375	anatop-min-voltage = <725000>;
	376	anatop-max-voltage = <1450000>;
	377	};
	378
379	reg_soc: regulator-vddsoc@140 {
380	compatible = "fsl,anatop-regulator";
381	regulator-name = "vddsoc";
382	regulator-min-microvolt = <725000>;
383	regulator-max-microvolt = <1450000>;
384	regulator-always-on;
385	anatop-reg-offset = <0x140>;
386	anatop-vol-bit-shift = <18>;
387	anatop-vol-bit-width = <5>;
388	anatop-delay-reg-offset = <0x170>;
389	anatop-delay-bit-shift = <28>;
390	anatop-delay-bit-width = <2>;
391	anatop-min-bit-val = <1>;
392	anatop-min-voltage = <725000>;
393	anatop-max-voltage = <1450000>;
394	};
395	};
396
397	usbphy1: usbphy@020c9000 {
398	compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
399	reg = <0x020c9000 0x1000>;
400	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
401	clocks = <&clks IMX6UL_CLK_USBPHY1>;
402	phy-3p0-supply = <&reg_3p0>;
403	fsl,anatop = <&anatop>;
404	};
405
406	usbphy2: usbphy@020ca000 {
407	compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
408	reg = <0x020ca000 0x1000>;
409	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
410	clocks = <&clks IMX6UL_CLK_USBPHY2>;
411	phy-3p0-supply = <&reg_3p0>;
412	fsl,anatop = <&anatop>;
413	};
414
415	epit1: epit@020d0000 {
416	reg = <0x020d0000 0x4000>;
417	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
418	};
419
420	epit2: epit@020d4000 {
421	reg = <0x020d4000 0x4000>;
422	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
423	};
424
425	src: src@020d8000 {
426	compatible = "fsl,imx6ul-src", "fsl,imx51-src";
427	reg = <0x020d8000 0x4000>;
428	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
429	<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
430	#reset-cells = <1>;
431	};
432
433	gpc: gpc@020dc000 {
434	compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
435	reg = <0x020dc000 0x4000>;
436	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
437	};
438
439	iomuxc: iomuxc@020e0000 {
440	compatible = "fsl,imx6ul-iomuxc";
441	reg = <0x020e0000 0x4000>;
442	};
443
444	gpr: iomuxc-gpr@020e4000 {
445	compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
446	reg = <0x020e4000 0x4000>;
447	};
448
449	gpt2: gpt@020e8000 {
450	compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
451	reg = <0x020e8000 0x4000>;
452	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
453	clocks = <&clks IMX6UL_CLK_DUMMY>,
454	<&clks IMX6UL_CLK_DUMMY>;
455	clock-names = "ipg", "per";
456	};
457
458	pwm5: pwm@020f0000 {
459	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
460	reg = <0x020f0000 0x4000>;
461	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
462	clocks = <&clks IMX6UL_CLK_DUMMY>,
463	<&clks IMX6UL_CLK_DUMMY>;
464	clock-names = "ipg", "per";
465	#pwm-cells = <2>;
466	};
467
468	pwm6: pwm@020f4000 {
469	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
470	reg = <0x020f4000 0x4000>;
471	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
472	clocks = <&clks IMX6UL_CLK_DUMMY>,
473	<&clks IMX6UL_CLK_DUMMY>;
474	clock-names = "ipg", "per";
475	#pwm-cells = <2>;
476	};
477
478	pwm7: pwm@020f8000 {
479	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
480	reg = <0x020f8000 0x4000>;
481	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
482	clocks = <&clks IMX6UL_CLK_DUMMY>,
483	<&clks IMX6UL_CLK_DUMMY>;
484	clock-names = "ipg", "per";
485	#pwm-cells = <2>;
486	};
487
488	pwm8: pwm@020fc000 {
489	compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
490	reg = <0x020fc000 0x4000>;
491	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
492	clocks = <&clks IMX6UL_CLK_DUMMY>,
493	<&clks IMX6UL_CLK_DUMMY>;
494	clock-names = "ipg", "per";
495	#pwm-cells = <2>;
496	};
497	};
498
499	aips2: aips-bus@02100000 {
500	compatible = "fsl,aips-bus", "simple-bus";
501	#address-cells = <1>;
502	#size-cells = <1>;
503	reg = <0x02100000 0x100000>;
504	ranges;
505
cad2cb69 FL	506	usbotg1: usb@02184000 {
	507	compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
	508	reg = <0x02184000 0x200>;
	509	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	510	clocks = <&clks IMX6UL_CLK_USBOH3>;
	511	fsl,usbphy = <&usbphy1>;
	512	fsl,usbmisc = <&usbmisc 0>;
	513	fsl,anatop = <&anatop>;
	514	status = "disabled";
	515	};
	516
	517	usbotg2: usb@02184200 {
	518	compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
	519	reg = <0x02184200 0x200>;
	520	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	521	clocks = <&clks IMX6UL_CLK_USBOH3>;
	522	fsl,usbphy = <&usbphy2>;
	523	fsl,usbmisc = <&usbmisc 1>;
	524	status = "disabled";
	525	};
	526
	527	usbmisc: usbmisc@02184800 {
	528	#index-cells = <1>;
	529	compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
	530	reg = <0x02184800 0x200>;
	531	};
	532
01f3dc7d FD	533	fec1: ethernet@02188000 {
	534	compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
	535	reg = <0x02188000 0x4000>;
	536	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	537	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	538	clocks = <&clks IMX6UL_CLK_ENET>,
	539	<&clks IMX6UL_CLK_ENET_AHB>,
	540	<&clks IMX6UL_CLK_ENET_PTP>,
	541	<&clks IMX6UL_CLK_ENET_REF>,
	542	<&clks IMX6UL_CLK_ENET_REF>;
	543	clock-names = "ipg", "ahb", "ptp",
	544	"enet_clk_ref", "enet_out";
	545	fsl,num-tx-queues=<1>;
	546	fsl,num-rx-queues=<1>;
	547	status = "disabled";
	548	};
	549
a5fcccbc FL	550	usdhc1: usdhc@02190000 {
	551	compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
	552	reg = <0x02190000 0x4000>;
	553	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
	554	clocks = <&clks IMX6UL_CLK_USDHC1>,
	555	<&clks IMX6UL_CLK_USDHC1>,
	556	<&clks IMX6UL_CLK_USDHC1>;
	557	clock-names = "ipg", "ahb", "per";
	558	bus-width = <4>;
	559	status = "disabled";
	560	};
	561
	562	usdhc2: usdhc@02194000 {
	563	compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
	564	reg = <0x02194000 0x4000>;
	565	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	566	clocks = <&clks IMX6UL_CLK_USDHC2>,
	567	<&clks IMX6UL_CLK_USDHC2>,
	568	<&clks IMX6UL_CLK_USDHC2>;
	569	clock-names = "ipg", "ahb", "per";
	570	bus-width = <4>;
	571	status = "disabled";
	572	};
	573
	574	i2c1: i2c@021a0000 {
	575	#address-cells = <1>;
	576	#size-cells = <0>;
	577	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
	578	reg = <0x021a0000 0x4000>;
	579	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	580	clocks = <&clks IMX6UL_CLK_I2C1>;
	581	status = "disabled";
	582	};
	583
	584	i2c2: i2c@021a4000 {
	585	#address-cells = <1>;
	586	#size-cells = <0>;
	587	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
	588	reg = <0x021a4000 0x4000>;
	589	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	590	clocks = <&clks IMX6UL_CLK_I2C2>;
	591	status = "disabled";
	592	};
	593
	594	i2c3: i2c@021a8000 {
	595	#address-cells = <1>;
	596	#size-cells = <0>;
	597	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
	598	reg = <0x021a8000 0x4000>;
	599	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	600	clocks = <&clks IMX6UL_CLK_I2C3>;
	601	status = "disabled";
	602	};
	603
5ff807a5 FL	604	qspi: qspi@021e0000 {
	605	#address-cells = <1>;
	606	#size-cells = <0>;
	607	compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
	608	reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
	609	reg-names = "QuadSPI", "QuadSPI-memory";
	610	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	611	clocks = <&clks IMX6UL_CLK_QSPI>,
	612	<&clks IMX6UL_CLK_QSPI>;
	613	clock-names = "qspi_en", "qspi";
	614	status = "disabled";
	615	};
	616
a5fcccbc FL	617	uart2: serial@021e8000 {
	618	compatible = "fsl,imx6ul-uart",
	619	"fsl,imx6q-uart";
	620	reg = <0x021e8000 0x4000>;
	621	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	622	clocks = <&clks IMX6UL_CLK_UART2_IPG>,
	623	<&clks IMX6UL_CLK_UART2_SERIAL>;
	624	clock-names = "ipg", "per";
	625	status = "disabled";
	626	};
	627
	628	uart3: serial@021ec000 {
	629	compatible = "fsl,imx6ul-uart",
	630	"fsl,imx6q-uart";
	631	reg = <0x021ec000 0x4000>;
	632	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	633	clocks = <&clks IMX6UL_CLK_UART3_IPG>,
	634	<&clks IMX6UL_CLK_UART3_SERIAL>;
	635	clock-names = "ipg", "per";
	636	status = "disabled";
	637	};
	638
	639	uart4: serial@021f0000 {
	640	compatible = "fsl,imx6ul-uart",
	641	"fsl,imx6q-uart";
	642	reg = <0x021f0000 0x4000>;
	643	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	644	clocks = <&clks IMX6UL_CLK_UART4_IPG>,
	645	<&clks IMX6UL_CLK_UART4_SERIAL>;
	646	clock-names = "ipg", "per";
	647	status = "disabled";
	648	};
	649
	650	uart5: serial@021f4000 {
	651	compatible = "fsl,imx6ul-uart",
	652	"fsl,imx6q-uart";
	653	reg = <0x021f4000 0x4000>;
	654	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	655	clocks = <&clks IMX6UL_CLK_UART5_IPG>,
	656	<&clks IMX6UL_CLK_UART5_SERIAL>;
	657	clock-names = "ipg", "per";
	658	status = "disabled";
	659	};
	660
	661	i2c4: i2c@021f8000 {
	662	#address-cells = <1>;
	663	#size-cells = <0>;
	664	compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
	665	reg = <0x021f8000 0x4000>;
	666	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
	667	clocks = <&clks IMX6UL_CLK_I2C4>;
	668	status = "disabled";
	669	};
	670
	671	uart6: serial@021fc000 {
	672	compatible = "fsl,imx6ul-uart",
	673	"fsl,imx6q-uart";
	674	reg = <0x021fc000 0x4000>;
	675	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	676	clocks = <&clks IMX6UL_CLK_UART6_IPG>,
	677	<&clks IMX6UL_CLK_UART6_SERIAL>;
	678	clock-names = "ipg", "per";
	679	status = "disabled";
	680	};
681	};
682	};
683	};