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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Pentium 4/Xeon CPU on demand clock modulation/speed scaling | |
3 | * (C) 2002 - 2003 Dominik Brodowski <[email protected]> | |
4 | * (C) 2002 Zwane Mwaikambo <[email protected]> | |
5 | * (C) 2002 Arjan van de Ven <[email protected]> | |
6 | * (C) 2002 Tora T. Engstad | |
7 | * All Rights Reserved | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * The author(s) of this software shall not be held liable for damages | |
15 | * of any nature resulting due to the use of this software. This | |
16 | * software is provided AS-IS with no warranties. | |
32ee8c3e | 17 | * |
1da177e4 LT |
18 | * Date Errata Description |
19 | * 20020525 N44, O17 12.5% or 25% DC causes lockup | |
20 | * | |
21 | */ | |
22 | ||
1da177e4 | 23 | #include <linux/kernel.h> |
32ee8c3e | 24 | #include <linux/module.h> |
1da177e4 LT |
25 | #include <linux/init.h> |
26 | #include <linux/smp.h> | |
27 | #include <linux/cpufreq.h> | |
1da177e4 | 28 | #include <linux/cpumask.h> |
bbfebd66 | 29 | #include <linux/timex.h> |
1da177e4 | 30 | |
32ee8c3e | 31 | #include <asm/processor.h> |
1da177e4 | 32 | #include <asm/msr.h> |
199785ea | 33 | #include <asm/timer.h> |
1da177e4 LT |
34 | |
35 | #include "speedstep-lib.h" | |
36 | ||
37 | #define PFX "p4-clockmod: " | |
1da177e4 LT |
38 | |
39 | /* | |
40 | * Duty Cycle (3bits), note DC_DISABLE is not specified in | |
41 | * intel docs i just use it to mean disable | |
42 | */ | |
43 | enum { | |
44 | DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT, | |
45 | DC_64PT, DC_75PT, DC_88PT, DC_DISABLE | |
46 | }; | |
47 | ||
48 | #define DC_ENTRIES 8 | |
49 | ||
50 | ||
51 | static int has_N44_O17_errata[NR_CPUS]; | |
52 | static unsigned int stock_freq; | |
53 | static struct cpufreq_driver p4clockmod_driver; | |
54 | static unsigned int cpufreq_p4_get(unsigned int cpu); | |
55 | ||
56 | static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate) | |
57 | { | |
58 | u32 l, h; | |
59 | ||
bbfebd66 DJ |
60 | if (!cpu_online(cpu) || |
61 | (newstate > DC_DISABLE) || (newstate == DC_RESV)) | |
1da177e4 LT |
62 | return -EINVAL; |
63 | ||
551948bc | 64 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h); |
1da177e4 LT |
65 | |
66 | if (l & 0x01) | |
2d06d8c4 | 67 | pr_debug("CPU#%d currently thermal throttled\n", cpu); |
1da177e4 | 68 | |
bbfebd66 DJ |
69 | if (has_N44_O17_errata[cpu] && |
70 | (newstate == DC_25PT || newstate == DC_DFLT)) | |
1da177e4 LT |
71 | newstate = DC_38PT; |
72 | ||
551948bc | 73 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); |
1da177e4 | 74 | if (newstate == DC_DISABLE) { |
2d06d8c4 | 75 | pr_debug("CPU#%d disabling modulation\n", cpu); |
551948bc | 76 | wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h); |
1da177e4 | 77 | } else { |
2d06d8c4 | 78 | pr_debug("CPU#%d setting duty cycle to %d%%\n", |
1da177e4 | 79 | cpu, ((125 * newstate) / 10)); |
32ee8c3e | 80 | /* bits 63 - 5 : reserved |
1da177e4 LT |
81 | * bit 4 : enable/disable |
82 | * bits 3-1 : duty cycle | |
83 | * bit 0 : reserved | |
84 | */ | |
85 | l = (l & ~14); | |
86 | l = l | (1<<4) | ((newstate & 0x7)<<1); | |
551948bc | 87 | wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h); |
1da177e4 LT |
88 | } |
89 | ||
90 | return 0; | |
91 | } | |
92 | ||
93 | ||
94 | static struct cpufreq_frequency_table p4clockmod_table[] = { | |
95 | {DC_RESV, CPUFREQ_ENTRY_INVALID}, | |
96 | {DC_DFLT, 0}, | |
97 | {DC_25PT, 0}, | |
98 | {DC_38PT, 0}, | |
99 | {DC_50PT, 0}, | |
100 | {DC_64PT, 0}, | |
101 | {DC_75PT, 0}, | |
102 | {DC_88PT, 0}, | |
103 | {DC_DISABLE, 0}, | |
104 | {DC_RESV, CPUFREQ_TABLE_END}, | |
105 | }; | |
106 | ||
107 | ||
108 | static int cpufreq_p4_target(struct cpufreq_policy *policy, | |
109 | unsigned int target_freq, | |
110 | unsigned int relation) | |
111 | { | |
112 | unsigned int newstate = DC_RESV; | |
113 | struct cpufreq_freqs freqs; | |
1da177e4 LT |
114 | int i; |
115 | ||
bbfebd66 DJ |
116 | if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], |
117 | target_freq, relation, &newstate)) | |
1da177e4 LT |
118 | return -EINVAL; |
119 | ||
120 | freqs.old = cpufreq_p4_get(policy->cpu); | |
121 | freqs.new = stock_freq * p4clockmod_table[newstate].index / 8; | |
122 | ||
123 | if (freqs.new == freqs.old) | |
124 | return 0; | |
125 | ||
126 | /* notifiers */ | |
835481d9 | 127 | for_each_cpu(i, policy->cpus) { |
1da177e4 LT |
128 | freqs.cpu = i; |
129 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
130 | } | |
131 | ||
bbfebd66 DJ |
132 | /* run on each logical CPU, |
133 | * see section 13.15.3 of IA32 Intel Architecture Software | |
32ee8c3e | 134 | * Developer's Manual, Volume 3 |
1da177e4 | 135 | */ |
835481d9 | 136 | for_each_cpu(i, policy->cpus) |
1da177e4 | 137 | cpufreq_p4_setdc(i, p4clockmod_table[newstate].index); |
1da177e4 LT |
138 | |
139 | /* notifiers */ | |
835481d9 | 140 | for_each_cpu(i, policy->cpus) { |
1da177e4 LT |
141 | freqs.cpu = i; |
142 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
143 | } | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | ||
149 | static int cpufreq_p4_verify(struct cpufreq_policy *policy) | |
150 | { | |
151 | return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]); | |
152 | } | |
153 | ||
154 | ||
155 | static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c) | |
156 | { | |
4e74663c DB |
157 | if (c->x86 == 0x06) { |
158 | if (cpu_has(c, X86_FEATURE_EST)) | |
853cee26 NC |
159 | printk_once(KERN_WARNING PFX "Warning: EST-capable " |
160 | "CPU detected. The acpi-cpufreq module offers " | |
161 | "voltage scaling in addition to frequency " | |
bbfebd66 DJ |
162 | "scaling. You should use that instead of " |
163 | "p4-clockmod, if possible.\n"); | |
4e74663c DB |
164 | switch (c->x86_model) { |
165 | case 0x0E: /* Core */ | |
166 | case 0x0F: /* Core Duo */ | |
8529154e | 167 | case 0x16: /* Celeron Core */ |
43195037 | 168 | case 0x1C: /* Atom */ |
4e74663c | 169 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; |
bbfebd66 | 170 | return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE); |
4e74663c DB |
171 | case 0x0D: /* Pentium M (Dothan) */ |
172 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; | |
173 | /* fall through */ | |
174 | case 0x09: /* Pentium M (Banias) */ | |
bbfebd66 | 175 | return speedstep_get_frequency(SPEEDSTEP_CPU_PM); |
4e74663c | 176 | } |
1da177e4 LT |
177 | } |
178 | ||
9d1f44ee | 179 | if (c->x86 != 0xF) |
1da177e4 | 180 | return 0; |
1da177e4 LT |
181 | |
182 | /* on P-4s, the TSC runs with constant frequency independent whether | |
183 | * throttling is active or not. */ | |
184 | p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS; | |
185 | ||
bbfebd66 | 186 | if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) { |
1da177e4 LT |
187 | printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. " |
188 | "The speedstep-ich or acpi cpufreq modules offer " | |
189 | "voltage scaling in addition of frequency scaling. " | |
190 | "You should use either one instead of p4-clockmod, " | |
191 | "if possible.\n"); | |
bbfebd66 | 192 | return speedstep_get_frequency(SPEEDSTEP_CPU_P4M); |
1da177e4 LT |
193 | } |
194 | ||
bbfebd66 | 195 | return speedstep_get_frequency(SPEEDSTEP_CPU_P4D); |
1da177e4 LT |
196 | } |
197 | ||
32ee8c3e | 198 | |
1da177e4 LT |
199 | |
200 | static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy) | |
201 | { | |
92cb7612 | 202 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
1da177e4 LT |
203 | int cpuid = 0; |
204 | unsigned int i; | |
205 | ||
206 | #ifdef CONFIG_SMP | |
7ad728f9 | 207 | cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu)); |
1da177e4 LT |
208 | #endif |
209 | ||
210 | /* Errata workaround */ | |
211 | cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask; | |
212 | switch (cpuid) { | |
213 | case 0x0f07: | |
214 | case 0x0f0a: | |
215 | case 0x0f11: | |
216 | case 0x0f12: | |
217 | has_N44_O17_errata[policy->cpu] = 1; | |
2d06d8c4 | 218 | pr_debug("has errata -- disabling low frequencies\n"); |
1da177e4 | 219 | } |
32ee8c3e | 220 | |
199785ea MCO |
221 | if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D && |
222 | c->x86_model < 2) { | |
223 | /* switch to maximum frequency and measure result */ | |
224 | cpufreq_p4_setdc(policy->cpu, DC_DISABLE); | |
225 | recalibrate_cpu_khz(); | |
226 | } | |
1da177e4 LT |
227 | /* get max frequency */ |
228 | stock_freq = cpufreq_p4_get_frequency(c); | |
229 | if (!stock_freq) | |
230 | return -EINVAL; | |
231 | ||
232 | /* table init */ | |
bbfebd66 DJ |
233 | for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) { |
234 | if ((i < 2) && (has_N44_O17_errata[policy->cpu])) | |
1da177e4 LT |
235 | p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID; |
236 | else | |
237 | p4clockmod_table[i].frequency = (stock_freq * i)/8; | |
238 | } | |
239 | cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu); | |
32ee8c3e | 240 | |
1da177e4 | 241 | /* cpuinfo and default policy values */ |
36e8abf3 DJ |
242 | |
243 | /* the transition latency is set to be 1 higher than the maximum | |
244 | * transition latency of the ondemand governor */ | |
245 | policy->cpuinfo.transition_latency = 10000001; | |
1da177e4 LT |
246 | policy->cur = stock_freq; |
247 | ||
248 | return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]); | |
249 | } | |
250 | ||
251 | ||
252 | static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy) | |
253 | { | |
32ee8c3e | 254 | cpufreq_frequency_table_put_attr(policy->cpu); |
1da177e4 LT |
255 | return 0; |
256 | } | |
257 | ||
258 | static unsigned int cpufreq_p4_get(unsigned int cpu) | |
259 | { | |
1da177e4 LT |
260 | u32 l, h; |
261 | ||
551948bc | 262 | rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h); |
1da177e4 LT |
263 | |
264 | if (l & 0x10) { | |
265 | l = l >> 1; | |
266 | l &= 0x7; | |
267 | } else | |
268 | l = DC_DISABLE; | |
269 | ||
270 | if (l != DC_DISABLE) | |
bbfebd66 | 271 | return stock_freq * l / 8; |
1da177e4 LT |
272 | |
273 | return stock_freq; | |
274 | } | |
275 | ||
bbfebd66 | 276 | static struct freq_attr *p4clockmod_attr[] = { |
1da177e4 LT |
277 | &cpufreq_freq_attr_scaling_available_freqs, |
278 | NULL, | |
279 | }; | |
280 | ||
281 | static struct cpufreq_driver p4clockmod_driver = { | |
32ee8c3e | 282 | .verify = cpufreq_p4_verify, |
1da177e4 LT |
283 | .target = cpufreq_p4_target, |
284 | .init = cpufreq_p4_cpu_init, | |
285 | .exit = cpufreq_p4_cpu_exit, | |
286 | .get = cpufreq_p4_get, | |
287 | .name = "p4-clockmod", | |
288 | .owner = THIS_MODULE, | |
289 | .attr = p4clockmod_attr, | |
290 | }; | |
291 | ||
292 | ||
293 | static int __init cpufreq_p4_init(void) | |
32ee8c3e | 294 | { |
92cb7612 | 295 | struct cpuinfo_x86 *c = &cpu_data(0); |
1da177e4 LT |
296 | int ret; |
297 | ||
298 | /* | |
32ee8c3e | 299 | * THERM_CONTROL is architectural for IA32 now, so |
1da177e4 LT |
300 | * we can rely on the capability checks |
301 | */ | |
302 | if (c->x86_vendor != X86_VENDOR_INTEL) | |
303 | return -ENODEV; | |
304 | ||
8ce116e5 IM |
305 | if (!test_cpu_cap(c, X86_FEATURE_ACPI) || |
306 | !test_cpu_cap(c, X86_FEATURE_ACC)) | |
1da177e4 LT |
307 | return -ENODEV; |
308 | ||
309 | ret = cpufreq_register_driver(&p4clockmod_driver); | |
310 | if (!ret) | |
bbfebd66 DJ |
311 | printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock " |
312 | "Modulation available\n"); | |
1da177e4 | 313 | |
bbfebd66 | 314 | return ret; |
1da177e4 LT |
315 | } |
316 | ||
317 | ||
318 | static void __exit cpufreq_p4_exit(void) | |
319 | { | |
320 | cpufreq_unregister_driver(&p4clockmod_driver); | |
321 | } | |
322 | ||
323 | ||
bbfebd66 DJ |
324 | MODULE_AUTHOR("Zwane Mwaikambo <[email protected]>"); |
325 | MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)"); | |
326 | MODULE_LICENSE("GPL"); | |
1da177e4 LT |
327 | |
328 | late_initcall(cpufreq_p4_init); | |
329 | module_exit(cpufreq_p4_exit); |