[linux.git] / arch / x86 / kernel / cpu / cpufreq / p4-clockmod.c

/*
 *	Pentium 4/Xeon CPU on demand clock modulation/speed scaling
 *	(C) 2002 - 2003 Dominik Brodowski <[email protected]>
 *	(C) 2002 Zwane Mwaikambo <[email protected]>
 *	(C) 2002 Arjan van de Ven <[email protected]>
 *	(C) 2002 Tora T. Engstad
 *	All Rights Reserved
 *
 *	This program is free software; you can redistribute it and/or
 *      modify it under the terms of the GNU General Public License
 *      as published by the Free Software Foundation; either version
 *      2 of the License, or (at your option) any later version.
 *
 *      The author(s) of this software shall not be held liable for damages
 *      of any nature resulting due to the use of this software. This
 *      software is provided AS-IS with no warranties.
 *
 *	Date		Errata			Description
 *	20020525	N44, O17	12.5% or 25% DC causes lockup
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include <linux/cpumask.h>

#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/timex.h>

#include "speedstep-lib.h"

#define PFX	"p4-clockmod: "
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "p4-clockmod", msg)

/*
 * Duty Cycle (3bits), note DC_DISABLE is not specified in
 * intel docs i just use it to mean disable
 */
enum {
	DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
	DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
};

#define DC_ENTRIES	8


static int has_N44_O17_errata[NR_CPUS];
static unsigned int stock_freq;
static struct cpufreq_driver p4clockmod_driver;
static unsigned int cpufreq_p4_get(unsigned int cpu);

static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
{
	u32 l, h;

	if (!cpu_online(cpu) || (newstate > DC_DISABLE) || (newstate == DC_RESV))
		return -EINVAL;

	rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h);

	if (l & 0x01)
		dprintk("CPU#%d currently thermal throttled\n", cpu);

	if (has_N44_O17_errata[cpu] && (newstate == DC_25PT || newstate == DC_DFLT))
		newstate = DC_38PT;

	rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
	if (newstate == DC_DISABLE) {
		dprintk("CPU#%d disabling modulation\n", cpu);
		wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
	} else {
		dprintk("CPU#%d setting duty cycle to %d%%\n",
			cpu, ((125 * newstate) / 10));
		/* bits 63 - 5	: reserved
		 * bit  4	: enable/disable
		 * bits 3-1	: duty cycle
		 * bit  0	: reserved
		 */
		l = (l & ~14);
		l = l | (1<<4) | ((newstate & 0x7)<<1);
		wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h);
	}

	return 0;
}


static struct cpufreq_frequency_table p4clockmod_table[] = {
	{DC_RESV, CPUFREQ_ENTRY_INVALID},
	{DC_DFLT, 0},
	{DC_25PT, 0},
	{DC_38PT, 0},
	{DC_50PT, 0},
	{DC_64PT, 0},
	{DC_75PT, 0},
	{DC_88PT, 0},
	{DC_DISABLE, 0},
	{DC_RESV, CPUFREQ_TABLE_END},
};


static int cpufreq_p4_target(struct cpufreq_policy *policy,
			     unsigned int target_freq,
			     unsigned int relation)
{
	unsigned int    newstate = DC_RESV;
	struct cpufreq_freqs freqs;
	int i;

	if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
		return -EINVAL;

	freqs.old = cpufreq_p4_get(policy->cpu);
	freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;

	if (freqs.new == freqs.old)
		return 0;

	/* notifiers */
	for_each_cpu_mask(i, policy->cpus) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	}

	/* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
	 * Developer's Manual, Volume 3
	 */
	for_each_cpu_mask(i, policy->cpus)
		cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);

	/* notifiers */
	for_each_cpu_mask(i, policy->cpus) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	}

	return 0;
}


static int cpufreq_p4_verify(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
}


static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
{
	if (c->x86 == 0x06) {
		if (cpu_has(c, X86_FEATURE_EST))
			printk(KERN_WARNING PFX "Warning: EST-capable CPU detected. "
			       "The acpi-cpufreq module offers voltage scaling"
			       " in addition of frequency scaling. You should use "
			       "that instead of p4-clockmod, if possible.\n");
		switch (c->x86_model) {
		case 0x0E: /* Core */
		case 0x0F: /* Core Duo */
			p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
			return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PCORE);
		case 0x0D: /* Pentium M (Dothan) */
			p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
			/* fall through */
		case 0x09: /* Pentium M (Banias) */
			return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
		}
	}

	if (c->x86 != 0xF) {
		printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <[email protected]>\n");
		return 0;
	}

	/* on P-4s, the TSC runs with constant frequency independent whether
	 * throttling is active or not. */
	p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;

	if (speedstep_detect_processor() == SPEEDSTEP_PROCESSOR_P4M) {
		printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
		       "The speedstep-ich or acpi cpufreq modules offer "
		       "voltage scaling in addition of frequency scaling. "
		       "You should use either one instead of p4-clockmod, "
		       "if possible.\n");
		return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4M);
	}

	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4D);
}


static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
{
	struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
	int cpuid = 0;
	unsigned int i;

#ifdef CONFIG_SMP
	policy->cpus = per_cpu(cpu_sibling_map, policy->cpu);
#endif

	/* Errata workaround */
	cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_mask;
	switch (cpuid) {
	case 0x0f07:
	case 0x0f0a:
	case 0x0f11:
	case 0x0f12:
		has_N44_O17_errata[policy->cpu] = 1;
		dprintk("has errata -- disabling low frequencies\n");
	}

	/* get max frequency */
	stock_freq = cpufreq_p4_get_frequency(c);
	if (!stock_freq)
		return -EINVAL;

	/* table init */
	for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
		if ((i<2) && (has_N44_O17_errata[policy->cpu]))
			p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
		else
			p4clockmod_table[i].frequency = (stock_freq * i)/8;
	}
	cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);

	/* cpuinfo and default policy values */
	policy->cpuinfo.transition_latency = 1000000; /* assumed */
	policy->cur = stock_freq;

	return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
}


static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	return 0;
}

static unsigned int cpufreq_p4_get(unsigned int cpu)
{
	u32 l, h;

	rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);

	if (l & 0x10) {
		l = l >> 1;
		l &= 0x7;
	} else
		l = DC_DISABLE;

	if (l != DC_DISABLE)
		return (stock_freq * l / 8);

	return stock_freq;
}

static struct freq_attr* p4clockmod_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver p4clockmod_driver = {
	.verify		= cpufreq_p4_verify,
	.target		= cpufreq_p4_target,
	.init		= cpufreq_p4_cpu_init,
	.exit		= cpufreq_p4_cpu_exit,
	.get		= cpufreq_p4_get,
	.name		= "p4-clockmod",
	.owner		= THIS_MODULE,
	.attr		= p4clockmod_attr,
};


static int __init cpufreq_p4_init(void)
{
	struct cpuinfo_x86 *c = &cpu_data(0);
	int ret;

	/*
	 * THERM_CONTROL is architectural for IA32 now, so
	 * we can rely on the capability checks
	 */
	if (c->x86_vendor != X86_VENDOR_INTEL)
		return -ENODEV;

	if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) ||
		!test_bit(X86_FEATURE_ACC, c->x86_capability))
		return -ENODEV;

	ret = cpufreq_register_driver(&p4clockmod_driver);
	if (!ret)
		printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");

	return (ret);
}


static void __exit cpufreq_p4_exit(void)
{
	cpufreq_unregister_driver(&p4clockmod_driver);
}


MODULE_AUTHOR ("Zwane Mwaikambo <[email protected]>");
MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
MODULE_LICENSE ("GPL");

late_initcall(cpufreq_p4_init);
module_exit(cpufreq_p4_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Pentium 4/Xeon CPU on demand clock modulation/speed scaling
	3	* (C) 2002 - 2003 Dominik Brodowski <[email protected]>
	4	* (C) 2002 Zwane Mwaikambo <[email protected]>
	5	* (C) 2002 Arjan van de Ven <[email protected]>
	6	* (C) 2002 Tora T. Engstad
	7	* All Rights Reserved
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*
	14	* The author(s) of this software shall not be held liable for damages
	15	* of any nature resulting due to the use of this software. This
	16	* software is provided AS-IS with no warranties.
32ee8c3e	17	*
1da177e4 LT	18	* Date Errata Description
	19	* 20020525 N44, O17 12.5% or 25% DC causes lockup
	20	*
	21	*/
	22
1da177e4	23	#include <linux/kernel.h>
32ee8c3e	24	#include <linux/module.h>
1da177e4 LT	25	#include <linux/init.h>
	26	#include <linux/smp.h>
	27	#include <linux/cpufreq.h>
	28	#include <linux/slab.h>
	29	#include <linux/cpumask.h>
	30
32ee8c3e	31	#include <asm/processor.h>
1da177e4 LT	32	#include <asm/msr.h>
	33	#include <asm/timex.h>
	34
	35	#include "speedstep-lib.h"
	36
	37	#define PFX "p4-clockmod: "
	38	#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "p4-clockmod", msg)
	39
	40	/*
	41	* Duty Cycle (3bits), note DC_DISABLE is not specified in
	42	* intel docs i just use it to mean disable
	43	*/
	44	enum {
	45	DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
	46	DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
	47	};
	48
	49	#define DC_ENTRIES 8
	50
	51
	52	static int has_N44_O17_errata[NR_CPUS];
	53	static unsigned int stock_freq;
	54	static struct cpufreq_driver p4clockmod_driver;
	55	static unsigned int cpufreq_p4_get(unsigned int cpu);
	56
	57	static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
	58	{
	59	u32 l, h;
	60
	61	if (!cpu_online(cpu) \|\| (newstate > DC_DISABLE) \|\| (newstate == DC_RESV))
	62	return -EINVAL;
	63
551948bc	64	rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h);
1da177e4 LT	65
	66	if (l & 0x01)
	67	dprintk("CPU#%d currently thermal throttled\n", cpu);
	68
	69	if (has_N44_O17_errata[cpu] && (newstate == DC_25PT \|\| newstate == DC_DFLT))
	70	newstate = DC_38PT;
	71
551948bc	72	rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
1da177e4 LT	73	if (newstate == DC_DISABLE) {
1da177e4 LT	74	dprintk("CPU#%d disabling modulation\n", cpu);
551948bc	75	wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
1da177e4 LT	76	} else {
	77	dprintk("CPU#%d setting duty cycle to %d%%\n",
	78	cpu, ((125 * newstate) / 10));
32ee8c3e	79	/* bits 63 - 5 : reserved
1da177e4 LT	80	* bit 4 : enable/disable
	81	* bits 3-1 : duty cycle
	82	* bit 0 : reserved
	83	*/
	84	l = (l & ~14);
	85	l = l \| (1<<4) \| ((newstate & 0x7)<<1);
551948bc	86	wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h);
1da177e4 LT	87	}
	88
	89	return 0;
	90	}
	91
	92
	93	static struct cpufreq_frequency_table p4clockmod_table[] = {
	94	{DC_RESV, CPUFREQ_ENTRY_INVALID},
	95	{DC_DFLT, 0},
	96	{DC_25PT, 0},
	97	{DC_38PT, 0},
	98	{DC_50PT, 0},
	99	{DC_64PT, 0},
	100	{DC_75PT, 0},
	101	{DC_88PT, 0},
	102	{DC_DISABLE, 0},
	103	{DC_RESV, CPUFREQ_TABLE_END},
	104	};
	105
	106
	107	static int cpufreq_p4_target(struct cpufreq_policy *policy,
	108	unsigned int target_freq,
	109	unsigned int relation)
	110	{
	111	unsigned int newstate = DC_RESV;
	112	struct cpufreq_freqs freqs;
1da177e4 LT	113	int i;
	114
	115	if (cpufreq_frequency_table_target(policy, &p4clockmod_table[0], target_freq, relation, &newstate))
	116	return -EINVAL;
	117
	118	freqs.old = cpufreq_p4_get(policy->cpu);
	119	freqs.new = stock_freq * p4clockmod_table[newstate].index / 8;
	120
	121	if (freqs.new == freqs.old)
	122	return 0;
	123
	124	/* notifiers */
	125	for_each_cpu_mask(i, policy->cpus) {
	126	freqs.cpu = i;
	127	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	128	}
	129
	130	/* run on each logical CPU, see section 13.15.3 of IA32 Intel Architecture Software
32ee8c3e	131	* Developer's Manual, Volume 3
1da177e4	132	*/
551948bc	133	for_each_cpu_mask(i, policy->cpus)
1da177e4	134	cpufreq_p4_setdc(i, p4clockmod_table[newstate].index);
1da177e4 LT	135
	136	/* notifiers */
	137	for_each_cpu_mask(i, policy->cpus) {
	138	freqs.cpu = i;
	139	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	140	}
	141
	142	return 0;
	143	}
	144
	145
	146	static int cpufreq_p4_verify(struct cpufreq_policy *policy)
	147	{
	148	return cpufreq_frequency_table_verify(policy, &p4clockmod_table[0]);
	149	}
	150
	151
	152	static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
	153	{
4e74663c DB	154	if (c->x86 == 0x06) {
	155	if (cpu_has(c, X86_FEATURE_EST))
	156	printk(KERN_WARNING PFX "Warning: EST-capable CPU detected. "
	157	"The acpi-cpufreq module offers voltage scaling"
	158	" in addition of frequency scaling. You should use "
	159	"that instead of p4-clockmod, if possible.\n");
	160	switch (c->x86_model) {
	161	case 0x0E: /* Core */
	162	case 0x0F: /* Core Duo */
	163	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
	164	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PCORE);
	165	case 0x0D: /* Pentium M (Dothan) */
	166	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
	167	/* fall through */
	168	case 0x09: /* Pentium M (Banias) */
	169	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_PM);
	170	}
1da177e4 LT	171	}
	172
	173	if (c->x86 != 0xF) {
4e74663c	174	printk(KERN_WARNING PFX "Unknown p4-clockmod-capable CPU. Please send an e-mail to <[email protected]>\n");
1da177e4 LT	175	return 0;
	176	}
	177
	178	/* on P-4s, the TSC runs with constant frequency independent whether
	179	* throttling is active or not. */
	180	p4clockmod_driver.flags \|= CPUFREQ_CONST_LOOPS;
	181
	182	if (speedstep_detect_processor() == SPEEDSTEP_PROCESSOR_P4M) {
	183	printk(KERN_WARNING PFX "Warning: Pentium 4-M detected. "
	184	"The speedstep-ich or acpi cpufreq modules offer "
	185	"voltage scaling in addition of frequency scaling. "
	186	"You should use either one instead of p4-clockmod, "
	187	"if possible.\n");
	188	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4M);
	189	}
	190
	191	return speedstep_get_processor_frequency(SPEEDSTEP_PROCESSOR_P4D);
	192	}
	193
32ee8c3e	194
1da177e4 LT	195
	196	static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
	197	{
92cb7612	198	struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
1da177e4 LT	199	int cpuid = 0;
	200	unsigned int i;
	201
	202	#ifdef CONFIG_SMP
d5a7430d	203	policy->cpus = per_cpu(cpu_sibling_map, policy->cpu);
1da177e4 LT	204	#endif
	205
	206	/* Errata workaround */
	207	cpuid = (c->x86 << 8) \| (c->x86_model << 4) \| c->x86_mask;
	208	switch (cpuid) {
	209	case 0x0f07:
	210	case 0x0f0a:
	211	case 0x0f11:
	212	case 0x0f12:
	213	has_N44_O17_errata[policy->cpu] = 1;
	214	dprintk("has errata -- disabling low frequencies\n");
	215	}
32ee8c3e	216
1da177e4 LT	217	/* get max frequency */
	218	stock_freq = cpufreq_p4_get_frequency(c);
	219	if (!stock_freq)
	220	return -EINVAL;
	221
	222	/* table init */
	223	for (i=1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
	224	if ((i<2) && (has_N44_O17_errata[policy->cpu]))
	225	p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	226	else
	227	p4clockmod_table[i].frequency = (stock_freq * i)/8;
	228	}
	229	cpufreq_frequency_table_get_attr(p4clockmod_table, policy->cpu);
32ee8c3e	230
1da177e4	231	/* cpuinfo and default policy values */
1da177e4 LT	232	policy->cpuinfo.transition_latency = 1000000; /* assumed */
	233	policy->cur = stock_freq;
	234
	235	return cpufreq_frequency_table_cpuinfo(policy, &p4clockmod_table[0]);
	236	}
	237
	238
	239	static int cpufreq_p4_cpu_exit(struct cpufreq_policy *policy)
	240	{
32ee8c3e	241	cpufreq_frequency_table_put_attr(policy->cpu);
1da177e4 LT	242	return 0;
	243	}
	244
	245	static unsigned int cpufreq_p4_get(unsigned int cpu)
	246	{
1da177e4 LT	247	u32 l, h;
1da177e4 LT	248
551948bc	249	rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
1da177e4 LT	250
	251	if (l & 0x10) {
	252	l = l >> 1;
	253	l &= 0x7;
	254	} else
	255	l = DC_DISABLE;
	256
	257	if (l != DC_DISABLE)
	258	return (stock_freq * l / 8);
	259
	260	return stock_freq;
	261	}
	262
	263	static struct freq_attr* p4clockmod_attr[] = {
	264	&cpufreq_freq_attr_scaling_available_freqs,
	265	NULL,
	266	};
	267
	268	static struct cpufreq_driver p4clockmod_driver = {
32ee8c3e	269	.verify = cpufreq_p4_verify,
1da177e4 LT	270	.target = cpufreq_p4_target,
	271	.init = cpufreq_p4_cpu_init,
	272	.exit = cpufreq_p4_cpu_exit,
	273	.get = cpufreq_p4_get,
	274	.name = "p4-clockmod",
	275	.owner = THIS_MODULE,
	276	.attr = p4clockmod_attr,
	277	};
	278
	279
	280	static int __init cpufreq_p4_init(void)
32ee8c3e	281	{
92cb7612	282	struct cpuinfo_x86 *c = &cpu_data(0);
1da177e4 LT	283	int ret;
	284
	285	/*
32ee8c3e	286	* THERM_CONTROL is architectural for IA32 now, so
1da177e4 LT	287	* we can rely on the capability checks
	288	*/
	289	if (c->x86_vendor != X86_VENDOR_INTEL)
	290	return -ENODEV;
	291
	292	if (!test_bit(X86_FEATURE_ACPI, c->x86_capability) \|\|
	293	!test_bit(X86_FEATURE_ACC, c->x86_capability))
	294	return -ENODEV;
	295
	296	ret = cpufreq_register_driver(&p4clockmod_driver);
	297	if (!ret)
	298	printk(KERN_INFO PFX "P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
	299
	300	return (ret);
	301	}
	302
	303
	304	static void __exit cpufreq_p4_exit(void)
	305	{
	306	cpufreq_unregister_driver(&p4clockmod_driver);
	307	}
	308
	309
	310	MODULE_AUTHOR ("Zwane Mwaikambo <[email protected]>");
	311	MODULE_DESCRIPTION ("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
	312	MODULE_LICENSE ("GPL");
	313
	314	late_initcall(cpufreq_p4_init);
	315	module_exit(cpufreq_p4_exit);