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[PATCH] natsemi: NAPI and a bugfix
[linux.git] / drivers / net / e100.c
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1da177e4
LT		 1/*******************************************************************************
2
05479938 3
611494dc 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
05479938
JB		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
1da177e4 9 any later version.
05479938
JB		 10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 14 more details.
05479938 15
1da177e4 16 You should have received a copy of the GNU General Public License along with
05479938 17 this program; if not, write to the Free Software Foundation, Inc., 59
1da177e4 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
05479938 19
1da177e4
LT		 20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
05479938 22
1da177e4
LT		 23 Contact Information:
24 Linux NICS <[email protected]>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by [email protected]. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
117 * placed.
118 *
119 * V. Miscellaneous
120 *
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
126 *
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
128 *
129 * Thanks to JC ([email protected]) for helping with
130 * testing/troubleshooting the development driver.
131 *
132 * TODO:
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
ac7c6669
OM		 135 *
136 * FIXES:
137 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
138 * - Stratus87247: protect MDI control register manipulations
1da177e4
LT		 139 */
140
141#include <linux/config.h>
142#include <linux/module.h>
143#include <linux/moduleparam.h>
144#include <linux/kernel.h>
145#include <linux/types.h>
146#include <linux/slab.h>
147#include <linux/delay.h>
148#include <linux/init.h>
149#include <linux/pci.h>
1e7f0bd8 150#include <linux/dma-mapping.h>
1da177e4
LT		 151#include <linux/netdevice.h>
152#include <linux/etherdevice.h>
153#include <linux/mii.h>
154#include <linux/if_vlan.h>
155#include <linux/skbuff.h>
156#include <linux/ethtool.h>
157#include <linux/string.h>
158#include <asm/unaligned.h>
159
160
161#define DRV_NAME "e100"
162#define DRV_EXT "-NAPI"
24180333 163#define DRV_VERSION "3.5.10-k2"DRV_EXT
1da177e4 164#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
042e2fb7 165#define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation"
1da177e4
LT		 166#define PFX DRV_NAME ": "
167
168#define E100_WATCHDOG_PERIOD (2 * HZ)
169#define E100_NAPI_WEIGHT 16
170
171MODULE_DESCRIPTION(DRV_DESCRIPTION);
172MODULE_AUTHOR(DRV_COPYRIGHT);
173MODULE_LICENSE("GPL");
174MODULE_VERSION(DRV_VERSION);
175
176static int debug = 3;
177module_param(debug, int, 0);
178MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
179#define DPRINTK(nlevel, klevel, fmt, args...) \
180 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
181 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
182 __FUNCTION__ , ## args))
183
184#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
185 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
186 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
187static struct pci_device_id e100_id_table[] = {
188 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
189 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
190 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
192 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
193 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
194 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
195 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
198 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
199 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
200 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
201 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
206 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
207 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
208 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
209 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
210 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
214 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
215 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
216 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
217 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
042e2fb7
MC		 218 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
219 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
220 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
221 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
222 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
1da177e4
LT		 223 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
224 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
225 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
226 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
227 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
042e2fb7 228 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
1da177e4
LT		 229 { 0, }
230};
231MODULE_DEVICE_TABLE(pci, e100_id_table);
232
233enum mac {
234 mac_82557_D100_A = 0,
235 mac_82557_D100_B = 1,
236 mac_82557_D100_C = 2,
237 mac_82558_D101_A4 = 4,
238 mac_82558_D101_B0 = 5,
239 mac_82559_D101M = 8,
240 mac_82559_D101S = 9,
241 mac_82550_D102 = 12,
242 mac_82550_D102_C = 13,
243 mac_82551_E = 14,
244 mac_82551_F = 15,
245 mac_82551_10 = 16,
246 mac_unknown = 0xFF,
247};
248
249enum phy {
250 phy_100a = 0x000003E0,
251 phy_100c = 0x035002A8,
252 phy_82555_tx = 0x015002A8,
253 phy_nsc_tx = 0x5C002000,
254 phy_82562_et = 0x033002A8,
255 phy_82562_em = 0x032002A8,
256 phy_82562_ek = 0x031002A8,
257 phy_82562_eh = 0x017002A8,
258 phy_unknown = 0xFFFFFFFF,
259};
260
261/* CSR (Control/Status Registers) */
262struct csr {
263 struct {
264 u8 status;
265 u8 stat_ack;
266 u8 cmd_lo;
267 u8 cmd_hi;
268 u32 gen_ptr;
269 } scb;
270 u32 port;
271 u16 flash_ctrl;
272 u8 eeprom_ctrl_lo;
273 u8 eeprom_ctrl_hi;
274 u32 mdi_ctrl;
275 u32 rx_dma_count;
276};
277
278enum scb_status {
279 rus_ready = 0x10,
280 rus_mask = 0x3C,
281};
282
1f53367d
MC		 283enum ru_state {
284 RU_SUSPENDED = 0,
285 RU_RUNNING = 1,
286 RU_UNINITIALIZED = -1,
287};
288
1da177e4
LT		 289enum scb_stat_ack {
290 stat_ack_not_ours = 0x00,
291 stat_ack_sw_gen = 0x04,
292 stat_ack_rnr = 0x10,
293 stat_ack_cu_idle = 0x20,
294 stat_ack_frame_rx = 0x40,
295 stat_ack_cu_cmd_done = 0x80,
296 stat_ack_not_present = 0xFF,
297 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
298 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
299};
300
301enum scb_cmd_hi {
302 irq_mask_none = 0x00,
303 irq_mask_all = 0x01,
304 irq_sw_gen = 0x02,
305};
306
307enum scb_cmd_lo {
308 cuc_nop = 0x00,
309 ruc_start = 0x01,
310 ruc_load_base = 0x06,
311 cuc_start = 0x10,
312 cuc_resume = 0x20,
313 cuc_dump_addr = 0x40,
314 cuc_dump_stats = 0x50,
315 cuc_load_base = 0x60,
316 cuc_dump_reset = 0x70,
317};
318
319enum cuc_dump {
320 cuc_dump_complete = 0x0000A005,
321 cuc_dump_reset_complete = 0x0000A007,
322};
05479938 323
1da177e4
LT		 324enum port {
325 software_reset = 0x0000,
326 selftest = 0x0001,
327 selective_reset = 0x0002,
328};
329
330enum eeprom_ctrl_lo {
331 eesk = 0x01,
332 eecs = 0x02,
333 eedi = 0x04,
334 eedo = 0x08,
335};
336
337enum mdi_ctrl {
338 mdi_write = 0x04000000,
339 mdi_read = 0x08000000,
340 mdi_ready = 0x10000000,
341};
342
343enum eeprom_op {
344 op_write = 0x05,
345 op_read = 0x06,
346 op_ewds = 0x10,
347 op_ewen = 0x13,
348};
349
350enum eeprom_offsets {
351 eeprom_cnfg_mdix = 0x03,
352 eeprom_id = 0x0A,
353 eeprom_config_asf = 0x0D,
354 eeprom_smbus_addr = 0x90,
355};
356
357enum eeprom_cnfg_mdix {
358 eeprom_mdix_enabled = 0x0080,
359};
360
361enum eeprom_id {
362 eeprom_id_wol = 0x0020,
363};
364
365enum eeprom_config_asf {
366 eeprom_asf = 0x8000,
367 eeprom_gcl = 0x4000,
368};
369
370enum cb_status {
371 cb_complete = 0x8000,
372 cb_ok = 0x2000,
373};
374
375enum cb_command {
376 cb_nop = 0x0000,
377 cb_iaaddr = 0x0001,
378 cb_config = 0x0002,
379 cb_multi = 0x0003,
380 cb_tx = 0x0004,
381 cb_ucode = 0x0005,
382 cb_dump = 0x0006,
383 cb_tx_sf = 0x0008,
384 cb_cid = 0x1f00,
385 cb_i = 0x2000,
386 cb_s = 0x4000,
387 cb_el = 0x8000,
388};
389
390struct rfd {
391 u16 status;
392 u16 command;
393 u32 link;
394 u32 rbd;
395 u16 actual_size;
396 u16 size;
397};
398
399struct rx {
400 struct rx *next, *prev;
401 struct sk_buff *skb;
402 dma_addr_t dma_addr;
403};
404
405#if defined(__BIG_ENDIAN_BITFIELD)
406#define X(a,b) b,a
407#else
408#define X(a,b) a,b
409#endif
410struct config {
411/*0*/ u8 X(byte_count:6, pad0:2);
412/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
413/*2*/ u8 adaptive_ifs;
414/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
415 term_write_cache_line:1), pad3:4);
416/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
417/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
418/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
419 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
420 rx_discard_overruns:1), rx_save_bad_frames:1);
421/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
422 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
423 tx_dynamic_tbd:1);
424/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
425/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
426 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
427/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
428 loopback:2);
429/*11*/ u8 X(linear_priority:3, pad11:5);
430/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
431/*13*/ u8 ip_addr_lo;
432/*14*/ u8 ip_addr_hi;
433/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
434 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
435 pad15_2:1), crs_or_cdt:1);
436/*16*/ u8 fc_delay_lo;
437/*17*/ u8 fc_delay_hi;
438/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
439 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
440/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
441 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
442 full_duplex_force:1), full_duplex_pin:1);
443/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
444/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
445/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
446 u8 pad_d102[9];
447};
448
449#define E100_MAX_MULTICAST_ADDRS 64
450struct multi {
451 u16 count;
452 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
453};
454
455/* Important: keep total struct u32-aligned */
456#define UCODE_SIZE 134
457struct cb {
458 u16 status;
459 u16 command;
460 u32 link;
461 union {
462 u8 iaaddr[ETH_ALEN];
463 u32 ucode[UCODE_SIZE];
464 struct config config;
465 struct multi multi;
466 struct {
467 u32 tbd_array;
468 u16 tcb_byte_count;
469 u8 threshold;
470 u8 tbd_count;
471 struct {
472 u32 buf_addr;
473 u16 size;
474 u16 eol;
475 } tbd;
476 } tcb;
477 u32 dump_buffer_addr;
478 } u;
479 struct cb *next, *prev;
480 dma_addr_t dma_addr;
481 struct sk_buff *skb;
482};
483
484enum loopback {
485 lb_none = 0, lb_mac = 1, lb_phy = 3,
486};
487
488struct stats {
489 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
490 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
491 tx_multiple_collisions, tx_total_collisions;
492 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
493 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
494 rx_short_frame_errors;
495 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
496 u16 xmt_tco_frames, rcv_tco_frames;
497 u32 complete;
498};
499
500struct mem {
501 struct {
502 u32 signature;
503 u32 result;
504 } selftest;
505 struct stats stats;
506 u8 dump_buf[596];
507};
508
509struct param_range {
510 u32 min;
511 u32 max;
512 u32 count;
513};
514
515struct params {
516 struct param_range rfds;
517 struct param_range cbs;
518};
519
520struct nic {
521 /* Begin: frequently used values: keep adjacent for cache effect */
522 u32 msg_enable ____cacheline_aligned;
523 struct net_device *netdev;
524 struct pci_dev *pdev;
525
526 struct rx *rxs ____cacheline_aligned;
527 struct rx *rx_to_use;
528 struct rx *rx_to_clean;
529 struct rfd blank_rfd;
1f53367d 530 enum ru_state ru_running;
1da177e4
LT		 531
532 spinlock_t cb_lock ____cacheline_aligned;
533 spinlock_t cmd_lock;
534 struct csr __iomem *csr;
535 enum scb_cmd_lo cuc_cmd;
536 unsigned int cbs_avail;
537 struct cb *cbs;
538 struct cb *cb_to_use;
539 struct cb *cb_to_send;
540 struct cb *cb_to_clean;
541 u16 tx_command;
542 /* End: frequently used values: keep adjacent for cache effect */
543
544 enum {
545 ich = (1 << 0),
546 promiscuous = (1 << 1),
547 multicast_all = (1 << 2),
548 wol_magic = (1 << 3),
549 ich_10h_workaround = (1 << 4),
550 } flags ____cacheline_aligned;
551
552 enum mac mac;
553 enum phy phy;
554 struct params params;
555 struct net_device_stats net_stats;
556 struct timer_list watchdog;
557 struct timer_list blink_timer;
558 struct mii_if_info mii;
2acdb1e0 559 struct work_struct tx_timeout_task;
1da177e4
LT		 560 enum loopback loopback;
561
562 struct mem *mem;
563 dma_addr_t dma_addr;
564
565 dma_addr_t cbs_dma_addr;
566 u8 adaptive_ifs;
567 u8 tx_threshold;
568 u32 tx_frames;
569 u32 tx_collisions;
570 u32 tx_deferred;
571 u32 tx_single_collisions;
572 u32 tx_multiple_collisions;
573 u32 tx_fc_pause;
574 u32 tx_tco_frames;
575
576 u32 rx_fc_pause;
577 u32 rx_fc_unsupported;
578 u32 rx_tco_frames;
579 u32 rx_over_length_errors;
580
581 u8 rev_id;
582 u16 leds;
583 u16 eeprom_wc;
584 u16 eeprom[256];
ac7c6669 585 spinlock_t mdio_lock;
1da177e4
LT		 586};
587
588static inline void e100_write_flush(struct nic *nic)
589{
590 /* Flush previous PCI writes through intermediate bridges
591 * by doing a benign read */
592 (void)readb(&nic->csr->scb.status);
593}
594
858119e1 595static void e100_enable_irq(struct nic *nic)
1da177e4
LT		 596{
597 unsigned long flags;
598
599 spin_lock_irqsave(&nic->cmd_lock, flags);
600 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
601 spin_unlock_irqrestore(&nic->cmd_lock, flags);
602 e100_write_flush(nic);
603}
604
858119e1 605static void e100_disable_irq(struct nic *nic)
1da177e4
LT		 606{
607 unsigned long flags;
608
609 spin_lock_irqsave(&nic->cmd_lock, flags);
610 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
611 spin_unlock_irqrestore(&nic->cmd_lock, flags);
612 e100_write_flush(nic);
613}
614
615static void e100_hw_reset(struct nic *nic)
616{
617 /* Put CU and RU into idle with a selective reset to get
618 * device off of PCI bus */
619 writel(selective_reset, &nic->csr->port);
620 e100_write_flush(nic); udelay(20);
621
622 /* Now fully reset device */
623 writel(software_reset, &nic->csr->port);
624 e100_write_flush(nic); udelay(20);
625
626 /* Mask off our interrupt line - it's unmasked after reset */
627 e100_disable_irq(nic);
628}
629
630static int e100_self_test(struct nic *nic)
631{
632 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
633
634 /* Passing the self-test is a pretty good indication
635 * that the device can DMA to/from host memory */
636
637 nic->mem->selftest.signature = 0;
638 nic->mem->selftest.result = 0xFFFFFFFF;
639
640 writel(selftest | dma_addr, &nic->csr->port);
641 e100_write_flush(nic);
642 /* Wait 10 msec for self-test to complete */
643 msleep(10);
644
645 /* Interrupts are enabled after self-test */
646 e100_disable_irq(nic);
647
648 /* Check results of self-test */
649 if(nic->mem->selftest.result != 0) {
650 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
651 nic->mem->selftest.result);
652 return -ETIMEDOUT;
653 }
654 if(nic->mem->selftest.signature == 0) {
655 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
656 return -ETIMEDOUT;
657 }
658
659 return 0;
660}
661
662static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
663{
664 u32 cmd_addr_data[3];
665 u8 ctrl;
666 int i, j;
667
668 /* Three cmds: write/erase enable, write data, write/erase disable */
669 cmd_addr_data[0] = op_ewen << (addr_len - 2);
670 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
671 cpu_to_le16(data);
672 cmd_addr_data[2] = op_ewds << (addr_len - 2);
673
674 /* Bit-bang cmds to write word to eeprom */
675 for(j = 0; j < 3; j++) {
676
677 /* Chip select */
678 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
679 e100_write_flush(nic); udelay(4);
680
681 for(i = 31; i >= 0; i--) {
682 ctrl = (cmd_addr_data[j] & (1 << i)) ?
683 eecs | eedi : eecs;
684 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
685 e100_write_flush(nic); udelay(4);
686
687 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
688 e100_write_flush(nic); udelay(4);
689 }
690 /* Wait 10 msec for cmd to complete */
691 msleep(10);
692
693 /* Chip deselect */
694 writeb(0, &nic->csr->eeprom_ctrl_lo);
695 e100_write_flush(nic); udelay(4);
696 }
697};
698
699/* General technique stolen from the eepro100 driver - very clever */
700static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
701{
702 u32 cmd_addr_data;
703 u16 data = 0;
704 u8 ctrl;
705 int i;
706
707 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
708
709 /* Chip select */
710 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
711 e100_write_flush(nic); udelay(4);
712
713 /* Bit-bang to read word from eeprom */
714 for(i = 31; i >= 0; i--) {
715 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
716 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
717 e100_write_flush(nic); udelay(4);
05479938 718
1da177e4
LT		 719 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
720 e100_write_flush(nic); udelay(4);
05479938 721
1da177e4
LT		 722 /* Eeprom drives a dummy zero to EEDO after receiving
723 * complete address. Use this to adjust addr_len. */
724 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
725 if(!(ctrl & eedo) && i > 16) {
726 *addr_len -= (i - 16);
727 i = 17;
728 }
05479938 729
1da177e4
LT		 730 data = (data << 1) | (ctrl & eedo ? 1 : 0);
731 }
732
733 /* Chip deselect */
734 writeb(0, &nic->csr->eeprom_ctrl_lo);
735 e100_write_flush(nic); udelay(4);
736
737 return le16_to_cpu(data);
738};
739
740/* Load entire EEPROM image into driver cache and validate checksum */
741static int e100_eeprom_load(struct nic *nic)
742{
743 u16 addr, addr_len = 8, checksum = 0;
744
745 /* Try reading with an 8-bit addr len to discover actual addr len */
746 e100_eeprom_read(nic, &addr_len, 0);
747 nic->eeprom_wc = 1 << addr_len;
748
749 for(addr = 0; addr < nic->eeprom_wc; addr++) {
750 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
751 if(addr < nic->eeprom_wc - 1)
752 checksum += cpu_to_le16(nic->eeprom[addr]);
753 }
754
755 /* The checksum, stored in the last word, is calculated such that
756 * the sum of words should be 0xBABA */
757 checksum = le16_to_cpu(0xBABA - checksum);
758 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
759 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
760 return -EAGAIN;
761 }
762
763 return 0;
764}
765
766/* Save (portion of) driver EEPROM cache to device and update checksum */
767static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
768{
769 u16 addr, addr_len = 8, checksum = 0;
770
771 /* Try reading with an 8-bit addr len to discover actual addr len */
772 e100_eeprom_read(nic, &addr_len, 0);
773 nic->eeprom_wc = 1 << addr_len;
774
775 if(start + count >= nic->eeprom_wc)
776 return -EINVAL;
777
778 for(addr = start; addr < start + count; addr++)
779 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
780
781 /* The checksum, stored in the last word, is calculated such that
782 * the sum of words should be 0xBABA */
783 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
784 checksum += cpu_to_le16(nic->eeprom[addr]);
785 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
786 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
787 nic->eeprom[nic->eeprom_wc - 1]);
788
789 return 0;
790}
791
962082b6 792#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
e6280f26 793#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
858119e1 794static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
1da177e4
LT		 795{
796 unsigned long flags;
797 unsigned int i;
798 int err = 0;
799
800 spin_lock_irqsave(&nic->cmd_lock, flags);
801
802 /* Previous command is accepted when SCB clears */
803 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
804 if(likely(!readb(&nic->csr->scb.cmd_lo)))
805 break;
806 cpu_relax();
e6280f26 807 if(unlikely(i > E100_WAIT_SCB_FAST))
1da177e4
LT		 808 udelay(5);
809 }
810 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
811 err = -EAGAIN;
812 goto err_unlock;
813 }
814
815 if(unlikely(cmd != cuc_resume))
816 writel(dma_addr, &nic->csr->scb.gen_ptr);
817 writeb(cmd, &nic->csr->scb.cmd_lo);
818
819err_unlock:
820 spin_unlock_irqrestore(&nic->cmd_lock, flags);
821
822 return err;
823}
824
858119e1 825static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
1da177e4
LT		 826 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
827{
828 struct cb *cb;
829 unsigned long flags;
830 int err = 0;
831
832 spin_lock_irqsave(&nic->cb_lock, flags);
833
834 if(unlikely(!nic->cbs_avail)) {
835 err = -ENOMEM;
836 goto err_unlock;
837 }
838
839 cb = nic->cb_to_use;
840 nic->cb_to_use = cb->next;
841 nic->cbs_avail--;
842 cb->skb = skb;
843
844 if(unlikely(!nic->cbs_avail))
845 err = -ENOSPC;
846
847 cb_prepare(nic, cb, skb);
848
849 /* Order is important otherwise we'll be in a race with h/w:
850 * set S-bit in current first, then clear S-bit in previous. */
851 cb->command |= cpu_to_le16(cb_s);
852 wmb();
853 cb->prev->command &= cpu_to_le16(~cb_s);
854
855 while(nic->cb_to_send != nic->cb_to_use) {
856 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
857 nic->cb_to_send->dma_addr))) {
858 /* Ok, here's where things get sticky. It's
859 * possible that we can't schedule the command
860 * because the controller is too busy, so
861 * let's just queue the command and try again
862 * when another command is scheduled. */
962082b6
MC		 863 if(err == -ENOSPC) {
864 //request a reset
865 schedule_work(&nic->tx_timeout_task);
866 }
1da177e4
LT		 867 break;
868 } else {
869 nic->cuc_cmd = cuc_resume;
870 nic->cb_to_send = nic->cb_to_send->next;
871 }
872 }
873
874err_unlock:
875 spin_unlock_irqrestore(&nic->cb_lock, flags);
876
877 return err;
878}
879
880static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
881{
882 u32 data_out = 0;
883 unsigned int i;
ac7c6669 884 unsigned long flags;
1da177e4 885
ac7c6669
OM		 886
887 /*
888 * Stratus87247: we shouldn't be writing the MDI control
889 * register until the Ready bit shows True. Also, since
890 * manipulation of the MDI control registers is a multi-step
891 * procedure it should be done under lock.
892 */
893 spin_lock_irqsave(&nic->mdio_lock, flags);
894 for (i = 100; i; --i) {
895 if (readl(&nic->csr->mdi_ctrl) & mdi_ready)
896 break;
897 udelay(20);
898 }
899 if (unlikely(!i)) {
900 printk("e100.mdio_ctrl(%s) won't go Ready\n",
901 nic->netdev->name );
902 spin_unlock_irqrestore(&nic->mdio_lock, flags);
903 return 0; /* No way to indicate timeout error */
904 }
1da177e4
LT		 905 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
906
ac7c6669 907 for (i = 0; i < 100; i++) {
1da177e4 908 udelay(20);
ac7c6669 909 if ((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
1da177e4
LT		 910 break;
911 }
ac7c6669 912 spin_unlock_irqrestore(&nic->mdio_lock, flags);
1da177e4
LT		 913 DPRINTK(HW, DEBUG,
914 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
915 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
916 return (u16)data_out;
917}
918
919static int mdio_read(struct net_device *netdev, int addr, int reg)
920{
921 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
922}
923
924static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
925{
926 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
927}
928
929static void e100_get_defaults(struct nic *nic)
930{
2afecc04
JB		 931 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
932 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1da177e4
LT		 933
934 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
935 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
936 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
937 if(nic->mac == mac_unknown)
938 nic->mac = mac_82557_D100_A;
939
940 nic->params.rfds = rfds;
941 nic->params.cbs = cbs;
942
943 /* Quadwords to DMA into FIFO before starting frame transmit */
944 nic->tx_threshold = 0xE0;
945
962082b6
MC		 946 /* no interrupt for every tx completion, delay = 256us if not 557*/
947 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
948 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1da177e4
LT		 949
950 /* Template for a freshly allocated RFD */
951 nic->blank_rfd.command = cpu_to_le16(cb_el);
952 nic->blank_rfd.rbd = 0xFFFFFFFF;
953 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
954
955 /* MII setup */
956 nic->mii.phy_id_mask = 0x1F;
957 nic->mii.reg_num_mask = 0x1F;
958 nic->mii.dev = nic->netdev;
959 nic->mii.mdio_read = mdio_read;
960 nic->mii.mdio_write = mdio_write;
961}
962
963static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
964{
965 struct config *config = &cb->u.config;
966 u8 *c = (u8 *)config;
967
968 cb->command = cpu_to_le16(cb_config);
969
970 memset(config, 0, sizeof(struct config));
971
972 config->byte_count = 0x16; /* bytes in this struct */
973 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
974 config->direct_rx_dma = 0x1; /* reserved */
975 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
976 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
977 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
978 config->tx_underrun_retry = 0x3; /* # of underrun retries */
979 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
980 config->pad10 = 0x6;
981 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
982 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
983 config->ifs = 0x6; /* x16 = inter frame spacing */
984 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
985 config->pad15_1 = 0x1;
986 config->pad15_2 = 0x1;
987 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
988 config->fc_delay_hi = 0x40; /* time delay for fc frame */
989 config->tx_padding = 0x1; /* 1=pad short frames */
990 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
991 config->pad18 = 0x1;
992 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
993 config->pad20_1 = 0x1F;
994 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
995 config->pad21_1 = 0x5;
996
997 config->adaptive_ifs = nic->adaptive_ifs;
998 config->loopback = nic->loopback;
999
1000 if(nic->mii.force_media && nic->mii.full_duplex)
1001 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1002
1003 if(nic->flags & promiscuous || nic->loopback) {
1004 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1005 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1006 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1007 }
1008
1009 if(nic->flags & multicast_all)
1010 config->multicast_all = 0x1; /* 1=accept, 0=no */
1011
6bdacb1a
MC		 1012 /* disable WoL when up */
1013 if(netif_running(nic->netdev) || !(nic->flags & wol_magic))
1da177e4
LT		 1014 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1015
1016 if(nic->mac >= mac_82558_D101_A4) {
1017 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1018 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1019 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1020 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1021 if(nic->mac >= mac_82559_D101M)
1022 config->tno_intr = 0x1; /* TCO stats enable */
1023 else
1024 config->standard_stat_counter = 0x0;
1025 }
1026
1027 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1028 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1029 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1030 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1031 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1032 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1033}
1034
2afecc04
JB		 1035/********************************************************/
1036/* Micro code for 8086:1229 Rev 8 */
1037/********************************************************/
1038
1039/* Parameter values for the D101M B-step */
1040#define D101M_CPUSAVER_TIMER_DWORD 78
1041#define D101M_CPUSAVER_BUNDLE_DWORD 65
1042#define D101M_CPUSAVER_MIN_SIZE_DWORD 126
1043
1044#define D101M_B_RCVBUNDLE_UCODE \
1045{\
10460x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
10470x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
10480x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
10490x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
10500x00380438, 0x00000000, 0x00140000, 0x00380555, \
10510x00308000, 0x00100662, 0x00100561, 0x000E0408, \
10520x00134861, 0x000C0002, 0x00103093, 0x00308000, \
10530x00100624, 0x00100561, 0x000E0408, 0x00100861, \
10540x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
10550x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
10560x00000000, 0x00000000, 0x00000000, 0x00000000, \
10570x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
10580x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
10590x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
10600x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
10610x00041000, 0x00010004, 0x00130826, 0x000C0006, \
10620x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
10630x00000000, 0x00000000, 0x00000000, 0x00000000, \
10640x00000000, 0x00000000, 0x00000000, 0x00000000, \
10650x00080600, 0x00101B10, 0x00050004, 0x00100826, \
10660x00101210, 0x00380C34, 0x00000000, 0x00000000, \
10670x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
10680x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
10690x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
10700x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
10710x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
10720x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
10730x00130826, 0x000C0001, 0x00220559, 0x00101313, \
10740x00380559, 0x00000000, 0x00000000, 0x00000000, \
10750x00000000, 0x00000000, 0x00000000, 0x00000000, \
10760x00000000, 0x00130831, 0x0010090B, 0x00124813, \
10770x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
10780x003806A8, 0x00000000, 0x00000000, 0x00000000, \
1079}
1080
1081/********************************************************/
1082/* Micro code for 8086:1229 Rev 9 */
1083/********************************************************/
1084
1085/* Parameter values for the D101S */
1086#define D101S_CPUSAVER_TIMER_DWORD 78
1087#define D101S_CPUSAVER_BUNDLE_DWORD 67
1088#define D101S_CPUSAVER_MIN_SIZE_DWORD 128
1089
1090#define D101S_RCVBUNDLE_UCODE \
1091{\
10920x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
10930x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
10940x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
10950x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
10960x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
10970x00308000, 0x00100610, 0x00100561, 0x000E0408, \
10980x00134861, 0x000C0002, 0x00103093, 0x00308000, \
10990x00100624, 0x00100561, 0x000E0408, 0x00100861, \
11000x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
11010x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
11020x00000000, 0x00000000, 0x00000000, 0x00000000, \
11030x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
11040x003A047E, 0x00044010, 0x00380819, 0x00000000, \
11050x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
11060x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
11070x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
11080x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
11090x00101313, 0x00380700, 0x00000000, 0x00000000, \
11100x00000000, 0x00000000, 0x00000000, 0x00000000, \
11110x00080600, 0x00101B10, 0x00050004, 0x00100826, \
11120x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
11130x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
11140x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
11150x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
11160x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
11170x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
11180x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
11190x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
11200x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
11210x00000000, 0x00000000, 0x00000000, 0x00000000, \
11220x00000000, 0x00000000, 0x00000000, 0x00130831, \
11230x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
11240x00041000, 0x00010004, 0x00380700 \
1125}
1126
1127/********************************************************/
1128/* Micro code for the 8086:1229 Rev F/10 */
1129/********************************************************/
1130
1131/* Parameter values for the D102 E-step */
1132#define D102_E_CPUSAVER_TIMER_DWORD 42
1133#define D102_E_CPUSAVER_BUNDLE_DWORD 54
1134#define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
1135
1136#define D102_E_RCVBUNDLE_UCODE \
1137{\
11380x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x0EF70E36, 0x1FFF1FFF, \
11390x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
11400x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
11410x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
11420x00000000, 0x00000000, 0x00000000, 0x00000000, \
11430x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
11440x00000000, 0x00000000, 0x00000000, 0x00000000, \
11450x00000000, 0x00000000, 0x00000000, 0x00000000, \
11460x00000000, 0x00000000, 0x00000000, 0x00000000, \
11470x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
11480x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
11490x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
11500x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
11510x00300006, 0x00E014FB, 0x00000000, 0x00000000, \
11520x00000000, 0x00000000, 0x00000000, 0x00000000, \
11530x00000000, 0x00000000, 0x00000000, 0x00000000, \
11540x00000000, 0x00000000, 0x00000000, 0x00000000, \
11550x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000, \
11560x00906EFD, 0x00900EFD, 0x00E00EF8, 0x00000000, \
11570x00000000, 0x00000000, 0x00000000, 0x00000000, \
11580x00000000, 0x00000000, 0x00000000, 0x00000000, \
11590x00000000, 0x00000000, 0x00000000, 0x00000000, \
11600x00000000, 0x00000000, 0x00000000, 0x00000000, \
11610x00000000, 0x00000000, 0x00000000, 0x00000000, \
11620x00000000, 0x00000000, 0x00000000, 0x00000000, \
11630x00000000, 0x00000000, 0x00000000, 0x00000000, \
11640x00000000, 0x00000000, 0x00000000, 0x00000000, \
11650x00000000, 0x00000000, 0x00000000, 0x00000000, \
11660x00000000, 0x00000000, 0x00000000, 0x00000000, \
11670x00000000, 0x00000000, 0x00000000, 0x00000000, \
11680x00000000, 0x00000000, 0x00000000, 0x00000000, \
11690x00000000, 0x00000000, 0x00000000, 0x00000000, \
11700x00000000, 0x00000000, 0x00000000, 0x00000000, \
1171}
1172
24180333 1173static void e100_setup_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1da177e4 1174{
2afecc04
JB		 1175/* *INDENT-OFF* */
1176 static struct {
1177 u32 ucode[UCODE_SIZE + 1];
1178 u8 mac;
1179 u8 timer_dword;
1180 u8 bundle_dword;
1181 u8 min_size_dword;
1182 } ucode_opts[] = {
1183 { D101M_B_RCVBUNDLE_UCODE,
1184 mac_82559_D101M,
1185 D101M_CPUSAVER_TIMER_DWORD,
1186 D101M_CPUSAVER_BUNDLE_DWORD,
1187 D101M_CPUSAVER_MIN_SIZE_DWORD },
1188 { D101S_RCVBUNDLE_UCODE,
1189 mac_82559_D101S,
1190 D101S_CPUSAVER_TIMER_DWORD,
1191 D101S_CPUSAVER_BUNDLE_DWORD,
1192 D101S_CPUSAVER_MIN_SIZE_DWORD },
1193 { D102_E_RCVBUNDLE_UCODE,
1194 mac_82551_F,
1195 D102_E_CPUSAVER_TIMER_DWORD,
1196 D102_E_CPUSAVER_BUNDLE_DWORD,
1197 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1198 { D102_E_RCVBUNDLE_UCODE,
1199 mac_82551_10,
1200 D102_E_CPUSAVER_TIMER_DWORD,
1201 D102_E_CPUSAVER_BUNDLE_DWORD,
1202 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1203 { {0}, 0, 0, 0, 0}
1204 }, *opts;
1205/* *INDENT-ON* */
1206
1207/*************************************************************************
1208* CPUSaver parameters
1209*
1210* All CPUSaver parameters are 16-bit literals that are part of a
1211* "move immediate value" instruction. By changing the value of
1212* the literal in the instruction before the code is loaded, the
1213* driver can change the algorithm.
1214*
1215* INTDELAY - This loads the dead-man timer with its inital value.
05479938 1216* When this timer expires the interrupt is asserted, and the
2afecc04
JB		 1217* timer is reset each time a new packet is received. (see
1218* BUNDLEMAX below to set the limit on number of chained packets)
1219* The current default is 0x600 or 1536. Experiments show that
1220* the value should probably stay within the 0x200 - 0x1000.
1221*
05479938 1222* BUNDLEMAX -
2afecc04
JB		 1223* This sets the maximum number of frames that will be bundled. In
1224* some situations, such as the TCP windowing algorithm, it may be
1225* better to limit the growth of the bundle size than let it go as
1226* high as it can, because that could cause too much added latency.
1227* The default is six, because this is the number of packets in the
1228* default TCP window size. A value of 1 would make CPUSaver indicate
1229* an interrupt for every frame received. If you do not want to put
1230* a limit on the bundle size, set this value to xFFFF.
1231*
05479938 1232* BUNDLESMALL -
2afecc04
JB		 1233* This contains a bit-mask describing the minimum size frame that
1234* will be bundled. The default masks the lower 7 bits, which means
1235* that any frame less than 128 bytes in length will not be bundled,
1236* but will instead immediately generate an interrupt. This does
1237* not affect the current bundle in any way. Any frame that is 128
1238* bytes or large will be bundled normally. This feature is meant
1239* to provide immediate indication of ACK frames in a TCP environment.
1240* Customers were seeing poor performance when a machine with CPUSaver
1241* enabled was sending but not receiving. The delay introduced when
1242* the ACKs were received was enough to reduce total throughput, because
1243* the sender would sit idle until the ACK was finally seen.
1244*
1245* The current default is 0xFF80, which masks out the lower 7 bits.
1246* This means that any frame which is x7F (127) bytes or smaller
05479938 1247* will cause an immediate interrupt. Because this value must be a
2afecc04
JB		 1248* bit mask, there are only a few valid values that can be used. To
1249* turn this feature off, the driver can write the value xFFFF to the
1250* lower word of this instruction (in the same way that the other
1251* parameters are used). Likewise, a value of 0xF800 (2047) would
1252* cause an interrupt to be generated for every frame, because all
1253* standard Ethernet frames are <= 2047 bytes in length.
1254*************************************************************************/
1255
05479938 1256/* if you wish to disable the ucode functionality, while maintaining the
2afecc04
JB		 1257 * workarounds it provides, set the following defines to:
1258 * BUNDLESMALL 0
1259 * BUNDLEMAX 1
1260 * INTDELAY 1
1261 */
1262#define BUNDLESMALL 1
1263#define BUNDLEMAX (u16)6
1264#define INTDELAY (u16)1536 /* 0x600 */
1265
1266 /* do not load u-code for ICH devices */
1267 if (nic->flags & ich)
1268 goto noloaducode;
1269
1270 /* Search for ucode match against h/w rev_id */
1271 for (opts = ucode_opts; opts->mac; opts++) {
1272 int i;
1273 u32 *ucode = opts->ucode;
1274 if (nic->mac != opts->mac)
1275 continue;
1276
1277 /* Insert user-tunable settings */
1278 ucode[opts->timer_dword] &= 0xFFFF0000;
1279 ucode[opts->timer_dword] |= INTDELAY;
1280 ucode[opts->bundle_dword] &= 0xFFFF0000;
1281 ucode[opts->bundle_dword] |= BUNDLEMAX;
1282 ucode[opts->min_size_dword] &= 0xFFFF0000;
1283 ucode[opts->min_size_dword] |= (BUNDLESMALL) ? 0xFFFF : 0xFF80;
1284
1285 for (i = 0; i < UCODE_SIZE; i++)
875521dd 1286 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
24180333 1287 cb->command = cpu_to_le16(cb_ucode | cb_el);
2afecc04
JB		 1288 return;
1289 }
1290
1291noloaducode:
24180333
JB		 1292 cb->command = cpu_to_le16(cb_nop | cb_el);
1293}
1294
1295static inline int e100_exec_cb_wait(struct nic *nic, struct sk_buff *skb,
1296 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
1297{
1298 int err = 0, counter = 50;
1299 struct cb *cb = nic->cb_to_clean;
1300
1301 if ((err = e100_exec_cb(nic, NULL, e100_setup_ucode)))
1302 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
05479938 1303
24180333
JB		 1304 /* must restart cuc */
1305 nic->cuc_cmd = cuc_start;
1306
1307 /* wait for completion */
1308 e100_write_flush(nic);
1309 udelay(10);
1310
1311 /* wait for possibly (ouch) 500ms */
1312 while (!(cb->status & cpu_to_le16(cb_complete))) {
1313 msleep(10);
1314 if (!--counter) break;
1315 }
05479938 1316
24180333
JB		 1317 /* ack any interupts, something could have been set */
1318 writeb(~0, &nic->csr->scb.stat_ack);
1319
1320 /* if the command failed, or is not OK, notify and return */
1321 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1322 DPRINTK(PROBE,ERR, "ucode load failed\n");
1323 err = -EPERM;
1324 }
05479938 1325
24180333 1326 return err;
1da177e4
LT		 1327}
1328
1329static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1330 struct sk_buff *skb)
1331{
1332 cb->command = cpu_to_le16(cb_iaaddr);
1333 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1334}
1335
1336static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1337{
1338 cb->command = cpu_to_le16(cb_dump);
1339 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1340 offsetof(struct mem, dump_buf));
1341}
1342
1343#define NCONFIG_AUTO_SWITCH 0x0080
1344#define MII_NSC_CONG MII_RESV1
1345#define NSC_CONG_ENABLE 0x0100
1346#define NSC_CONG_TXREADY 0x0400
1347#define ADVERTISE_FC_SUPPORTED 0x0400
1348static int e100_phy_init(struct nic *nic)
1349{
1350 struct net_device *netdev = nic->netdev;
1351 u32 addr;
1352 u16 bmcr, stat, id_lo, id_hi, cong;
1353
1354 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1355 for(addr = 0; addr < 32; addr++) {
1356 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1357 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1358 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1359 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1360 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1361 break;
1362 }
1363 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1364 if(addr == 32)
1365 return -EAGAIN;
1366
1367 /* Selected the phy and isolate the rest */
1368 for(addr = 0; addr < 32; addr++) {
1369 if(addr != nic->mii.phy_id) {
1370 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1371 } else {
1372 bmcr = mdio_read(netdev, addr, MII_BMCR);
1373 mdio_write(netdev, addr, MII_BMCR,
1374 bmcr & ~BMCR_ISOLATE);
1375 }
1376 }
1377
1378 /* Get phy ID */
1379 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1380 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1381 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1382 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1383
1384 /* Handle National tx phys */
1385#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1386 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1387 /* Disable congestion control */
1388 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1389 cong |= NSC_CONG_TXREADY;
1390 cong &= ~NSC_CONG_ENABLE;
1391 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1392 }
1393
05479938 1394 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
64895145
MC		 1395 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000))) {
1396 /* enable/disable MDI/MDI-X auto-switching.
1397 MDI/MDI-X auto-switching is disabled for 82551ER/QM chips */
1398 if((nic->mac == mac_82551_E) || (nic->mac == mac_82551_F) ||
05479938
JB		 1399 (nic->mac == mac_82551_10) || (nic->mii.force_media) ||
1400 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))
64895145
MC		 1401 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 0);
1402 else
1403 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, NCONFIG_AUTO_SWITCH);
1404 }
1da177e4
LT		 1405
1406 return 0;
1407}
1408
1409static int e100_hw_init(struct nic *nic)
1410{
1411 int err;
1412
1413 e100_hw_reset(nic);
1414
1415 DPRINTK(HW, ERR, "e100_hw_init\n");
1416 if(!in_interrupt() && (err = e100_self_test(nic)))
1417 return err;
1418
1419 if((err = e100_phy_init(nic)))
1420 return err;
1421 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1422 return err;
1423 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1424 return err;
24180333 1425 if ((err = e100_exec_cb_wait(nic, NULL, e100_setup_ucode)))
1da177e4
LT		 1426 return err;
1427 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1428 return err;
1429 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1430 return err;
1431 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1432 nic->dma_addr + offsetof(struct mem, stats))))
1433 return err;
1434 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1435 return err;
1436
1437 e100_disable_irq(nic);
1438
1439 return 0;
1440}
1441
1442static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1443{
1444 struct net_device *netdev = nic->netdev;
1445 struct dev_mc_list *list = netdev->mc_list;
1446 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1447
1448 cb->command = cpu_to_le16(cb_multi);
1449 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1450 for(i = 0; list && i < count; i++, list = list->next)
1451 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1452 ETH_ALEN);
1453}
1454
1455static void e100_set_multicast_list(struct net_device *netdev)
1456{
1457 struct nic *nic = netdev_priv(netdev);
1458
1459 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1460 netdev->mc_count, netdev->flags);
1461
1462 if(netdev->flags & IFF_PROMISC)
1463 nic->flags |= promiscuous;
1464 else
1465 nic->flags &= ~promiscuous;
1466
1467 if(netdev->flags & IFF_ALLMULTI ||
1468 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1469 nic->flags |= multicast_all;
1470 else
1471 nic->flags &= ~multicast_all;
1472
1473 e100_exec_cb(nic, NULL, e100_configure);
1474 e100_exec_cb(nic, NULL, e100_multi);
1475}
1476
1477static void e100_update_stats(struct nic *nic)
1478{
1479 struct net_device_stats *ns = &nic->net_stats;
1480 struct stats *s = &nic->mem->stats;
1481 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1482 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1483 &s->complete;
1484
1485 /* Device's stats reporting may take several microseconds to
1486 * complete, so where always waiting for results of the
1487 * previous command. */
1488
1489 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1490 *complete = 0;
1491 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1492 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1493 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1494 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1495 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1496 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1497 ns->collisions += nic->tx_collisions;
1498 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1499 le32_to_cpu(s->tx_lost_crs);
1da177e4
LT		 1500 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1501 nic->rx_over_length_errors;
1502 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1503 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1504 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1505 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
ecf7130b 1506 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1da177e4
LT		 1507 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1508 le32_to_cpu(s->rx_alignment_errors) +
1509 le32_to_cpu(s->rx_short_frame_errors) +
1510 le32_to_cpu(s->rx_cdt_errors);
1511 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1512 nic->tx_single_collisions +=
1513 le32_to_cpu(s->tx_single_collisions);
1514 nic->tx_multiple_collisions +=
1515 le32_to_cpu(s->tx_multiple_collisions);
1516 if(nic->mac >= mac_82558_D101_A4) {
1517 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1518 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1519 nic->rx_fc_unsupported +=
1520 le32_to_cpu(s->fc_rcv_unsupported);
1521 if(nic->mac >= mac_82559_D101M) {
1522 nic->tx_tco_frames +=
1523 le16_to_cpu(s->xmt_tco_frames);
1524 nic->rx_tco_frames +=
1525 le16_to_cpu(s->rcv_tco_frames);
1526 }
1527 }
1528 }
1529
05479938 1530
1f53367d
MC		 1531 if(e100_exec_cmd(nic, cuc_dump_reset, 0))
1532 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1da177e4
LT		 1533}
1534
1535static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1536{
1537 /* Adjust inter-frame-spacing (IFS) between two transmits if
1538 * we're getting collisions on a half-duplex connection. */
1539
1540 if(duplex == DUPLEX_HALF) {
1541 u32 prev = nic->adaptive_ifs;
1542 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1543
1544 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1545 (nic->tx_frames > min_frames)) {
1546 if(nic->adaptive_ifs < 60)
1547 nic->adaptive_ifs += 5;
1548 } else if (nic->tx_frames < min_frames) {
1549 if(nic->adaptive_ifs >= 5)
1550 nic->adaptive_ifs -= 5;
1551 }
1552 if(nic->adaptive_ifs != prev)
1553 e100_exec_cb(nic, NULL, e100_configure);
1554 }
1555}
1556
1557static void e100_watchdog(unsigned long data)
1558{
1559 struct nic *nic = (struct nic *)data;
1560 struct ethtool_cmd cmd;
1561
1562 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1563
1564 /* mii library handles link maintenance tasks */
1565
1566 mii_ethtool_gset(&nic->mii, &cmd);
1567
1568 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1569 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1570 cmd.speed == SPEED_100 ? "100" : "10",
1571 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1572 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1573 DPRINTK(LINK, INFO, "link down\n");
1574 }
1575
1576 mii_check_link(&nic->mii);
1577
1578 /* Software generated interrupt to recover from (rare) Rx
05479938
JB		 1579 * allocation failure.
1580 * Unfortunately have to use a spinlock to not re-enable interrupts
1581 * accidentally, due to hardware that shares a register between the
1582 * interrupt mask bit and the SW Interrupt generation bit */
1da177e4
LT		 1583 spin_lock_irq(&nic->cmd_lock);
1584 writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1585 spin_unlock_irq(&nic->cmd_lock);
1586 e100_write_flush(nic);
1587
1588 e100_update_stats(nic);
1589 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1590
1591 if(nic->mac <= mac_82557_D100_C)
1592 /* Issue a multicast command to workaround a 557 lock up */
1593 e100_set_multicast_list(nic->netdev);
1594
1595 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1596 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1597 nic->flags |= ich_10h_workaround;
1598 else
1599 nic->flags &= ~ich_10h_workaround;
1600
1601 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1602}
1603
858119e1 1604static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1da177e4
LT		 1605 struct sk_buff *skb)
1606{
1607 cb->command = nic->tx_command;
962082b6 1608 /* interrupt every 16 packets regardless of delay */
996ec353
MC		 1609 if((nic->cbs_avail & ~15) == nic->cbs_avail)
1610 cb->command |= cpu_to_le16(cb_i);
1da177e4
LT		 1611 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1612 cb->u.tcb.tcb_byte_count = 0;
1613 cb->u.tcb.threshold = nic->tx_threshold;
1614 cb->u.tcb.tbd_count = 1;
1615 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1616 skb->data, skb->len, PCI_DMA_TODEVICE));
611494dc 1617 /* check for mapping failure? */
1da177e4
LT		 1618 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1619}
1620
1621static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1622{
1623 struct nic *nic = netdev_priv(netdev);
1624 int err;
1625
1626 if(nic->flags & ich_10h_workaround) {
1627 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1628 Issue a NOP command followed by a 1us delay before
1629 issuing the Tx command. */
1f53367d
MC		 1630 if(e100_exec_cmd(nic, cuc_nop, 0))
1631 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1da177e4
LT		 1632 udelay(1);
1633 }
1634
1635 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1636
1637 switch(err) {
1638 case -ENOSPC:
1639 /* We queued the skb, but now we're out of space. */
1640 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1641 netif_stop_queue(netdev);
1642 break;
1643 case -ENOMEM:
1644 /* This is a hard error - log it. */
1645 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1646 netif_stop_queue(netdev);
1647 return 1;
1648 }
1649
1650 netdev->trans_start = jiffies;
1651 return 0;
1652}
1653
858119e1 1654static int e100_tx_clean(struct nic *nic)
1da177e4
LT		 1655{
1656 struct cb *cb;
1657 int tx_cleaned = 0;
1658
1659 spin_lock(&nic->cb_lock);
1660
1661 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1662 nic->cb_to_clean->status);
1663
1664 /* Clean CBs marked complete */
1665 for(cb = nic->cb_to_clean;
1666 cb->status & cpu_to_le16(cb_complete);
1667 cb = nic->cb_to_clean = cb->next) {
1668 if(likely(cb->skb != NULL)) {
1669 nic->net_stats.tx_packets++;
1670 nic->net_stats.tx_bytes += cb->skb->len;
1671
1672 pci_unmap_single(nic->pdev,
1673 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1674 le16_to_cpu(cb->u.tcb.tbd.size),
1675 PCI_DMA_TODEVICE);
1676 dev_kfree_skb_any(cb->skb);
1677 cb->skb = NULL;
1678 tx_cleaned = 1;
1679 }
1680 cb->status = 0;
1681 nic->cbs_avail++;
1682 }
1683
1684 spin_unlock(&nic->cb_lock);
1685
1686 /* Recover from running out of Tx resources in xmit_frame */
1687 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1688 netif_wake_queue(nic->netdev);
1689
1690 return tx_cleaned;
1691}
1692
1693static void e100_clean_cbs(struct nic *nic)
1694{
1695 if(nic->cbs) {
1696 while(nic->cbs_avail != nic->params.cbs.count) {
1697 struct cb *cb = nic->cb_to_clean;
1698 if(cb->skb) {
1699 pci_unmap_single(nic->pdev,
1700 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1701 le16_to_cpu(cb->u.tcb.tbd.size),
1702 PCI_DMA_TODEVICE);
1703 dev_kfree_skb(cb->skb);
1704 }
1705 nic->cb_to_clean = nic->cb_to_clean->next;
1706 nic->cbs_avail++;
1707 }
1708 pci_free_consistent(nic->pdev,
1709 sizeof(struct cb) * nic->params.cbs.count,
1710 nic->cbs, nic->cbs_dma_addr);
1711 nic->cbs = NULL;
1712 nic->cbs_avail = 0;
1713 }
1714 nic->cuc_cmd = cuc_start;
1715 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1716 nic->cbs;
1717}
1718
1719static int e100_alloc_cbs(struct nic *nic)
1720{
1721 struct cb *cb;
1722 unsigned int i, count = nic->params.cbs.count;
1723
1724 nic->cuc_cmd = cuc_start;
1725 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1726 nic->cbs_avail = 0;
1727
1728 nic->cbs = pci_alloc_consistent(nic->pdev,
1729 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1730 if(!nic->cbs)
1731 return -ENOMEM;
1732
1733 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1734 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1735 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1736
1737 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1738 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1739 ((i+1) % count) * sizeof(struct cb));
1740 cb->skb = NULL;
1741 }
1742
1743 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1744 nic->cbs_avail = count;
1745
1746 return 0;
1747}
1748
1f53367d 1749static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1da177e4 1750{
1f53367d
MC		 1751 if(!nic->rxs) return;
1752 if(RU_SUSPENDED != nic->ru_running) return;
1753
1754 /* handle init time starts */
1755 if(!rx) rx = nic->rxs;
1756
1da177e4 1757 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1f53367d
MC		 1758 if(rx->skb) {
1759 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1760 nic->ru_running = RU_RUNNING;
1da177e4
LT		 1761 }
1762}
1763
1764#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
858119e1 1765static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1da177e4
LT		 1766{
1767 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN)))
1768 return -ENOMEM;
1769
1770 /* Align, init, and map the RFD. */
1771 rx->skb->dev = nic->netdev;
1772 skb_reserve(rx->skb, NET_IP_ALIGN);
1773 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1774 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1775 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1776
1f53367d
MC		 1777 if(pci_dma_mapping_error(rx->dma_addr)) {
1778 dev_kfree_skb_any(rx->skb);
097688ef 1779 rx->skb = NULL;
1f53367d
MC		 1780 rx->dma_addr = 0;
1781 return -ENOMEM;
1782 }
1783
1da177e4
LT		 1784 /* Link the RFD to end of RFA by linking previous RFD to
1785 * this one, and clearing EL bit of previous. */
1786 if(rx->prev->skb) {
1787 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1788 put_unaligned(cpu_to_le32(rx->dma_addr),
1789 (u32 *)&prev_rfd->link);
1790 wmb();
1791 prev_rfd->command &= ~cpu_to_le16(cb_el);
1792 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1793 sizeof(struct rfd), PCI_DMA_TODEVICE);
1794 }
1795
1796 return 0;
1797}
1798
858119e1 1799static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1da177e4
LT		 1800 unsigned int *work_done, unsigned int work_to_do)
1801{
1802 struct sk_buff *skb = rx->skb;
1803 struct rfd *rfd = (struct rfd *)skb->data;
1804 u16 rfd_status, actual_size;
1805
1806 if(unlikely(work_done && *work_done >= work_to_do))
1807 return -EAGAIN;
1808
1809 /* Need to sync before taking a peek at cb_complete bit */
1810 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1811 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1812 rfd_status = le16_to_cpu(rfd->status);
1813
1814 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1815
1816 /* If data isn't ready, nothing to indicate */
1817 if(unlikely(!(rfd_status & cb_complete)))
1f53367d 1818 return -ENODATA;
1da177e4
LT		 1819
1820 /* Get actual data size */
1821 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1822 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1823 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1824
1825 /* Get data */
1826 pci_unmap_single(nic->pdev, rx->dma_addr,
1827 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1828
1f53367d
MC		 1829 /* this allows for a fast restart without re-enabling interrupts */
1830 if(le16_to_cpu(rfd->command) & cb_el)
1831 nic->ru_running = RU_SUSPENDED;
1832
1da177e4
LT		 1833 /* Pull off the RFD and put the actual data (minus eth hdr) */
1834 skb_reserve(skb, sizeof(struct rfd));
1835 skb_put(skb, actual_size);
1836 skb->protocol = eth_type_trans(skb, nic->netdev);
1837
1838 if(unlikely(!(rfd_status & cb_ok))) {
1839 /* Don't indicate if hardware indicates errors */
1da177e4 1840 dev_kfree_skb_any(skb);
136df52d 1841 } else if(actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1da177e4
LT		 1842 /* Don't indicate oversized frames */
1843 nic->rx_over_length_errors++;
1da177e4
LT		 1844 dev_kfree_skb_any(skb);
1845 } else {
1846 nic->net_stats.rx_packets++;
1847 nic->net_stats.rx_bytes += actual_size;
1848 nic->netdev->last_rx = jiffies;
1849 netif_receive_skb(skb);
1850 if(work_done)
1851 (*work_done)++;
1852 }
1853
1854 rx->skb = NULL;
1855
1856 return 0;
1857}
1858
858119e1 1859static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1da177e4
LT		 1860 unsigned int work_to_do)
1861{
1862 struct rx *rx;
1f53367d
MC		 1863 int restart_required = 0;
1864 struct rx *rx_to_start = NULL;
1865
1866 /* are we already rnr? then pay attention!!! this ensures that
05479938 1867 * the state machine progression never allows a start with a
1f53367d
MC		 1868 * partially cleaned list, avoiding a race between hardware
1869 * and rx_to_clean when in NAPI mode */
1870 if(RU_SUSPENDED == nic->ru_running)
1871 restart_required = 1;
1da177e4
LT		 1872
1873 /* Indicate newly arrived packets */
1874 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1f53367d
MC		 1875 int err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1876 if(-EAGAIN == err) {
1877 /* hit quota so have more work to do, restart once
1878 * cleanup is complete */
1879 restart_required = 0;
1880 break;
1881 } else if(-ENODATA == err)
1da177e4
LT		 1882 break; /* No more to clean */
1883 }
1884
1f53367d
MC		 1885 /* save our starting point as the place we'll restart the receiver */
1886 if(restart_required)
1887 rx_to_start = nic->rx_to_clean;
1888
1da177e4
LT		 1889 /* Alloc new skbs to refill list */
1890 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1891 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1892 break; /* Better luck next time (see watchdog) */
1893 }
1894
1f53367d
MC		 1895 if(restart_required) {
1896 // ack the rnr?
1897 writeb(stat_ack_rnr, &nic->csr->scb.stat_ack);
1898 e100_start_receiver(nic, rx_to_start);
1899 if(work_done)
1900 (*work_done)++;
1901 }
1da177e4
LT		 1902}
1903
1904static void e100_rx_clean_list(struct nic *nic)
1905{
1906 struct rx *rx;
1907 unsigned int i, count = nic->params.rfds.count;
1908
1f53367d
MC		 1909 nic->ru_running = RU_UNINITIALIZED;
1910
1da177e4
LT		 1911 if(nic->rxs) {
1912 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1913 if(rx->skb) {
1914 pci_unmap_single(nic->pdev, rx->dma_addr,
1915 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1916 dev_kfree_skb(rx->skb);
1917 }
1918 }
1919 kfree(nic->rxs);
1920 nic->rxs = NULL;
1921 }
1922
1923 nic->rx_to_use = nic->rx_to_clean = NULL;
1da177e4
LT		 1924}
1925
1926static int e100_rx_alloc_list(struct nic *nic)
1927{
1928 struct rx *rx;
1929 unsigned int i, count = nic->params.rfds.count;
1930
1931 nic->rx_to_use = nic->rx_to_clean = NULL;
1f53367d 1932 nic->ru_running = RU_UNINITIALIZED;
1da177e4
LT		 1933
1934 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1935 return -ENOMEM;
1936 memset(nic->rxs, 0, sizeof(struct rx) * count);
1937
1938 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1939 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1940 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1941 if(e100_rx_alloc_skb(nic, rx)) {
1942 e100_rx_clean_list(nic);
1943 return -ENOMEM;
1944 }
1945 }
1946
1947 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1f53367d 1948 nic->ru_running = RU_SUSPENDED;
1da177e4
LT		 1949
1950 return 0;
1951}
1952
1953static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1954{
1955 struct net_device *netdev = dev_id;
1956 struct nic *nic = netdev_priv(netdev);
1957 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1958
1959 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1960
1961 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1962 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1963 return IRQ_NONE;
1964
1965 /* Ack interrupt(s) */
1966 writeb(stat_ack, &nic->csr->scb.stat_ack);
1967
1968 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1969 if(stat_ack & stat_ack_rnr)
1f53367d 1970 nic->ru_running = RU_SUSPENDED;
1da177e4 1971
0685c31b
MC		 1972 if(likely(netif_rx_schedule_prep(netdev))) {
1973 e100_disable_irq(nic);
1974 __netif_rx_schedule(netdev);
1975 }
1da177e4
LT		 1976
1977 return IRQ_HANDLED;
1978}
1979
1980static int e100_poll(struct net_device *netdev, int *budget)
1981{
1982 struct nic *nic = netdev_priv(netdev);
1983 unsigned int work_to_do = min(netdev->quota, *budget);
1984 unsigned int work_done = 0;
1985 int tx_cleaned;
1986
1987 e100_rx_clean(nic, &work_done, work_to_do);
1988 tx_cleaned = e100_tx_clean(nic);
1989
1990 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1991 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1992 netif_rx_complete(netdev);
1993 e100_enable_irq(nic);
1994 return 0;
1995 }
1996
1997 *budget -= work_done;
1998 netdev->quota -= work_done;
1999
2000 return 1;
2001}
2002
2003#ifdef CONFIG_NET_POLL_CONTROLLER
2004static void e100_netpoll(struct net_device *netdev)
2005{
2006 struct nic *nic = netdev_priv(netdev);
611494dc 2007
1da177e4
LT		 2008 e100_disable_irq(nic);
2009 e100_intr(nic->pdev->irq, netdev, NULL);
2010 e100_tx_clean(nic);
2011 e100_enable_irq(nic);
2012}
2013#endif
2014
2015static struct net_device_stats *e100_get_stats(struct net_device *netdev)
2016{
2017 struct nic *nic = netdev_priv(netdev);
2018 return &nic->net_stats;
2019}
2020
2021static int e100_set_mac_address(struct net_device *netdev, void *p)
2022{
2023 struct nic *nic = netdev_priv(netdev);
2024 struct sockaddr *addr = p;
2025
2026 if (!is_valid_ether_addr(addr->sa_data))
2027 return -EADDRNOTAVAIL;
2028
2029 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2030 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2031
2032 return 0;
2033}
2034
2035static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2036{
2037 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2038 return -EINVAL;
2039 netdev->mtu = new_mtu;
2040 return 0;
2041}
2042
6bdacb1a 2043#ifdef CONFIG_PM
1da177e4
LT		 2044static int e100_asf(struct nic *nic)
2045{
2046 /* ASF can be enabled from eeprom */
2047 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2048 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2049 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2050 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2051}
6bdacb1a 2052#endif
1da177e4
LT		 2053
2054static int e100_up(struct nic *nic)
2055{
2056 int err;
2057
2058 if((err = e100_rx_alloc_list(nic)))
2059 return err;
2060 if((err = e100_alloc_cbs(nic)))
2061 goto err_rx_clean_list;
2062 if((err = e100_hw_init(nic)))
2063 goto err_clean_cbs;
2064 e100_set_multicast_list(nic->netdev);
097688ef 2065 e100_start_receiver(nic, NULL);
1da177e4
LT		 2066 mod_timer(&nic->watchdog, jiffies);
2067 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
2068 nic->netdev->name, nic->netdev)))
2069 goto err_no_irq;
1da177e4 2070 netif_wake_queue(nic->netdev);
0236ebb7
MC		 2071 netif_poll_enable(nic->netdev);
2072 /* enable ints _after_ enabling poll, preventing a race between
2073 * disable ints+schedule */
2074 e100_enable_irq(nic);
1da177e4
LT		 2075 return 0;
2076
2077err_no_irq:
2078 del_timer_sync(&nic->watchdog);
2079err_clean_cbs:
2080 e100_clean_cbs(nic);
2081err_rx_clean_list:
2082 e100_rx_clean_list(nic);
2083 return err;
2084}
2085
2086static void e100_down(struct nic *nic)
2087{
0236ebb7
MC		 2088 /* wait here for poll to complete */
2089 netif_poll_disable(nic->netdev);
2090 netif_stop_queue(nic->netdev);
1da177e4
LT		 2091 e100_hw_reset(nic);
2092 free_irq(nic->pdev->irq, nic->netdev);
2093 del_timer_sync(&nic->watchdog);
2094 netif_carrier_off(nic->netdev);
1da177e4
LT		 2095 e100_clean_cbs(nic);
2096 e100_rx_clean_list(nic);
2097}
2098
2099static void e100_tx_timeout(struct net_device *netdev)
2100{
2101 struct nic *nic = netdev_priv(netdev);
2102
05479938 2103 /* Reset outside of interrupt context, to avoid request_irq
2acdb1e0
MC		 2104 * in interrupt context */
2105 schedule_work(&nic->tx_timeout_task);
2106}
2107
2108static void e100_tx_timeout_task(struct net_device *netdev)
2109{
2110 struct nic *nic = netdev_priv(netdev);
2111
1da177e4
LT		 2112 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2113 readb(&nic->csr->scb.status));
2114 e100_down(netdev_priv(netdev));
2115 e100_up(netdev_priv(netdev));
2116}
2117
2118static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2119{
2120 int err;
2121 struct sk_buff *skb;
2122
2123 /* Use driver resources to perform internal MAC or PHY
2124 * loopback test. A single packet is prepared and transmitted
2125 * in loopback mode, and the test passes if the received
2126 * packet compares byte-for-byte to the transmitted packet. */
2127
2128 if((err = e100_rx_alloc_list(nic)))
2129 return err;
2130 if((err = e100_alloc_cbs(nic)))
2131 goto err_clean_rx;
2132
2133 /* ICH PHY loopback is broken so do MAC loopback instead */
2134 if(nic->flags & ich && loopback_mode == lb_phy)
2135 loopback_mode = lb_mac;
2136
2137 nic->loopback = loopback_mode;
2138 if((err = e100_hw_init(nic)))
2139 goto err_loopback_none;
2140
2141 if(loopback_mode == lb_phy)
2142 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2143 BMCR_LOOPBACK);
2144
097688ef 2145 e100_start_receiver(nic, NULL);
1da177e4
LT		 2146
2147 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
2148 err = -ENOMEM;
2149 goto err_loopback_none;
2150 }
2151 skb_put(skb, ETH_DATA_LEN);
2152 memset(skb->data, 0xFF, ETH_DATA_LEN);
2153 e100_xmit_frame(skb, nic->netdev);
2154
2155 msleep(10);
2156
2157 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2158 skb->data, ETH_DATA_LEN))
2159 err = -EAGAIN;
2160
2161err_loopback_none:
2162 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2163 nic->loopback = lb_none;
2164 e100_hw_init(nic);
2165 e100_clean_cbs(nic);
2166err_clean_rx:
2167 e100_rx_clean_list(nic);
2168 return err;
2169}
2170
2171#define MII_LED_CONTROL 0x1B
2172static void e100_blink_led(unsigned long data)
2173{
2174 struct nic *nic = (struct nic *)data;
2175 enum led_state {
2176 led_on = 0x01,
2177 led_off = 0x04,
2178 led_on_559 = 0x05,
2179 led_on_557 = 0x07,
2180 };
2181
2182 nic->leds = (nic->leds & led_on) ? led_off :
2183 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2184 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
2185 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2186}
2187
2188static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2189{
2190 struct nic *nic = netdev_priv(netdev);
2191 return mii_ethtool_gset(&nic->mii, cmd);
2192}
2193
2194static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2195{
2196 struct nic *nic = netdev_priv(netdev);
2197 int err;
2198
2199 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2200 err = mii_ethtool_sset(&nic->mii, cmd);
2201 e100_exec_cb(nic, NULL, e100_configure);
2202
2203 return err;
2204}
2205
2206static void e100_get_drvinfo(struct net_device *netdev,
2207 struct ethtool_drvinfo *info)
2208{
2209 struct nic *nic = netdev_priv(netdev);
2210 strcpy(info->driver, DRV_NAME);
2211 strcpy(info->version, DRV_VERSION);
2212 strcpy(info->fw_version, "N/A");
2213 strcpy(info->bus_info, pci_name(nic->pdev));
2214}
2215
2216static int e100_get_regs_len(struct net_device *netdev)
2217{
2218 struct nic *nic = netdev_priv(netdev);
2219#define E100_PHY_REGS 0x1C
2220#define E100_REGS_LEN 1 + E100_PHY_REGS + \
2221 sizeof(nic->mem->dump_buf) / sizeof(u32)
2222 return E100_REGS_LEN * sizeof(u32);
2223}
2224
2225static void e100_get_regs(struct net_device *netdev,
2226 struct ethtool_regs *regs, void *p)
2227{
2228 struct nic *nic = netdev_priv(netdev);
2229 u32 *buff = p;
2230 int i;
2231
2232 regs->version = (1 << 24) | nic->rev_id;
2233 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
2234 readb(&nic->csr->scb.cmd_lo) << 16 |
2235 readw(&nic->csr->scb.status);
2236 for(i = E100_PHY_REGS; i >= 0; i--)
2237 buff[1 + E100_PHY_REGS - i] =
2238 mdio_read(netdev, nic->mii.phy_id, i);
2239 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2240 e100_exec_cb(nic, NULL, e100_dump);
2241 msleep(10);
2242 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2243 sizeof(nic->mem->dump_buf));
2244}
2245
2246static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2247{
2248 struct nic *nic = netdev_priv(netdev);
2249 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2250 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2251}
2252
2253static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2254{
2255 struct nic *nic = netdev_priv(netdev);
2256
2257 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2258 return -EOPNOTSUPP;
2259
2260 if(wol->wolopts)
2261 nic->flags |= wol_magic;
2262 else
2263 nic->flags &= ~wol_magic;
2264
1da177e4
LT		 2265 e100_exec_cb(nic, NULL, e100_configure);
2266
2267 return 0;
2268}
2269
2270static u32 e100_get_msglevel(struct net_device *netdev)
2271{
2272 struct nic *nic = netdev_priv(netdev);
2273 return nic->msg_enable;
2274}
2275
2276static void e100_set_msglevel(struct net_device *netdev, u32 value)
2277{
2278 struct nic *nic = netdev_priv(netdev);
2279 nic->msg_enable = value;
2280}
2281
2282static int e100_nway_reset(struct net_device *netdev)
2283{
2284 struct nic *nic = netdev_priv(netdev);
2285 return mii_nway_restart(&nic->mii);
2286}
2287
2288static u32 e100_get_link(struct net_device *netdev)
2289{
2290 struct nic *nic = netdev_priv(netdev);
2291 return mii_link_ok(&nic->mii);
2292}
2293
2294static int e100_get_eeprom_len(struct net_device *netdev)
2295{
2296 struct nic *nic = netdev_priv(netdev);
2297 return nic->eeprom_wc << 1;
2298}
2299
2300#define E100_EEPROM_MAGIC 0x1234
2301static int e100_get_eeprom(struct net_device *netdev,
2302 struct ethtool_eeprom *eeprom, u8 *bytes)
2303{
2304 struct nic *nic = netdev_priv(netdev);
2305
2306 eeprom->magic = E100_EEPROM_MAGIC;
2307 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2308
2309 return 0;
2310}
2311
2312static int e100_set_eeprom(struct net_device *netdev,
2313 struct ethtool_eeprom *eeprom, u8 *bytes)
2314{
2315 struct nic *nic = netdev_priv(netdev);
2316
2317 if(eeprom->magic != E100_EEPROM_MAGIC)
2318 return -EINVAL;
2319
2320 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2321
2322 return e100_eeprom_save(nic, eeprom->offset >> 1,
2323 (eeprom->len >> 1) + 1);
2324}
2325
2326static void e100_get_ringparam(struct net_device *netdev,
2327 struct ethtool_ringparam *ring)
2328{
2329 struct nic *nic = netdev_priv(netdev);
2330 struct param_range *rfds = &nic->params.rfds;
2331 struct param_range *cbs = &nic->params.cbs;
2332
2333 ring->rx_max_pending = rfds->max;
2334 ring->tx_max_pending = cbs->max;
2335 ring->rx_mini_max_pending = 0;
2336 ring->rx_jumbo_max_pending = 0;
2337 ring->rx_pending = rfds->count;
2338 ring->tx_pending = cbs->count;
2339 ring->rx_mini_pending = 0;
2340 ring->rx_jumbo_pending = 0;
2341}
2342
2343static int e100_set_ringparam(struct net_device *netdev,
2344 struct ethtool_ringparam *ring)
2345{
2346 struct nic *nic = netdev_priv(netdev);
2347 struct param_range *rfds = &nic->params.rfds;
2348 struct param_range *cbs = &nic->params.cbs;
2349
05479938 2350 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1da177e4
LT		 2351 return -EINVAL;
2352
2353 if(netif_running(netdev))
2354 e100_down(nic);
2355 rfds->count = max(ring->rx_pending, rfds->min);
2356 rfds->count = min(rfds->count, rfds->max);
2357 cbs->count = max(ring->tx_pending, cbs->min);
2358 cbs->count = min(cbs->count, cbs->max);
2359 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2360 rfds->count, cbs->count);
2361 if(netif_running(netdev))
2362 e100_up(nic);
2363
2364 return 0;
2365}
2366
2367static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2368 "Link test (on/offline)",
2369 "Eeprom test (on/offline)",
2370 "Self test (offline)",
2371 "Mac loopback (offline)",
2372 "Phy loopback (offline)",
2373};
2374#define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
2375
2376static int e100_diag_test_count(struct net_device *netdev)
2377{
2378 return E100_TEST_LEN;
2379}
2380
2381static void e100_diag_test(struct net_device *netdev,
2382 struct ethtool_test *test, u64 *data)
2383{
2384 struct ethtool_cmd cmd;
2385 struct nic *nic = netdev_priv(netdev);
2386 int i, err;
2387
2388 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2389 data[0] = !mii_link_ok(&nic->mii);
2390 data[1] = e100_eeprom_load(nic);
2391 if(test->flags & ETH_TEST_FL_OFFLINE) {
2392
2393 /* save speed, duplex & autoneg settings */
2394 err = mii_ethtool_gset(&nic->mii, &cmd);
2395
2396 if(netif_running(netdev))
2397 e100_down(nic);
2398 data[2] = e100_self_test(nic);
2399 data[3] = e100_loopback_test(nic, lb_mac);
2400 data[4] = e100_loopback_test(nic, lb_phy);
2401
2402 /* restore speed, duplex & autoneg settings */
2403 err = mii_ethtool_sset(&nic->mii, &cmd);
2404
2405 if(netif_running(netdev))
2406 e100_up(nic);
2407 }
2408 for(i = 0; i < E100_TEST_LEN; i++)
2409 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
a074fb86
MC		 2410
2411 msleep_interruptible(4 * 1000);
1da177e4
LT		 2412}
2413
2414static int e100_phys_id(struct net_device *netdev, u32 data)
2415{
2416 struct nic *nic = netdev_priv(netdev);
2417
2418 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2419 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2420 mod_timer(&nic->blink_timer, jiffies);
2421 msleep_interruptible(data * 1000);
2422 del_timer_sync(&nic->blink_timer);
2423 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2424
2425 return 0;
2426}
2427
2428static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2429 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2430 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2431 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2432 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2433 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2434 "tx_heartbeat_errors", "tx_window_errors",
2435 /* device-specific stats */
2436 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2437 "tx_flow_control_pause", "rx_flow_control_pause",
2438 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2439};
2440#define E100_NET_STATS_LEN 21
2441#define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2442
2443static int e100_get_stats_count(struct net_device *netdev)
2444{
2445 return E100_STATS_LEN;
2446}
2447
2448static void e100_get_ethtool_stats(struct net_device *netdev,
2449 struct ethtool_stats *stats, u64 *data)
2450{
2451 struct nic *nic = netdev_priv(netdev);
2452 int i;
2453
2454 for(i = 0; i < E100_NET_STATS_LEN; i++)
2455 data[i] = ((unsigned long *)&nic->net_stats)[i];
2456
2457 data[i++] = nic->tx_deferred;
2458 data[i++] = nic->tx_single_collisions;
2459 data[i++] = nic->tx_multiple_collisions;
2460 data[i++] = nic->tx_fc_pause;
2461 data[i++] = nic->rx_fc_pause;
2462 data[i++] = nic->rx_fc_unsupported;
2463 data[i++] = nic->tx_tco_frames;
2464 data[i++] = nic->rx_tco_frames;
2465}
2466
2467static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2468{
2469 switch(stringset) {
2470 case ETH_SS_TEST:
2471 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2472 break;
2473 case ETH_SS_STATS:
2474 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2475 break;
2476 }
2477}
2478
2479static struct ethtool_ops e100_ethtool_ops = {
2480 .get_settings = e100_get_settings,
2481 .set_settings = e100_set_settings,
2482 .get_drvinfo = e100_get_drvinfo,
2483 .get_regs_len = e100_get_regs_len,
2484 .get_regs = e100_get_regs,
2485 .get_wol = e100_get_wol,
2486 .set_wol = e100_set_wol,
2487 .get_msglevel = e100_get_msglevel,
2488 .set_msglevel = e100_set_msglevel,
2489 .nway_reset = e100_nway_reset,
2490 .get_link = e100_get_link,
2491 .get_eeprom_len = e100_get_eeprom_len,
2492 .get_eeprom = e100_get_eeprom,
2493 .set_eeprom = e100_set_eeprom,
2494 .get_ringparam = e100_get_ringparam,
2495 .set_ringparam = e100_set_ringparam,
2496 .self_test_count = e100_diag_test_count,
2497 .self_test = e100_diag_test,
2498 .get_strings = e100_get_strings,
2499 .phys_id = e100_phys_id,
2500 .get_stats_count = e100_get_stats_count,
2501 .get_ethtool_stats = e100_get_ethtool_stats,
a92dd923 2502 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 2503};
2504
2505static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2506{
2507 struct nic *nic = netdev_priv(netdev);
2508
2509 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2510}
2511
2512static int e100_alloc(struct nic *nic)
2513{
2514 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2515 &nic->dma_addr);
2516 return nic->mem ? 0 : -ENOMEM;
2517}
2518
2519static void e100_free(struct nic *nic)
2520{
2521 if(nic->mem) {
2522 pci_free_consistent(nic->pdev, sizeof(struct mem),
2523 nic->mem, nic->dma_addr);
2524 nic->mem = NULL;
2525 }
2526}
2527
2528static int e100_open(struct net_device *netdev)
2529{
2530 struct nic *nic = netdev_priv(netdev);
2531 int err = 0;
2532
2533 netif_carrier_off(netdev);
2534 if((err = e100_up(nic)))
2535 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2536 return err;
2537}
2538
2539static int e100_close(struct net_device *netdev)
2540{
2541 e100_down(netdev_priv(netdev));
2542 return 0;
2543}
2544
2545static int __devinit e100_probe(struct pci_dev *pdev,
2546 const struct pci_device_id *ent)
2547{
2548 struct net_device *netdev;
2549 struct nic *nic;
2550 int err;
2551
2552 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2553 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2554 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2555 return -ENOMEM;
2556 }
2557
2558 netdev->open = e100_open;
2559 netdev->stop = e100_close;
2560 netdev->hard_start_xmit = e100_xmit_frame;
2561 netdev->get_stats = e100_get_stats;
2562 netdev->set_multicast_list = e100_set_multicast_list;
2563 netdev->set_mac_address = e100_set_mac_address;
2564 netdev->change_mtu = e100_change_mtu;
2565 netdev->do_ioctl = e100_do_ioctl;
2566 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2567 netdev->tx_timeout = e100_tx_timeout;
2568 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2569 netdev->poll = e100_poll;
2570 netdev->weight = E100_NAPI_WEIGHT;
2571#ifdef CONFIG_NET_POLL_CONTROLLER
2572 netdev->poll_controller = e100_netpoll;
2573#endif
2574 strcpy(netdev->name, pci_name(pdev));
2575
2576 nic = netdev_priv(netdev);
2577 nic->netdev = netdev;
2578 nic->pdev = pdev;
2579 nic->msg_enable = (1 << debug) - 1;
2580 pci_set_drvdata(pdev, netdev);
2581
2582 if((err = pci_enable_device(pdev))) {
2583 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2584 goto err_out_free_dev;
2585 }
2586
2587 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2588 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2589 "base address, aborting.\n");
2590 err = -ENODEV;
2591 goto err_out_disable_pdev;
2592 }
2593
2594 if((err = pci_request_regions(pdev, DRV_NAME))) {
2595 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2596 goto err_out_disable_pdev;
2597 }
2598
1e7f0bd8 2599 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 2600 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2601 goto err_out_free_res;
2602 }
2603
2604 SET_MODULE_OWNER(netdev);
2605 SET_NETDEV_DEV(netdev, &pdev->dev);
2606
2607 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2608 if(!nic->csr) {
2609 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2610 err = -ENOMEM;
2611 goto err_out_free_res;
2612 }
2613
2614 if(ent->driver_data)
2615 nic->flags |= ich;
2616 else
2617 nic->flags &= ~ich;
2618
2619 e100_get_defaults(nic);
2620
1f53367d 2621 /* locks must be initialized before calling hw_reset */
1da177e4
LT		 2622 spin_lock_init(&nic->cb_lock);
2623 spin_lock_init(&nic->cmd_lock);
ac7c6669 2624 spin_lock_init(&nic->mdio_lock);
1da177e4
LT		 2625
2626 /* Reset the device before pci_set_master() in case device is in some
2627 * funky state and has an interrupt pending - hint: we don't have the
2628 * interrupt handler registered yet. */
2629 e100_hw_reset(nic);
2630
2631 pci_set_master(pdev);
2632
2633 init_timer(&nic->watchdog);
2634 nic->watchdog.function = e100_watchdog;
2635 nic->watchdog.data = (unsigned long)nic;
2636 init_timer(&nic->blink_timer);
2637 nic->blink_timer.function = e100_blink_led;
2638 nic->blink_timer.data = (unsigned long)nic;
2639
2acdb1e0
MC		 2640 INIT_WORK(&nic->tx_timeout_task,
2641 (void (*)(void *))e100_tx_timeout_task, netdev);
2642
1da177e4
LT		 2643 if((err = e100_alloc(nic))) {
2644 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2645 goto err_out_iounmap;
2646 }
2647
1da177e4
LT		 2648 if((err = e100_eeprom_load(nic)))
2649 goto err_out_free;
2650
f92d8728
MC		 2651 e100_phy_init(nic);
2652
1da177e4 2653 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
a92dd923
JL		 2654 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2655 if(!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 2656 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2657 "EEPROM, aborting.\n");
2658 err = -EAGAIN;
2659 goto err_out_free;
2660 }
2661
2662 /* Wol magic packet can be enabled from eeprom */
2663 if((nic->mac >= mac_82558_D101_A4) &&
2664 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2665 nic->flags |= wol_magic;
2666
6bdacb1a 2667 /* ack any pending wake events, disable PME */
3435dbce
JB		 2668 err = pci_enable_wake(pdev, 0, 0);
2669 if (err)
2670 DPRINTK(PROBE, ERR, "Error clearing wake event\n");
1da177e4
LT		 2671
2672 strcpy(netdev->name, "eth%d");
2673 if((err = register_netdev(netdev))) {
2674 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2675 goto err_out_free;
2676 }
2677
2678 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2679 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2680 pci_resource_start(pdev, 0), pdev->irq,
2681 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2682 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2683
2684 return 0;
2685
2686err_out_free:
2687 e100_free(nic);
2688err_out_iounmap:
2689 iounmap(nic->csr);
2690err_out_free_res:
2691 pci_release_regions(pdev);
2692err_out_disable_pdev:
2693 pci_disable_device(pdev);
2694err_out_free_dev:
2695 pci_set_drvdata(pdev, NULL);
2696 free_netdev(netdev);
2697 return err;
2698}
2699
2700static void __devexit e100_remove(struct pci_dev *pdev)
2701{
2702 struct net_device *netdev = pci_get_drvdata(pdev);
2703
2704 if(netdev) {
2705 struct nic *nic = netdev_priv(netdev);
2706 unregister_netdev(netdev);
2707 e100_free(nic);
2708 iounmap(nic->csr);
2709 free_netdev(netdev);
2710 pci_release_regions(pdev);
2711 pci_disable_device(pdev);
2712 pci_set_drvdata(pdev, NULL);
2713 }
2714}
2715
2716#ifdef CONFIG_PM
2717static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2718{
2719 struct net_device *netdev = pci_get_drvdata(pdev);
2720 struct nic *nic = netdev_priv(netdev);
3435dbce 2721 int retval;
1da177e4
LT		 2722
2723 if(netif_running(netdev))
2724 e100_down(nic);
2725 e100_hw_reset(nic);
2726 netif_device_detach(netdev);
2727
2728 pci_save_state(pdev);
3435dbce
JB		 2729 retval = pci_enable_wake(pdev, pci_choose_state(pdev, state),
2730 nic->flags & (wol_magic | e100_asf(nic)));
2731 if (retval)
2732 DPRINTK(PROBE,ERR, "Error enabling wake\n");
1da177e4 2733 pci_disable_device(pdev);
3435dbce
JB		 2734 retval = pci_set_power_state(pdev, pci_choose_state(pdev, state));
2735 if (retval)
2736 DPRINTK(PROBE,ERR, "Error %d setting power state\n", retval);
1da177e4
LT		 2737
2738 return 0;
2739}
2740
2741static int e100_resume(struct pci_dev *pdev)
2742{
2743 struct net_device *netdev = pci_get_drvdata(pdev);
2744 struct nic *nic = netdev_priv(netdev);
3435dbce 2745 int retval;
1da177e4 2746
3435dbce
JB		 2747 retval = pci_set_power_state(pdev, PCI_D0);
2748 if (retval)
2749 DPRINTK(PROBE,ERR, "Error waking adapter\n");
1da177e4 2750 pci_restore_state(pdev);
6bdacb1a 2751 /* ack any pending wake events, disable PME */
3435dbce
JB		 2752 retval = pci_enable_wake(pdev, 0, 0);
2753 if (retval)
2754 DPRINTK(PROBE,ERR, "Error clearing wake events\n");
1da177e4
LT		 2755
2756 netif_device_attach(netdev);
2757 if(netif_running(netdev))
2758 e100_up(nic);
2759
2760 return 0;
2761}
2762#endif
2763
6bdacb1a 2764
d18c3db5 2765static void e100_shutdown(struct pci_dev *pdev)
6bdacb1a 2766{
6bdacb1a
MC		 2767 struct net_device *netdev = pci_get_drvdata(pdev);
2768 struct nic *nic = netdev_priv(netdev);
3435dbce 2769 int retval;
6bdacb1a
MC		 2770
2771#ifdef CONFIG_PM
3435dbce 2772 retval = pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
6bdacb1a 2773#else
3435dbce 2774 retval = pci_enable_wake(pdev, 0, nic->flags & (wol_magic));
6bdacb1a 2775#endif
3435dbce
JB		 2776 if (retval)
2777 DPRINTK(PROBE,ERR, "Error enabling wake\n");
6bdacb1a
MC		 2778}
2779
2780
1da177e4
LT		 2781static struct pci_driver e100_driver = {
2782 .name = DRV_NAME,
2783 .id_table = e100_id_table,
2784 .probe = e100_probe,
2785 .remove = __devexit_p(e100_remove),
2786#ifdef CONFIG_PM
2787 .suspend = e100_suspend,
2788 .resume = e100_resume,
2789#endif
05479938 2790 .shutdown = e100_shutdown,
1da177e4
LT		 2791};
2792
2793static int __init e100_init_module(void)
2794{
2795 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2796 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2797 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2798 }
2799 return pci_module_init(&e100_driver);
2800}
2801
2802static void __exit e100_cleanup_module(void)
2803{
2804 pci_unregister_driver(&e100_driver);
2805}
2806
2807module_init(e100_init_module);
2808module_exit(e100_cleanup_module);
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