[linux.git] / drivers / pwm / pwm-cros-ec.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Expose a PWM controlled by the ChromeOS EC to the host processor.
 *
 * Copyright (C) 2016 Google, Inc.
 */

#include <linux/module.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_ec_proto.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

/**
 * struct cros_ec_pwm_device - Driver data for EC PWM
 *
 * @dev: Device node
 * @ec: Pointer to EC device
 * @chip: PWM controller chip
 */
struct cros_ec_pwm_device {
	struct device *dev;
	struct cros_ec_device *ec;
	struct pwm_chip chip;
};

/**
 * struct cros_ec_pwm - per-PWM driver data
 * @duty_cycle: cached duty cycle
 */
struct cros_ec_pwm {
	u16 duty_cycle;
};

static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *c)
{
	return container_of(c, struct cros_ec_pwm_device, chip);
}

static int cros_ec_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct cros_ec_pwm *channel;

	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
	if (!channel)
		return -ENOMEM;

	pwm_set_chip_data(pwm, channel);

	return 0;
}

static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);

	kfree(channel);
}

static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty)
{
	struct {
		struct cros_ec_command msg;
		struct ec_params_pwm_set_duty params;
	} __packed buf;
	struct ec_params_pwm_set_duty *params = &buf.params;
	struct cros_ec_command *msg = &buf.msg;

	memset(&buf, 0, sizeof(buf));

	msg->version = 0;
	msg->command = EC_CMD_PWM_SET_DUTY;
	msg->insize = 0;
	msg->outsize = sizeof(*params);

	params->duty = duty;
	params->pwm_type = EC_PWM_TYPE_GENERIC;
	params->index = index;

	return cros_ec_cmd_xfer_status(ec, msg);
}

static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index)
{
	struct {
		struct cros_ec_command msg;
		union {
			struct ec_params_pwm_get_duty params;
			struct ec_response_pwm_get_duty resp;
		};
	} __packed buf;
	struct ec_params_pwm_get_duty *params = &buf.params;
	struct ec_response_pwm_get_duty *resp = &buf.resp;
	struct cros_ec_command *msg = &buf.msg;
	int ret;

	memset(&buf, 0, sizeof(buf));

	msg->version = 0;
	msg->command = EC_CMD_PWM_GET_DUTY;
	msg->insize = sizeof(*resp);
	msg->outsize = sizeof(*params);

	params->pwm_type = EC_PWM_TYPE_GENERIC;
	params->index = index;

	ret = cros_ec_cmd_xfer_status(ec, msg);
	if (ret < 0)
		return ret;

	return resp->duty;
}

static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			     const struct pwm_state *state)
{
	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
	u16 duty_cycle;
	int ret;

	/* The EC won't let us change the period */
	if (state->period != EC_PWM_MAX_DUTY)
		return -EINVAL;

	/*
	 * EC doesn't separate the concept of duty cycle and enabled, but
	 * kernel does. Translate.
	 */
	duty_cycle = state->enabled ? state->duty_cycle : 0;

	ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle);
	if (ret < 0)
		return ret;

	channel->duty_cycle = state->duty_cycle;

	return 0;
}

static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				  struct pwm_state *state)
{
	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
	int ret;

	ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm);
	if (ret < 0) {
		dev_err(chip->dev, "error getting initial duty: %d\n", ret);
		return;
	}

	state->enabled = (ret > 0);
	state->period = EC_PWM_MAX_DUTY;

	/*
	 * Note that "disabled" and "duty cycle == 0" are treated the same. If
	 * the cached duty cycle is not zero, used the cached duty cycle. This
	 * ensures that the configured duty cycle is kept across a disable and
	 * enable operation and avoids potentially confusing consumers.
	 *
	 * For the case of the initial hardware readout, channel->duty_cycle
	 * will be 0 and the actual duty cycle read from the EC is used.
	 */
	if (ret == 0 && channel->duty_cycle > 0)
		state->duty_cycle = channel->duty_cycle;
	else
		state->duty_cycle = ret;
}

static struct pwm_device *
cros_ec_pwm_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
{
	struct pwm_device *pwm;

	if (args->args[0] >= pc->npwm)
		return ERR_PTR(-EINVAL);

	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
	if (IS_ERR(pwm))
		return pwm;

	/* The EC won't let us change the period */
	pwm->args.period = EC_PWM_MAX_DUTY;

	return pwm;
}

static const struct pwm_ops cros_ec_pwm_ops = {
	.request = cros_ec_pwm_request,
	.free = cros_ec_pwm_free,
	.get_state	= cros_ec_pwm_get_state,
	.apply		= cros_ec_pwm_apply,
	.owner		= THIS_MODULE,
};

/*
 * Determine the number of supported PWMs. The EC does not return the number
 * of PWMs it supports directly, so we have to read the pwm duty cycle for
 * subsequent channels until we get an error.
 */
static int cros_ec_num_pwms(struct cros_ec_device *ec)
{
	int i, ret;

	/* The index field is only 8 bits */
	for (i = 0; i <= U8_MAX; i++) {
		ret = cros_ec_pwm_get_duty(ec, i);
		/*
		 * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
		 * responses; everything else is treated as an error.
		 * The EC error codes map to -EOPNOTSUPP and -EINVAL,
		 * so check for those.
		 */
		switch (ret) {
		case -EOPNOTSUPP:	/* invalid command */
			return -ENODEV;
		case -EINVAL:		/* invalid parameter */
			return i;
		default:
			if (ret < 0)
				return ret;
			break;
		}
	}

	return U8_MAX;
}

static int cros_ec_pwm_probe(struct platform_device *pdev)
{
	struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
	struct device *dev = &pdev->dev;
	struct cros_ec_pwm_device *ec_pwm;
	struct pwm_chip *chip;
	int ret;

	if (!ec) {
		dev_err(dev, "no parent EC device\n");
		return -EINVAL;
	}

	ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
	if (!ec_pwm)
		return -ENOMEM;
	chip = &ec_pwm->chip;
	ec_pwm->ec = ec;

	/* PWM chip */
	chip->dev = dev;
	chip->ops = &cros_ec_pwm_ops;
	chip->of_xlate = cros_ec_pwm_xlate;
	chip->of_pwm_n_cells = 1;
	chip->base = -1;
	ret = cros_ec_num_pwms(ec);
	if (ret < 0) {
		dev_err(dev, "Couldn't find PWMs: %d\n", ret);
		return ret;
	}
	chip->npwm = ret;
	dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);

	ret = pwmchip_add(chip);
	if (ret < 0) {
		dev_err(dev, "cannot register PWM: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, ec_pwm);

	return ret;
}

static int cros_ec_pwm_remove(struct platform_device *dev)
{
	struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev);
	struct pwm_chip *chip = &ec_pwm->chip;

	return pwmchip_remove(chip);
}

#ifdef CONFIG_OF
static const struct of_device_id cros_ec_pwm_of_match[] = {
	{ .compatible = "google,cros-ec-pwm" },
	{},
};
MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
#endif

static struct platform_driver cros_ec_pwm_driver = {
	.probe = cros_ec_pwm_probe,
	.remove = cros_ec_pwm_remove,
	.driver = {
		.name = "cros-ec-pwm",
		.of_match_table = of_match_ptr(cros_ec_pwm_of_match),
	},
};
module_platform_driver(cros_ec_pwm_driver);

MODULE_ALIAS("platform:cros-ec-pwm");
MODULE_DESCRIPTION("ChromeOS EC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4964cb52	1	// SPDX-License-Identifier: GPL-2.0
1f0d3bb0	2	/*
1f0d3bb0	3	* Expose a PWM controlled by the ChromeOS EC to the host processor.
4964cb52 EBS	4	*
4964cb52 EBS	5	* Copyright (C) 2016 Google, Inc.
1f0d3bb0 BN	6	*/
	7
	8	#include <linux/module.h>
840d9f13 EBS	9	#include <linux/platform_data/cros_ec_commands.h>
840d9f13 EBS	10	#include <linux/platform_data/cros_ec_proto.h>
1f0d3bb0 BN	11	#include <linux/platform_device.h>
	12	#include <linux/pwm.h>
	13	#include <linux/slab.h>
	14
	15	/**
	16	* struct cros_ec_pwm_device - Driver data for EC PWM
	17	*
	18	* @dev: Device node
	19	* @ec: Pointer to EC device
	20	* @chip: PWM controller chip
	21	*/
	22	struct cros_ec_pwm_device {
	23	struct device *dev;
	24	struct cros_ec_device *ec;
	25	struct pwm_chip chip;
	26	};
	27
1db37f95 TR	28	/**
	29	* struct cros_ec_pwm - per-PWM driver data
	30	* @duty_cycle: cached duty cycle
	31	*/
	32	struct cros_ec_pwm {
	33	u16 duty_cycle;
	34	};
	35
1f0d3bb0 BN	36	static inline struct cros_ec_pwm_device pwm_to_cros_ec_pwm(struct pwm_chip c)
	37	{
	38	return container_of(c, struct cros_ec_pwm_device, chip);
	39	}
	40
1db37f95 TR	41	static int cros_ec_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	42	{
	43	struct cros_ec_pwm *channel;
	44
	45	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
	46	if (!channel)
	47	return -ENOMEM;
	48
	49	pwm_set_chip_data(pwm, channel);
	50
	51	return 0;
	52	}
	53
	54	static void cros_ec_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	55	{
	56	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
	57
	58	kfree(channel);
	59	}
	60
1f0d3bb0 BN	61	static int cros_ec_pwm_set_duty(struct cros_ec_device *ec, u8 index, u16 duty)
	62	{
	63	struct {
	64	struct cros_ec_command msg;
	65	struct ec_params_pwm_set_duty params;
065cfbbb	66	} __packed buf;
1f0d3bb0 BN	67	struct ec_params_pwm_set_duty *params = &buf.params;
	68	struct cros_ec_command *msg = &buf.msg;
	69
	70	memset(&buf, 0, sizeof(buf));
	71
	72	msg->version = 0;
	73	msg->command = EC_CMD_PWM_SET_DUTY;
	74	msg->insize = 0;
	75	msg->outsize = sizeof(*params);
	76
	77	params->duty = duty;
	78	params->pwm_type = EC_PWM_TYPE_GENERIC;
	79	params->index = index;
	80
	81	return cros_ec_cmd_xfer_status(ec, msg);
	82	}
	83
be020f0d	84	static int cros_ec_pwm_get_duty(struct cros_ec_device *ec, u8 index)
1f0d3bb0 BN	85	{
	86	struct {
	87	struct cros_ec_command msg;
	88	union {
	89	struct ec_params_pwm_get_duty params;
	90	struct ec_response_pwm_get_duty resp;
	91	};
065cfbbb	92	} __packed buf;
1f0d3bb0 BN	93	struct ec_params_pwm_get_duty *params = &buf.params;
	94	struct ec_response_pwm_get_duty *resp = &buf.resp;
	95	struct cros_ec_command *msg = &buf.msg;
	96	int ret;
	97
	98	memset(&buf, 0, sizeof(buf));
	99
	100	msg->version = 0;
	101	msg->command = EC_CMD_PWM_GET_DUTY;
e47866a1 NV	102	msg->insize = sizeof(*resp);
e47866a1 NV	103	msg->outsize = sizeof(*params);
1f0d3bb0 BN	104
	105	params->pwm_type = EC_PWM_TYPE_GENERIC;
	106	params->index = index;
	107
	108	ret = cros_ec_cmd_xfer_status(ec, msg);
1f0d3bb0 BN	109	if (ret < 0)
	110	return ret;
	111
	112	return resp->duty;
	113	}
	114
1f0d3bb0	115	static int cros_ec_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	116	const struct pwm_state *state)
1f0d3bb0 BN	117	{
1f0d3bb0 BN	118	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
1db37f95 TR	119	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
	120	u16 duty_cycle;
	121	int ret;
1f0d3bb0 BN	122
	123	/* The EC won't let us change the period */
	124	if (state->period != EC_PWM_MAX_DUTY)
	125	return -EINVAL;
	126
	127	/*
	128	* EC doesn't separate the concept of duty cycle and enabled, but
	129	* kernel does. Translate.
	130	*/
	131	duty_cycle = state->enabled ? state->duty_cycle : 0;
	132
1db37f95 TR	133	ret = cros_ec_pwm_set_duty(ec_pwm->ec, pwm->hwpwm, duty_cycle);
	134	if (ret < 0)
	135	return ret;
	136
	137	channel->duty_cycle = state->duty_cycle;
	138
	139	return 0;
1f0d3bb0 BN	140	}
	141
	142	static void cros_ec_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
	143	struct pwm_state *state)
	144	{
	145	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
1db37f95	146	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
1f0d3bb0 BN	147	int ret;
	148
	149	ret = cros_ec_pwm_get_duty(ec_pwm->ec, pwm->hwpwm);
	150	if (ret < 0) {
	151	dev_err(chip->dev, "error getting initial duty: %d\n", ret);
	152	return;
	153	}
	154
	155	state->enabled = (ret > 0);
	156	state->period = EC_PWM_MAX_DUTY;
	157
1db37f95 TR	158	/*
	159	* Note that "disabled" and "duty cycle == 0" are treated the same. If
	160	* the cached duty cycle is not zero, used the cached duty cycle. This
	161	* ensures that the configured duty cycle is kept across a disable and
	162	* enable operation and avoids potentially confusing consumers.
	163	*
	164	* For the case of the initial hardware readout, channel->duty_cycle
	165	* will be 0 and the actual duty cycle read from the EC is used.
	166	*/
	167	if (ret == 0 && channel->duty_cycle > 0)
	168	state->duty_cycle = channel->duty_cycle;
	169	else
	170	state->duty_cycle = ret;
1f0d3bb0 BN	171	}
	172
	173	static struct pwm_device *
	174	cros_ec_pwm_xlate(struct pwm_chip pc, const struct of_phandle_args args)
	175	{
	176	struct pwm_device *pwm;
	177
	178	if (args->args[0] >= pc->npwm)
	179	return ERR_PTR(-EINVAL);
	180
	181	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
	182	if (IS_ERR(pwm))
	183	return pwm;
	184
	185	/* The EC won't let us change the period */
	186	pwm->args.period = EC_PWM_MAX_DUTY;
	187
	188	return pwm;
	189	}
	190
	191	static const struct pwm_ops cros_ec_pwm_ops = {
1db37f95 TR	192	.request = cros_ec_pwm_request,
1db37f95 TR	193	.free = cros_ec_pwm_free,
1f0d3bb0 BN	194	.get_state = cros_ec_pwm_get_state,
	195	.apply = cros_ec_pwm_apply,
	196	.owner = THIS_MODULE,
	197	};
	198
d509f8a7 GR	199	/*
	200	* Determine the number of supported PWMs. The EC does not return the number
	201	* of PWMs it supports directly, so we have to read the pwm duty cycle for
	202	* subsequent channels until we get an error.
	203	*/
1f0d3bb0 BN	204	static int cros_ec_num_pwms(struct cros_ec_device *ec)
	205	{
	206	int i, ret;
	207
	208	/* The index field is only 8 bits */
	209	for (i = 0; i <= U8_MAX; i++) {
be020f0d	210	ret = cros_ec_pwm_get_duty(ec, i);
1f0d3bb0 BN	211	/*
	212	* We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
	213	* responses; everything else is treated as an error.
be020f0d GR	214	* The EC error codes map to -EOPNOTSUPP and -EINVAL,
be020f0d GR	215	* so check for those.
1f0d3bb0	216	*/
d509f8a7 GR	217	switch (ret) {
d509f8a7 GR	218	case -EOPNOTSUPP: /* invalid command */
1f0d3bb0	219	return -ENODEV;
d509f8a7	220	case -EINVAL: /* invalid parameter */
1f0d3bb0	221	return i;
d509f8a7 GR	222	default:
	223	if (ret < 0)
	224	return ret;
	225	break;
	226	}
1f0d3bb0 BN	227	}
	228
	229	return U8_MAX;
	230	}
	231
	232	static int cros_ec_pwm_probe(struct platform_device *pdev)
	233	{
	234	struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
	235	struct device *dev = &pdev->dev;
	236	struct cros_ec_pwm_device *ec_pwm;
	237	struct pwm_chip *chip;
	238	int ret;
	239
	240	if (!ec) {
	241	dev_err(dev, "no parent EC device\n");
	242	return -EINVAL;
	243	}
	244
	245	ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
	246	if (!ec_pwm)
	247	return -ENOMEM;
	248	chip = &ec_pwm->chip;
	249	ec_pwm->ec = ec;
	250
	251	/* PWM chip */
	252	chip->dev = dev;
	253	chip->ops = &cros_ec_pwm_ops;
	254	chip->of_xlate = cros_ec_pwm_xlate;
	255	chip->of_pwm_n_cells = 1;
	256	chip->base = -1;
	257	ret = cros_ec_num_pwms(ec);
	258	if (ret < 0) {
	259	dev_err(dev, "Couldn't find PWMs: %d\n", ret);
	260	return ret;
	261	}
	262	chip->npwm = ret;
	263	dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);
	264
	265	ret = pwmchip_add(chip);
	266	if (ret < 0) {
	267	dev_err(dev, "cannot register PWM: %d\n", ret);
	268	return ret;
	269	}
	270
	271	platform_set_drvdata(pdev, ec_pwm);
	272
	273	return ret;
	274	}
	275
	276	static int cros_ec_pwm_remove(struct platform_device *dev)
	277	{
	278	struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev);
	279	struct pwm_chip *chip = &ec_pwm->chip;
	280
	281	return pwmchip_remove(chip);
	282	}
	283
	284	#ifdef CONFIG_OF
	285	static const struct of_device_id cros_ec_pwm_of_match[] = {
	286	{ .compatible = "google,cros-ec-pwm" },
	287	{},
	288	};
	289	MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
	290	#endif
291
292	static struct platform_driver cros_ec_pwm_driver = {
293	.probe = cros_ec_pwm_probe,
294	.remove = cros_ec_pwm_remove,
295	.driver = {
296	.name = "cros-ec-pwm",
297	.of_match_table = of_match_ptr(cros_ec_pwm_of_match),
298	},
299	};
300	module_platform_driver(cros_ec_pwm_driver);
301
302	MODULE_ALIAS("platform:cros-ec-pwm");
303	MODULE_DESCRIPTION("ChromeOS EC PWM driver");
304	MODULE_LICENSE("GPL v2");