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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/holtmann/bluet...
[linux.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
40239396 66#include <linux/mdio.h>
1da177e4
LT		 67#include <linux/skbuff.h>
68#include <linux/init.h>
69#include <linux/delay.h>
70#include <linux/stddef.h>
71#include <linux/ioctl.h>
72#include <linux/timex.h>
1da177e4 73#include <linux/ethtool.h>
1da177e4 74#include <linux/workqueue.h>
be3a6b02 75#include <linux/if_vlan.h>
7d3d0439
RA		 76#include <linux/ip.h>
77#include <linux/tcp.h>
78#include <net/tcp.h>
1da177e4 79
1da177e4
LT		 80#include <asm/system.h>
81#include <asm/uaccess.h>
20346722 82#include <asm/io.h>
fe931395 83#include <asm/div64.h>
330ce0de 84#include <asm/irq.h>
1da177e4
LT		 85
86/* local include */
87#include "s2io.h"
88#include "s2io-regs.h"
89
29d0a2b0 90#define DRV_VERSION "2.0.26.25"
6c1792f4 91
1da177e4 92/* S2io Driver name & version. */
20346722 93static char s2io_driver_name[] = "Neterion";
6c1792f4 94static char s2io_driver_version[] = DRV_VERSION;
1da177e4 95
6d517a27
VP		 96static int rxd_size[2] = {32,48};
97static int rxd_count[2] = {127,85};
da6971d8 98
1ee6dd77 99static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 100{
101 int ret;
102
103 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
104 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
105
106 return ret;
107}
108
20346722 109/*
1da177e4
LT		 110 * Cards with following subsystem_id have a link state indication
111 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
112 * macro below identifies these cards given the subsystem_id.
113 */
541ae68f
K		 114#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
115 (dev_type == XFRAME_I_DEVICE) ? \
116 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
117 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 118
119#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
120 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 121
92b84437
SS		 122static inline int is_s2io_card_up(const struct s2io_nic * sp)
123{
124 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
125}
126
1da177e4
LT		 127/* Ethtool related variables and Macros. */
128static char s2io_gstrings[][ETH_GSTRING_LEN] = {
129 "Register test\t(offline)",
130 "Eeprom test\t(offline)",
131 "Link test\t(online)",
132 "RLDRAM test\t(offline)",
133 "BIST Test\t(offline)"
134};
135
fa1f0cb3 136static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 137 {"tmac_frms"},
138 {"tmac_data_octets"},
139 {"tmac_drop_frms"},
140 {"tmac_mcst_frms"},
141 {"tmac_bcst_frms"},
142 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 143 {"tmac_ttl_octets"},
144 {"tmac_ucst_frms"},
145 {"tmac_nucst_frms"},
1da177e4 146 {"tmac_any_err_frms"},
bd1034f0 147 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 148 {"tmac_vld_ip_octets"},
149 {"tmac_vld_ip"},
150 {"tmac_drop_ip"},
151 {"tmac_icmp"},
152 {"tmac_rst_tcp"},
153 {"tmac_tcp"},
154 {"tmac_udp"},
155 {"rmac_vld_frms"},
156 {"rmac_data_octets"},
157 {"rmac_fcs_err_frms"},
158 {"rmac_drop_frms"},
159 {"rmac_vld_mcst_frms"},
160 {"rmac_vld_bcst_frms"},
161 {"rmac_in_rng_len_err_frms"},
bd1034f0 162 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 163 {"rmac_long_frms"},
164 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 165 {"rmac_unsup_ctrl_frms"},
166 {"rmac_ttl_octets"},
167 {"rmac_accepted_ucst_frms"},
168 {"rmac_accepted_nucst_frms"},
1da177e4 169 {"rmac_discarded_frms"},
bd1034f0
AR		 170 {"rmac_drop_events"},
171 {"rmac_ttl_less_fb_octets"},
172 {"rmac_ttl_frms"},
1da177e4
LT		 173 {"rmac_usized_frms"},
174 {"rmac_osized_frms"},
175 {"rmac_frag_frms"},
176 {"rmac_jabber_frms"},
bd1034f0
AR		 177 {"rmac_ttl_64_frms"},
178 {"rmac_ttl_65_127_frms"},
179 {"rmac_ttl_128_255_frms"},
180 {"rmac_ttl_256_511_frms"},
181 {"rmac_ttl_512_1023_frms"},
182 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 183 {"rmac_ip"},
184 {"rmac_ip_octets"},
185 {"rmac_hdr_err_ip"},
186 {"rmac_drop_ip"},
187 {"rmac_icmp"},
188 {"rmac_tcp"},
189 {"rmac_udp"},
190 {"rmac_err_drp_udp"},
bd1034f0
AR		 191 {"rmac_xgmii_err_sym"},
192 {"rmac_frms_q0"},
193 {"rmac_frms_q1"},
194 {"rmac_frms_q2"},
195 {"rmac_frms_q3"},
196 {"rmac_frms_q4"},
197 {"rmac_frms_q5"},
198 {"rmac_frms_q6"},
199 {"rmac_frms_q7"},
200 {"rmac_full_q0"},
201 {"rmac_full_q1"},
202 {"rmac_full_q2"},
203 {"rmac_full_q3"},
204 {"rmac_full_q4"},
205 {"rmac_full_q5"},
206 {"rmac_full_q6"},
207 {"rmac_full_q7"},
1da177e4 208 {"rmac_pause_cnt"},
bd1034f0
AR		 209 {"rmac_xgmii_data_err_cnt"},
210 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 211 {"rmac_accepted_ip"},
212 {"rmac_err_tcp"},
bd1034f0
AR		 213 {"rd_req_cnt"},
214 {"new_rd_req_cnt"},
215 {"new_rd_req_rtry_cnt"},
216 {"rd_rtry_cnt"},
217 {"wr_rtry_rd_ack_cnt"},
218 {"wr_req_cnt"},
219 {"new_wr_req_cnt"},
220 {"new_wr_req_rtry_cnt"},
221 {"wr_rtry_cnt"},
222 {"wr_disc_cnt"},
223 {"rd_rtry_wr_ack_cnt"},
224 {"txp_wr_cnt"},
225 {"txd_rd_cnt"},
226 {"txd_wr_cnt"},
227 {"rxd_rd_cnt"},
228 {"rxd_wr_cnt"},
229 {"txf_rd_cnt"},
fa1f0cb3
SS		 230 {"rxf_wr_cnt"}
231};
232
233static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 234 {"rmac_ttl_1519_4095_frms"},
235 {"rmac_ttl_4096_8191_frms"},
236 {"rmac_ttl_8192_max_frms"},
237 {"rmac_ttl_gt_max_frms"},
238 {"rmac_osized_alt_frms"},
239 {"rmac_jabber_alt_frms"},
240 {"rmac_gt_max_alt_frms"},
241 {"rmac_vlan_frms"},
242 {"rmac_len_discard"},
243 {"rmac_fcs_discard"},
244 {"rmac_pf_discard"},
245 {"rmac_da_discard"},
246 {"rmac_red_discard"},
247 {"rmac_rts_discard"},
248 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 249 {"link_fault_cnt"}
250};
251
252static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 253 {"\n DRIVER STATISTICS"},
254 {"single_bit_ecc_errs"},
255 {"double_bit_ecc_errs"},
bd1034f0
AR		 256 {"parity_err_cnt"},
257 {"serious_err_cnt"},
258 {"soft_reset_cnt"},
259 {"fifo_full_cnt"},
8116f3cf
SS		 260 {"ring_0_full_cnt"},
261 {"ring_1_full_cnt"},
262 {"ring_2_full_cnt"},
263 {"ring_3_full_cnt"},
264 {"ring_4_full_cnt"},
265 {"ring_5_full_cnt"},
266 {"ring_6_full_cnt"},
267 {"ring_7_full_cnt"},
43b7c451
SH		 268 {"alarm_transceiver_temp_high"},
269 {"alarm_transceiver_temp_low"},
270 {"alarm_laser_bias_current_high"},
271 {"alarm_laser_bias_current_low"},
272 {"alarm_laser_output_power_high"},
273 {"alarm_laser_output_power_low"},
274 {"warn_transceiver_temp_high"},
275 {"warn_transceiver_temp_low"},
276 {"warn_laser_bias_current_high"},
277 {"warn_laser_bias_current_low"},
278 {"warn_laser_output_power_high"},
279 {"warn_laser_output_power_low"},
280 {"lro_aggregated_pkts"},
281 {"lro_flush_both_count"},
282 {"lro_out_of_sequence_pkts"},
283 {"lro_flush_due_to_max_pkts"},
284 {"lro_avg_aggr_pkts"},
285 {"mem_alloc_fail_cnt"},
286 {"pci_map_fail_cnt"},
287 {"watchdog_timer_cnt"},
288 {"mem_allocated"},
289 {"mem_freed"},
290 {"link_up_cnt"},
291 {"link_down_cnt"},
292 {"link_up_time"},
293 {"link_down_time"},
294 {"tx_tcode_buf_abort_cnt"},
295 {"tx_tcode_desc_abort_cnt"},
296 {"tx_tcode_parity_err_cnt"},
297 {"tx_tcode_link_loss_cnt"},
298 {"tx_tcode_list_proc_err_cnt"},
299 {"rx_tcode_parity_err_cnt"},
300 {"rx_tcode_abort_cnt"},
301 {"rx_tcode_parity_abort_cnt"},
302 {"rx_tcode_rda_fail_cnt"},
303 {"rx_tcode_unkn_prot_cnt"},
304 {"rx_tcode_fcs_err_cnt"},
305 {"rx_tcode_buf_size_err_cnt"},
306 {"rx_tcode_rxd_corrupt_cnt"},
307 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 308 {"tda_err_cnt"},
309 {"pfc_err_cnt"},
310 {"pcc_err_cnt"},
311 {"tti_err_cnt"},
312 {"tpa_err_cnt"},
313 {"sm_err_cnt"},
314 {"lso_err_cnt"},
315 {"mac_tmac_err_cnt"},
316 {"mac_rmac_err_cnt"},
317 {"xgxs_txgxs_err_cnt"},
318 {"xgxs_rxgxs_err_cnt"},
319 {"rc_err_cnt"},
320 {"prc_pcix_err_cnt"},
321 {"rpa_err_cnt"},
322 {"rda_err_cnt"},
323 {"rti_err_cnt"},
324 {"mc_err_cnt"}
1da177e4
LT		 325};
326
4c3616cd
AMR		 327#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
328#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
329#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3
SS		 330
331#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
332#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
333
334#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
335#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4 336
4c3616cd 337#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
1da177e4
LT		 338#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
339
25fff88e
K		 340#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
341 init_timer(&timer); \
342 timer.function = handle; \
343 timer.data = (unsigned long) arg; \
344 mod_timer(&timer, (jiffies + exp)) \
345
2fd37688
SS		 346/* copy mac addr to def_mac_addr array */
347static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
348{
349 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
350 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
351 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
352 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
353 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
354 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
355}
04025095 356
be3a6b02
K		 357/* Add the vlan */
358static void s2io_vlan_rx_register(struct net_device *dev,
04025095 359 struct vlan_group *grp)
be3a6b02 360{
2fda096d 361 int i;
4cf1653a 362 struct s2io_nic *nic = netdev_priv(dev);
2fda096d
SR		 363 unsigned long flags[MAX_TX_FIFOS];
364 struct mac_info *mac_control = &nic->mac_control;
365 struct config_param *config = &nic->config;
366
367 for (i = 0; i < config->tx_fifo_num; i++)
368 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
be3a6b02 369
be3a6b02 370 nic->vlgrp = grp;
2fda096d
SR		 371 for (i = config->tx_fifo_num - 1; i >= 0; i--)
372 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
373 flags[i]);
be3a6b02
K		 374}
375
cdb5bf02 376/* Unregister the vlan */
04025095 377static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 378{
379 int i;
4cf1653a 380 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02
SH		 381 unsigned long flags[MAX_TX_FIFOS];
382 struct mac_info *mac_control = &nic->mac_control;
383 struct config_param *config = &nic->config;
384
385 for (i = 0; i < config->tx_fifo_num; i++)
386 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
387
388 if (nic->vlgrp)
389 vlan_group_set_device(nic->vlgrp, vid, NULL);
390
391 for (i = config->tx_fifo_num - 1; i >= 0; i--)
392 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
393 flags[i]);
394}
395
20346722 396/*
1da177e4
LT		 397 * Constants to be programmed into the Xena's registers, to configure
398 * the XAUI.
399 */
400
1da177e4 401#define END_SIGN 0x0
f71e1309 402static const u64 herc_act_dtx_cfg[] = {
541ae68f 403 /* Set address */
e960fc5c 404 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 405 /* Write data */
e960fc5c 406 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 407 /* Set address */
408 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
409 /* Write data */
410 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
411 /* Set address */
e960fc5c 412 0x801205150D440000ULL, 0x801205150D4400E0ULL,
413 /* Write data */
414 0x801205150D440004ULL, 0x801205150D4400E4ULL,
415 /* Set address */
541ae68f
K		 416 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
417 /* Write data */
418 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
419 /* Done */
420 END_SIGN
421};
422
f71e1309 423static const u64 xena_dtx_cfg[] = {
c92ca04b 424 /* Set address */
1da177e4 425 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 426 /* Write data */
427 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
428 /* Set address */
429 0x8001051500000000ULL, 0x80010515000000E0ULL,
430 /* Write data */
431 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
432 /* Set address */
1da177e4 433 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 434 /* Write data */
435 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 436 END_SIGN
437};
438
20346722 439/*
1da177e4
LT		 440 * Constants for Fixing the MacAddress problem seen mostly on
441 * Alpha machines.
442 */
f71e1309 443static const u64 fix_mac[] = {
1da177e4
LT		 444 0x0060000000000000ULL, 0x0060600000000000ULL,
445 0x0040600000000000ULL, 0x0000600000000000ULL,
446 0x0020600000000000ULL, 0x0060600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0060600000000000ULL,
450 0x0020600000000000ULL, 0x0060600000000000ULL,
451 0x0020600000000000ULL, 0x0060600000000000ULL,
452 0x0020600000000000ULL, 0x0060600000000000ULL,
453 0x0020600000000000ULL, 0x0060600000000000ULL,
454 0x0020600000000000ULL, 0x0060600000000000ULL,
455 0x0020600000000000ULL, 0x0060600000000000ULL,
456 0x0020600000000000ULL, 0x0000600000000000ULL,
457 0x0040600000000000ULL, 0x0060600000000000ULL,
458 END_SIGN
459};
460
b41477f3
AR		 461MODULE_LICENSE("GPL");
462MODULE_VERSION(DRV_VERSION);
463
464
1da177e4 465/* Module Loadable parameters. */
6cfc482b 466S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 467S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 468S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 469S2IO_PARM_INT(rx_ring_mode, 1);
470S2IO_PARM_INT(use_continuous_tx_intrs, 1);
471S2IO_PARM_INT(rmac_pause_time, 0x100);
472S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
473S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
474S2IO_PARM_INT(shared_splits, 0);
475S2IO_PARM_INT(tmac_util_period, 5);
476S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 477S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 478/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
479S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 480/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 481S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 482/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 483S2IO_PARM_INT(intr_type, 2);
7d3d0439 484/* Large receive offload feature */
43b7c451
SH		 485static unsigned int lro_enable;
486module_param_named(lro, lro_enable, uint, 0);
487
7d3d0439
RA		 488/* Max pkts to be aggregated by LRO at one time. If not specified,
489 * aggregation happens until we hit max IP pkt size(64K)
490 */
b41477f3 491S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 492S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 493
494S2IO_PARM_INT(napi, 1);
495S2IO_PARM_INT(ufo, 0);
926930b2 496S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 497
498static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
499 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
500static unsigned int rx_ring_sz[MAX_RX_RINGS] =
501 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
502static unsigned int rts_frm_len[MAX_RX_RINGS] =
503 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
504
505module_param_array(tx_fifo_len, uint, NULL, 0);
506module_param_array(rx_ring_sz, uint, NULL, 0);
507module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 508
20346722 509/*
1da177e4 510 * S2IO device table.
20346722 511 * This table lists all the devices that this driver supports.
1da177e4
LT		 512 */
513static struct pci_device_id s2io_tbl[] __devinitdata = {
514 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
515 PCI_ANY_ID, PCI_ANY_ID},
516 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
517 PCI_ANY_ID, PCI_ANY_ID},
518 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 519 PCI_ANY_ID, PCI_ANY_ID},
520 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
521 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 522 {0,}
523};
524
525MODULE_DEVICE_TABLE(pci, s2io_tbl);
526
d796fdb7
LV		 527static struct pci_error_handlers s2io_err_handler = {
528 .error_detected = s2io_io_error_detected,
529 .slot_reset = s2io_io_slot_reset,
530 .resume = s2io_io_resume,
531};
532
1da177e4
LT		 533static struct pci_driver s2io_driver = {
534 .name = "S2IO",
535 .id_table = s2io_tbl,
536 .probe = s2io_init_nic,
537 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 538 .err_handler = &s2io_err_handler,
1da177e4
LT		 539};
540
541/* A simplifier macro used both by init and free shared_mem Fns(). */
542#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
543
3a3d5756
SH		 544/* netqueue manipulation helper functions */
545static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
546{
fd2ea0a7
DM		 547 if (!sp->config.multiq) {
548 int i;
549
3a3d5756
SH		 550 for (i = 0; i < sp->config.tx_fifo_num; i++)
551 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 552 }
fd2ea0a7 553 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 554}
555
556static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
557{
fd2ea0a7 558 if (!sp->config.multiq)
3a3d5756
SH		 559 sp->mac_control.fifos[fifo_no].queue_state =
560 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 561
562 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 563}
564
565static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
566{
fd2ea0a7
DM		 567 if (!sp->config.multiq) {
568 int i;
569
3a3d5756
SH		 570 for (i = 0; i < sp->config.tx_fifo_num; i++)
571 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 572 }
fd2ea0a7 573 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 574}
575
576static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
577{
fd2ea0a7 578 if (!sp->config.multiq)
3a3d5756
SH		 579 sp->mac_control.fifos[fifo_no].queue_state =
580 FIFO_QUEUE_START;
fd2ea0a7
DM		 581
582 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 583}
584
585static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
586{
fd2ea0a7
DM		 587 if (!sp->config.multiq) {
588 int i;
589
3a3d5756
SH		 590 for (i = 0; i < sp->config.tx_fifo_num; i++)
591 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 592 }
fd2ea0a7 593 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 594}
595
596static inline void s2io_wake_tx_queue(
597 struct fifo_info *fifo, int cnt, u8 multiq)
598{
599
3a3d5756
SH		 600 if (multiq) {
601 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
602 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 603 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 604 if (netif_queue_stopped(fifo->dev)) {
605 fifo->queue_state = FIFO_QUEUE_START;
606 netif_wake_queue(fifo->dev);
607 }
608 }
609}
610
1da177e4
LT		 611/**
612 * init_shared_mem - Allocation and Initialization of Memory
613 * @nic: Device private variable.
20346722
K		 614 * Description: The function allocates all the memory areas shared
615 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 616 * Rx descriptors and the statistics block.
617 */
618
619static int init_shared_mem(struct s2io_nic *nic)
620{
621 u32 size;
622 void *tmp_v_addr, *tmp_v_addr_next;
623 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 624 struct RxD_block *pre_rxd_blk = NULL;
372cc597 625 int i, j, blk_cnt;
1da177e4
LT		 626 int lst_size, lst_per_page;
627 struct net_device *dev = nic->dev;
8ae418cf 628 unsigned long tmp;
1ee6dd77 629 struct buffAdd *ba;
1da177e4 630
1ee6dd77 631 struct mac_info *mac_control;
1da177e4 632 struct config_param *config;
491976b2 633 unsigned long long mem_allocated = 0;
1da177e4
LT		 634
635 mac_control = &nic->mac_control;
636 config = &nic->config;
637
638
639 /* Allocation and initialization of TXDLs in FIOFs */
640 size = 0;
641 for (i = 0; i < config->tx_fifo_num; i++) {
642 size += config->tx_cfg[i].fifo_len;
643 }
644 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 645 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 646 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 647 return -EINVAL;
1da177e4
LT		 648 }
649
2fda096d
SR		 650 size = 0;
651 for (i = 0; i < config->tx_fifo_num; i++) {
652 size = config->tx_cfg[i].fifo_len;
653 /*
654 * Legal values are from 2 to 8192
655 */
656 if (size < 2) {
657 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
658 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
659 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
660 "are 2 to 8192\n");
661 return -EINVAL;
662 }
663 }
664
1ee6dd77 665 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 666 lst_per_page = PAGE_SIZE / lst_size;
667
668 for (i = 0; i < config->tx_fifo_num; i++) {
669 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 670 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
bd684e43 671 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
20346722
K		 672 GFP_KERNEL);
673 if (!mac_control->fifos[i].list_info) {
0c61ed5f 674 DBG_PRINT(INFO_DBG,
1da177e4
LT		 675 "Malloc failed for list_info\n");
676 return -ENOMEM;
677 }
491976b2 678 mem_allocated += list_holder_size;
1da177e4
LT		 679 }
680 for (i = 0; i < config->tx_fifo_num; i++) {
681 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
682 lst_per_page);
20346722
K		 683 mac_control->fifos[i].tx_curr_put_info.offset = 0;
684 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 685 config->tx_cfg[i].fifo_len - 1;
20346722
K		 686 mac_control->fifos[i].tx_curr_get_info.offset = 0;
687 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 688 config->tx_cfg[i].fifo_len - 1;
20346722
K		 689 mac_control->fifos[i].fifo_no = i;
690 mac_control->fifos[i].nic = nic;
fed5eccd 691 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
3a3d5756 692 mac_control->fifos[i].dev = dev;
20346722 693
1da177e4
LT		 694 for (j = 0; j < page_num; j++) {
695 int k = 0;
696 dma_addr_t tmp_p;
697 void *tmp_v;
698 tmp_v = pci_alloc_consistent(nic->pdev,
699 PAGE_SIZE, &tmp_p);
700 if (!tmp_v) {
0c61ed5f 701 DBG_PRINT(INFO_DBG,
1da177e4 702 "pci_alloc_consistent ");
0c61ed5f 703 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 704 return -ENOMEM;
705 }
776bd20f 706 /* If we got a zero DMA address(can happen on
707 * certain platforms like PPC), reallocate.
708 * Store virtual address of page we don't want,
709 * to be freed later.
710 */
711 if (!tmp_p) {
712 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 713 DBG_PRINT(INIT_DBG,
776bd20f 714 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 715 DBG_PRINT(INIT_DBG,
6b4d617d 716 "Virtual address %p\n", tmp_v);
776bd20f 717 tmp_v = pci_alloc_consistent(nic->pdev,
718 PAGE_SIZE, &tmp_p);
719 if (!tmp_v) {
0c61ed5f 720 DBG_PRINT(INFO_DBG,
776bd20f 721 "pci_alloc_consistent ");
0c61ed5f 722 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 723 return -ENOMEM;
724 }
491976b2 725 mem_allocated += PAGE_SIZE;
776bd20f 726 }
1da177e4
LT		 727 while (k < lst_per_page) {
728 int l = (j * lst_per_page) + k;
729 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 730 break;
731 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 732 tmp_v + (k * lst_size);
20346722 733 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 734 tmp_p + (k * lst_size);
735 k++;
736 }
737 }
738 }
1da177e4 739
2fda096d
SR		 740 for (i = 0; i < config->tx_fifo_num; i++) {
741 size = config->tx_cfg[i].fifo_len;
742 mac_control->fifos[i].ufo_in_band_v
743 = kcalloc(size, sizeof(u64), GFP_KERNEL);
744 if (!mac_control->fifos[i].ufo_in_band_v)
745 return -ENOMEM;
746 mem_allocated += (size * sizeof(u64));
747 }
fed5eccd 748
1da177e4
LT		 749 /* Allocation and initialization of RXDs in Rings */
750 size = 0;
751 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 752 if (config->rx_cfg[i].num_rxd %
753 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 754 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
755 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
756 i);
757 DBG_PRINT(ERR_DBG, "RxDs per Block");
758 return FAILURE;
759 }
760 size += config->rx_cfg[i].num_rxd;
20346722 761 mac_control->rings[i].block_count =
da6971d8
AR		 762 config->rx_cfg[i].num_rxd /
763 (rxd_count[nic->rxd_mode] + 1 );
764 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
765 mac_control->rings[i].block_count;
1da177e4 766 }
da6971d8 767 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 768 size = (size * (sizeof(struct RxD1)));
da6971d8 769 else
1ee6dd77 770 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 771
772 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 773 mac_control->rings[i].rx_curr_get_info.block_index = 0;
774 mac_control->rings[i].rx_curr_get_info.offset = 0;
775 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 776 config->rx_cfg[i].num_rxd - 1;
20346722
K		 777 mac_control->rings[i].rx_curr_put_info.block_index = 0;
778 mac_control->rings[i].rx_curr_put_info.offset = 0;
779 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 780 config->rx_cfg[i].num_rxd - 1;
20346722
K		 781 mac_control->rings[i].nic = nic;
782 mac_control->rings[i].ring_no = i;
0425b46a 783 mac_control->rings[i].lro = lro_enable;
20346722 784
da6971d8
AR		 785 blk_cnt = config->rx_cfg[i].num_rxd /
786 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 787 /* Allocating all the Rx blocks */
788 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 789 struct rx_block_info *rx_blocks;
da6971d8
AR		 790 int l;
791
792 rx_blocks = &mac_control->rings[i].rx_blocks[j];
793 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 794 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
795 &tmp_p_addr);
796 if (tmp_v_addr == NULL) {
797 /*
20346722
K		 798 * In case of failure, free_shared_mem()
799 * is called, which should free any
800 * memory that was alloced till the
1da177e4
LT		 801 * failure happened.
802 */
da6971d8 803 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 804 return -ENOMEM;
805 }
491976b2 806 mem_allocated += size;
1da177e4 807 memset(tmp_v_addr, 0, size);
da6971d8
AR		 808 rx_blocks->block_virt_addr = tmp_v_addr;
809 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 810 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 811 rxd_count[nic->rxd_mode],
812 GFP_KERNEL);
372cc597
SS		 813 if (!rx_blocks->rxds)
814 return -ENOMEM;
8a4bdbaa 815 mem_allocated +=
491976b2 816 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 817 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
818 rx_blocks->rxds[l].virt_addr =
819 rx_blocks->block_virt_addr +
820 (rxd_size[nic->rxd_mode] * l);
821 rx_blocks->rxds[l].dma_addr =
822 rx_blocks->block_dma_addr +
823 (rxd_size[nic->rxd_mode] * l);
824 }
1da177e4
LT		 825 }
826 /* Interlinking all Rx Blocks */
827 for (j = 0; j < blk_cnt; j++) {
20346722
K		 828 tmp_v_addr =
829 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 830 tmp_v_addr_next =
20346722 831 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 832 blk_cnt].block_virt_addr;
20346722
K		 833 tmp_p_addr =
834 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 835 tmp_p_addr_next =
20346722 836 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 837 blk_cnt].block_dma_addr;
838
1ee6dd77 839 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 840 pre_rxd_blk->reserved_2_pNext_RxD_block =
841 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 842 pre_rxd_blk->pNext_RxD_Blk_physical =
843 (u64) tmp_p_addr_next;
844 }
845 }
6d517a27 846 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 847 /*
848 * Allocation of Storages for buffer addresses in 2BUFF mode
849 * and the buffers as well.
850 */
851 for (i = 0; i < config->rx_ring_num; i++) {
852 blk_cnt = config->rx_cfg[i].num_rxd /
853 (rxd_count[nic->rxd_mode]+ 1);
854 mac_control->rings[i].ba =
1ee6dd77 855 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 856 GFP_KERNEL);
da6971d8 857 if (!mac_control->rings[i].ba)
1da177e4 858 return -ENOMEM;
491976b2 859 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 860 for (j = 0; j < blk_cnt; j++) {
861 int k = 0;
862 mac_control->rings[i].ba[j] =
1ee6dd77 863 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 864 (rxd_count[nic->rxd_mode] + 1)),
865 GFP_KERNEL);
866 if (!mac_control->rings[i].ba[j])
1da177e4 867 return -ENOMEM;
491976b2
SH		 868 mem_allocated += (sizeof(struct buffAdd) * \
869 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 870 while (k != rxd_count[nic->rxd_mode]) {
871 ba = &mac_control->rings[i].ba[j][k];
872
873 ba->ba_0_org = (void *) kmalloc
874 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
875 if (!ba->ba_0_org)
876 return -ENOMEM;
8a4bdbaa 877 mem_allocated +=
491976b2 878 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 879 tmp = (unsigned long)ba->ba_0_org;
880 tmp += ALIGN_SIZE;
881 tmp &= ~((unsigned long) ALIGN_SIZE);
882 ba->ba_0 = (void *) tmp;
883
884 ba->ba_1_org = (void *) kmalloc
885 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
886 if (!ba->ba_1_org)
887 return -ENOMEM;
8a4bdbaa 888 mem_allocated
491976b2 889 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 890 tmp = (unsigned long) ba->ba_1_org;
891 tmp += ALIGN_SIZE;
892 tmp &= ~((unsigned long) ALIGN_SIZE);
893 ba->ba_1 = (void *) tmp;
894 k++;
895 }
1da177e4
LT		 896 }
897 }
898 }
1da177e4
LT		 899
900 /* Allocation and initialization of Statistics block */
1ee6dd77 901 size = sizeof(struct stat_block);
1da177e4
LT		 902 mac_control->stats_mem = pci_alloc_consistent
903 (nic->pdev, size, &mac_control->stats_mem_phy);
904
905 if (!mac_control->stats_mem) {
20346722
K		 906 /*
907 * In case of failure, free_shared_mem() is called, which
908 * should free any memory that was alloced till the
1da177e4
LT		 909 * failure happened.
910 */
911 return -ENOMEM;
912 }
491976b2 913 mem_allocated += size;
1da177e4
LT		 914 mac_control->stats_mem_sz = size;
915
916 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 917 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 918 memset(tmp_v_addr, 0, size);
1da177e4
LT		 919 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
920 (unsigned long long) tmp_p_addr);
491976b2 921 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 922 return SUCCESS;
923}
924
20346722
K		 925/**
926 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 927 * @nic: Device private variable.
928 * Description: This function is to free all memory locations allocated by
929 * the init_shared_mem() function and return it to the kernel.
930 */
931
932static void free_shared_mem(struct s2io_nic *nic)
933{
934 int i, j, blk_cnt, size;
935 void *tmp_v_addr;
936 dma_addr_t tmp_p_addr;
1ee6dd77 937 struct mac_info *mac_control;
1da177e4
LT		 938 struct config_param *config;
939 int lst_size, lst_per_page;
8910b49f 940 struct net_device *dev;
491976b2 941 int page_num = 0;
1da177e4
LT		 942
943 if (!nic)
944 return;
945
8910b49f
MG		 946 dev = nic->dev;
947
1da177e4
LT		 948 mac_control = &nic->mac_control;
949 config = &nic->config;
950
1ee6dd77 951 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 952 lst_per_page = PAGE_SIZE / lst_size;
953
954 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 955 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
956 lst_per_page);
1da177e4
LT		 957 for (j = 0; j < page_num; j++) {
958 int mem_blks = (j * lst_per_page);
776bd20f 959 if (!mac_control->fifos[i].list_info)
6aa20a22 960 return;
776bd20f 961 if (!mac_control->fifos[i].list_info[mem_blks].
962 list_virt_addr)
1da177e4
LT		 963 break;
964 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 965 mac_control->fifos[i].
966 list_info[mem_blks].
1da177e4 967 list_virt_addr,
20346722
K		 968 mac_control->fifos[i].
969 list_info[mem_blks].
1da177e4 970 list_phy_addr);
8a4bdbaa 971 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 972 += PAGE_SIZE;
1da177e4 973 }
776bd20f 974 /* If we got a zero DMA address during allocation,
975 * free the page now
976 */
977 if (mac_control->zerodma_virt_addr) {
978 pci_free_consistent(nic->pdev, PAGE_SIZE,
979 mac_control->zerodma_virt_addr,
980 (dma_addr_t)0);
6aa20a22 981 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 982 "%s: Freeing TxDL with zero DMA addr. ",
983 dev->name);
984 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
985 mac_control->zerodma_virt_addr);
8a4bdbaa 986 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 987 += PAGE_SIZE;
776bd20f 988 }
20346722 989 kfree(mac_control->fifos[i].list_info);
8a4bdbaa 990 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 991 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 992 }
993
1da177e4 994 size = SIZE_OF_BLOCK;
1da177e4 995 for (i = 0; i < config->rx_ring_num; i++) {
20346722 996 blk_cnt = mac_control->rings[i].block_count;
1da177e4 997 for (j = 0; j < blk_cnt; j++) {
20346722
K		 998 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
999 block_virt_addr;
1000 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1001 block_dma_addr;
1da177e4
LT		 1002 if (tmp_v_addr == NULL)
1003 break;
1004 pci_free_consistent(nic->pdev, size,
1005 tmp_v_addr, tmp_p_addr);
491976b2 1006 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 1007 kfree(mac_control->rings[i].rx_blocks[j].rxds);
8a4bdbaa 1008 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1009 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 1010 }
1011 }
1012
6d517a27 1013 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1014 /* Freeing buffer storage addresses in 2BUFF mode. */
1015 for (i = 0; i < config->rx_ring_num; i++) {
1016 blk_cnt = config->rx_cfg[i].num_rxd /
1017 (rxd_count[nic->rxd_mode] + 1);
1018 for (j = 0; j < blk_cnt; j++) {
1019 int k = 0;
1020 if (!mac_control->rings[i].ba[j])
1021 continue;
1022 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 1023 struct buffAdd *ba =
da6971d8
AR		 1024 &mac_control->rings[i].ba[j][k];
1025 kfree(ba->ba_0_org);
491976b2
SH		 1026 nic->mac_control.stats_info->sw_stat.\
1027 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 1028 kfree(ba->ba_1_org);
491976b2
SH		 1029 nic->mac_control.stats_info->sw_stat.\
1030 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 1031 k++;
1032 }
1033 kfree(mac_control->rings[i].ba[j]);
9caab458
SS		 1034 nic->mac_control.stats_info->sw_stat.mem_freed +=
1035 (sizeof(struct buffAdd) *
1036 (rxd_count[nic->rxd_mode] + 1));
1da177e4 1037 }
da6971d8 1038 kfree(mac_control->rings[i].ba);
8a4bdbaa 1039 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1040 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 1041 }
1da177e4 1042 }
1da177e4 1043
2fda096d
SR		 1044 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1045 if (mac_control->fifos[i].ufo_in_band_v) {
1046 nic->mac_control.stats_info->sw_stat.mem_freed
1047 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1048 kfree(mac_control->fifos[i].ufo_in_band_v);
1049 }
1050 }
1051
1da177e4 1052 if (mac_control->stats_mem) {
2fda096d
SR		 1053 nic->mac_control.stats_info->sw_stat.mem_freed +=
1054 mac_control->stats_mem_sz;
1da177e4
LT		 1055 pci_free_consistent(nic->pdev,
1056 mac_control->stats_mem_sz,
1057 mac_control->stats_mem,
1058 mac_control->stats_mem_phy);
491976b2 1059 }
1da177e4
LT		 1060}
1061
541ae68f
K		 1062/**
1063 * s2io_verify_pci_mode -
1064 */
1065
1ee6dd77 1066static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1067{
1ee6dd77 1068 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1069 register u64 val64 = 0;
1070 int mode;
1071
1072 val64 = readq(&bar0->pci_mode);
1073 mode = (u8)GET_PCI_MODE(val64);
1074
1075 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1076 return -1; /* Unknown PCI mode */
1077 return mode;
1078}
1079
c92ca04b
AR		 1080#define NEC_VENID 0x1033
1081#define NEC_DEVID 0x0125
1082static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1083{
1084 struct pci_dev *tdev = NULL;
26d36b64
AC		 1085 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1086 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1087 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1088 pci_dev_put(tdev);
c92ca04b 1089 return 1;
7ad62dbc 1090 }
c92ca04b
AR		 1091 }
1092 }
1093 return 0;
1094}
541ae68f 1095
7b32a312 1096static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1097/**
1098 * s2io_print_pci_mode -
1099 */
1ee6dd77 1100static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1101{
1ee6dd77 1102 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1103 register u64 val64 = 0;
1104 int mode;
1105 struct config_param *config = &nic->config;
1106
1107 val64 = readq(&bar0->pci_mode);
1108 mode = (u8)GET_PCI_MODE(val64);
1109
1110 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1111 return -1; /* Unknown PCI mode */
1112
c92ca04b
AR		 1113 config->bus_speed = bus_speed[mode];
1114
1115 if (s2io_on_nec_bridge(nic->pdev)) {
1116 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1117 nic->dev->name);
1118 return mode;
1119 }
1120
541ae68f
K		 1121 if (val64 & PCI_MODE_32_BITS) {
1122 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1123 } else {
1124 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1125 }
1126
1127 switch(mode) {
1128 case PCI_MODE_PCI_33:
1129 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 1130 break;
1131 case PCI_MODE_PCI_66:
1132 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 1133 break;
1134 case PCI_MODE_PCIX_M1_66:
1135 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 1136 break;
1137 case PCI_MODE_PCIX_M1_100:
1138 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 1139 break;
1140 case PCI_MODE_PCIX_M1_133:
1141 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 1142 break;
1143 case PCI_MODE_PCIX_M2_66:
1144 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 1145 break;
1146 case PCI_MODE_PCIX_M2_100:
1147 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 1148 break;
1149 case PCI_MODE_PCIX_M2_133:
1150 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 1151 break;
1152 default:
1153 return -1; /* Unsupported bus speed */
1154 }
1155
1156 return mode;
1157}
1158
b7c5678f
RV		 1159/**
1160 * init_tti - Initialization transmit traffic interrupt scheme
1161 * @nic: device private variable
1162 * @link: link status (UP/DOWN) used to enable/disable continuous
1163 * transmit interrupts
1164 * Description: The function configures transmit traffic interrupts
1165 * Return Value: SUCCESS on success and
1166 * '-1' on failure
1167 */
1168
0d66afe7 1169static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1170{
1171 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1172 register u64 val64 = 0;
1173 int i;
1174 struct config_param *config;
1175
1176 config = &nic->config;
1177
1178 for (i = 0; i < config->tx_fifo_num; i++) {
1179 /*
1180 * TTI Initialization. Default Tx timer gets us about
1181 * 250 interrupts per sec. Continuous interrupts are enabled
1182 * by default.
1183 */
1184 if (nic->device_type == XFRAME_II_DEVICE) {
1185 int count = (nic->config.bus_speed * 125)/2;
1186 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1187 } else
1188 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1189
1190 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1191 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1192 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1193 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1194 if (i == 0)
1195 if (use_continuous_tx_intrs && (link == LINK_UP))
1196 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1197 writeq(val64, &bar0->tti_data1_mem);
1198
ac731ab6
SH		 1199 if (nic->config.intr_type == MSI_X) {
1200 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1201 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1202 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1203 TTI_DATA2_MEM_TX_UFC_D(0x300);
1204 } else {
1205 if ((nic->config.tx_steering_type ==
1206 TX_DEFAULT_STEERING) &&
1207 (config->tx_fifo_num > 1) &&
1208 (i >= nic->udp_fifo_idx) &&
1209 (i < (nic->udp_fifo_idx +
1210 nic->total_udp_fifos)))
1211 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1212 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1213 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1214 TTI_DATA2_MEM_TX_UFC_D(0x120);
1215 else
1216 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1217 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1218 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1219 TTI_DATA2_MEM_TX_UFC_D(0x80);
1220 }
b7c5678f
RV		 1221
1222 writeq(val64, &bar0->tti_data2_mem);
1223
1224 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1225 TTI_CMD_MEM_OFFSET(i);
1226 writeq(val64, &bar0->tti_command_mem);
1227
1228 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1229 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1230 return FAILURE;
1231 }
1232
1233 return SUCCESS;
1234}
1235
20346722
K		 1236/**
1237 * init_nic - Initialization of hardware
b7c5678f 1238 * @nic: device private variable
20346722
K		 1239 * Description: The function sequentially configures every block
1240 * of the H/W from their reset values.
1241 * Return Value: SUCCESS on success and
1da177e4
LT		 1242 * '-1' on failure (endian settings incorrect).
1243 */
1244
1245static int init_nic(struct s2io_nic *nic)
1246{
1ee6dd77 1247 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1248 struct net_device *dev = nic->dev;
1249 register u64 val64 = 0;
1250 void __iomem *add;
1251 u32 time;
1252 int i, j;
1ee6dd77 1253 struct mac_info *mac_control;
1da177e4 1254 struct config_param *config;
c92ca04b 1255 int dtx_cnt = 0;
1da177e4 1256 unsigned long long mem_share;
20346722 1257 int mem_size;
1da177e4
LT		 1258
1259 mac_control = &nic->mac_control;
1260 config = &nic->config;
1261
5e25b9dd 1262 /* to set the swapper controle on the card */
20346722 1263 if(s2io_set_swapper(nic)) {
1da177e4 1264 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
9f74ffde 1265 return -EIO;
1da177e4
LT		 1266 }
1267
541ae68f
K		 1268 /*
1269 * Herc requires EOI to be removed from reset before XGXS, so..
1270 */
1271 if (nic->device_type & XFRAME_II_DEVICE) {
1272 val64 = 0xA500000000ULL;
1273 writeq(val64, &bar0->sw_reset);
1274 msleep(500);
1275 val64 = readq(&bar0->sw_reset);
1276 }
1277
1da177e4
LT		 1278 /* Remove XGXS from reset state */
1279 val64 = 0;
1280 writeq(val64, &bar0->sw_reset);
1da177e4 1281 msleep(500);
20346722 1282 val64 = readq(&bar0->sw_reset);
1da177e4 1283
7962024e
SH		 1284 /* Ensure that it's safe to access registers by checking
1285 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1286 */
1287 if (nic->device_type == XFRAME_II_DEVICE) {
1288 for (i = 0; i < 50; i++) {
1289 val64 = readq(&bar0->adapter_status);
1290 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1291 break;
1292 msleep(10);
1293 }
1294 if (i == 50)
1295 return -ENODEV;
1296 }
1297
1da177e4
LT		 1298 /* Enable Receiving broadcasts */
1299 add = &bar0->mac_cfg;
1300 val64 = readq(&bar0->mac_cfg);
1301 val64 |= MAC_RMAC_BCAST_ENABLE;
1302 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1303 writel((u32) val64, add);
1304 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1305 writel((u32) (val64 >> 32), (add + 4));
1306
1307 /* Read registers in all blocks */
1308 val64 = readq(&bar0->mac_int_mask);
1309 val64 = readq(&bar0->mc_int_mask);
1310 val64 = readq(&bar0->xgxs_int_mask);
1311
1312 /* Set MTU */
1313 val64 = dev->mtu;
1314 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1315
541ae68f
K		 1316 if (nic->device_type & XFRAME_II_DEVICE) {
1317 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1318 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1319 &bar0->dtx_control, UF);
541ae68f
K		 1320 if (dtx_cnt & 0x1)
1321 msleep(1); /* Necessary!! */
1da177e4
LT		 1322 dtx_cnt++;
1323 }
541ae68f 1324 } else {
c92ca04b
AR		 1325 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1326 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1327 &bar0->dtx_control, UF);
1328 val64 = readq(&bar0->dtx_control);
1329 dtx_cnt++;
1da177e4
LT		 1330 }
1331 }
1332
1333 /* Tx DMA Initialization */
1334 val64 = 0;
1335 writeq(val64, &bar0->tx_fifo_partition_0);
1336 writeq(val64, &bar0->tx_fifo_partition_1);
1337 writeq(val64, &bar0->tx_fifo_partition_2);
1338 writeq(val64, &bar0->tx_fifo_partition_3);
1339
1340
1341 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1342 val64 |=
b7c5678f 1343 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1da177e4 1344 13) | vBIT(config->tx_cfg[i].fifo_priority,
b7c5678f 1345 ((j * 32) + 5), 3);
1da177e4
LT		 1346
1347 if (i == (config->tx_fifo_num - 1)) {
1348 if (i % 2 == 0)
1349 i++;
1350 }
1351
1352 switch (i) {
1353 case 1:
1354 writeq(val64, &bar0->tx_fifo_partition_0);
1355 val64 = 0;
b7c5678f 1356 j = 0;
1da177e4
LT		 1357 break;
1358 case 3:
1359 writeq(val64, &bar0->tx_fifo_partition_1);
1360 val64 = 0;
b7c5678f 1361 j = 0;
1da177e4
LT		 1362 break;
1363 case 5:
1364 writeq(val64, &bar0->tx_fifo_partition_2);
1365 val64 = 0;
b7c5678f 1366 j = 0;
1da177e4
LT		 1367 break;
1368 case 7:
1369 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1370 val64 = 0;
1371 j = 0;
1372 break;
1373 default:
1374 j++;
1da177e4
LT		 1375 break;
1376 }
1377 }
1378
5e25b9dd
K		 1379 /*
1380 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1381 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1382 */
541ae68f 1383 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1384 (nic->pdev->revision < 4))
5e25b9dd
K		 1385 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1386
1da177e4
LT		 1387 val64 = readq(&bar0->tx_fifo_partition_0);
1388 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1389 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1390
20346722
K		 1391 /*
1392 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1393 * integrity checking.
1394 */
1395 val64 = readq(&bar0->tx_pa_cfg);
1396 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1397 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1398 writeq(val64, &bar0->tx_pa_cfg);
1399
1400 /* Rx DMA intialization. */
1401 val64 = 0;
1402 for (i = 0; i < config->rx_ring_num; i++) {
1403 val64 |=
1404 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1405 3);
1406 }
1407 writeq(val64, &bar0->rx_queue_priority);
1408
20346722
K		 1409 /*
1410 * Allocating equal share of memory to all the
1da177e4
LT		 1411 * configured Rings.
1412 */
1413 val64 = 0;
541ae68f
K		 1414 if (nic->device_type & XFRAME_II_DEVICE)
1415 mem_size = 32;
1416 else
1417 mem_size = 64;
1418
1da177e4
LT		 1419 for (i = 0; i < config->rx_ring_num; i++) {
1420 switch (i) {
1421 case 0:
20346722
K		 1422 mem_share = (mem_size / config->rx_ring_num +
1423 mem_size % config->rx_ring_num);
1da177e4
LT		 1424 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1425 continue;
1426 case 1:
20346722 1427 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1428 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1429 continue;
1430 case 2:
20346722 1431 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1432 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1433 continue;
1434 case 3:
20346722 1435 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1436 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1437 continue;
1438 case 4:
20346722 1439 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1440 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1441 continue;
1442 case 5:
20346722 1443 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1444 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1445 continue;
1446 case 6:
20346722 1447 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1448 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1449 continue;
1450 case 7:
20346722 1451 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1452 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1453 continue;
1454 }
1455 }
1456 writeq(val64, &bar0->rx_queue_cfg);
1457
20346722 1458 /*
5e25b9dd 1459 * Filling Tx round robin registers
b7c5678f 1460 * as per the number of FIFOs for equal scheduling priority
1da177e4 1461 */
5e25b9dd
K		 1462 switch (config->tx_fifo_num) {
1463 case 1:
b7c5678f 1464 val64 = 0x0;
5e25b9dd
K		 1465 writeq(val64, &bar0->tx_w_round_robin_0);
1466 writeq(val64, &bar0->tx_w_round_robin_1);
1467 writeq(val64, &bar0->tx_w_round_robin_2);
1468 writeq(val64, &bar0->tx_w_round_robin_3);
1469 writeq(val64, &bar0->tx_w_round_robin_4);
1470 break;
1471 case 2:
b7c5678f 1472 val64 = 0x0001000100010001ULL;
5e25b9dd 1473 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1474 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1475 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1476 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1477 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1478 writeq(val64, &bar0->tx_w_round_robin_4);
1479 break;
1480 case 3:
b7c5678f 1481 val64 = 0x0001020001020001ULL;
5e25b9dd 1482 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1483 val64 = 0x0200010200010200ULL;
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1485 val64 = 0x0102000102000102ULL;
5e25b9dd 1486 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1487 val64 = 0x0001020001020001ULL;
5e25b9dd 1488 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1489 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1490 writeq(val64, &bar0->tx_w_round_robin_4);
1491 break;
1492 case 4:
b7c5678f 1493 val64 = 0x0001020300010203ULL;
5e25b9dd 1494 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1496 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1497 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1498 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1499 writeq(val64, &bar0->tx_w_round_robin_4);
1500 break;
1501 case 5:
b7c5678f 1502 val64 = 0x0001020304000102ULL;
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1504 val64 = 0x0304000102030400ULL;
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1506 val64 = 0x0102030400010203ULL;
5e25b9dd 1507 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1508 val64 = 0x0400010203040001ULL;
5e25b9dd 1509 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1510 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1511 writeq(val64, &bar0->tx_w_round_robin_4);
1512 break;
1513 case 6:
b7c5678f 1514 val64 = 0x0001020304050001ULL;
5e25b9dd 1515 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1516 val64 = 0x0203040500010203ULL;
5e25b9dd 1517 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1518 val64 = 0x0405000102030405ULL;
5e25b9dd 1519 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1520 val64 = 0x0001020304050001ULL;
5e25b9dd 1521 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1522 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1523 writeq(val64, &bar0->tx_w_round_robin_4);
1524 break;
1525 case 7:
b7c5678f 1526 val64 = 0x0001020304050600ULL;
5e25b9dd 1527 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1528 val64 = 0x0102030405060001ULL;
5e25b9dd 1529 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1530 val64 = 0x0203040506000102ULL;
5e25b9dd 1531 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1532 val64 = 0x0304050600010203ULL;
5e25b9dd 1533 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1534 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1535 writeq(val64, &bar0->tx_w_round_robin_4);
1536 break;
1537 case 8:
b7c5678f 1538 val64 = 0x0001020304050607ULL;
5e25b9dd 1539 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1541 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1542 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1543 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1544 writeq(val64, &bar0->tx_w_round_robin_4);
1545 break;
1546 }
1547
b41477f3 1548 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1549 val64 = readq(&bar0->tx_fifo_partition_0);
1550 val64 |= (TX_FIFO_PARTITION_EN);
1551 writeq(val64, &bar0->tx_fifo_partition_0);
1552
5e25b9dd 1553 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1554 * number of Rings and steering based on QoS with
1555 * equal priority.
1556 */
5e25b9dd
K		 1557 switch (config->rx_ring_num) {
1558 case 1:
0425b46a
SH		 1559 val64 = 0x0;
1560 writeq(val64, &bar0->rx_w_round_robin_0);
1561 writeq(val64, &bar0->rx_w_round_robin_1);
1562 writeq(val64, &bar0->rx_w_round_robin_2);
1563 writeq(val64, &bar0->rx_w_round_robin_3);
1564 writeq(val64, &bar0->rx_w_round_robin_4);
1565
5e25b9dd
K		 1566 val64 = 0x8080808080808080ULL;
1567 writeq(val64, &bar0->rts_qos_steering);
1568 break;
1569 case 2:
0425b46a 1570 val64 = 0x0001000100010001ULL;
5e25b9dd 1571 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1572 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1573 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1574 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1575 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1576 writeq(val64, &bar0->rx_w_round_robin_4);
1577
1578 val64 = 0x8080808040404040ULL;
1579 writeq(val64, &bar0->rts_qos_steering);
1580 break;
1581 case 3:
0425b46a 1582 val64 = 0x0001020001020001ULL;
5e25b9dd 1583 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1584 val64 = 0x0200010200010200ULL;
5e25b9dd 1585 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1586 val64 = 0x0102000102000102ULL;
5e25b9dd 1587 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1588 val64 = 0x0001020001020001ULL;
5e25b9dd 1589 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1590 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1591 writeq(val64, &bar0->rx_w_round_robin_4);
1592
1593 val64 = 0x8080804040402020ULL;
1594 writeq(val64, &bar0->rts_qos_steering);
1595 break;
1596 case 4:
0425b46a 1597 val64 = 0x0001020300010203ULL;
5e25b9dd 1598 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1599 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1600 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1601 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1602 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1603 writeq(val64, &bar0->rx_w_round_robin_4);
1604
1605 val64 = 0x8080404020201010ULL;
1606 writeq(val64, &bar0->rts_qos_steering);
1607 break;
1608 case 5:
0425b46a 1609 val64 = 0x0001020304000102ULL;
5e25b9dd 1610 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1611 val64 = 0x0304000102030400ULL;
5e25b9dd 1612 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1613 val64 = 0x0102030400010203ULL;
5e25b9dd 1614 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1615 val64 = 0x0400010203040001ULL;
5e25b9dd 1616 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1617 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1618 writeq(val64, &bar0->rx_w_round_robin_4);
1619
1620 val64 = 0x8080404020201008ULL;
1621 writeq(val64, &bar0->rts_qos_steering);
1622 break;
1623 case 6:
0425b46a 1624 val64 = 0x0001020304050001ULL;
5e25b9dd 1625 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1626 val64 = 0x0203040500010203ULL;
5e25b9dd 1627 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1628 val64 = 0x0405000102030405ULL;
5e25b9dd 1629 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1630 val64 = 0x0001020304050001ULL;
5e25b9dd 1631 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1632 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1633 writeq(val64, &bar0->rx_w_round_robin_4);
1634
1635 val64 = 0x8080404020100804ULL;
1636 writeq(val64, &bar0->rts_qos_steering);
1637 break;
1638 case 7:
0425b46a 1639 val64 = 0x0001020304050600ULL;
5e25b9dd 1640 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1641 val64 = 0x0102030405060001ULL;
5e25b9dd 1642 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1643 val64 = 0x0203040506000102ULL;
5e25b9dd 1644 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1645 val64 = 0x0304050600010203ULL;
5e25b9dd 1646 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1647 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1648 writeq(val64, &bar0->rx_w_round_robin_4);
1649
1650 val64 = 0x8080402010080402ULL;
1651 writeq(val64, &bar0->rts_qos_steering);
1652 break;
1653 case 8:
0425b46a 1654 val64 = 0x0001020304050607ULL;
5e25b9dd 1655 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1656 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1657 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1658 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1659 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1660 writeq(val64, &bar0->rx_w_round_robin_4);
1661
1662 val64 = 0x8040201008040201ULL;
1663 writeq(val64, &bar0->rts_qos_steering);
1664 break;
1665 }
1da177e4
LT		 1666
1667 /* UDP Fix */
1668 val64 = 0;
20346722 1669 for (i = 0; i < 8; i++)
1da177e4
LT		 1670 writeq(val64, &bar0->rts_frm_len_n[i]);
1671
5e25b9dd
K		 1672 /* Set the default rts frame length for the rings configured */
1673 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1674 for (i = 0 ; i < config->rx_ring_num ; i++)
1675 writeq(val64, &bar0->rts_frm_len_n[i]);
1676
1677 /* Set the frame length for the configured rings
1678 * desired by the user
1679 */
1680 for (i = 0; i < config->rx_ring_num; i++) {
1681 /* If rts_frm_len[i] == 0 then it is assumed that user not
1682 * specified frame length steering.
1683 * If the user provides the frame length then program
1684 * the rts_frm_len register for those values or else
1685 * leave it as it is.
1686 */
1687 if (rts_frm_len[i] != 0) {
1688 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1689 &bar0->rts_frm_len_n[i]);
1690 }
1691 }
8a4bdbaa 1692
9fc93a41
SS		 1693 /* Disable differentiated services steering logic */
1694 for (i = 0; i < 64; i++) {
1695 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1696 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1697 dev->name);
1698 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1699 return -ENODEV;
9fc93a41
SS		 1700 }
1701 }
1702
20346722 1703 /* Program statistics memory */
1da177e4 1704 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1705
541ae68f
K		 1706 if (nic->device_type == XFRAME_II_DEVICE) {
1707 val64 = STAT_BC(0x320);
1708 writeq(val64, &bar0->stat_byte_cnt);
1709 }
1710
20346722 1711 /*
1da177e4
LT		 1712 * Initializing the sampling rate for the device to calculate the
1713 * bandwidth utilization.
1714 */
1715 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1716 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1717 writeq(val64, &bar0->mac_link_util);
1718
20346722
K		 1719 /*
1720 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1721 * Scheme.
1722 */
1da177e4 1723
b7c5678f
RV		 1724 /* Initialize TTI */
1725 if (SUCCESS != init_tti(nic, nic->last_link_state))
1726 return -ENODEV;
1da177e4 1727
8a4bdbaa
SS		 1728 /* RTI Initialization */
1729 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1730 /*
8a4bdbaa
SS		 1731 * Programmed to generate Apprx 500 Intrs per
1732 * second
1733 */
1734 int count = (nic->config.bus_speed * 125)/4;
1735 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1736 } else
1737 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1738 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1739 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1740 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1741
1742 writeq(val64, &bar0->rti_data1_mem);
1743
1744 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1745 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1746 if (nic->config.intr_type == MSI_X)
1747 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1748 RTI_DATA2_MEM_RX_UFC_D(0x40));
1749 else
1750 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1751 RTI_DATA2_MEM_RX_UFC_D(0x80));
1752 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1753
8a4bdbaa
SS		 1754 for (i = 0; i < config->rx_ring_num; i++) {
1755 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1756 | RTI_CMD_MEM_OFFSET(i);
1757 writeq(val64, &bar0->rti_command_mem);
1da177e4 1758
8a4bdbaa
SS		 1759 /*
1760 * Once the operation completes, the Strobe bit of the
1761 * command register will be reset. We poll for this
1762 * particular condition. We wait for a maximum of 500ms
1763 * for the operation to complete, if it's not complete
1764 * by then we return error.
1765 */
1766 time = 0;
f957bcf0 1767 while (true) {
8a4bdbaa
SS		 1768 val64 = readq(&bar0->rti_command_mem);
1769 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1770 break;
b6e3f982 1771
8a4bdbaa
SS		 1772 if (time > 10) {
1773 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1774 dev->name);
9f74ffde 1775 return -ENODEV;
b6e3f982 1776 }
8a4bdbaa
SS		 1777 time++;
1778 msleep(50);
1da177e4 1779 }
1da177e4
LT		 1780 }
1781
20346722
K		 1782 /*
1783 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1784 * the 8 Queues on Rx side.
1785 */
1786 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1787 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1788
1789 /* Disable RMAC PAD STRIPPING */
509a2671 1790 add = &bar0->mac_cfg;
1da177e4
LT		 1791 val64 = readq(&bar0->mac_cfg);
1792 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1793 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1794 writel((u32) (val64), add);
1795 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1796 writel((u32) (val64 >> 32), (add + 4));
1797 val64 = readq(&bar0->mac_cfg);
1798
7d3d0439
RA		 1799 /* Enable FCS stripping by adapter */
1800 add = &bar0->mac_cfg;
1801 val64 = readq(&bar0->mac_cfg);
1802 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1803 if (nic->device_type == XFRAME_II_DEVICE)
1804 writeq(val64, &bar0->mac_cfg);
1805 else {
1806 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807 writel((u32) (val64), add);
1808 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1809 writel((u32) (val64 >> 32), (add + 4));
1810 }
1811
20346722
K		 1812 /*
1813 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1814 * generated by xena.
1815 */
1816 val64 = readq(&bar0->rmac_pause_cfg);
1817 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1818 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1819 writeq(val64, &bar0->rmac_pause_cfg);
1820
20346722 1821 /*
1da177e4
LT		 1822 * Set the Threshold Limit for Generating the pause frame
1823 * If the amount of data in any Queue exceeds ratio of
1824 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1825 * pause frame is generated
1826 */
1827 val64 = 0;
1828 for (i = 0; i < 4; i++) {
1829 val64 |=
1830 (((u64) 0xFF00 | nic->mac_control.
1831 mc_pause_threshold_q0q3)
1832 << (i * 2 * 8));
1833 }
1834 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1835
1836 val64 = 0;
1837 for (i = 0; i < 4; i++) {
1838 val64 |=
1839 (((u64) 0xFF00 | nic->mac_control.
1840 mc_pause_threshold_q4q7)
1841 << (i * 2 * 8));
1842 }
1843 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1844
20346722
K		 1845 /*
1846 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1847 * exceeded the limit pointed by shared_splits
1848 */
1849 val64 = readq(&bar0->pic_control);
1850 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1851 writeq(val64, &bar0->pic_control);
1852
863c11a9
AR		 1853 if (nic->config.bus_speed == 266) {
1854 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1855 writeq(0x0, &bar0->read_retry_delay);
1856 writeq(0x0, &bar0->write_retry_delay);
1857 }
1858
541ae68f
K		 1859 /*
1860 * Programming the Herc to split every write transaction
1861 * that does not start on an ADB to reduce disconnects.
1862 */
1863 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1864 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1865 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1866 writeq(val64, &bar0->misc_control);
1867 val64 = readq(&bar0->pic_control2);
b7b5a128 1868 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1869 writeq(val64, &bar0->pic_control2);
541ae68f 1870 }
c92ca04b
AR		 1871 if (strstr(nic->product_name, "CX4")) {
1872 val64 = TMAC_AVG_IPG(0x17);
1873 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1874 }
1875
1da177e4
LT		 1876 return SUCCESS;
1877}
a371a07d
K		 1878#define LINK_UP_DOWN_INTERRUPT 1
1879#define MAC_RMAC_ERR_TIMER 2
1880
1ee6dd77 1881static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d
K		 1882{
1883 if (nic->device_type == XFRAME_II_DEVICE)
1884 return LINK_UP_DOWN_INTERRUPT;
1885 else
1886 return MAC_RMAC_ERR_TIMER;
1887}
8116f3cf 1888
9caab458
SS		 1889/**
1890 * do_s2io_write_bits - update alarm bits in alarm register
1891 * @value: alarm bits
1892 * @flag: interrupt status
1893 * @addr: address value
1894 * Description: update alarm bits in alarm register
1895 * Return Value:
1896 * NONE.
1897 */
1898static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1899{
1900 u64 temp64;
1901
1902 temp64 = readq(addr);
1903
1904 if(flag == ENABLE_INTRS)
1905 temp64 &= ~((u64) value);
1906 else
1907 temp64 |= ((u64) value);
1908 writeq(temp64, addr);
1909}
1da177e4 1910
43b7c451 1911static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1912{
1913 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1914 register u64 gen_int_mask = 0;
01e16faa 1915 u64 interruptible;
9caab458 1916
01e16faa 1917 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458
SS		 1918 if (mask & TX_DMA_INTR) {
1919
1920 gen_int_mask |= TXDMA_INT_M;
1921
1922 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1923 TXDMA_PCC_INT | TXDMA_TTI_INT |
1924 TXDMA_LSO_INT | TXDMA_TPA_INT |
1925 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1926
1927 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1928 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1929 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1930 &bar0->pfc_err_mask);
1931
1932 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1933 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1934 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1935
1936 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1937 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1938 PCC_N_SERR | PCC_6_COF_OV_ERR |
1939 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1940 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1941 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1942
1943 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1944 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1945
1946 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1947 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1948 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1949 flag, &bar0->lso_err_mask);
1950
1951 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1952 flag, &bar0->tpa_err_mask);
1953
1954 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1955
1956 }
1957
1958 if (mask & TX_MAC_INTR) {
1959 gen_int_mask |= TXMAC_INT_M;
1960 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1961 &bar0->mac_int_mask);
1962 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1963 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1964 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1965 flag, &bar0->mac_tmac_err_mask);
1966 }
1967
1968 if (mask & TX_XGXS_INTR) {
1969 gen_int_mask |= TXXGXS_INT_M;
1970 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1971 &bar0->xgxs_int_mask);
1972 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1973 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1974 flag, &bar0->xgxs_txgxs_err_mask);
1975 }
1976
1977 if (mask & RX_DMA_INTR) {
1978 gen_int_mask |= RXDMA_INT_M;
1979 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1980 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1981 flag, &bar0->rxdma_int_mask);
1982 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1983 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1984 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1985 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1986 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1987 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1988 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1989 &bar0->prc_pcix_err_mask);
1990 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1991 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1992 &bar0->rpa_err_mask);
1993 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1994 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1995 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1996 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1997 flag, &bar0->rda_err_mask);
1998 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1999 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2000 flag, &bar0->rti_err_mask);
2001 }
2002
2003 if (mask & RX_MAC_INTR) {
2004 gen_int_mask |= RXMAC_INT_M;
2005 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2006 &bar0->mac_int_mask);
01e16faa 2007 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
9caab458 2008 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
01e16faa
SH		 2009 RMAC_DOUBLE_ECC_ERR;
2010 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2011 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2012 do_s2io_write_bits(interruptible,
9caab458
SS		 2013 flag, &bar0->mac_rmac_err_mask);
2014 }
2015
2016 if (mask & RX_XGXS_INTR)
2017 {
2018 gen_int_mask |= RXXGXS_INT_M;
2019 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2020 &bar0->xgxs_int_mask);
2021 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2022 &bar0->xgxs_rxgxs_err_mask);
2023 }
2024
2025 if (mask & MC_INTR) {
2026 gen_int_mask |= MC_INT_M;
2027 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2028 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2029 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2030 &bar0->mc_err_mask);
2031 }
2032 nic->general_int_mask = gen_int_mask;
2033
2034 /* Remove this line when alarm interrupts are enabled */
2035 nic->general_int_mask = 0;
2036}
20346722
K		 2037/**
2038 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2039 * @nic: device private variable,
2040 * @mask: A mask indicating which Intr block must be modified and,
2041 * @flag: A flag indicating whether to enable or disable the Intrs.
2042 * Description: This function will either disable or enable the interrupts
20346722
K		 2043 * depending on the flag argument. The mask argument can be used to
2044 * enable/disable any Intr block.
1da177e4
LT		 2045 * Return Value: NONE.
2046 */
2047
2048static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2049{
1ee6dd77 2050 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2051 register u64 temp64 = 0, intr_mask = 0;
2052
2053 intr_mask = nic->general_int_mask;
1da177e4
LT		 2054
2055 /* Top level interrupt classification */
2056 /* PIC Interrupts */
9caab458 2057 if (mask & TX_PIC_INTR) {
1da177e4 2058 /* Enable PIC Intrs in the general intr mask register */
9caab458 2059 intr_mask |= TXPIC_INT_M;
1da177e4 2060 if (flag == ENABLE_INTRS) {
20346722 2061 /*
a371a07d 2062 * If Hercules adapter enable GPIO otherwise
b41477f3 2063 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 2064 * interrupts for now.
2065 * TODO
1da177e4 2066 */
a371a07d
K		 2067 if (s2io_link_fault_indication(nic) ==
2068 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 2069 do_s2io_write_bits(PIC_INT_GPIO, flag,
2070 &bar0->pic_int_mask);
2071 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2072 &bar0->gpio_int_mask);
2073 } else
a371a07d 2074 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2075 } else if (flag == DISABLE_INTRS) {
20346722
K		 2076 /*
2077 * Disable PIC Intrs in the general
2078 * intr mask register
1da177e4
LT		 2079 */
2080 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2081 }
2082 }
2083
1da177e4
LT		 2084 /* Tx traffic interrupts */
2085 if (mask & TX_TRAFFIC_INTR) {
9caab458 2086 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2087 if (flag == ENABLE_INTRS) {
20346722 2088 /*
1da177e4 2089 * Enable all the Tx side interrupts
20346722 2090 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2091 */
2092 writeq(0x0, &bar0->tx_traffic_mask);
2093 } else if (flag == DISABLE_INTRS) {
20346722
K		 2094 /*
2095 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2096 * register.
2097 */
2098 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2099 }
2100 }
2101
2102 /* Rx traffic interrupts */
2103 if (mask & RX_TRAFFIC_INTR) {
9caab458 2104 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2105 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2106 /* writing 0 Enables all 8 RX interrupt levels */
2107 writeq(0x0, &bar0->rx_traffic_mask);
2108 } else if (flag == DISABLE_INTRS) {
20346722
K		 2109 /*
2110 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2111 * register.
2112 */
2113 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2114 }
2115 }
9caab458
SS		 2116
2117 temp64 = readq(&bar0->general_int_mask);
2118 if (flag == ENABLE_INTRS)
2119 temp64 &= ~((u64) intr_mask);
2120 else
2121 temp64 = DISABLE_ALL_INTRS;
2122 writeq(temp64, &bar0->general_int_mask);
2123
2124 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2125}
2126
19a60522
SS		 2127/**
2128 * verify_pcc_quiescent- Checks for PCC quiescent state
2129 * Return: 1 If PCC is quiescence
2130 * 0 If PCC is not quiescence
2131 */
1ee6dd77 2132static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2133{
19a60522 2134 int ret = 0, herc;
1ee6dd77 2135 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2136 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2137
19a60522 2138 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2139
f957bcf0 2140 if (flag == false) {
44c10138 2141 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2142 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2143 ret = 1;
19a60522
SS		 2144 } else {
2145 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2146 ret = 1;
20346722
K		 2147 }
2148 } else {
44c10138 2149 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2150 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2151 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2152 ret = 1;
5e25b9dd
K		 2153 } else {
2154 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2155 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2156 ret = 1;
20346722
K		 2157 }
2158 }
2159
2160 return ret;
2161}
2162/**
2163 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2164 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2165 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2166 * differs and the calling function passes the input argument flag to
2167 * indicate this.
20346722 2168 * Return: 1 If xena is quiescence
1da177e4
LT		 2169 * 0 If Xena is not quiescence
2170 */
2171
1ee6dd77 2172static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2173{
19a60522 2174 int mode;
1ee6dd77 2175 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2176 u64 val64 = readq(&bar0->adapter_status);
2177 mode = s2io_verify_pci_mode(sp);
1da177e4 2178
19a60522
SS		 2179 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2180 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2181 return 0;
2182 }
2183 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2184 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2185 return 0;
2186 }
2187 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2188 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2189 return 0;
2190 }
2191 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2192 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2193 return 0;
2194 }
2195 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2196 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2197 return 0;
2198 }
2199 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2200 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2201 return 0;
2202 }
2203 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2204 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2205 return 0;
2206 }
2207 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2208 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2209 return 0;
1da177e4
LT		 2210 }
2211
19a60522
SS		 2212 /*
2213 * In PCI 33 mode, the P_PLL is not used, and therefore,
2214 * the the P_PLL_LOCK bit in the adapter_status register will
2215 * not be asserted.
2216 */
2217 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2218 sp->device_type == XFRAME_II_DEVICE && mode !=
2219 PCI_MODE_PCI_33) {
2220 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2221 return 0;
2222 }
2223 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2224 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2225 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2226 return 0;
2227 }
2228 return 1;
1da177e4
LT		 2229}
2230
2231/**
2232 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2233 * @sp: Pointer to device specifc structure
20346722 2234 * Description :
1da177e4
LT		 2235 * New procedure to clear mac address reading problems on Alpha platforms
2236 *
2237 */
2238
1ee6dd77 2239static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2240{
1ee6dd77 2241 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2242 u64 val64;
2243 int i = 0;
2244
2245 while (fix_mac[i] != END_SIGN) {
2246 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2247 udelay(10);
1da177e4
LT		 2248 val64 = readq(&bar0->gpio_control);
2249 }
2250}
2251
2252/**
20346722 2253 * start_nic - Turns the device on
1da177e4 2254 * @nic : device private variable.
20346722
K		 2255 * Description:
2256 * This function actually turns the device on. Before this function is
2257 * called,all Registers are configured from their reset states
2258 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2259 * calling this function, the device interrupts are cleared and the NIC is
2260 * literally switched on by writing into the adapter control register.
20346722 2261 * Return Value:
1da177e4
LT		 2262 * SUCCESS on success and -1 on failure.
2263 */
2264
2265static int start_nic(struct s2io_nic *nic)
2266{
1ee6dd77 2267 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2268 struct net_device *dev = nic->dev;
2269 register u64 val64 = 0;
20346722 2270 u16 subid, i;
1ee6dd77 2271 struct mac_info *mac_control;
1da177e4
LT		 2272 struct config_param *config;
2273
2274 mac_control = &nic->mac_control;
2275 config = &nic->config;
2276
2277 /* PRC Initialization and configuration */
2278 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2279 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2280 &bar0->prc_rxd0_n[i]);
2281
2282 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2283 if (nic->rxd_mode == RXD_MODE_1)
2284 val64 |= PRC_CTRL_RC_ENABLED;
2285 else
2286 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2287 if (nic->device_type == XFRAME_II_DEVICE)
2288 val64 |= PRC_CTRL_GROUP_READS;
2289 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2290 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2291 writeq(val64, &bar0->prc_ctrl_n[i]);
2292 }
2293
da6971d8
AR		 2294 if (nic->rxd_mode == RXD_MODE_3B) {
2295 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2296 val64 = readq(&bar0->rx_pa_cfg);
2297 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2298 writeq(val64, &bar0->rx_pa_cfg);
2299 }
1da177e4 2300
926930b2
SS		 2301 if (vlan_tag_strip == 0) {
2302 val64 = readq(&bar0->rx_pa_cfg);
2303 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2304 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2305 nic->vlan_strip_flag = 0;
926930b2
SS		 2306 }
2307
20346722 2308 /*
1da177e4
LT		 2309 * Enabling MC-RLDRAM. After enabling the device, we timeout
2310 * for around 100ms, which is approximately the time required
2311 * for the device to be ready for operation.
2312 */
2313 val64 = readq(&bar0->mc_rldram_mrs);
2314 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2315 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2316 val64 = readq(&bar0->mc_rldram_mrs);
2317
20346722 2318 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2319
2320 /* Enabling ECC Protection. */
2321 val64 = readq(&bar0->adapter_control);
2322 val64 &= ~ADAPTER_ECC_EN;
2323 writeq(val64, &bar0->adapter_control);
2324
20346722
K		 2325 /*
2326 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2327 * it.
2328 */
2329 val64 = readq(&bar0->adapter_status);
19a60522 2330 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2331 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2332 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2333 (unsigned long long) val64);
2334 return FAILURE;
2335 }
2336
20346722 2337 /*
1da177e4 2338 * With some switches, link might be already up at this point.
20346722
K		 2339 * Because of this weird behavior, when we enable laser,
2340 * we may not get link. We need to handle this. We cannot
2341 * figure out which switch is misbehaving. So we are forced to
2342 * make a global change.
1da177e4
LT		 2343 */
2344
2345 /* Enabling Laser. */
2346 val64 = readq(&bar0->adapter_control);
2347 val64 |= ADAPTER_EOI_TX_ON;
2348 writeq(val64, &bar0->adapter_control);
2349
c92ca04b
AR		 2350 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2351 /*
2352 * Dont see link state interrupts initally on some switches,
2353 * so directly scheduling the link state task here.
2354 */
2355 schedule_work(&nic->set_link_task);
2356 }
1da177e4
LT		 2357 /* SXE-002: Initialize link and activity LED */
2358 subid = nic->pdev->subsystem_device;
541ae68f
K		 2359 if (((subid & 0xFF) >= 0x07) &&
2360 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2361 val64 = readq(&bar0->gpio_control);
2362 val64 |= 0x0000800000000000ULL;
2363 writeq(val64, &bar0->gpio_control);
2364 val64 = 0x0411040400000000ULL;
509a2671 2365 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2366 }
2367
1da177e4
LT		 2368 return SUCCESS;
2369}
fed5eccd
AR		 2370/**
2371 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2372 */
1ee6dd77
RB		 2373static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2374 TxD *txdlp, int get_off)
fed5eccd 2375{
1ee6dd77 2376 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2377 struct sk_buff *skb;
1ee6dd77 2378 struct TxD *txds;
fed5eccd
AR		 2379 u16 j, frg_cnt;
2380
2381 txds = txdlp;
2fda096d 2382 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
fed5eccd
AR		 2383 pci_unmap_single(nic->pdev, (dma_addr_t)
2384 txds->Buffer_Pointer, sizeof(u64),
2385 PCI_DMA_TODEVICE);
2386 txds++;
2387 }
2388
2389 skb = (struct sk_buff *) ((unsigned long)
2390 txds->Host_Control);
2391 if (!skb) {
1ee6dd77 2392 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2393 return NULL;
2394 }
2395 pci_unmap_single(nic->pdev, (dma_addr_t)
2396 txds->Buffer_Pointer,
2397 skb->len - skb->data_len,
2398 PCI_DMA_TODEVICE);
2399 frg_cnt = skb_shinfo(skb)->nr_frags;
2400 if (frg_cnt) {
2401 txds++;
2402 for (j = 0; j < frg_cnt; j++, txds++) {
2403 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2404 if (!txds->Buffer_Pointer)
2405 break;
6aa20a22 2406 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2407 txds->Buffer_Pointer,
2408 frag->size, PCI_DMA_TODEVICE);
2409 }
2410 }
1ee6dd77 2411 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2412 return(skb);
2413}
1da177e4 2414
20346722
K		 2415/**
2416 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2417 * @nic : device private variable.
20346722 2418 * Description:
1da177e4 2419 * Free all queued Tx buffers.
20346722 2420 * Return Value: void
1da177e4
LT		 2421*/
2422
2423static void free_tx_buffers(struct s2io_nic *nic)
2424{
2425 struct net_device *dev = nic->dev;
2426 struct sk_buff *skb;
1ee6dd77 2427 struct TxD *txdp;
1da177e4 2428 int i, j;
1ee6dd77 2429 struct mac_info *mac_control;
1da177e4 2430 struct config_param *config;
fed5eccd 2431 int cnt = 0;
1da177e4
LT		 2432
2433 mac_control = &nic->mac_control;
2434 config = &nic->config;
2435
2436 for (i = 0; i < config->tx_fifo_num; i++) {
2fda096d
SR		 2437 unsigned long flags;
2438 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
b35b3b49 2439 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
491976b2
SH		 2440 txdp = (struct TxD *) \
2441 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2442 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2443 if (skb) {
8a4bdbaa 2444 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2445 += skb->truesize;
fed5eccd
AR		 2446 dev_kfree_skb(skb);
2447 cnt++;
1da177e4 2448 }
1da177e4
LT		 2449 }
2450 DBG_PRINT(INTR_DBG,
2451 "%s:forcibly freeing %d skbs on FIFO%d\n",
2452 dev->name, cnt, i);
20346722
K		 2453 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2454 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2fda096d 2455 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
1da177e4
LT		 2456 }
2457}
2458
20346722
K		 2459/**
2460 * stop_nic - To stop the nic
1da177e4 2461 * @nic ; device private variable.
20346722
K		 2462 * Description:
2463 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2464 * function does. This function is called to stop the device.
2465 * Return Value:
2466 * void.
2467 */
2468
2469static void stop_nic(struct s2io_nic *nic)
2470{
1ee6dd77 2471 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2472 register u64 val64 = 0;
5d3213cc 2473 u16 interruptible;
1ee6dd77 2474 struct mac_info *mac_control;
1da177e4
LT		 2475 struct config_param *config;
2476
2477 mac_control = &nic->mac_control;
2478 config = &nic->config;
2479
2480 /* Disable all interrupts */
9caab458 2481 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2482 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2483 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2484 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2485
5d3213cc
AR		 2486 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2487 val64 = readq(&bar0->adapter_control);
2488 val64 &= ~(ADAPTER_CNTL_EN);
2489 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2490}
2491
20346722
K		 2492/**
2493 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2494 * @ring_info: per ring structure
3f78d885
SH		 2495 * @from_card_up: If this is true, we will map the buffer to get
2496 * the dma address for buf0 and buf1 to give it to the card.
2497 * Else we will sync the already mapped buffer to give it to the card.
20346722 2498 * Description:
1da177e4
LT		 2499 * The function allocates Rx side skbs and puts the physical
2500 * address of these buffers into the RxD buffer pointers, so that the NIC
2501 * can DMA the received frame into these locations.
2502 * The NIC supports 3 receive modes, viz
2503 * 1. single buffer,
2504 * 2. three buffer and
2505 * 3. Five buffer modes.
20346722
K		 2506 * Each mode defines how many fragments the received frame will be split
2507 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2508 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2509 * is split into 3 fragments. As of now only single buffer mode is
2510 * supported.
2511 * Return Value:
2512 * SUCCESS on success or an appropriate -ve value on failure.
2513 */
8d8bb39b
FT		 2514static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2515 int from_card_up)
1da177e4 2516{
1da177e4 2517 struct sk_buff *skb;
1ee6dd77 2518 struct RxD_t *rxdp;
0425b46a 2519 int off, size, block_no, block_no1;
1da177e4 2520 u32 alloc_tab = 0;
20346722 2521 u32 alloc_cnt;
20346722 2522 u64 tmp;
1ee6dd77 2523 struct buffAdd *ba;
1ee6dd77 2524 struct RxD_t *first_rxdp = NULL;
363dc367 2525 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2526 int rxd_index = 0;
6d517a27
VP		 2527 struct RxD1 *rxdp1;
2528 struct RxD3 *rxdp3;
0425b46a 2529 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2530
0425b46a 2531 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2532
0425b46a 2533 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2534 while (alloc_tab < alloc_cnt) {
0425b46a 2535 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2536
0425b46a
SH		 2537 off = ring->rx_curr_put_info.offset;
2538
2539 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2540
2541 rxd_index = off + 1;
2542 if (block_no)
2543 rxd_index += (block_no * ring->rxd_count);
da6971d8 2544
7d2e3cb7 2545 if ((block_no == block_no1) &&
0425b46a
SH		 2546 (off == ring->rx_curr_get_info.offset) &&
2547 (rxdp->Host_Control)) {
da6971d8 2548 DBG_PRINT(INTR_DBG, "%s: Get and Put",
0425b46a 2549 ring->dev->name);
1da177e4
LT		 2550 DBG_PRINT(INTR_DBG, " info equated\n");
2551 goto end;
2552 }
0425b46a
SH		 2553 if (off && (off == ring->rxd_count)) {
2554 ring->rx_curr_put_info.block_index++;
2555 if (ring->rx_curr_put_info.block_index ==
2556 ring->block_count)
2557 ring->rx_curr_put_info.block_index = 0;
2558 block_no = ring->rx_curr_put_info.block_index;
2559 off = 0;
2560 ring->rx_curr_put_info.offset = off;
2561 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2562 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2563 ring->dev->name, rxdp);
2564
1da177e4 2565 }
c9fcbf47 2566
da6971d8 2567 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
0425b46a 2568 ((ring->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2569 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2570 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2571 goto end;
2572 }
da6971d8 2573 /* calculate size of skb based on ring mode */
0425b46a 2574 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
da6971d8 2575 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2576 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2577 size += NET_IP_ALIGN;
da6971d8 2578 else
0425b46a 2579 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2580
da6971d8
AR		 2581 /* allocate skb */
2582 skb = dev_alloc_skb(size);
2583 if(!skb) {
0425b46a 2584 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
0c61ed5f 2585 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2586 if (first_rxdp) {
2587 wmb();
2588 first_rxdp->Control_1 |= RXD_OWN_XENA;
2589 }
0425b46a 2590 stats->mem_alloc_fail_cnt++;
7d2e3cb7 2591
da6971d8
AR		 2592 return -ENOMEM ;
2593 }
0425b46a
SH		 2594 stats->mem_allocated += skb->truesize;
2595
2596 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2597 /* 1 buffer mode - normal operation mode */
6d517a27 2598 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2599 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2600 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2601 rxdp1->Buffer0_ptr = pci_map_single
0425b46a 2602 (ring->pdev, skb->data, size - NET_IP_ALIGN,
863c11a9 2603 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 2604 if (pci_dma_mapping_error(nic->pdev,
2605 rxdp1->Buffer0_ptr))
491abf25
VP		 2606 goto pci_map_failed;
2607
8a4bdbaa 2608 rxdp->Control_2 =
491976b2 2609 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
0425b46a
SH		 2610 rxdp->Host_Control = (unsigned long) (skb);
2611 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2612 /*
6d517a27
VP		 2613 * 2 buffer mode -
2614 * 2 buffer mode provides 128
da6971d8 2615 * byte aligned receive buffers.
da6971d8
AR		 2616 */
2617
6d517a27 2618 rxdp3 = (struct RxD3*)rxdp;
491976b2 2619 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2620 Buffer0_ptr = rxdp3->Buffer0_ptr;
2621 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2622 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2623 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2624 rxdp3->Buffer0_ptr = Buffer0_ptr;
2625 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2626
0425b46a 2627 ba = &ring->ba[block_no][off];
da6971d8
AR		 2628 skb_reserve(skb, BUF0_LEN);
2629 tmp = (u64)(unsigned long) skb->data;
2630 tmp += ALIGN_SIZE;
2631 tmp &= ~ALIGN_SIZE;
2632 skb->data = (void *) (unsigned long)tmp;
27a884dc 2633 skb_reset_tail_pointer(skb);
da6971d8 2634
3f78d885 2635 if (from_card_up) {
6d517a27 2636 rxdp3->Buffer0_ptr =
0425b46a
SH		 2637 pci_map_single(ring->pdev, ba->ba_0,
2638 BUF0_LEN, PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 2639 if (pci_dma_mapping_error(nic->pdev,
2640 rxdp3->Buffer0_ptr))
3f78d885
SH		 2641 goto pci_map_failed;
2642 } else
0425b46a 2643 pci_dma_sync_single_for_device(ring->pdev,
6d517a27 2644 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2645 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25 2646
da6971d8 2647 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2648 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2649 /* Two buffer mode */
2650
2651 /*
6aa20a22 2652 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2653 * L4 payload
2654 */
6d517a27 2655 rxdp3->Buffer2_ptr = pci_map_single
0425b46a 2656 (ring->pdev, skb->data, ring->mtu + 4,
da6971d8
AR		 2657 PCI_DMA_FROMDEVICE);
2658
8d8bb39b
FT		 2659 if (pci_dma_mapping_error(nic->pdev,
2660 rxdp3->Buffer2_ptr))
491abf25
VP		 2661 goto pci_map_failed;
2662
3f78d885 2663 if (from_card_up) {
0425b46a
SH		 2664 rxdp3->Buffer1_ptr =
2665 pci_map_single(ring->pdev,
75c30b13
AR		 2666 ba->ba_1, BUF1_LEN,
2667 PCI_DMA_FROMDEVICE);
0425b46a 2668
8d8bb39b
FT		 2669 if (pci_dma_mapping_error(nic->pdev,
2670 rxdp3->Buffer1_ptr)) {
3f78d885
SH		 2671 pci_unmap_single
2672 (ring->pdev,
2673 (dma_addr_t)(unsigned long)
2674 skb->data,
2675 ring->mtu + 4,
2676 PCI_DMA_FROMDEVICE);
2677 goto pci_map_failed;
2678 }
75c30b13 2679 }
da6971d8
AR		 2680 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2681 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
0425b46a 2682 (ring->mtu + 4);
da6971d8 2683 }
b7b5a128 2684 rxdp->Control_2 |= s2BIT(0);
0425b46a 2685 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2686 }
303bcb4b
K		 2687 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2688 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2689 off++;
0425b46a 2690 if (off == (ring->rxd_count + 1))
da6971d8 2691 off = 0;
0425b46a 2692 ring->rx_curr_put_info.offset = off;
20346722 2693
da6971d8 2694 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2695 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2696 if (first_rxdp) {
2697 wmb();
2698 first_rxdp->Control_1 |= RXD_OWN_XENA;
2699 }
2700 first_rxdp = rxdp;
2701 }
0425b46a 2702 ring->rx_bufs_left += 1;
1da177e4
LT		 2703 alloc_tab++;
2704 }
2705
2706 end:
303bcb4b
K		 2707 /* Transfer ownership of first descriptor to adapter just before
2708 * exiting. Before that, use memory barrier so that ownership
2709 * and other fields are seen by adapter correctly.
2710 */
2711 if (first_rxdp) {
2712 wmb();
2713 first_rxdp->Control_1 |= RXD_OWN_XENA;
2714 }
2715
1da177e4 2716 return SUCCESS;
491abf25
VP		 2717pci_map_failed:
2718 stats->pci_map_fail_cnt++;
2719 stats->mem_freed += skb->truesize;
2720 dev_kfree_skb_irq(skb);
2721 return -ENOMEM;
1da177e4
LT		 2722}
2723
da6971d8
AR		 2724static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2725{
2726 struct net_device *dev = sp->dev;
2727 int j;
2728 struct sk_buff *skb;
1ee6dd77
RB		 2729 struct RxD_t *rxdp;
2730 struct mac_info *mac_control;
2731 struct buffAdd *ba;
6d517a27
VP		 2732 struct RxD1 *rxdp1;
2733 struct RxD3 *rxdp3;
da6971d8
AR		 2734
2735 mac_control = &sp->mac_control;
2736 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2737 rxdp = mac_control->rings[ring_no].
2738 rx_blocks[blk].rxds[j].virt_addr;
2739 skb = (struct sk_buff *)
2740 ((unsigned long) rxdp->Host_Control);
2741 if (!skb) {
2742 continue;
2743 }
2744 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2745 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2746 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2747 rxdp1->Buffer0_ptr,
2748 dev->mtu +
2749 HEADER_ETHERNET_II_802_3_SIZE
2750 + HEADER_802_2_SIZE +
2751 HEADER_SNAP_SIZE,
2752 PCI_DMA_FROMDEVICE);
1ee6dd77 2753 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2754 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2755 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2756 ba = &mac_control->rings[ring_no].
2757 ba[blk][j];
2758 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2759 rxdp3->Buffer0_ptr,
2760 BUF0_LEN,
da6971d8
AR		 2761 PCI_DMA_FROMDEVICE);
2762 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2763 rxdp3->Buffer1_ptr,
2764 BUF1_LEN,
da6971d8
AR		 2765 PCI_DMA_FROMDEVICE);
2766 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2767 rxdp3->Buffer2_ptr,
2768 dev->mtu + 4,
da6971d8 2769 PCI_DMA_FROMDEVICE);
1ee6dd77 2770 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2771 }
491976b2 2772 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8 2773 dev_kfree_skb(skb);
0425b46a 2774 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2775 }
2776}
2777
1da177e4 2778/**
20346722 2779 * free_rx_buffers - Frees all Rx buffers
1da177e4 2780 * @sp: device private variable.
20346722 2781 * Description:
1da177e4
LT		 2782 * This function will free all Rx buffers allocated by host.
2783 * Return Value:
2784 * NONE.
2785 */
2786
2787static void free_rx_buffers(struct s2io_nic *sp)
2788{
2789 struct net_device *dev = sp->dev;
da6971d8 2790 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2791 struct mac_info *mac_control;
1da177e4 2792 struct config_param *config;
1da177e4
LT		 2793
2794 mac_control = &sp->mac_control;
2795 config = &sp->config;
2796
2797 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2798 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2799 free_rxd_blk(sp,i,blk);
1da177e4 2800
20346722
K		 2801 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2802 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2803 mac_control->rings[i].rx_curr_put_info.offset = 0;
2804 mac_control->rings[i].rx_curr_get_info.offset = 0;
0425b46a 2805 mac_control->rings[i].rx_bufs_left = 0;
1da177e4
LT		 2806 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2807 dev->name, buf_cnt, i);
2808 }
2809}
2810
8d8bb39b 2811static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2812{
8d8bb39b 2813 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
f61e0a35
SH		 2814 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2815 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2816 }
2817 return 0;
2818}
2819
1da177e4
LT		 2820/**
2821 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2822 * @napi : pointer to the napi structure.
20346722 2823 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2824 * during one pass through the 'Poll" function.
2825 * Description:
2826 * Comes into picture only if NAPI support has been incorporated. It does
2827 * the same thing that rx_intr_handler does, but not in a interrupt context
2828 * also It will process only a given number of packets.
2829 * Return value:
2830 * 0 on success and 1 if there are No Rx packets to be processed.
2831 */
2832
f61e0a35 2833static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2834{
f61e0a35
SH		 2835 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2836 struct net_device *dev = ring->dev;
1da177e4 2837 struct config_param *config;
f61e0a35
SH		 2838 struct mac_info *mac_control;
2839 int pkts_processed = 0;
1a79d1c3
AV		 2840 u8 __iomem *addr = NULL;
2841 u8 val8 = 0;
4cf1653a 2842 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2843 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2844 int budget_org = budget;
1da177e4 2845
1da177e4 2846 config = &nic->config;
f61e0a35 2847 mac_control = &nic->mac_control;
1da177e4 2848
f61e0a35
SH		 2849 if (unlikely(!is_s2io_card_up(nic)))
2850 return 0;
1da177e4 2851
f61e0a35 2852 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2853 s2io_chk_rx_buffers(nic, ring);
1da177e4 2854
f61e0a35 2855 if (pkts_processed < budget_org) {
288379f0 2856 napi_complete(napi);
f61e0a35 2857 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2858 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2859 addr += 7 - ring->ring_no;
2860 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2861 writeb(val8, addr);
2862 val8 = readb(addr);
1da177e4 2863 }
f61e0a35
SH		 2864 return pkts_processed;
2865}
2866static int s2io_poll_inta(struct napi_struct *napi, int budget)
2867{
2868 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2869 struct ring_info *ring;
f61e0a35
SH		 2870 struct config_param *config;
2871 struct mac_info *mac_control;
2872 int pkts_processed = 0;
2873 int ring_pkts_processed, i;
2874 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2875 int budget_org = budget;
1da177e4 2876
f61e0a35
SH		 2877 config = &nic->config;
2878 mac_control = &nic->mac_control;
1da177e4 2879
f61e0a35
SH		 2880 if (unlikely(!is_s2io_card_up(nic)))
2881 return 0;
1da177e4 2882
1da177e4 2883 for (i = 0; i < config->rx_ring_num; i++) {
f61e0a35
SH		 2884 ring = &mac_control->rings[i];
2885 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2886 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2887 pkts_processed += ring_pkts_processed;
2888 budget -= ring_pkts_processed;
2889 if (budget <= 0)
1da177e4 2890 break;
1da177e4 2891 }
f61e0a35 2892 if (pkts_processed < budget_org) {
288379f0 2893 napi_complete(napi);
f61e0a35
SH		 2894 /* Re enable the Rx interrupts for the ring */
2895 writeq(0, &bar0->rx_traffic_mask);
2896 readl(&bar0->rx_traffic_mask);
2897 }
2898 return pkts_processed;
1da177e4 2899}
20346722 2900
b41477f3 2901#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2902/**
b41477f3 2903 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2904 * @dev : pointer to the device structure.
2905 * Description:
b41477f3
AR		 2906 * This function will be called by upper layer to check for events on the
2907 * interface in situations where interrupts are disabled. It is used for
2908 * specific in-kernel networking tasks, such as remote consoles and kernel
2909 * debugging over the network (example netdump in RedHat).
612eff0e 2910 */
612eff0e
BH		 2911static void s2io_netpoll(struct net_device *dev)
2912{
4cf1653a 2913 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2914 struct mac_info *mac_control;
612eff0e 2915 struct config_param *config;
1ee6dd77 2916 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2917 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2918 int i;
2919
d796fdb7
LV		 2920 if (pci_channel_offline(nic->pdev))
2921 return;
2922
612eff0e
BH		 2923 disable_irq(dev->irq);
2924
612eff0e
BH		 2925 mac_control = &nic->mac_control;
2926 config = &nic->config;
2927
612eff0e 2928 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2929 writeq(val64, &bar0->tx_traffic_int);
2930
6aa20a22 2931 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2932 * run out of skbs and will fail and eventually netpoll application such
2933 * as netdump will fail.
2934 */
2935 for (i = 0; i < config->tx_fifo_num; i++)
2936 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2937
b41477f3 2938 /* check for received packet and indicate up to network */
612eff0e 2939 for (i = 0; i < config->rx_ring_num; i++)
f61e0a35 2940 rx_intr_handler(&mac_control->rings[i], 0);
612eff0e
BH		 2941
2942 for (i = 0; i < config->rx_ring_num; i++) {
8d8bb39b
FT		 2943 if (fill_rx_buffers(nic, &mac_control->rings[i], 0) ==
2944 -ENOMEM) {
0c61ed5f
RV		 2945 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2946 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2947 break;
2948 }
2949 }
612eff0e
BH		 2950 enable_irq(dev->irq);
2951 return;
2952}
2953#endif
2954
20346722 2955/**
1da177e4 2956 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2957 * @ring_info: per ring structure.
2958 * @budget: budget for napi processing.
20346722
K		 2959 * Description:
2960 * If the interrupt is because of a received frame or if the
1da177e4 2961 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2962 * called. It picks out the RxD at which place the last Rx processing had
2963 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2964 * the offset.
2965 * Return Value:
f61e0a35 2966 * No. of napi packets processed.
1da177e4 2967 */
f61e0a35 2968static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2969{
c9fcbf47 2970 int get_block, put_block;
1ee6dd77
RB		 2971 struct rx_curr_get_info get_info, put_info;
2972 struct RxD_t *rxdp;
1da177e4 2973 struct sk_buff *skb;
f61e0a35 2974 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2975 int i;
6d517a27
VP		 2976 struct RxD1* rxdp1;
2977 struct RxD3* rxdp3;
7d3d0439 2978
20346722
K		 2979 get_info = ring_data->rx_curr_get_info;
2980 get_block = get_info.block_index;
1ee6dd77 2981 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2982 put_block = put_info.block_index;
da6971d8 2983 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2984
da6971d8 2985 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2986 /*
2987 * If your are next to put index then it's
2988 * FIFO full condition
2989 */
da6971d8
AR		 2990 if ((get_block == put_block) &&
2991 (get_info.offset + 1) == put_info.offset) {
0425b46a
SH		 2992 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2993 ring_data->dev->name);
da6971d8
AR		 2994 break;
2995 }
20346722
K		 2996 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2997 if (skb == NULL) {
2998 DBG_PRINT(ERR_DBG, "%s: The skb is ",
0425b46a 2999 ring_data->dev->name);
20346722 3000 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
f61e0a35 3001 return 0;
1da177e4 3002 }
0425b46a 3003 if (ring_data->rxd_mode == RXD_MODE_1) {
6d517a27 3004 rxdp1 = (struct RxD1*)rxdp;
0425b46a 3005 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 3006 rxdp1->Buffer0_ptr,
0425b46a 3007 ring_data->mtu +
6d517a27
VP		 3008 HEADER_ETHERNET_II_802_3_SIZE +
3009 HEADER_802_2_SIZE +
3010 HEADER_SNAP_SIZE,
3011 PCI_DMA_FROMDEVICE);
0425b46a 3012 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
6d517a27 3013 rxdp3 = (struct RxD3*)rxdp;
0425b46a 3014 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
6d517a27
VP		 3015 rxdp3->Buffer0_ptr,
3016 BUF0_LEN, PCI_DMA_FROMDEVICE);
0425b46a 3017 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 3018 rxdp3->Buffer2_ptr,
0425b46a 3019 ring_data->mtu + 4,
6d517a27 3020 PCI_DMA_FROMDEVICE);
da6971d8 3021 }
863c11a9 3022 prefetch(skb->data);
20346722
K		 3023 rx_osm_handler(ring_data, rxdp);
3024 get_info.offset++;
da6971d8
AR		 3025 ring_data->rx_curr_get_info.offset = get_info.offset;
3026 rxdp = ring_data->rx_blocks[get_block].
3027 rxds[get_info.offset].virt_addr;
0425b46a 3028 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3029 get_info.offset = 0;
da6971d8 3030 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3031 get_block++;
da6971d8
AR		 3032 if (get_block == ring_data->block_count)
3033 get_block = 0;
3034 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 3035 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3036 }
1da177e4 3037
f61e0a35
SH		 3038 if (ring_data->nic->config.napi) {
3039 budget--;
3040 napi_pkts++;
3041 if (!budget)
0425b46a
SH		 3042 break;
3043 }
20346722 3044 pkt_cnt++;
1da177e4
LT		 3045 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3046 break;
3047 }
0425b46a 3048 if (ring_data->lro) {
7d3d0439
RA		 3049 /* Clear all LRO sessions before exiting */
3050 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 3051 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3052 if (lro->in_use) {
0425b46a 3053 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3054 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3055 clear_lro_session(lro);
3056 }
3057 }
3058 }
f61e0a35 3059 return(napi_pkts);
1da177e4 3060}
20346722
K		 3061
3062/**
1da177e4
LT		 3063 * tx_intr_handler - Transmit interrupt handler
3064 * @nic : device private variable
20346722
K		 3065 * Description:
3066 * If an interrupt was raised to indicate DMA complete of the
3067 * Tx packet, this function is called. It identifies the last TxD
3068 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3069 * DMA'ed into the NICs internal memory.
3070 * Return Value:
3071 * NONE
3072 */
3073
1ee6dd77 3074static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3075{
1ee6dd77 3076 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3077 struct tx_curr_get_info get_info, put_info;
3a3d5756 3078 struct sk_buff *skb = NULL;
1ee6dd77 3079 struct TxD *txdlp;
3a3d5756 3080 int pkt_cnt = 0;
2fda096d 3081 unsigned long flags = 0;
f9046eb3 3082 u8 err_mask;
1da177e4 3083
2fda096d
SR		 3084 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3085 return;
3086
20346722 3087 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 3088 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3089 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 3090 list_virt_addr;
3091 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3092 (get_info.offset != put_info.offset) &&
3093 (txdlp->Host_Control)) {
3094 /* Check for TxD errors */
3095 if (txdlp->Control_1 & TXD_T_CODE) {
3096 unsigned long long err;
3097 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 3098 if (err & 0x1) {
3099 nic->mac_control.stats_info->sw_stat.
3100 parity_err_cnt++;
3101 }
491976b2
SH		 3102
3103 /* update t_code statistics */
f9046eb3
OH		 3104 err_mask = err >> 48;
3105 switch(err_mask) {
491976b2
SH		 3106 case 2:
3107 nic->mac_control.stats_info->sw_stat.
3108 tx_buf_abort_cnt++;
3109 break;
3110
3111 case 3:
3112 nic->mac_control.stats_info->sw_stat.
3113 tx_desc_abort_cnt++;
3114 break;
3115
3116 case 7:
3117 nic->mac_control.stats_info->sw_stat.
3118 tx_parity_err_cnt++;
3119 break;
3120
3121 case 10:
3122 nic->mac_control.stats_info->sw_stat.
3123 tx_link_loss_cnt++;
3124 break;
3125
3126 case 15:
3127 nic->mac_control.stats_info->sw_stat.
3128 tx_list_proc_err_cnt++;
3129 break;
3130 }
20346722 3131 }
1da177e4 3132
fed5eccd 3133 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3134 if (skb == NULL) {
2fda096d 3135 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
20346722 3136 DBG_PRINT(ERR_DBG, "%s: Null skb ",
b39d66a8 3137 __func__);
20346722
K		 3138 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3139 return;
3140 }
3a3d5756 3141 pkt_cnt++;
20346722 3142
20346722 3143 /* Updating the statistics block */
dc56e634 3144 nic->dev->stats.tx_bytes += skb->len;
491976b2 3145 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 3146 dev_kfree_skb_irq(skb);
3147
3148 get_info.offset++;
863c11a9
AR		 3149 if (get_info.offset == get_info.fifo_len + 1)
3150 get_info.offset = 0;
1ee6dd77 3151 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 3152 [get_info.offset].list_virt_addr;
3153 fifo_data->tx_curr_get_info.offset =
3154 get_info.offset;
1da177e4
LT		 3155 }
3156
3a3d5756 3157 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3158
3159 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3160}
3161
bd1034f0
AR		 3162/**
3163 * s2io_mdio_write - Function to write in to MDIO registers
3164 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3165 * @addr : address value
3166 * @value : data value
3167 * @dev : pointer to net_device structure
3168 * Description:
3169 * This function is used to write values to the MDIO registers
3170 * NONE
3171 */
3172static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3173{
3174 u64 val64 = 0x0;
4cf1653a 3175 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3176 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3177
3178 //address transaction
3179 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3180 | MDIO_MMD_DEV_ADDR(mmd_type)
3181 | MDIO_MMS_PRT_ADDR(0x0);
3182 writeq(val64, &bar0->mdio_control);
3183 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3184 writeq(val64, &bar0->mdio_control);
3185 udelay(100);
3186
3187 //Data transaction
3188 val64 = 0x0;
3189 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3190 | MDIO_MMD_DEV_ADDR(mmd_type)
3191 | MDIO_MMS_PRT_ADDR(0x0)
3192 | MDIO_MDIO_DATA(value)
3193 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3194 writeq(val64, &bar0->mdio_control);
3195 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3196 writeq(val64, &bar0->mdio_control);
3197 udelay(100);
3198
3199 val64 = 0x0;
3200 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3201 | MDIO_MMD_DEV_ADDR(mmd_type)
3202 | MDIO_MMS_PRT_ADDR(0x0)
3203 | MDIO_OP(MDIO_OP_READ_TRANS);
3204 writeq(val64, &bar0->mdio_control);
3205 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3206 writeq(val64, &bar0->mdio_control);
3207 udelay(100);
3208
3209}
3210
3211/**
3212 * s2io_mdio_read - Function to write in to MDIO registers
3213 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3214 * @addr : address value
3215 * @dev : pointer to net_device structure
3216 * Description:
3217 * This function is used to read values to the MDIO registers
3218 * NONE
3219 */
3220static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3221{
3222 u64 val64 = 0x0;
3223 u64 rval64 = 0x0;
4cf1653a 3224 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3225 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3226
3227 /* address transaction */
3228 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3229 | MDIO_MMD_DEV_ADDR(mmd_type)
3230 | MDIO_MMS_PRT_ADDR(0x0);
3231 writeq(val64, &bar0->mdio_control);
3232 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3233 writeq(val64, &bar0->mdio_control);
3234 udelay(100);
3235
3236 /* Data transaction */
3237 val64 = 0x0;
3238 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3239 | MDIO_MMD_DEV_ADDR(mmd_type)
3240 | MDIO_MMS_PRT_ADDR(0x0)
3241 | MDIO_OP(MDIO_OP_READ_TRANS);
3242 writeq(val64, &bar0->mdio_control);
3243 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3244 writeq(val64, &bar0->mdio_control);
3245 udelay(100);
3246
3247 /* Read the value from regs */
3248 rval64 = readq(&bar0->mdio_control);
3249 rval64 = rval64 & 0xFFFF0000;
3250 rval64 = rval64 >> 16;
3251 return rval64;
3252}
3253/**
3254 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3255 * @counter : couter value to be updated
3256 * @flag : flag to indicate the status
3257 * @type : counter type
3258 * Description:
3259 * This function is to check the status of the xpak counters value
3260 * NONE
3261 */
3262
3263static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3264{
3265 u64 mask = 0x3;
3266 u64 val64;
3267 int i;
3268 for(i = 0; i <index; i++)
3269 mask = mask << 0x2;
3270
3271 if(flag > 0)
3272 {
3273 *counter = *counter + 1;
3274 val64 = *regs_stat & mask;
3275 val64 = val64 >> (index * 0x2);
3276 val64 = val64 + 1;
3277 if(val64 == 3)
3278 {
3279 switch(type)
3280 {
3281 case 1:
3282 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3283 "service. Excessive temperatures may "
3284 "result in premature transceiver "
3285 "failure \n");
3286 break;
3287 case 2:
3288 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3289 "service Excessive bias currents may "
3290 "indicate imminent laser diode "
3291 "failure \n");
3292 break;
3293 case 3:
3294 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3295 "service Excessive laser output "
3296 "power may saturate far-end "
3297 "receiver\n");
3298 break;
3299 default:
3300 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3301 "type \n");
3302 }
3303 val64 = 0x0;
3304 }
3305 val64 = val64 << (index * 0x2);
3306 *regs_stat = (*regs_stat & (~mask)) | (val64);
3307
3308 } else {
3309 *regs_stat = *regs_stat & (~mask);
3310 }
3311}
3312
3313/**
3314 * s2io_updt_xpak_counter - Function to update the xpak counters
3315 * @dev : pointer to net_device struct
3316 * Description:
3317 * This function is to upate the status of the xpak counters value
3318 * NONE
3319 */
3320static void s2io_updt_xpak_counter(struct net_device *dev)
3321{
3322 u16 flag = 0x0;
3323 u16 type = 0x0;
3324 u16 val16 = 0x0;
3325 u64 val64 = 0x0;
3326 u64 addr = 0x0;
3327
4cf1653a 3328 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3329 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3330
3331 /* Check the communication with the MDIO slave */
40239396 3332 addr = MDIO_CTRL1;
bd1034f0 3333 val64 = 0x0;
40239396 3334 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3335 if((val64 == 0xFFFF) || (val64 == 0x0000))
3336 {
3337 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3338 "Returned %llx\n", (unsigned long long)val64);
3339 return;
3340 }
3341
40239396
BH		 3342 /* Check for the expected value of control reg 1 */
3343 if(val64 != MDIO_CTRL1_SPEED10G)
bd1034f0
AR		 3344 {
3345 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
40239396
BH		 3346 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x%x\n",
3347 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3348 return;
3349 }
3350
3351 /* Loading the DOM register to MDIO register */
3352 addr = 0xA100;
40239396
BH		 3353 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3354 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3355
3356 /* Reading the Alarm flags */
3357 addr = 0xA070;
3358 val64 = 0x0;
40239396 3359 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3360
3361 flag = CHECKBIT(val64, 0x7);
3362 type = 1;
3363 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3364 &stat_info->xpak_stat.xpak_regs_stat,
3365 0x0, flag, type);
3366
3367 if(CHECKBIT(val64, 0x6))
3368 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3369
3370 flag = CHECKBIT(val64, 0x3);
3371 type = 2;
3372 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3373 &stat_info->xpak_stat.xpak_regs_stat,
3374 0x2, flag, type);
3375
3376 if(CHECKBIT(val64, 0x2))
3377 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3378
3379 flag = CHECKBIT(val64, 0x1);
3380 type = 3;
3381 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3382 &stat_info->xpak_stat.xpak_regs_stat,
3383 0x4, flag, type);
3384
3385 if(CHECKBIT(val64, 0x0))
3386 stat_info->xpak_stat.alarm_laser_output_power_low++;
3387
3388 /* Reading the Warning flags */
3389 addr = 0xA074;
3390 val64 = 0x0;
40239396 3391 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3392
3393 if(CHECKBIT(val64, 0x7))
3394 stat_info->xpak_stat.warn_transceiver_temp_high++;
3395
3396 if(CHECKBIT(val64, 0x6))
3397 stat_info->xpak_stat.warn_transceiver_temp_low++;
3398
3399 if(CHECKBIT(val64, 0x3))
3400 stat_info->xpak_stat.warn_laser_bias_current_high++;
3401
3402 if(CHECKBIT(val64, 0x2))
3403 stat_info->xpak_stat.warn_laser_bias_current_low++;
3404
3405 if(CHECKBIT(val64, 0x1))
3406 stat_info->xpak_stat.warn_laser_output_power_high++;
3407
3408 if(CHECKBIT(val64, 0x0))
3409 stat_info->xpak_stat.warn_laser_output_power_low++;
3410}
3411
20346722 3412/**
1da177e4 3413 * wait_for_cmd_complete - waits for a command to complete.
20346722 3414 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3415 * s2io_nic structure.
20346722
K		 3416 * Description: Function that waits for a command to Write into RMAC
3417 * ADDR DATA registers to be completed and returns either success or
3418 * error depending on whether the command was complete or not.
1da177e4
LT		 3419 * Return value:
3420 * SUCCESS on success and FAILURE on failure.
3421 */
3422
9fc93a41
SS		 3423static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3424 int bit_state)
1da177e4 3425{
9fc93a41 3426 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3427 u64 val64;
3428
9fc93a41
SS		 3429 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3430 return FAILURE;
3431
3432 do {
c92ca04b 3433 val64 = readq(addr);
9fc93a41
SS		 3434 if (bit_state == S2IO_BIT_RESET) {
3435 if (!(val64 & busy_bit)) {
3436 ret = SUCCESS;
3437 break;
3438 }
3439 } else {
3440 if (!(val64 & busy_bit)) {
3441 ret = SUCCESS;
3442 break;
3443 }
1da177e4 3444 }
c92ca04b
AR		 3445
3446 if(in_interrupt())
9fc93a41 3447 mdelay(delay);
c92ca04b 3448 else
9fc93a41 3449 msleep(delay);
c92ca04b 3450
9fc93a41
SS		 3451 if (++cnt >= 10)
3452 delay = 50;
3453 } while (cnt < 20);
1da177e4
LT		 3454 return ret;
3455}
19a60522
SS		 3456/*
3457 * check_pci_device_id - Checks if the device id is supported
3458 * @id : device id
3459 * Description: Function to check if the pci device id is supported by driver.
3460 * Return value: Actual device id if supported else PCI_ANY_ID
3461 */
3462static u16 check_pci_device_id(u16 id)
3463{
3464 switch (id) {
3465 case PCI_DEVICE_ID_HERC_WIN:
3466 case PCI_DEVICE_ID_HERC_UNI:
3467 return XFRAME_II_DEVICE;
3468 case PCI_DEVICE_ID_S2IO_UNI:
3469 case PCI_DEVICE_ID_S2IO_WIN:
3470 return XFRAME_I_DEVICE;
3471 default:
3472 return PCI_ANY_ID;
3473 }
3474}
1da177e4 3475
20346722
K		 3476/**
3477 * s2io_reset - Resets the card.
1da177e4
LT		 3478 * @sp : private member of the device structure.
3479 * Description: Function to Reset the card. This function then also
20346722 3480 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3481 * the card reset also resets the configuration space.
3482 * Return value:
3483 * void.
3484 */
3485
1ee6dd77 3486static void s2io_reset(struct s2io_nic * sp)
1da177e4 3487{
1ee6dd77 3488 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3489 u64 val64;
5e25b9dd 3490 u16 subid, pci_cmd;
19a60522
SS		 3491 int i;
3492 u16 val16;
491976b2
SH		 3493 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3494 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3495
19a60522 3496 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
b39d66a8 3497 __func__, sp->dev->name);
1da177e4 3498
0b1f7ebe 3499 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3500 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3501
1da177e4
LT		 3502 val64 = SW_RESET_ALL;
3503 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3504 if (strstr(sp->product_name, "CX4")) {
3505 msleep(750);
3506 }
19a60522
SS		 3507 msleep(250);
3508 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3509
19a60522
SS		 3510 /* Restore the PCI state saved during initialization. */
3511 pci_restore_state(sp->pdev);
3512 pci_read_config_word(sp->pdev, 0x2, &val16);
3513 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3514 break;
3515 msleep(200);
3516 }
1da177e4 3517
19a60522 3518 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
b39d66a8 3519 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __func__);
19a60522
SS		 3520 }
3521
3522 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3523
3524 s2io_init_pci(sp);
1da177e4 3525
20346722
K		 3526 /* Set swapper to enable I/O register access */
3527 s2io_set_swapper(sp);
3528
faa4f796
SH		 3529 /* restore mac_addr entries */
3530 do_s2io_restore_unicast_mc(sp);
3531
cc6e7c44
RA		 3532 /* Restore the MSIX table entries from local variables */
3533 restore_xmsi_data(sp);
3534
5e25b9dd 3535 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3536 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3537 /* Clear "detected parity error" bit */
303bcb4b 3538 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3539
303bcb4b
K		 3540 /* Clearing PCIX Ecc status register */
3541 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3542
303bcb4b 3543 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3544 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3545 }
5e25b9dd 3546
20346722
K		 3547 /* Reset device statistics maintained by OS */
3548 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3549
491976b2
SH		 3550 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3551 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3552 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3553 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3554 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3555 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3556 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3557 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3558 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3559 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3560 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3561 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3562 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3563 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3564 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3565 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3566 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3567 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3568 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3569
1da177e4
LT		 3570 /* SXE-002: Configure link and activity LED to turn it off */
3571 subid = sp->pdev->subsystem_device;
541ae68f
K		 3572 if (((subid & 0xFF) >= 0x07) &&
3573 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3574 val64 = readq(&bar0->gpio_control);
3575 val64 |= 0x0000800000000000ULL;
3576 writeq(val64, &bar0->gpio_control);
3577 val64 = 0x0411040400000000ULL;
509a2671 3578 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3579 }
3580
541ae68f
K		 3581 /*
3582 * Clear spurious ECC interrupts that would have occured on
3583 * XFRAME II cards after reset.
3584 */
3585 if (sp->device_type == XFRAME_II_DEVICE) {
3586 val64 = readq(&bar0->pcc_err_reg);
3587 writeq(val64, &bar0->pcc_err_reg);
3588 }
3589
f957bcf0 3590 sp->device_enabled_once = false;
1da177e4
LT		 3591}
3592
3593/**
20346722
K		 3594 * s2io_set_swapper - to set the swapper controle on the card
3595 * @sp : private member of the device structure,
1da177e4 3596 * pointer to the s2io_nic structure.
20346722 3597 * Description: Function to set the swapper control on the card
1da177e4
LT		 3598 * correctly depending on the 'endianness' of the system.
3599 * Return value:
3600 * SUCCESS on success and FAILURE on failure.
3601 */
3602
1ee6dd77 3603static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3604{
3605 struct net_device *dev = sp->dev;
1ee6dd77 3606 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3607 u64 val64, valt, valr;
3608
20346722 3609 /*
1da177e4
LT		 3610 * Set proper endian settings and verify the same by reading
3611 * the PIF Feed-back register.
3612 */
3613
3614 val64 = readq(&bar0->pif_rd_swapper_fb);
3615 if (val64 != 0x0123456789ABCDEFULL) {
3616 int i = 0;
3617 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3618 0x8100008181000081ULL, /* FE=1, SE=0 */
3619 0x4200004242000042ULL, /* FE=0, SE=1 */
3620 0}; /* FE=0, SE=0 */
3621
3622 while(i<4) {
3623 writeq(value[i], &bar0->swapper_ctrl);
3624 val64 = readq(&bar0->pif_rd_swapper_fb);
3625 if (val64 == 0x0123456789ABCDEFULL)
3626 break;
3627 i++;
3628 }
3629 if (i == 4) {
3630 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3631 dev->name);
3632 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3633 (unsigned long long) val64);
3634 return FAILURE;
3635 }
3636 valr = value[i];
3637 } else {
3638 valr = readq(&bar0->swapper_ctrl);
3639 }
3640
3641 valt = 0x0123456789ABCDEFULL;
3642 writeq(valt, &bar0->xmsi_address);
3643 val64 = readq(&bar0->xmsi_address);
3644
3645 if(val64 != valt) {
3646 int i = 0;
3647 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3648 0x0081810000818100ULL, /* FE=1, SE=0 */
3649 0x0042420000424200ULL, /* FE=0, SE=1 */
3650 0}; /* FE=0, SE=0 */
3651
3652 while(i<4) {
3653 writeq((value[i] | valr), &bar0->swapper_ctrl);
3654 writeq(valt, &bar0->xmsi_address);
3655 val64 = readq(&bar0->xmsi_address);
3656 if(val64 == valt)
3657 break;
3658 i++;
3659 }
3660 if(i == 4) {
20346722 3661 unsigned long long x = val64;
1da177e4 3662 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3663 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3664 return FAILURE;
3665 }
3666 }
3667 val64 = readq(&bar0->swapper_ctrl);
3668 val64 &= 0xFFFF000000000000ULL;
3669
3670#ifdef __BIG_ENDIAN
20346722
K		 3671 /*
3672 * The device by default set to a big endian format, so a
1da177e4
LT		 3673 * big endian driver need not set anything.
3674 */
3675 val64 |= (SWAPPER_CTRL_TXP_FE |
3676 SWAPPER_CTRL_TXP_SE |
3677 SWAPPER_CTRL_TXD_R_FE |
3678 SWAPPER_CTRL_TXD_W_FE |
3679 SWAPPER_CTRL_TXF_R_FE |
3680 SWAPPER_CTRL_RXD_R_FE |
3681 SWAPPER_CTRL_RXD_W_FE |
3682 SWAPPER_CTRL_RXF_W_FE |
3683 SWAPPER_CTRL_XMSI_FE |
1da177e4 3684 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3685 if (sp->config.intr_type == INTA)
cc6e7c44 3686 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3687 writeq(val64, &bar0->swapper_ctrl);
3688#else
20346722 3689 /*
1da177e4 3690 * Initially we enable all bits to make it accessible by the
20346722 3691 * driver, then we selectively enable only those bits that
1da177e4
LT		 3692 * we want to set.
3693 */
3694 val64 |= (SWAPPER_CTRL_TXP_FE |
3695 SWAPPER_CTRL_TXP_SE |
3696 SWAPPER_CTRL_TXD_R_FE |
3697 SWAPPER_CTRL_TXD_R_SE |
3698 SWAPPER_CTRL_TXD_W_FE |
3699 SWAPPER_CTRL_TXD_W_SE |
3700 SWAPPER_CTRL_TXF_R_FE |
3701 SWAPPER_CTRL_RXD_R_FE |
3702 SWAPPER_CTRL_RXD_R_SE |
3703 SWAPPER_CTRL_RXD_W_FE |
3704 SWAPPER_CTRL_RXD_W_SE |
3705 SWAPPER_CTRL_RXF_W_FE |
3706 SWAPPER_CTRL_XMSI_FE |
1da177e4 3707 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3708 if (sp->config.intr_type == INTA)
cc6e7c44 3709 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3710 writeq(val64, &bar0->swapper_ctrl);
3711#endif
3712 val64 = readq(&bar0->swapper_ctrl);
3713
20346722
K		 3714 /*
3715 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3716 * feedback register.
3717 */
3718 val64 = readq(&bar0->pif_rd_swapper_fb);
3719 if (val64 != 0x0123456789ABCDEFULL) {
3720 /* Endian settings are incorrect, calls for another dekko. */
3721 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3722 dev->name);
3723 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3724 (unsigned long long) val64);
3725 return FAILURE;
3726 }
3727
3728 return SUCCESS;
3729}
3730
1ee6dd77 3731static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3732{
1ee6dd77 3733 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3734 u64 val64;
3735 int ret = 0, cnt = 0;
3736
3737 do {
3738 val64 = readq(&bar0->xmsi_access);
b7b5a128 3739 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3740 break;
3741 mdelay(1);
3742 cnt++;
3743 } while(cnt < 5);
3744 if (cnt == 5) {
3745 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3746 ret = 1;
3747 }
3748
3749 return ret;
3750}
3751
1ee6dd77 3752static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3753{
1ee6dd77 3754 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3755 u64 val64;
f61e0a35
SH		 3756 int i, msix_index;
3757
3758
3759 if (nic->device_type == XFRAME_I_DEVICE)
3760 return;
cc6e7c44 3761
75c30b13 3762 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
f61e0a35 3763 msix_index = (i) ? ((i-1) * 8 + 1): 0;
cc6e7c44
RA		 3764 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3765 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3766 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3767 writeq(val64, &bar0->xmsi_access);
f61e0a35 3768 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3769 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3770 continue;
3771 }
3772 }
3773}
3774
1ee6dd77 3775static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3776{
1ee6dd77 3777 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3778 u64 val64, addr, data;
f61e0a35
SH		 3779 int i, msix_index;
3780
3781 if (nic->device_type == XFRAME_I_DEVICE)
3782 return;
cc6e7c44
RA		 3783
3784 /* Store and display */
75c30b13 3785 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
f61e0a35
SH		 3786 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3787 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3788 writeq(val64, &bar0->xmsi_access);
f61e0a35 3789 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3790 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3791 continue;
3792 }
3793 addr = readq(&bar0->xmsi_address);
3794 data = readq(&bar0->xmsi_data);
3795 if (addr && data) {
3796 nic->msix_info[i].addr = addr;
3797 nic->msix_info[i].data = data;
3798 }
3799 }
3800}
3801
1ee6dd77 3802static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3803{
1ee6dd77 3804 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3805 u64 rx_mat;
cc6e7c44
RA		 3806 u16 msi_control; /* Temp variable */
3807 int ret, i, j, msix_indx = 1;
3808
f61e0a35 3809 nic->entries = kmalloc(nic->num_entries * sizeof(struct msix_entry),
cc6e7c44 3810 GFP_KERNEL);
bd684e43 3811 if (!nic->entries) {
491976b2 3812 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
b39d66a8 3813 __func__);
c53d4945 3814 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3815 return -ENOMEM;
3816 }
8a4bdbaa 3817 nic->mac_control.stats_info->sw_stat.mem_allocated
f61e0a35
SH		 3818 += (nic->num_entries * sizeof(struct msix_entry));
3819
3820 memset(nic->entries, 0, nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3821
3822 nic->s2io_entries =
f61e0a35 3823 kmalloc(nic->num_entries * sizeof(struct s2io_msix_entry),
cc6e7c44 3824 GFP_KERNEL);
bd684e43 3825 if (!nic->s2io_entries) {
8a4bdbaa 3826 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
b39d66a8 3827 __func__);
c53d4945 3828 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3829 kfree(nic->entries);
8a4bdbaa 3830 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3831 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3832 return -ENOMEM;
3833 }
8a4bdbaa 3834 nic->mac_control.stats_info->sw_stat.mem_allocated
f61e0a35
SH		 3835 += (nic->num_entries * sizeof(struct s2io_msix_entry));
3836 memset(nic->s2io_entries, 0,
3837 nic->num_entries * sizeof(struct s2io_msix_entry));
cc6e7c44 3838
ac731ab6
SH		 3839 nic->entries[0].entry = 0;
3840 nic->s2io_entries[0].entry = 0;
3841 nic->s2io_entries[0].in_use = MSIX_FLG;
3842 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3843 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3844
f61e0a35
SH		 3845 for (i = 1; i < nic->num_entries; i++) {
3846 nic->entries[i].entry = ((i - 1) * 8) + 1;
3847 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3848 nic->s2io_entries[i].arg = NULL;
3849 nic->s2io_entries[i].in_use = 0;
3850 }
3851
8a4bdbaa 3852 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3853 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3854 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3855 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3856 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3857 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3858 msix_indx += 8;
cc6e7c44 3859 }
8a4bdbaa 3860 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3861 readq(&bar0->rx_mat);
cc6e7c44 3862
f61e0a35 3863 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3864 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3865 if (ret) {
073a2436 3866 DBG_PRINT(ERR_DBG, "s2io: Enabling MSI-X failed\n");
cc6e7c44 3867 kfree(nic->entries);
8a4bdbaa 3868 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3869 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44 3870 kfree(nic->s2io_entries);
8a4bdbaa 3871 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3872 += (nic->num_entries * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3873 nic->entries = NULL;
3874 nic->s2io_entries = NULL;
3875 return -ENOMEM;
3876 }
3877
3878 /*
3879 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3880 * in the herc NIC. (Temp change, needs to be removed later)
3881 */
3882 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3883 msi_control |= 0x1; /* Enable MSI */
3884 pci_write_config_word(nic->pdev, 0x42, msi_control);
3885
3886 return 0;
3887}
3888
8abc4d5b 3889/* Handle software interrupt used during MSI(X) test */
33390a70 3890static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3891{
3892 struct s2io_nic *sp = dev_id;
3893
3894 sp->msi_detected = 1;
3895 wake_up(&sp->msi_wait);
3896
3897 return IRQ_HANDLED;
3898}
3899
3900/* Test interrupt path by forcing a a software IRQ */
33390a70 3901static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3902{
3903 struct pci_dev *pdev = sp->pdev;
3904 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3905 int err;
3906 u64 val64, saved64;
3907
3908 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3909 sp->name, sp);
3910 if (err) {
3911 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3912 sp->dev->name, pci_name(pdev), pdev->irq);
3913 return err;
3914 }
3915
3916 init_waitqueue_head (&sp->msi_wait);
3917 sp->msi_detected = 0;
3918
3919 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3920 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3921 val64 |= SCHED_INT_CTRL_TIMER_EN;
3922 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3923 writeq(val64, &bar0->scheduled_int_ctrl);
3924
3925 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3926
3927 if (!sp->msi_detected) {
3928 /* MSI(X) test failed, go back to INTx mode */
2450022a 3929 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
8abc4d5b
SS		 3930 "using MSI(X) during test\n", sp->dev->name,
3931 pci_name(pdev));
3932
3933 err = -EOPNOTSUPP;
3934 }
3935
3936 free_irq(sp->entries[1].vector, sp);
3937
3938 writeq(saved64, &bar0->scheduled_int_ctrl);
3939
3940 return err;
3941}
18b2b7bd
SH		 3942
3943static void remove_msix_isr(struct s2io_nic *sp)
3944{
3945 int i;
3946 u16 msi_control;
3947
f61e0a35 3948 for (i = 0; i < sp->num_entries; i++) {
18b2b7bd
SH		 3949 if (sp->s2io_entries[i].in_use ==
3950 MSIX_REGISTERED_SUCCESS) {
3951 int vector = sp->entries[i].vector;
3952 void *arg = sp->s2io_entries[i].arg;
3953 free_irq(vector, arg);
3954 }
3955 }
3956
3957 kfree(sp->entries);
3958 kfree(sp->s2io_entries);
3959 sp->entries = NULL;
3960 sp->s2io_entries = NULL;
3961
3962 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3963 msi_control &= 0xFFFE; /* Disable MSI */
3964 pci_write_config_word(sp->pdev, 0x42, msi_control);
3965
3966 pci_disable_msix(sp->pdev);
3967}
3968
3969static void remove_inta_isr(struct s2io_nic *sp)
3970{
3971 struct net_device *dev = sp->dev;
3972
3973 free_irq(sp->pdev->irq, dev);
3974}
3975
1da177e4
LT		 3976/* ********************************************************* *
3977 * Functions defined below concern the OS part of the driver *
3978 * ********************************************************* */
3979
20346722 3980/**
1da177e4
LT		 3981 * s2io_open - open entry point of the driver
3982 * @dev : pointer to the device structure.
3983 * Description:
3984 * This function is the open entry point of the driver. It mainly calls a
3985 * function to allocate Rx buffers and inserts them into the buffer
20346722 3986 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3987 * Return value:
3988 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3989 * file on failure.
3990 */
3991
ac1f60db 3992static int s2io_open(struct net_device *dev)
1da177e4 3993{
4cf1653a 3994 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 3995 int err = 0;
3996
20346722
K		 3997 /*
3998 * Make sure you have link off by default every time
1da177e4
LT		 3999 * Nic is initialized
4000 */
4001 netif_carrier_off(dev);
0b1f7ebe 4002 sp->last_link_state = 0;
1da177e4
LT		 4003
4004 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 4005 err = s2io_card_up(sp);
4006 if (err) {
1da177e4
LT		 4007 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4008 dev->name);
e6a8fee2 4009 goto hw_init_failed;
1da177e4
LT		 4010 }
4011
2fd37688 4012 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4013 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4014 s2io_card_down(sp);
20346722 4015 err = -ENODEV;
e6a8fee2 4016 goto hw_init_failed;
1da177e4 4017 }
3a3d5756 4018 s2io_start_all_tx_queue(sp);
1da177e4 4019 return 0;
20346722 4020
20346722 4021hw_init_failed:
eaae7f72 4022 if (sp->config.intr_type == MSI_X) {
491976b2 4023 if (sp->entries) {
cc6e7c44 4024 kfree(sp->entries);
8a4bdbaa 4025 sp->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 4026 += (sp->num_entries * sizeof(struct msix_entry));
491976b2
SH		 4027 }
4028 if (sp->s2io_entries) {
cc6e7c44 4029 kfree(sp->s2io_entries);
8a4bdbaa 4030 sp->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 4031 += (sp->num_entries * sizeof(struct s2io_msix_entry));
491976b2 4032 }
cc6e7c44 4033 }
20346722 4034 return err;
1da177e4
LT		 4035}
4036
4037/**
4038 * s2io_close -close entry point of the driver
4039 * @dev : device pointer.
4040 * Description:
4041 * This is the stop entry point of the driver. It needs to undo exactly
4042 * whatever was done by the open entry point,thus it's usually referred to
4043 * as the close function.Among other things this function mainly stops the
4044 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4045 * Return value:
4046 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4047 * file on failure.
4048 */
4049
ac1f60db 4050static int s2io_close(struct net_device *dev)
1da177e4 4051{
4cf1653a 4052 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4053 struct config_param *config = &sp->config;
4054 u64 tmp64;
4055 int offset;
cc6e7c44 4056
9f74ffde
SH		 4057 /* Return if the device is already closed *
4058 * Can happen when s2io_card_up failed in change_mtu *
4059 */
4060 if (!is_s2io_card_up(sp))
4061 return 0;
4062
3a3d5756 4063 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4064 /* delete all populated mac entries */
4065 for (offset = 1; offset < config->max_mc_addr; offset++) {
4066 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4067 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4068 do_s2io_delete_unicast_mc(sp, tmp64);
4069 }
4070
e6a8fee2 4071 s2io_card_down(sp);
cc6e7c44 4072
1da177e4
LT		 4073 return 0;
4074}
4075
4076/**
4077 * s2io_xmit - Tx entry point of te driver
4078 * @skb : the socket buffer containing the Tx data.
4079 * @dev : device pointer.
4080 * Description :
4081 * This function is the Tx entry point of the driver. S2IO NIC supports
4082 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4083 * NOTE: when device cant queue the pkt,just the trans_start variable will
4084 * not be upadted.
4085 * Return value:
4086 * 0 on success & 1 on failure.
4087 */
4088
ac1f60db 4089static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4090{
4cf1653a 4091 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4092 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4093 register u64 val64;
1ee6dd77
RB		 4094 struct TxD *txdp;
4095 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4096 unsigned long flags = 0;
be3a6b02 4097 u16 vlan_tag = 0;
2fda096d 4098 struct fifo_info *fifo = NULL;
1ee6dd77 4099 struct mac_info *mac_control;
1da177e4 4100 struct config_param *config;
6cfc482b 4101 int do_spin_lock = 1;
75c30b13 4102 int offload_type;
6cfc482b 4103 int enable_per_list_interrupt = 0;
491abf25 4104 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4105
4106 mac_control = &sp->mac_control;
4107 config = &sp->config;
4108
20346722 4109 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4110
4111 if (unlikely(skb->len <= 0)) {
4112 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4113 dev_kfree_skb_any(skb);
6ed10654 4114 return NETDEV_TX_OK;
2fda096d 4115 }
491976b2 4116
92b84437 4117 if (!is_s2io_card_up(sp)) {
20346722 4118 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4119 dev->name);
20346722 4120 dev_kfree_skb(skb);
6ed10654 4121 return NETDEV_TX_OK;
1da177e4
LT		 4122 }
4123
4124 queue = 0;
3a3d5756 4125 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4126 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4127 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4128 if (skb->protocol == htons(ETH_P_IP)) {
4129 struct iphdr *ip;
4130 struct tcphdr *th;
4131 ip = ip_hdr(skb);
4132
4133 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4134 th = (struct tcphdr *)(((unsigned char *)ip) +
4135 ip->ihl*4);
4136
4137 if (ip->protocol == IPPROTO_TCP) {
4138 queue_len = sp->total_tcp_fifos;
4139 queue = (ntohs(th->source) +
4140 ntohs(th->dest)) &
4141 sp->fifo_selector[queue_len - 1];
4142 if (queue >= queue_len)
4143 queue = queue_len - 1;
4144 } else if (ip->protocol == IPPROTO_UDP) {
4145 queue_len = sp->total_udp_fifos;
4146 queue = (ntohs(th->source) +
4147 ntohs(th->dest)) &
4148 sp->fifo_selector[queue_len - 1];
4149 if (queue >= queue_len)
4150 queue = queue_len - 1;
4151 queue += sp->udp_fifo_idx;
4152 if (skb->len > 1024)
4153 enable_per_list_interrupt = 1;
4154 do_spin_lock = 0;
4155 }
4156 }
4157 }
4158 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4159 /* get fifo number based on skb->priority value */
4160 queue = config->fifo_mapping
4161 [skb->priority & (MAX_TX_FIFOS - 1)];
4162 fifo = &mac_control->fifos[queue];
3a3d5756 4163
6cfc482b
SH		 4164 if (do_spin_lock)
4165 spin_lock_irqsave(&fifo->tx_lock, flags);
4166 else {
4167 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4168 return NETDEV_TX_LOCKED;
4169 }
be3a6b02 4170
3a3d5756
SH		 4171 if (sp->config.multiq) {
4172 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4173 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4174 return NETDEV_TX_BUSY;
4175 }
b19fa1fa 4176 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4177 if (netif_queue_stopped(dev)) {
4178 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4179 return NETDEV_TX_BUSY;
4180 }
4181 }
4182
2fda096d
SR		 4183 put_off = (u16) fifo->tx_curr_put_info.offset;
4184 get_off = (u16) fifo->tx_curr_get_info.offset;
4185 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
20346722 4186
2fda096d 4187 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4188 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4189 if (txdp->Host_Control ||
4190 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4191 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4192 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4193 dev_kfree_skb(skb);
2fda096d 4194 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4195 return NETDEV_TX_OK;
1da177e4 4196 }
0b1f7ebe 4197
75c30b13 4198 offload_type = s2io_offload_type(skb);
75c30b13 4199 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4200 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4201 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4202 }
84fa7933 4203 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4204 txdp->Control_2 |=
4205 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4206 TXD_TX_CKO_UDP_EN);
4207 }
fed5eccd
AR		 4208 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4209 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4210 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4211 if (enable_per_list_interrupt)
4212 if (put_off & (queue_len >> 5))
4213 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4214 if (vlan_tag) {
be3a6b02
K		 4215 txdp->Control_2 |= TXD_VLAN_ENABLE;
4216 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4217 }
4218
fed5eccd 4219 frg_len = skb->len - skb->data_len;
75c30b13 4220 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4221 int ufo_size;
4222
75c30b13 4223 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4224 ufo_size &= ~7;
4225 txdp->Control_1 |= TXD_UFO_EN;
4226 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4227 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4228#ifdef __BIG_ENDIAN
3459feb8 4229 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4230 fifo->ufo_in_band_v[put_off] =
3459feb8 4231 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4232#else
2fda096d 4233 fifo->ufo_in_band_v[put_off] =
3459feb8 4234 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4235#endif
2fda096d 4236 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4237 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
2fda096d 4238 fifo->ufo_in_band_v,
fed5eccd 4239 sizeof(u64), PCI_DMA_TODEVICE);
8d8bb39b 4240 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4241 goto pci_map_failed;
fed5eccd 4242 txdp++;
fed5eccd 4243 }
1da177e4 4244
fed5eccd
AR		 4245 txdp->Buffer_Pointer = pci_map_single
4246 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4247 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4248 goto pci_map_failed;
4249
fed5eccd
AR		 4250 txdp->Host_Control = (unsigned long) skb;
4251 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4252 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4253 txdp->Control_1 |= TXD_UFO_EN;
4254
4255 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4256 /* For fragmented SKB. */
4257 for (i = 0; i < frg_cnt; i++) {
4258 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4259 /* A '0' length fragment will be ignored */
4260 if (!frag->size)
4261 continue;
1da177e4
LT		 4262 txdp++;
4263 txdp->Buffer_Pointer = (u64) pci_map_page
4264 (sp->pdev, frag->page, frag->page_offset,
4265 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4266 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4267 if (offload_type == SKB_GSO_UDP)
fed5eccd 4268 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4269 }
4270 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4271
75c30b13 4272 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4273 frg_cnt++; /* as Txd0 was used for inband header */
4274
1da177e4 4275 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4276 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4277 writeq(val64, &tx_fifo->TxDL_Pointer);
4278
4279 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4280 TX_FIFO_LAST_LIST);
75c30b13 4281 if (offload_type)
fed5eccd 4282 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4283
1da177e4
LT		 4284 writeq(val64, &tx_fifo->List_Control);
4285
303bcb4b
K		 4286 mmiowb();
4287
1da177e4 4288 put_off++;
2fda096d 4289 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4290 put_off = 0;
2fda096d 4291 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4292
4293 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4294 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4295 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4296 DBG_PRINT(TX_DBG,
4297 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4298 put_off, get_off);
3a3d5756 4299 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4300 }
491976b2 4301 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
2fda096d 4302 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4303
f6f4bfa3
SH		 4304 if (sp->config.intr_type == MSI_X)
4305 tx_intr_handler(fifo);
4306
6ed10654 4307 return NETDEV_TX_OK;
491abf25
VP		 4308pci_map_failed:
4309 stats->pci_map_fail_cnt++;
3a3d5756 4310 s2io_stop_tx_queue(sp, fifo->fifo_no);
491abf25
VP		 4311 stats->mem_freed += skb->truesize;
4312 dev_kfree_skb(skb);
2fda096d 4313 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4314 return NETDEV_TX_OK;
1da177e4
LT		 4315}
4316
25fff88e
K		 4317static void
4318s2io_alarm_handle(unsigned long data)
4319{
1ee6dd77 4320 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4321 struct net_device *dev = sp->dev;
25fff88e 4322
8116f3cf 4323 s2io_handle_errors(dev);
25fff88e
K		 4324 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4325}
4326
7d12e780 4327static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4328{
1ee6dd77
RB		 4329 struct ring_info *ring = (struct ring_info *)dev_id;
4330 struct s2io_nic *sp = ring->nic;
f61e0a35 4331 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4332
f61e0a35 4333 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4334 return IRQ_HANDLED;
92b84437 4335
f61e0a35 4336 if (sp->config.napi) {
1a79d1c3
AV		 4337 u8 __iomem *addr = NULL;
4338 u8 val8 = 0;
f61e0a35 4339
1a79d1c3 4340 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4341 addr += (7 - ring->ring_no);
4342 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4343 writeb(val8, addr);
4344 val8 = readb(addr);
288379f0 4345 napi_schedule(&ring->napi);
f61e0a35
SH		 4346 } else {
4347 rx_intr_handler(ring, 0);
8d8bb39b 4348 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4349 }
7d3d0439 4350
cc6e7c44
RA		 4351 return IRQ_HANDLED;
4352}
4353
7d12e780 4354static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4355{
ac731ab6
SH		 4356 int i;
4357 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4358 struct s2io_nic *sp = fifos->nic;
4359 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4360 struct config_param *config = &sp->config;
4361 u64 reason;
cc6e7c44 4362
ac731ab6
SH		 4363 if (unlikely(!is_s2io_card_up(sp)))
4364 return IRQ_NONE;
4365
4366 reason = readq(&bar0->general_int_status);
4367 if (unlikely(reason == S2IO_MINUS_ONE))
4368 /* Nothing much can be done. Get out */
92b84437 4369 return IRQ_HANDLED;
92b84437 4370
01e16faa
SH		 4371 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4372 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4373
01e16faa
SH		 4374 if (reason & GEN_INTR_TXPIC)
4375 s2io_txpic_intr_handle(sp);
ac731ab6 4376
01e16faa
SH		 4377 if (reason & GEN_INTR_TXTRAFFIC)
4378 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4379
01e16faa
SH		 4380 for (i = 0; i < config->tx_fifo_num; i++)
4381 tx_intr_handler(&fifos[i]);
ac731ab6 4382
01e16faa
SH		 4383 writeq(sp->general_int_mask, &bar0->general_int_mask);
4384 readl(&bar0->general_int_status);
4385 return IRQ_HANDLED;
4386 }
4387 /* The interrupt was not raised by us */
4388 return IRQ_NONE;
cc6e7c44 4389}
ac731ab6 4390
1ee6dd77 4391static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4392{
1ee6dd77 4393 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4394 u64 val64;
4395
4396 val64 = readq(&bar0->pic_int_status);
4397 if (val64 & PIC_INT_GPIO) {
4398 val64 = readq(&bar0->gpio_int_reg);
4399 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4400 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4401 /*
4402 * This is unstable state so clear both up/down
4403 * interrupt and adapter to re-evaluate the link state.
4404 */
a371a07d
K		 4405 val64 |= GPIO_INT_REG_LINK_DOWN;
4406 val64 |= GPIO_INT_REG_LINK_UP;
4407 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4408 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4409 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4410 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4411 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4412 }
c92ca04b
AR		 4413 else if (val64 & GPIO_INT_REG_LINK_UP) {
4414 val64 = readq(&bar0->adapter_status);
c92ca04b 4415 /* Enable Adapter */
19a60522
SS		 4416 val64 = readq(&bar0->adapter_control);
4417 val64 |= ADAPTER_CNTL_EN;
4418 writeq(val64, &bar0->adapter_control);
4419 val64 |= ADAPTER_LED_ON;
4420 writeq(val64, &bar0->adapter_control);
4421 if (!sp->device_enabled_once)
4422 sp->device_enabled_once = 1;
c92ca04b 4423
19a60522
SS		 4424 s2io_link(sp, LINK_UP);
4425 /*
4426 * unmask link down interrupt and mask link-up
4427 * intr
4428 */
4429 val64 = readq(&bar0->gpio_int_mask);
4430 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4431 val64 |= GPIO_INT_MASK_LINK_UP;
4432 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4433
c92ca04b
AR		 4434 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4435 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4436 s2io_link(sp, LINK_DOWN);
4437 /* Link is down so unmaks link up interrupt */
4438 val64 = readq(&bar0->gpio_int_mask);
4439 val64 &= ~GPIO_INT_MASK_LINK_UP;
4440 val64 |= GPIO_INT_MASK_LINK_DOWN;
4441 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4442
4443 /* turn off LED */
4444 val64 = readq(&bar0->adapter_control);
4445 val64 = val64 &(~ADAPTER_LED_ON);
4446 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4447 }
4448 }
c92ca04b 4449 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4450}
4451
8116f3cf
SS		 4452/**
4453 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4454 * @value: alarm bits
4455 * @addr: address value
4456 * @cnt: counter variable
4457 * Description: Check for alarm and increment the counter
4458 * Return Value:
4459 * 1 - if alarm bit set
4460 * 0 - if alarm bit is not set
4461 */
43b7c451 4462static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4463 unsigned long long *cnt)
4464{
4465 u64 val64;
4466 val64 = readq(addr);
4467 if ( val64 & value ) {
4468 writeq(val64, addr);
4469 (*cnt)++;
4470 return 1;
4471 }
4472 return 0;
4473
4474}
4475
4476/**
4477 * s2io_handle_errors - Xframe error indication handler
4478 * @nic: device private variable
4479 * Description: Handle alarms such as loss of link, single or
4480 * double ECC errors, critical and serious errors.
4481 * Return Value:
4482 * NONE
4483 */
4484static void s2io_handle_errors(void * dev_id)
4485{
4486 struct net_device *dev = (struct net_device *) dev_id;
4cf1653a 4487 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf
SS		 4488 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4489 u64 temp64 = 0,val64=0;
4490 int i = 0;
4491
4492 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4493 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4494
92b84437 4495 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4496 return;
4497
4498 if (pci_channel_offline(sp->pdev))
4499 return;
4500
4501 memset(&sw_stat->ring_full_cnt, 0,
4502 sizeof(sw_stat->ring_full_cnt));
4503
4504 /* Handling the XPAK counters update */
4505 if(stats->xpak_timer_count < 72000) {
4506 /* waiting for an hour */
4507 stats->xpak_timer_count++;
4508 } else {
4509 s2io_updt_xpak_counter(dev);
4510 /* reset the count to zero */
4511 stats->xpak_timer_count = 0;
4512 }
4513
4514 /* Handling link status change error Intr */
4515 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4516 val64 = readq(&bar0->mac_rmac_err_reg);
4517 writeq(val64, &bar0->mac_rmac_err_reg);
4518 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4519 schedule_work(&sp->set_link_task);
4520 }
4521
4522 /* In case of a serious error, the device will be Reset. */
4523 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4524 &sw_stat->serious_err_cnt))
4525 goto reset;
4526
4527 /* Check for data parity error */
4528 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4529 &sw_stat->parity_err_cnt))
4530 goto reset;
4531
4532 /* Check for ring full counter */
4533 if (sp->device_type == XFRAME_II_DEVICE) {
4534 val64 = readq(&bar0->ring_bump_counter1);
4535 for (i=0; i<4; i++) {
4536 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4537 temp64 >>= 64 - ((i+1)*16);
4538 sw_stat->ring_full_cnt[i] += temp64;
4539 }
4540
4541 val64 = readq(&bar0->ring_bump_counter2);
4542 for (i=0; i<4; i++) {
4543 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4544 temp64 >>= 64 - ((i+1)*16);
4545 sw_stat->ring_full_cnt[i+4] += temp64;
4546 }
4547 }
4548
4549 val64 = readq(&bar0->txdma_int_status);
4550 /*check for pfc_err*/
4551 if (val64 & TXDMA_PFC_INT) {
4552 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4553 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4554 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4555 &sw_stat->pfc_err_cnt))
4556 goto reset;
4557 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4558 &sw_stat->pfc_err_cnt);
4559 }
4560
4561 /*check for tda_err*/
4562 if (val64 & TXDMA_TDA_INT) {
4563 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4564 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4565 &sw_stat->tda_err_cnt))
4566 goto reset;
4567 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4568 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4569 }
4570 /*check for pcc_err*/
4571 if (val64 & TXDMA_PCC_INT) {
4572 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4573 | PCC_N_SERR | PCC_6_COF_OV_ERR
4574 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4575 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4576 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4577 &sw_stat->pcc_err_cnt))
4578 goto reset;
4579 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4580 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4581 }
4582
4583 /*check for tti_err*/
4584 if (val64 & TXDMA_TTI_INT) {
4585 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4586 &sw_stat->tti_err_cnt))
4587 goto reset;
4588 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4589 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4590 }
4591
4592 /*check for lso_err*/
4593 if (val64 & TXDMA_LSO_INT) {
4594 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4595 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4596 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4597 goto reset;
4598 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4599 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4600 }
4601
4602 /*check for tpa_err*/
4603 if (val64 & TXDMA_TPA_INT) {
4604 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4605 &sw_stat->tpa_err_cnt))
4606 goto reset;
4607 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4608 &sw_stat->tpa_err_cnt);
4609 }
4610
4611 /*check for sm_err*/
4612 if (val64 & TXDMA_SM_INT) {
4613 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4614 &sw_stat->sm_err_cnt))
4615 goto reset;
4616 }
4617
4618 val64 = readq(&bar0->mac_int_status);
4619 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4620 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4621 &bar0->mac_tmac_err_reg,
4622 &sw_stat->mac_tmac_err_cnt))
4623 goto reset;
4624 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4625 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4626 &bar0->mac_tmac_err_reg,
4627 &sw_stat->mac_tmac_err_cnt);
4628 }
4629
4630 val64 = readq(&bar0->xgxs_int_status);
4631 if (val64 & XGXS_INT_STATUS_TXGXS) {
4632 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4633 &bar0->xgxs_txgxs_err_reg,
4634 &sw_stat->xgxs_txgxs_err_cnt))
4635 goto reset;
4636 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4637 &bar0->xgxs_txgxs_err_reg,
4638 &sw_stat->xgxs_txgxs_err_cnt);
4639 }
4640
4641 val64 = readq(&bar0->rxdma_int_status);
4642 if (val64 & RXDMA_INT_RC_INT_M) {
4643 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4644 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4645 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4646 goto reset;
4647 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4648 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4649 &sw_stat->rc_err_cnt);
4650 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4651 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4652 &sw_stat->prc_pcix_err_cnt))
4653 goto reset;
4654 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4655 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4656 &sw_stat->prc_pcix_err_cnt);
4657 }
4658
4659 if (val64 & RXDMA_INT_RPA_INT_M) {
4660 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4661 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4662 goto reset;
4663 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4664 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4665 }
4666
4667 if (val64 & RXDMA_INT_RDA_INT_M) {
4668 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4669 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4670 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4671 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4672 goto reset;
4673 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4674 | RDA_MISC_ERR | RDA_PCIX_ERR,
4675 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4676 }
4677
4678 if (val64 & RXDMA_INT_RTI_INT_M) {
4679 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4680 &sw_stat->rti_err_cnt))
4681 goto reset;
4682 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4683 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4684 }
4685
4686 val64 = readq(&bar0->mac_int_status);
4687 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4688 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4689 &bar0->mac_rmac_err_reg,
4690 &sw_stat->mac_rmac_err_cnt))
4691 goto reset;
4692 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4693 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4694 &sw_stat->mac_rmac_err_cnt);
4695 }
4696
4697 val64 = readq(&bar0->xgxs_int_status);
4698 if (val64 & XGXS_INT_STATUS_RXGXS) {
4699 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4700 &bar0->xgxs_rxgxs_err_reg,
4701 &sw_stat->xgxs_rxgxs_err_cnt))
4702 goto reset;
4703 }
4704
4705 val64 = readq(&bar0->mc_int_status);
4706 if(val64 & MC_INT_STATUS_MC_INT) {
4707 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4708 &sw_stat->mc_err_cnt))
4709 goto reset;
4710
4711 /* Handling Ecc errors */
4712 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4713 writeq(val64, &bar0->mc_err_reg);
4714 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4715 sw_stat->double_ecc_errs++;
4716 if (sp->device_type != XFRAME_II_DEVICE) {
4717 /*
4718 * Reset XframeI only if critical error
4719 */
4720 if (val64 &
4721 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4722 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4723 goto reset;
4724 }
4725 } else
4726 sw_stat->single_ecc_errs++;
4727 }
4728 }
4729 return;
4730
4731reset:
3a3d5756 4732 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4733 schedule_work(&sp->rst_timer_task);
4734 sw_stat->soft_reset_cnt++;
4735 return;
4736}
4737
1da177e4
LT		 4738/**
4739 * s2io_isr - ISR handler of the device .
4740 * @irq: the irq of the device.
4741 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4742 * Description: This function is the ISR handler of the device. It
4743 * identifies the reason for the interrupt and calls the relevant
4744 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4745 * recv buffers, if their numbers are below the panic value which is
4746 * presently set to 25% of the original number of rcv buffers allocated.
4747 * Return value:
20346722 4748 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4749 * IRQ_NONE: will be returned if interrupt is not from our device
4750 */
7d12e780 4751static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4752{
4753 struct net_device *dev = (struct net_device *) dev_id;
4cf1653a 4754 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4755 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4756 int i;
19a60522 4757 u64 reason = 0;
1ee6dd77 4758 struct mac_info *mac_control;
1da177e4
LT		 4759 struct config_param *config;
4760
d796fdb7
LV		 4761 /* Pretend we handled any irq's from a disconnected card */
4762 if (pci_channel_offline(sp->pdev))
4763 return IRQ_NONE;
4764
596c5c97 4765 if (!is_s2io_card_up(sp))
92b84437 4766 return IRQ_NONE;
92b84437 4767
1da177e4
LT		 4768 mac_control = &sp->mac_control;
4769 config = &sp->config;
4770
20346722 4771 /*
1da177e4
LT		 4772 * Identify the cause for interrupt and call the appropriate
4773 * interrupt handler. Causes for the interrupt could be;
4774 * 1. Rx of packet.
4775 * 2. Tx complete.
4776 * 3. Link down.
1da177e4
LT		 4777 */
4778 reason = readq(&bar0->general_int_status);
4779
596c5c97
SS		 4780 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4781 /* Nothing much can be done. Get out */
4782 return IRQ_HANDLED;
1da177e4 4783 }
5d3213cc 4784
596c5c97
SS		 4785 if (reason & (GEN_INTR_RXTRAFFIC |
4786 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4787 {
4788 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4789
4790 if (config->napi) {
4791 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4792 napi_schedule(&sp->napi);
f61e0a35
SH		 4793 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4794 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4795 readl(&bar0->rx_traffic_int);
db874e65 4796 }
596c5c97
SS		 4797 } else {
4798 /*
4799 * rx_traffic_int reg is an R1 register, writing all 1's
4800 * will ensure that the actual interrupt causing bit
4801 * get's cleared and hence a read can be avoided.
4802 */
4803 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4804 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97
SS		 4805
4806 for (i = 0; i < config->rx_ring_num; i++)
f61e0a35 4807 rx_intr_handler(&mac_control->rings[i], 0);
db874e65 4808 }
596c5c97 4809
db874e65 4810 /*
596c5c97 4811 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4812 * will ensure that the actual interrupt causing bit get's
4813 * cleared and hence a read can be avoided.
4814 */
596c5c97
SS		 4815 if (reason & GEN_INTR_TXTRAFFIC)
4816 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4817
596c5c97
SS		 4818 for (i = 0; i < config->tx_fifo_num; i++)
4819 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4820
596c5c97
SS		 4821 if (reason & GEN_INTR_TXPIC)
4822 s2io_txpic_intr_handle(sp);
fe113638 4823
596c5c97
SS		 4824 /*
4825 * Reallocate the buffers from the interrupt handler itself.
4826 */
4827 if (!config->napi) {
4828 for (i = 0; i < config->rx_ring_num; i++)
8d8bb39b 4829 s2io_chk_rx_buffers(sp, &mac_control->rings[i]);
596c5c97
SS		 4830 }
4831 writeq(sp->general_int_mask, &bar0->general_int_mask);
4832 readl(&bar0->general_int_status);
20346722 4833
596c5c97 4834 return IRQ_HANDLED;
db874e65 4835
596c5c97
SS		 4836 }
4837 else if (!reason) {
4838 /* The interrupt was not raised by us */
4839 return IRQ_NONE;
4840 }
db874e65 4841
1da177e4
LT		 4842 return IRQ_HANDLED;
4843}
4844
7ba013ac
K		 4845/**
4846 * s2io_updt_stats -
4847 */
1ee6dd77 4848static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4849{
1ee6dd77 4850 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4851 u64 val64;
4852 int cnt = 0;
4853
92b84437 4854 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4855 /* Apprx 30us on a 133 MHz bus */
4856 val64 = SET_UPDT_CLICKS(10) |
4857 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4858 writeq(val64, &bar0->stat_cfg);
4859 do {
4860 udelay(100);
4861 val64 = readq(&bar0->stat_cfg);
b7b5a128 4862 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4863 break;
4864 cnt++;
4865 if (cnt == 5)
4866 break; /* Updt failed */
4867 } while(1);
8a4bdbaa 4868 }
7ba013ac
K		 4869}
4870
1da177e4 4871/**
20346722 4872 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4873 * @dev : pointer to the device structure.
4874 * Description:
20346722 4875 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4876 * structure and returns a pointer to the same.
4877 * Return value:
4878 * pointer to the updated net_device_stats structure.
4879 */
4880
ac1f60db 4881static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4882{
4cf1653a 4883 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4884 struct mac_info *mac_control;
1da177e4 4885 struct config_param *config;
0425b46a 4886 int i;
1da177e4 4887
20346722 4888
1da177e4
LT		 4889 mac_control = &sp->mac_control;
4890 config = &sp->config;
4891
7ba013ac
K		 4892 /* Configure Stats for immediate updt */
4893 s2io_updt_stats(sp);
4894
dc56e634
BL		 4895 /* Using sp->stats as a staging area, because reset (due to mtu
4896 change, for example) will clear some hardware counters */
4897 dev->stats.tx_packets +=
4898 le32_to_cpu(mac_control->stats_info->tmac_frms) -
4899 sp->stats.tx_packets;
7ba013ac
K		 4900 sp->stats.tx_packets =
4901 le32_to_cpu(mac_control->stats_info->tmac_frms);
dc56e634
BL		 4902 dev->stats.tx_errors +=
4903 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
4904 sp->stats.tx_errors;
20346722
K		 4905 sp->stats.tx_errors =
4906 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
dc56e634
BL		 4907 dev->stats.rx_errors +=
4908 le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
4909 sp->stats.rx_errors;
20346722 4910 sp->stats.rx_errors =
ee705dba 4911 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
dc56e634
BL		 4912 dev->stats.multicast =
4913 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
4914 sp->stats.multicast;
20346722
K		 4915 sp->stats.multicast =
4916 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
dc56e634
BL		 4917 dev->stats.rx_length_errors =
4918 le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
4919 sp->stats.rx_length_errors;
1da177e4 4920 sp->stats.rx_length_errors =
ee705dba 4921 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4 4922
0425b46a 4923 /* collect per-ring rx_packets and rx_bytes */
dc56e634 4924 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
0425b46a 4925 for (i = 0; i < config->rx_ring_num; i++) {
dc56e634
BL		 4926 dev->stats.rx_packets += mac_control->rings[i].rx_packets;
4927 dev->stats.rx_bytes += mac_control->rings[i].rx_bytes;
0425b46a
SH		 4928 }
4929
dc56e634 4930 return (&dev->stats);
1da177e4
LT		 4931}
4932
4933/**
4934 * s2io_set_multicast - entry point for multicast address enable/disable.
4935 * @dev : pointer to the device structure
4936 * Description:
20346722
K		 4937 * This function is a driver entry point which gets called by the kernel
4938 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4939 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4940 * determine, if multicast address must be enabled or if promiscuous mode
4941 * is to be disabled etc.
4942 * Return value:
4943 * void.
4944 */
4945
4946static void s2io_set_multicast(struct net_device *dev)
4947{
4948 int i, j, prev_cnt;
4949 struct dev_mc_list *mclist;
4cf1653a 4950 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4951 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4952 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4953 0xfeffffffffffULL;
faa4f796 4954 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4955 void __iomem *add;
faa4f796 4956 struct config_param *config = &sp->config;
1da177e4
LT		 4957
4958 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4959 /* Enable all Multicast addresses */
4960 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4961 &bar0->rmac_addr_data0_mem);
4962 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4963 &bar0->rmac_addr_data1_mem);
4964 val64 = RMAC_ADDR_CMD_MEM_WE |
4965 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 4966 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4967 writeq(val64, &bar0->rmac_addr_cmd_mem);
4968 /* Wait till command completes */
c92ca04b 4969 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4970 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4971 S2IO_BIT_RESET);
1da177e4
LT		 4972
4973 sp->m_cast_flg = 1;
faa4f796 4974 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4975 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4976 /* Disable all Multicast addresses */
4977 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4978 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4979 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4980 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4981 val64 = RMAC_ADDR_CMD_MEM_WE |
4982 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4983 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4984 writeq(val64, &bar0->rmac_addr_cmd_mem);
4985 /* Wait till command completes */
c92ca04b 4986 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4987 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4988 S2IO_BIT_RESET);
1da177e4
LT		 4989
4990 sp->m_cast_flg = 0;
4991 sp->all_multi_pos = 0;
4992 }
4993
4994 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4995 /* Put the NIC into promiscuous mode */
4996 add = &bar0->mac_cfg;
4997 val64 = readq(&bar0->mac_cfg);
4998 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4999
5000 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5001 writel((u32) val64, add);
5002 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5003 writel((u32) (val64 >> 32), (add + 4));
5004
926930b2
SS		 5005 if (vlan_tag_strip != 1) {
5006 val64 = readq(&bar0->rx_pa_cfg);
5007 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5008 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5009 sp->vlan_strip_flag = 0;
926930b2
SS		 5010 }
5011
1da177e4
LT		 5012 val64 = readq(&bar0->mac_cfg);
5013 sp->promisc_flg = 1;
776bd20f 5014 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5015 dev->name);
5016 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5017 /* Remove the NIC from promiscuous mode */
5018 add = &bar0->mac_cfg;
5019 val64 = readq(&bar0->mac_cfg);
5020 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5021
5022 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5023 writel((u32) val64, add);
5024 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5025 writel((u32) (val64 >> 32), (add + 4));
5026
926930b2
SS		 5027 if (vlan_tag_strip != 0) {
5028 val64 = readq(&bar0->rx_pa_cfg);
5029 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5030 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5031 sp->vlan_strip_flag = 1;
926930b2
SS		 5032 }
5033
1da177e4
LT		 5034 val64 = readq(&bar0->mac_cfg);
5035 sp->promisc_flg = 0;
776bd20f 5036 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 5037 dev->name);
5038 }
5039
5040 /* Update individual M_CAST address list */
5041 if ((!sp->m_cast_flg) && dev->mc_count) {
5042 if (dev->mc_count >
faa4f796 5043 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5044 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5045 dev->name);
5046 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5047 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5048 return;
5049 }
5050
5051 prev_cnt = sp->mc_addr_count;
5052 sp->mc_addr_count = dev->mc_count;
5053
5054 /* Clear out the previous list of Mc in the H/W. */
5055 for (i = 0; i < prev_cnt; i++) {
5056 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5057 &bar0->rmac_addr_data0_mem);
5058 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5059 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5060 val64 = RMAC_ADDR_CMD_MEM_WE |
5061 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5062 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5063 (config->mc_start_offset + i);
1da177e4
LT		 5064 writeq(val64, &bar0->rmac_addr_cmd_mem);
5065
5066 /* Wait for command completes */
c92ca04b 5067 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5068 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5069 S2IO_BIT_RESET)) {
1da177e4
LT		 5070 DBG_PRINT(ERR_DBG, "%s: Adding ",
5071 dev->name);
5072 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5073 return;
5074 }
5075 }
5076
5077 /* Create the new Rx filter list and update the same in H/W. */
5078 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5079 i++, mclist = mclist->next) {
5080 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5081 ETH_ALEN);
a7a80d5a 5082 mac_addr = 0;
1da177e4
LT		 5083 for (j = 0; j < ETH_ALEN; j++) {
5084 mac_addr |= mclist->dmi_addr[j];
5085 mac_addr <<= 8;
5086 }
5087 mac_addr >>= 8;
5088 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5089 &bar0->rmac_addr_data0_mem);
5090 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5091 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5092 val64 = RMAC_ADDR_CMD_MEM_WE |
5093 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5094 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5095 (i + config->mc_start_offset);
1da177e4
LT		 5096 writeq(val64, &bar0->rmac_addr_cmd_mem);
5097
5098 /* Wait for command completes */
c92ca04b 5099 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5100 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5101 S2IO_BIT_RESET)) {
1da177e4
LT		 5102 DBG_PRINT(ERR_DBG, "%s: Adding ",
5103 dev->name);
5104 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5105 return;
5106 }
5107 }
5108 }
5109}
5110
faa4f796
SH		 5111/* read from CAM unicast & multicast addresses and store it in
5112 * def_mac_addr structure
5113 */
dac499f9 5114static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5115{
5116 int offset;
5117 u64 mac_addr = 0x0;
5118 struct config_param *config = &sp->config;
5119
5120 /* store unicast & multicast mac addresses */
5121 for (offset = 0; offset < config->max_mc_addr; offset++) {
5122 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5123 /* if read fails disable the entry */
5124 if (mac_addr == FAILURE)
5125 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5126 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5127 }
5128}
5129
5130/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5131static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5132{
5133 int offset;
5134 struct config_param *config = &sp->config;
5135 /* restore unicast mac address */
5136 for (offset = 0; offset < config->max_mac_addr; offset++)
5137 do_s2io_prog_unicast(sp->dev,
5138 sp->def_mac_addr[offset].mac_addr);
5139
5140 /* restore multicast mac address */
5141 for (offset = config->mc_start_offset;
5142 offset < config->max_mc_addr; offset++)
5143 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5144}
5145
5146/* add a multicast MAC address to CAM */
5147static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5148{
5149 int i;
5150 u64 mac_addr = 0;
5151 struct config_param *config = &sp->config;
5152
5153 for (i = 0; i < ETH_ALEN; i++) {
5154 mac_addr <<= 8;
5155 mac_addr |= addr[i];
5156 }
5157 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5158 return SUCCESS;
5159
5160 /* check if the multicast mac already preset in CAM */
5161 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5162 u64 tmp64;
5163 tmp64 = do_s2io_read_unicast_mc(sp, i);
5164 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5165 break;
5166
5167 if (tmp64 == mac_addr)
5168 return SUCCESS;
5169 }
5170 if (i == config->max_mc_addr) {
5171 DBG_PRINT(ERR_DBG,
5172 "CAM full no space left for multicast MAC\n");
5173 return FAILURE;
5174 }
5175 /* Update the internal structure with this new mac address */
5176 do_s2io_copy_mac_addr(sp, i, mac_addr);
5177
5178 return (do_s2io_add_mac(sp, mac_addr, i));
5179}
5180
5181/* add MAC address to CAM */
5182static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5183{
5184 u64 val64;
5185 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5186
5187 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5188 &bar0->rmac_addr_data0_mem);
5189
5190 val64 =
5191 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5192 RMAC_ADDR_CMD_MEM_OFFSET(off);
5193 writeq(val64, &bar0->rmac_addr_cmd_mem);
5194
5195 /* Wait till command completes */
5196 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5197 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5198 S2IO_BIT_RESET)) {
faa4f796 5199 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5200 return FAILURE;
5201 }
5202 return SUCCESS;
5203}
faa4f796
SH		 5204/* deletes a specified unicast/multicast mac entry from CAM */
5205static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5206{
5207 int offset;
5208 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5209 struct config_param *config = &sp->config;
5210
5211 for (offset = 1;
5212 offset < config->max_mc_addr; offset++) {
5213 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5214 if (tmp64 == addr) {
5215 /* disable the entry by writing 0xffffffffffffULL */
5216 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5217 return FAILURE;
5218 /* store the new mac list from CAM */
5219 do_s2io_store_unicast_mc(sp);
5220 return SUCCESS;
5221 }
5222 }
5223 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5224 (unsigned long long)addr);
5225 return FAILURE;
5226}
5227
5228/* read mac entries from CAM */
5229static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5230{
5231 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5232 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5233
5234 /* read mac addr */
5235 val64 =
5236 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5237 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5238 writeq(val64, &bar0->rmac_addr_cmd_mem);
5239
5240 /* Wait till command completes */
5241 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5242 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5243 S2IO_BIT_RESET)) {
5244 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5245 return FAILURE;
5246 }
5247 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5248 return (tmp64 >> 16);
5249}
2fd37688
SS		 5250
5251/**
5252 * s2io_set_mac_addr driver entry point
5253 */
faa4f796 5254
2fd37688
SS		 5255static int s2io_set_mac_addr(struct net_device *dev, void *p)
5256{
5257 struct sockaddr *addr = p;
5258
5259 if (!is_valid_ether_addr(addr->sa_data))
5260 return -EINVAL;
5261
5262 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5263
5264 /* store the MAC address in CAM */
5265 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5266}
1da177e4 5267/**
2fd37688 5268 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5269 * @dev : pointer to the device structure.
5270 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5271 * Description : This procedure will program the Xframe to receive
1da177e4 5272 * frames with new Mac Address
20346722 5273 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5274 * as defined in errno.h file on failure.
5275 */
faa4f796 5276
2fd37688 5277static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5278{
4cf1653a 5279 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5280 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5281 int i;
faa4f796
SH		 5282 u64 tmp64;
5283 struct config_param *config = &sp->config;
1da177e4 5284
20346722 5285 /*
2fd37688
SS		 5286 * Set the new MAC address as the new unicast filter and reflect this
5287 * change on the device address registered with the OS. It will be
5288 * at offset 0.
5289 */
1da177e4
LT		 5290 for (i = 0; i < ETH_ALEN; i++) {
5291 mac_addr <<= 8;
5292 mac_addr |= addr[i];
2fd37688
SS		 5293 perm_addr <<= 8;
5294 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5295 }
5296
2fd37688
SS		 5297 /* check if the dev_addr is different than perm_addr */
5298 if (mac_addr == perm_addr)
d8d70caf
SS		 5299 return SUCCESS;
5300
faa4f796
SH		 5301 /* check if the mac already preset in CAM */
5302 for (i = 1; i < config->max_mac_addr; i++) {
5303 tmp64 = do_s2io_read_unicast_mc(sp, i);
5304 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5305 break;
5306
5307 if (tmp64 == mac_addr) {
5308 DBG_PRINT(INFO_DBG,
5309 "MAC addr:0x%llx already present in CAM\n",
5310 (unsigned long long)mac_addr);
5311 return SUCCESS;
5312 }
5313 }
5314 if (i == config->max_mac_addr) {
5315 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5316 return FAILURE;
5317 }
d8d70caf 5318 /* Update the internal structure with this new mac address */
faa4f796
SH		 5319 do_s2io_copy_mac_addr(sp, i, mac_addr);
5320 return (do_s2io_add_mac(sp, mac_addr, i));
1da177e4
LT		 5321}
5322
5323/**
20346722 5324 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5325 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5326 * @info: pointer to the structure with parameters given by ethtool to set
5327 * link information.
5328 * Description:
20346722 5329 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5330 * the NIC.
5331 * Return value:
5332 * 0 on success.
5333*/
5334
5335static int s2io_ethtool_sset(struct net_device *dev,
5336 struct ethtool_cmd *info)
5337{
4cf1653a 5338 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5339 if ((info->autoneg == AUTONEG_ENABLE) ||
5340 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5341 return -EINVAL;
5342 else {
5343 s2io_close(sp->dev);
5344 s2io_open(sp->dev);
5345 }
5346
5347 return 0;
5348}
5349
5350/**
20346722 5351 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5352 * @sp : private member of the device structure, pointer to the
5353 * s2io_nic structure.
5354 * @info : pointer to the structure with parameters given by ethtool
5355 * to return link information.
5356 * Description:
5357 * Returns link specific information like speed, duplex etc.. to ethtool.
5358 * Return value :
5359 * return 0 on success.
5360 */
5361
5362static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5363{
4cf1653a 5364 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5365 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5366 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5367 info->port = PORT_FIBRE;
1a7eb72b
SS		 5368
5369 /* info->transceiver */
5370 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5371
5372 if (netif_carrier_ok(sp->dev)) {
5373 info->speed = 10000;
5374 info->duplex = DUPLEX_FULL;
5375 } else {
5376 info->speed = -1;
5377 info->duplex = -1;
5378 }
5379
5380 info->autoneg = AUTONEG_DISABLE;
5381 return 0;
5382}
5383
5384/**
20346722
K		 5385 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5386 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5387 * s2io_nic structure.
5388 * @info : pointer to the structure with parameters given by ethtool to
5389 * return driver information.
5390 * Description:
5391 * Returns driver specefic information like name, version etc.. to ethtool.
5392 * Return value:
5393 * void
5394 */
5395
5396static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5397 struct ethtool_drvinfo *info)
5398{
4cf1653a 5399 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5400
dbc2309d
JL		 5401 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5402 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5403 strncpy(info->fw_version, "", sizeof(info->fw_version));
5404 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5405 info->regdump_len = XENA_REG_SPACE;
5406 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5407}
5408
5409/**
5410 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5411 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5412 * s2io_nic structure.
20346722 5413 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5414 * dumping the registers.
5415 * @reg_space: The input argumnet into which all the registers are dumped.
5416 * Description:
5417 * Dumps the entire register space of xFrame NIC into the user given
5418 * buffer area.
5419 * Return value :
5420 * void .
5421*/
5422
5423static void s2io_ethtool_gregs(struct net_device *dev,
5424 struct ethtool_regs *regs, void *space)
5425{
5426 int i;
5427 u64 reg;
5428 u8 *reg_space = (u8 *) space;
4cf1653a 5429 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5430
5431 regs->len = XENA_REG_SPACE;
5432 regs->version = sp->pdev->subsystem_device;
5433
5434 for (i = 0; i < regs->len; i += 8) {
5435 reg = readq(sp->bar0 + i);
5436 memcpy((reg_space + i), &reg, 8);
5437 }
5438}
5439
5440/**
5441 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5442 * @data : address of the private member of the device structure, which
1da177e4 5443 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5444 * Description: This is actually the timer function that alternates the
5445 * adapter LED bit of the adapter control bit to set/reset every time on
5446 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5447 * once every second.
5448*/
5449static void s2io_phy_id(unsigned long data)
5450{
1ee6dd77
RB		 5451 struct s2io_nic *sp = (struct s2io_nic *) data;
5452 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5453 u64 val64 = 0;
5454 u16 subid;
5455
5456 subid = sp->pdev->subsystem_device;
541ae68f
K		 5457 if ((sp->device_type == XFRAME_II_DEVICE) ||
5458 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5459 val64 = readq(&bar0->gpio_control);
5460 val64 ^= GPIO_CTRL_GPIO_0;
5461 writeq(val64, &bar0->gpio_control);
5462 } else {
5463 val64 = readq(&bar0->adapter_control);
5464 val64 ^= ADAPTER_LED_ON;
5465 writeq(val64, &bar0->adapter_control);
5466 }
5467
5468 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5469}
5470
5471/**
5472 * s2io_ethtool_idnic - To physically identify the nic on the system.
5473 * @sp : private member of the device structure, which is a pointer to the
5474 * s2io_nic structure.
20346722 5475 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5476 * ethtool.
5477 * Description: Used to physically identify the NIC on the system.
20346722 5478 * The Link LED will blink for a time specified by the user for
1da177e4 5479 * identification.
20346722 5480 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5481 * identification is possible only if it's link is up.
5482 * Return value:
5483 * int , returns 0 on success
5484 */
5485
5486static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5487{
5488 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5489 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5490 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5491 u16 subid;
5492
5493 subid = sp->pdev->subsystem_device;
5494 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 5495 if ((sp->device_type == XFRAME_I_DEVICE) &&
5496 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5497 val64 = readq(&bar0->adapter_control);
5498 if (!(val64 & ADAPTER_CNTL_EN)) {
5499 printk(KERN_ERR
5500 "Adapter Link down, cannot blink LED\n");
5501 return -EFAULT;
5502 }
5503 }
5504 if (sp->id_timer.function == NULL) {
5505 init_timer(&sp->id_timer);
5506 sp->id_timer.function = s2io_phy_id;
5507 sp->id_timer.data = (unsigned long) sp;
5508 }
5509 mod_timer(&sp->id_timer, jiffies);
5510 if (data)
20346722 5511 msleep_interruptible(data * HZ);
1da177e4 5512 else
20346722 5513 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5514 del_timer_sync(&sp->id_timer);
5515
541ae68f 5516 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5517 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5518 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5519 }
5520
5521 return 0;
5522}
5523
0cec35eb
SH		 5524static void s2io_ethtool_gringparam(struct net_device *dev,
5525 struct ethtool_ringparam *ering)
5526{
4cf1653a 5527 struct s2io_nic *sp = netdev_priv(dev);
0cec35eb
SH		 5528 int i,tx_desc_count=0,rx_desc_count=0;
5529
5530 if (sp->rxd_mode == RXD_MODE_1)
5531 ering->rx_max_pending = MAX_RX_DESC_1;
5532 else if (sp->rxd_mode == RXD_MODE_3B)
5533 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5534
5535 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5536 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5537 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5538
0cec35eb
SH		 5539 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5540 ering->tx_pending = tx_desc_count;
5541 rx_desc_count = 0;
8a4bdbaa 5542 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5543 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5544
0cec35eb
SH		 5545 ering->rx_pending = rx_desc_count;
5546
5547 ering->rx_mini_max_pending = 0;
5548 ering->rx_mini_pending = 0;
5549 if(sp->rxd_mode == RXD_MODE_1)
5550 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5551 else if (sp->rxd_mode == RXD_MODE_3B)
5552 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5553 ering->rx_jumbo_pending = rx_desc_count;
5554}
5555
1da177e4
LT		 5556/**
5557 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5558 * @sp : private member of the device structure, which is a pointer to the
5559 * s2io_nic structure.
1da177e4
LT		 5560 * @ep : pointer to the structure with pause parameters given by ethtool.
5561 * Description:
5562 * Returns the Pause frame generation and reception capability of the NIC.
5563 * Return value:
5564 * void
5565 */
5566static void s2io_ethtool_getpause_data(struct net_device *dev,
5567 struct ethtool_pauseparam *ep)
5568{
5569 u64 val64;
4cf1653a 5570 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5571 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5572
5573 val64 = readq(&bar0->rmac_pause_cfg);
5574 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5575 ep->tx_pause = true;
1da177e4 5576 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5577 ep->rx_pause = true;
5578 ep->autoneg = false;
1da177e4
LT		 5579}
5580
5581/**
5582 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5583 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5584 * s2io_nic structure.
5585 * @ep : pointer to the structure with pause parameters given by ethtool.
5586 * Description:
5587 * It can be used to set or reset Pause frame generation or reception
5588 * support of the NIC.
5589 * Return value:
5590 * int, returns 0 on Success
5591 */
5592
5593static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5594 struct ethtool_pauseparam *ep)
1da177e4
LT		 5595{
5596 u64 val64;
4cf1653a 5597 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5598 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5599
5600 val64 = readq(&bar0->rmac_pause_cfg);
5601 if (ep->tx_pause)
5602 val64 |= RMAC_PAUSE_GEN_ENABLE;
5603 else
5604 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5605 if (ep->rx_pause)
5606 val64 |= RMAC_PAUSE_RX_ENABLE;
5607 else
5608 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5609 writeq(val64, &bar0->rmac_pause_cfg);
5610 return 0;
5611}
5612
5613/**
5614 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5615 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5616 * s2io_nic structure.
5617 * @off : offset at which the data must be written
5618 * @data : Its an output parameter where the data read at the given
20346722 5619 * offset is stored.
1da177e4 5620 * Description:
20346722 5621 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5622 * read data.
5623 * NOTE: Will allow to read only part of the EEPROM visible through the
5624 * I2C bus.
5625 * Return value:
5626 * -1 on failure and 0 on success.
5627 */
5628
5629#define S2IO_DEV_ID 5
1ee6dd77 5630static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5631{
5632 int ret = -1;
5633 u32 exit_cnt = 0;
5634 u64 val64;
1ee6dd77 5635 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5636
ad4ebed0 5637 if (sp->device_type == XFRAME_I_DEVICE) {
5638 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5639 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5640 I2C_CONTROL_CNTL_START;
5641 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5642
ad4ebed0 5643 while (exit_cnt < 5) {
5644 val64 = readq(&bar0->i2c_control);
5645 if (I2C_CONTROL_CNTL_END(val64)) {
5646 *data = I2C_CONTROL_GET_DATA(val64);
5647 ret = 0;
5648 break;
5649 }
5650 msleep(50);
5651 exit_cnt++;
1da177e4 5652 }
1da177e4
LT		 5653 }
5654
ad4ebed0 5655 if (sp->device_type == XFRAME_II_DEVICE) {
5656 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5657 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5658 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5659 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5660 val64 |= SPI_CONTROL_REQ;
5661 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5662 while (exit_cnt < 5) {
5663 val64 = readq(&bar0->spi_control);
5664 if (val64 & SPI_CONTROL_NACK) {
5665 ret = 1;
5666 break;
5667 } else if (val64 & SPI_CONTROL_DONE) {
5668 *data = readq(&bar0->spi_data);
5669 *data &= 0xffffff;
5670 ret = 0;
5671 break;
5672 }
5673 msleep(50);
5674 exit_cnt++;
5675 }
5676 }
1da177e4
LT		 5677 return ret;
5678}
5679
5680/**
5681 * write_eeprom - actually writes the relevant part of the data value.
5682 * @sp : private member of the device structure, which is a pointer to the
5683 * s2io_nic structure.
5684 * @off : offset at which the data must be written
5685 * @data : The data that is to be written
20346722 5686 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5687 * the Eeprom. (max of 3)
5688 * Description:
5689 * Actually writes the relevant part of the data value into the Eeprom
5690 * through the I2C bus.
5691 * Return value:
5692 * 0 on success, -1 on failure.
5693 */
5694
1ee6dd77 5695static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5696{
5697 int exit_cnt = 0, ret = -1;
5698 u64 val64;
1ee6dd77 5699 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5700
ad4ebed0 5701 if (sp->device_type == XFRAME_I_DEVICE) {
5702 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5703 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5704 I2C_CONTROL_CNTL_START;
5705 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5706
5707 while (exit_cnt < 5) {
5708 val64 = readq(&bar0->i2c_control);
5709 if (I2C_CONTROL_CNTL_END(val64)) {
5710 if (!(val64 & I2C_CONTROL_NACK))
5711 ret = 0;
5712 break;
5713 }
5714 msleep(50);
5715 exit_cnt++;
5716 }
5717 }
1da177e4 5718
ad4ebed0 5719 if (sp->device_type == XFRAME_II_DEVICE) {
5720 int write_cnt = (cnt == 8) ? 0 : cnt;
5721 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5722
5723 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5724 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5725 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5726 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5727 val64 |= SPI_CONTROL_REQ;
5728 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5729 while (exit_cnt < 5) {
5730 val64 = readq(&bar0->spi_control);
5731 if (val64 & SPI_CONTROL_NACK) {
5732 ret = 1;
5733 break;
5734 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5735 ret = 0;
ad4ebed0 5736 break;
5737 }
5738 msleep(50);
5739 exit_cnt++;
1da177e4 5740 }
1da177e4 5741 }
1da177e4
LT		 5742 return ret;
5743}
1ee6dd77 5744static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5745{
b41477f3
AR		 5746 u8 *vpd_data;
5747 u8 data;
9dc737a7
AR		 5748 int i=0, cnt, fail = 0;
5749 int vpd_addr = 0x80;
5750
5751 if (nic->device_type == XFRAME_II_DEVICE) {
5752 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5753 vpd_addr = 0x80;
5754 }
5755 else {
5756 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5757 vpd_addr = 0x50;
5758 }
19a60522 5759 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5760
b41477f3 5761 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5762 if (!vpd_data) {
5763 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5764 return;
c53d4945 5765 }
491976b2 5766 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5767
9dc737a7
AR		 5768 for (i = 0; i < 256; i +=4 ) {
5769 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5770 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5771 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5772 for (cnt = 0; cnt <5; cnt++) {
5773 msleep(2);
5774 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5775 if (data == 0x80)
5776 break;
5777 }
5778 if (cnt >= 5) {
5779 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5780 fail = 1;
5781 break;
5782 }
5783 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5784 (u32 *)&vpd_data[i]);
5785 }
19a60522
SS		 5786
5787 if(!fail) {
5788 /* read serial number of adapter */
5789 for (cnt = 0; cnt < 256; cnt++) {
5790 if ((vpd_data[cnt] == 'S') &&
5791 (vpd_data[cnt+1] == 'N') &&
5792 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5793 memset(nic->serial_num, 0, VPD_STRING_LEN);
5794 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5795 vpd_data[cnt+2]);
5796 break;
5797 }
5798 }
5799 }
5800
5801 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5802 memset(nic->product_name, 0, vpd_data[1]);
5803 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5804 }
b41477f3 5805 kfree(vpd_data);
491976b2 5806 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5807}
5808
1da177e4
LT		 5809/**
5810 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5811 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5812 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5813 * containing all relevant information.
5814 * @data_buf : user defined value to be written into Eeprom.
5815 * Description: Reads the values stored in the Eeprom at given offset
5816 * for a given length. Stores these values int the input argument data
5817 * buffer 'data_buf' and returns these to the caller (ethtool.)
5818 * Return value:
5819 * int 0 on success
5820 */
5821
5822static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5823 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5824{
ad4ebed0 5825 u32 i, valid;
5826 u64 data;
4cf1653a 5827 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5828
5829 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5830
5831 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5832 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5833
5834 for (i = 0; i < eeprom->len; i += 4) {
5835 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5836 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5837 return -EFAULT;
5838 }
5839 valid = INV(data);
5840 memcpy((data_buf + i), &valid, 4);
5841 }
5842 return 0;
5843}
5844
5845/**
5846 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5847 * @sp : private member of the device structure, which is a pointer to the
5848 * s2io_nic structure.
20346722 5849 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5850 * containing all relevant information.
5851 * @data_buf ; user defined value to be written into Eeprom.
5852 * Description:
5853 * Tries to write the user provided value in the Eeprom, at the offset
5854 * given by the user.
5855 * Return value:
5856 * 0 on success, -EFAULT on failure.
5857 */
5858
5859static int s2io_ethtool_seeprom(struct net_device *dev,
5860 struct ethtool_eeprom *eeprom,
5861 u8 * data_buf)
5862{
5863 int len = eeprom->len, cnt = 0;
ad4ebed0 5864 u64 valid = 0, data;
4cf1653a 5865 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5866
5867 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5868 DBG_PRINT(ERR_DBG,
5869 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5870 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5871 eeprom->magic);
5872 return -EFAULT;
5873 }
5874
5875 while (len) {
5876 data = (u32) data_buf[cnt] & 0x000000FF;
5877 if (data) {
5878 valid = (u32) (data << 24);
5879 } else
5880 valid = data;
5881
5882 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5883 DBG_PRINT(ERR_DBG,
5884 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5885 DBG_PRINT(ERR_DBG,
5886 "write into the specified offset\n");
5887 return -EFAULT;
5888 }
5889 cnt++;
5890 len--;
5891 }
5892
5893 return 0;
5894}
5895
5896/**
20346722
K		 5897 * s2io_register_test - reads and writes into all clock domains.
5898 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5899 * s2io_nic structure.
5900 * @data : variable that returns the result of each of the test conducted b
5901 * by the driver.
5902 * Description:
5903 * Read and write into all clock domains. The NIC has 3 clock domains,
5904 * see that registers in all the three regions are accessible.
5905 * Return value:
5906 * 0 on success.
5907 */
5908
1ee6dd77 5909static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5910{
1ee6dd77 5911 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5912 u64 val64 = 0, exp_val;
1da177e4
LT		 5913 int fail = 0;
5914
20346722
K		 5915 val64 = readq(&bar0->pif_rd_swapper_fb);
5916 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5917 fail = 1;
5918 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5919 }
5920
5921 val64 = readq(&bar0->rmac_pause_cfg);
5922 if (val64 != 0xc000ffff00000000ULL) {
5923 fail = 1;
5924 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5925 }
5926
5927 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5928 if (sp->device_type == XFRAME_II_DEVICE)
5929 exp_val = 0x0404040404040404ULL;
5930 else
5931 exp_val = 0x0808080808080808ULL;
5932 if (val64 != exp_val) {
1da177e4
LT		 5933 fail = 1;
5934 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5935 }
5936
5937 val64 = readq(&bar0->xgxs_efifo_cfg);
5938 if (val64 != 0x000000001923141EULL) {
5939 fail = 1;
5940 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5941 }
5942
5943 val64 = 0x5A5A5A5A5A5A5A5AULL;
5944 writeq(val64, &bar0->xmsi_data);
5945 val64 = readq(&bar0->xmsi_data);
5946 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5947 fail = 1;
5948 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5949 }
5950
5951 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5952 writeq(val64, &bar0->xmsi_data);
5953 val64 = readq(&bar0->xmsi_data);
5954 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5955 fail = 1;
5956 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5957 }
5958
5959 *data = fail;
ad4ebed0 5960 return fail;
1da177e4
LT		 5961}
5962
5963/**
20346722 5964 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5965 * @sp : private member of the device structure, which is a pointer to the
5966 * s2io_nic structure.
5967 * @data:variable that returns the result of each of the test conducted by
5968 * the driver.
5969 * Description:
20346722 5970 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5971 * register.
5972 * Return value:
5973 * 0 on success.
5974 */
5975
1ee6dd77 5976static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5977{
5978 int fail = 0;
ad4ebed0 5979 u64 ret_data, org_4F0, org_7F0;
5980 u8 saved_4F0 = 0, saved_7F0 = 0;
5981 struct net_device *dev = sp->dev;
1da177e4
LT		 5982
5983 /* Test Write Error at offset 0 */
ad4ebed0 5984 /* Note that SPI interface allows write access to all areas
5985 * of EEPROM. Hence doing all negative testing only for Xframe I.
5986 */
5987 if (sp->device_type == XFRAME_I_DEVICE)
5988 if (!write_eeprom(sp, 0, 0, 3))
5989 fail = 1;
5990
5991 /* Save current values at offsets 0x4F0 and 0x7F0 */
5992 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5993 saved_4F0 = 1;
5994 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5995 saved_7F0 = 1;
1da177e4
LT		 5996
5997 /* Test Write at offset 4f0 */
ad4ebed0 5998 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5999 fail = 1;
6000 if (read_eeprom(sp, 0x4F0, &ret_data))
6001 fail = 1;
6002
ad4ebed0 6003 if (ret_data != 0x012345) {
26b7625c
AM		 6004 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6005 "Data written %llx Data read %llx\n",
6006 dev->name, (unsigned long long)0x12345,
6007 (unsigned long long)ret_data);
1da177e4 6008 fail = 1;
ad4ebed0 6009 }
1da177e4
LT		 6010
6011 /* Reset the EEPROM data go FFFF */
ad4ebed0 6012 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6013
6014 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6015 if (sp->device_type == XFRAME_I_DEVICE)
6016 if (!write_eeprom(sp, 0x07C, 0, 3))
6017 fail = 1;
1da177e4 6018
ad4ebed0 6019 /* Test Write Request at offset 0x7f0 */
6020 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6021 fail = 1;
ad4ebed0 6022 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6023 fail = 1;
6024
ad4ebed0 6025 if (ret_data != 0x012345) {
26b7625c
AM		 6026 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6027 "Data written %llx Data read %llx\n",
6028 dev->name, (unsigned long long)0x12345,
6029 (unsigned long long)ret_data);
1da177e4 6030 fail = 1;
ad4ebed0 6031 }
1da177e4
LT		 6032
6033 /* Reset the EEPROM data go FFFF */
ad4ebed0 6034 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6035
ad4ebed0 6036 if (sp->device_type == XFRAME_I_DEVICE) {
6037 /* Test Write Error at offset 0x80 */
6038 if (!write_eeprom(sp, 0x080, 0, 3))
6039 fail = 1;
1da177e4 6040
ad4ebed0 6041 /* Test Write Error at offset 0xfc */
6042 if (!write_eeprom(sp, 0x0FC, 0, 3))
6043 fail = 1;
1da177e4 6044
ad4ebed0 6045 /* Test Write Error at offset 0x100 */
6046 if (!write_eeprom(sp, 0x100, 0, 3))
6047 fail = 1;
1da177e4 6048
ad4ebed0 6049 /* Test Write Error at offset 4ec */
6050 if (!write_eeprom(sp, 0x4EC, 0, 3))
6051 fail = 1;
6052 }
6053
6054 /* Restore values at offsets 0x4F0 and 0x7F0 */
6055 if (saved_4F0)
6056 write_eeprom(sp, 0x4F0, org_4F0, 3);
6057 if (saved_7F0)
6058 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6059
6060 *data = fail;
ad4ebed0 6061 return fail;
1da177e4
LT		 6062}
6063
6064/**
6065 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6066 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6067 * s2io_nic structure.
20346722 6068 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6069 * the driver.
6070 * Description:
6071 * This invokes the MemBist test of the card. We give around
6072 * 2 secs time for the Test to complete. If it's still not complete
20346722 6073 * within this peiod, we consider that the test failed.
1da177e4
LT		 6074 * Return value:
6075 * 0 on success and -1 on failure.
6076 */
6077
1ee6dd77 6078static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6079{
6080 u8 bist = 0;
6081 int cnt = 0, ret = -1;
6082
6083 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6084 bist |= PCI_BIST_START;
6085 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6086
6087 while (cnt < 20) {
6088 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6089 if (!(bist & PCI_BIST_START)) {
6090 *data = (bist & PCI_BIST_CODE_MASK);
6091 ret = 0;
6092 break;
6093 }
6094 msleep(100);
6095 cnt++;
6096 }
6097
6098 return ret;
6099}
6100
6101/**
20346722
K		 6102 * s2io-link_test - verifies the link state of the nic
6103 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6104 * s2io_nic structure.
6105 * @data: variable that returns the result of each of the test conducted by
6106 * the driver.
6107 * Description:
20346722 6108 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6109 * argument 'data' appropriately.
6110 * Return value:
6111 * 0 on success.
6112 */
6113
1ee6dd77 6114static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6115{
1ee6dd77 6116 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6117 u64 val64;
6118
6119 val64 = readq(&bar0->adapter_status);
c92ca04b 6120 if(!(LINK_IS_UP(val64)))
1da177e4 6121 *data = 1;
c92ca04b
AR		 6122 else
6123 *data = 0;
1da177e4 6124
b41477f3 6125 return *data;
1da177e4
LT		 6126}
6127
6128/**
20346722
K		 6129 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6130 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6131 * s2io_nic structure.
20346722 6132 * @data - variable that returns the result of each of the test
1da177e4
LT		 6133 * conducted by the driver.
6134 * Description:
20346722 6135 * This is one of the offline test that tests the read and write
1da177e4
LT		 6136 * access to the RldRam chip on the NIC.
6137 * Return value:
6138 * 0 on success.
6139 */
6140
1ee6dd77 6141static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6142{
1ee6dd77 6143 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6144 u64 val64;
ad4ebed0 6145 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6146
6147 val64 = readq(&bar0->adapter_control);
6148 val64 &= ~ADAPTER_ECC_EN;
6149 writeq(val64, &bar0->adapter_control);
6150
6151 val64 = readq(&bar0->mc_rldram_test_ctrl);
6152 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6153 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6154
6155 val64 = readq(&bar0->mc_rldram_mrs);
6156 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6157 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6158
6159 val64 |= MC_RLDRAM_MRS_ENABLE;
6160 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6161
6162 while (iteration < 2) {
6163 val64 = 0x55555555aaaa0000ULL;
6164 if (iteration == 1) {
6165 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6166 }
6167 writeq(val64, &bar0->mc_rldram_test_d0);
6168
6169 val64 = 0xaaaa5a5555550000ULL;
6170 if (iteration == 1) {
6171 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6172 }
6173 writeq(val64, &bar0->mc_rldram_test_d1);
6174
6175 val64 = 0x55aaaaaaaa5a0000ULL;
6176 if (iteration == 1) {
6177 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6178 }
6179 writeq(val64, &bar0->mc_rldram_test_d2);
6180
ad4ebed0 6181 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6182 writeq(val64, &bar0->mc_rldram_test_add);
6183
ad4ebed0 6184 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6185 MC_RLDRAM_TEST_GO;
6186 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6187
6188 for (cnt = 0; cnt < 5; cnt++) {
6189 val64 = readq(&bar0->mc_rldram_test_ctrl);
6190 if (val64 & MC_RLDRAM_TEST_DONE)
6191 break;
6192 msleep(200);
6193 }
6194
6195 if (cnt == 5)
6196 break;
6197
ad4ebed0 6198 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6199 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6200
6201 for (cnt = 0; cnt < 5; cnt++) {
6202 val64 = readq(&bar0->mc_rldram_test_ctrl);
6203 if (val64 & MC_RLDRAM_TEST_DONE)
6204 break;
6205 msleep(500);
6206 }
6207
6208 if (cnt == 5)
6209 break;
6210
6211 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6212 if (!(val64 & MC_RLDRAM_TEST_PASS))
6213 test_fail = 1;
1da177e4
LT		 6214
6215 iteration++;
6216 }
6217
ad4ebed0 6218 *data = test_fail;
1da177e4 6219
ad4ebed0 6220 /* Bring the adapter out of test mode */
6221 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6222
6223 return test_fail;
1da177e4
LT		 6224}
6225
6226/**
6227 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6228 * @sp : private member of the device structure, which is a pointer to the
6229 * s2io_nic structure.
6230 * @ethtest : pointer to a ethtool command specific structure that will be
6231 * returned to the user.
20346722 6232 * @data : variable that returns the result of each of the test
1da177e4
LT		 6233 * conducted by the driver.
6234 * Description:
6235 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6236 * the health of the card.
6237 * Return value:
6238 * void
6239 */
6240
6241static void s2io_ethtool_test(struct net_device *dev,
6242 struct ethtool_test *ethtest,
6243 uint64_t * data)
6244{
4cf1653a 6245 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6246 int orig_state = netif_running(sp->dev);
6247
6248 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6249 /* Offline Tests. */
20346722 6250 if (orig_state)
1da177e4 6251 s2io_close(sp->dev);
1da177e4
LT		 6252
6253 if (s2io_register_test(sp, &data[0]))
6254 ethtest->flags |= ETH_TEST_FL_FAILED;
6255
6256 s2io_reset(sp);
1da177e4
LT		 6257
6258 if (s2io_rldram_test(sp, &data[3]))
6259 ethtest->flags |= ETH_TEST_FL_FAILED;
6260
6261 s2io_reset(sp);
1da177e4
LT		 6262
6263 if (s2io_eeprom_test(sp, &data[1]))
6264 ethtest->flags |= ETH_TEST_FL_FAILED;
6265
6266 if (s2io_bist_test(sp, &data[4]))
6267 ethtest->flags |= ETH_TEST_FL_FAILED;
6268
6269 if (orig_state)
6270 s2io_open(sp->dev);
6271
6272 data[2] = 0;
6273 } else {
6274 /* Online Tests. */
6275 if (!orig_state) {
6276 DBG_PRINT(ERR_DBG,
6277 "%s: is not up, cannot run test\n",
6278 dev->name);
6279 data[0] = -1;
6280 data[1] = -1;
6281 data[2] = -1;
6282 data[3] = -1;
6283 data[4] = -1;
6284 }
6285
6286 if (s2io_link_test(sp, &data[2]))
6287 ethtest->flags |= ETH_TEST_FL_FAILED;
6288
6289 data[0] = 0;
6290 data[1] = 0;
6291 data[3] = 0;
6292 data[4] = 0;
6293 }
6294}
6295
6296static void s2io_get_ethtool_stats(struct net_device *dev,
6297 struct ethtool_stats *estats,
6298 u64 * tmp_stats)
6299{
8116f3cf 6300 int i = 0, k;
4cf1653a 6301 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 6302 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6303
7ba013ac 6304 s2io_updt_stats(sp);
541ae68f
K		 6305 tmp_stats[i++] =
6306 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6307 le32_to_cpu(stat_info->tmac_frms);
6308 tmp_stats[i++] =
6309 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6310 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6311 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 6312 tmp_stats[i++] =
6313 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6314 le32_to_cpu(stat_info->tmac_mcst_frms);
6315 tmp_stats[i++] =
6316 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6317 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6318 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 6319 tmp_stats[i++] =
6320 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6321 le32_to_cpu(stat_info->tmac_ttl_octets);
6322 tmp_stats[i++] =
6323 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6324 le32_to_cpu(stat_info->tmac_ucst_frms);
6325 tmp_stats[i++] =
6326 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6327 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 6328 tmp_stats[i++] =
6329 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6330 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 6331 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6332 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 6333 tmp_stats[i++] =
6334 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6335 le32_to_cpu(stat_info->tmac_vld_ip);
6336 tmp_stats[i++] =
6337 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6338 le32_to_cpu(stat_info->tmac_drop_ip);
6339 tmp_stats[i++] =
6340 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6341 le32_to_cpu(stat_info->tmac_icmp);
6342 tmp_stats[i++] =
6343 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6344 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6345 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 6346 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6347 le32_to_cpu(stat_info->tmac_udp);
6348 tmp_stats[i++] =
6349 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6350 le32_to_cpu(stat_info->rmac_vld_frms);
6351 tmp_stats[i++] =
6352 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6353 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6354 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6355 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 6356 tmp_stats[i++] =
6357 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6358 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6359 tmp_stats[i++] =
6360 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6361 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6362 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6363 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6364 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6365 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 6366 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6367 tmp_stats[i++] =
6368 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6369 le32_to_cpu(stat_info->rmac_ttl_octets);
6370 tmp_stats[i++] =
6371 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6372 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6373 tmp_stats[i++] =
6374 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6375 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 6376 tmp_stats[i++] =
6377 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6378 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6379 tmp_stats[i++] =
6380 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6381 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6382 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6383 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 6384 tmp_stats[i++] =
6385 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6386 le32_to_cpu(stat_info->rmac_usized_frms);
6387 tmp_stats[i++] =
6388 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6389 le32_to_cpu(stat_info->rmac_osized_frms);
6390 tmp_stats[i++] =
6391 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6392 le32_to_cpu(stat_info->rmac_frag_frms);
6393 tmp_stats[i++] =
6394 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6395 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6396 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6397 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6398 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6399 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6400 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6401 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6402 tmp_stats[i++] =
6403 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6404 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6405 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6406 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6407 tmp_stats[i++] =
6408 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6409 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6410 tmp_stats[i++] =
6411 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6412 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6413 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6414 tmp_stats[i++] =
6415 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 6416 le32_to_cpu(stat_info->rmac_udp);
6417 tmp_stats[i++] =
6418 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6419 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6420 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6421 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6422 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6423 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6424 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6425 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6426 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6427 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6428 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6429 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6430 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6431 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6432 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6433 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6434 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6435 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6436 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 6437 tmp_stats[i++] =
6438 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6439 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6440 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6441 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 6442 tmp_stats[i++] =
6443 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6444 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6445 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6446 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6447 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6448 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6449 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6450 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6451 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6452 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6453 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6454 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6455 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6456 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6457 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6458 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6459 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6460 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6461 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6462 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6463 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6464
6465 /* Enhanced statistics exist only for Hercules */
6466 if(sp->device_type == XFRAME_II_DEVICE) {
6467 tmp_stats[i++] =
6468 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6469 tmp_stats[i++] =
6470 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6471 tmp_stats[i++] =
6472 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6473 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6474 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6475 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6476 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6477 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6478 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6479 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6480 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6481 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6482 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6483 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6484 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6485 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6486 }
6487
7ba013ac
K		 6488 tmp_stats[i++] = 0;
6489 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6490 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6491 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6492 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6493 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6494 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6495 for (k = 0; k < MAX_RX_RINGS; k++)
6496 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6497 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6498 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6499 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6500 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6501 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6502 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6503 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6504 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6505 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6506 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6507 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6508 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6509 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6510 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6511 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6512 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6513 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6514 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6515 int count = 0;
6aa20a22 6516 /*
bd1034f0
AR		 6517 * Since 64-bit divide does not work on all platforms,
6518 * do repeated subtraction.
6519 */
6520 while (tmp >= stat_info->sw_stat.num_aggregations) {
6521 tmp -= stat_info->sw_stat.num_aggregations;
6522 count++;
6523 }
6524 tmp_stats[i++] = count;
fe931395 6525 }
bd1034f0
AR		 6526 else
6527 tmp_stats[i++] = 0;
c53d4945 6528 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6529 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6530 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6531 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6532 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6533 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6534 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6535 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6536 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6537
6538 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6539 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6540 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6541 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6542 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6543
6544 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6545 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6546 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6547 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6548 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6549 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6550 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6551 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6552 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6553 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6554 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6555 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6556 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6557 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6558 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6559 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6560 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6561 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6562 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6563 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6564 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6565 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6566 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6567 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6568 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6569 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6570}
6571
ac1f60db 6572static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6573{
6574 return (XENA_REG_SPACE);
6575}
6576
6577
ac1f60db 6578static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6579{
4cf1653a 6580 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6581
6582 return (sp->rx_csum);
6583}
ac1f60db
AB		 6584
6585static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6586{
4cf1653a 6587 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6588
6589 if (data)
6590 sp->rx_csum = 1;
6591 else
6592 sp->rx_csum = 0;
6593
6594 return 0;
6595}
ac1f60db
AB		 6596
6597static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6598{
6599 return (XENA_EEPROM_SPACE);
6600}
6601
b9f2c044 6602static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6603{
4cf1653a 6604 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6605
6606 switch (sset) {
6607 case ETH_SS_TEST:
6608 return S2IO_TEST_LEN;
6609 case ETH_SS_STATS:
6610 switch(sp->device_type) {
6611 case XFRAME_I_DEVICE:
6612 return XFRAME_I_STAT_LEN;
6613 case XFRAME_II_DEVICE:
6614 return XFRAME_II_STAT_LEN;
6615 default:
6616 return 0;
6617 }
6618 default:
6619 return -EOPNOTSUPP;
6620 }
1da177e4 6621}
ac1f60db
AB		 6622
6623static void s2io_ethtool_get_strings(struct net_device *dev,
6624 u32 stringset, u8 * data)
1da177e4 6625{
fa1f0cb3 6626 int stat_size = 0;
4cf1653a 6627 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6628
1da177e4
LT		 6629 switch (stringset) {
6630 case ETH_SS_TEST:
6631 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6632 break;
6633 case ETH_SS_STATS:
fa1f0cb3
SS		 6634 stat_size = sizeof(ethtool_xena_stats_keys);
6635 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6636 if(sp->device_type == XFRAME_II_DEVICE) {
6637 memcpy(data + stat_size,
6638 &ethtool_enhanced_stats_keys,
6639 sizeof(ethtool_enhanced_stats_keys));
6640 stat_size += sizeof(ethtool_enhanced_stats_keys);
6641 }
6642
6643 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6644 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6645 }
6646}
1da177e4 6647
ac1f60db 6648static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6649{
6650 if (data)
6651 dev->features |= NETIF_F_IP_CSUM;
6652 else
6653 dev->features &= ~NETIF_F_IP_CSUM;
6654
6655 return 0;
6656}
6657
75c30b13
AR		 6658static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6659{
6660 return (dev->features & NETIF_F_TSO) != 0;
6661}
6662static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6663{
6664 if (data)
6665 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6666 else
6667 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6668
6669 return 0;
6670}
1da177e4 6671
7282d491 6672static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6673 .get_settings = s2io_ethtool_gset,
6674 .set_settings = s2io_ethtool_sset,
6675 .get_drvinfo = s2io_ethtool_gdrvinfo,
6676 .get_regs_len = s2io_ethtool_get_regs_len,
6677 .get_regs = s2io_ethtool_gregs,
6678 .get_link = ethtool_op_get_link,
6679 .get_eeprom_len = s2io_get_eeprom_len,
6680 .get_eeprom = s2io_ethtool_geeprom,
6681 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6682 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6683 .get_pauseparam = s2io_ethtool_getpause_data,
6684 .set_pauseparam = s2io_ethtool_setpause_data,
6685 .get_rx_csum = s2io_ethtool_get_rx_csum,
6686 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6687 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6688 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6689 .get_tso = s2io_ethtool_op_get_tso,
6690 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6691 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6692 .self_test = s2io_ethtool_test,
6693 .get_strings = s2io_ethtool_get_strings,
6694 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6695 .get_ethtool_stats = s2io_get_ethtool_stats,
6696 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6697};
6698
6699/**
20346722 6700 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6701 * @dev : Device pointer.
6702 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6703 * a proprietary structure used to pass information to the driver.
6704 * @cmd : This is used to distinguish between the different commands that
6705 * can be passed to the IOCTL functions.
6706 * Description:
20346722
K		 6707 * Currently there are no special functionality supported in IOCTL, hence
6708 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6709 */
6710
ac1f60db 6711static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6712{
6713 return -EOPNOTSUPP;
6714}
6715
6716/**
6717 * s2io_change_mtu - entry point to change MTU size for the device.
6718 * @dev : device pointer.
6719 * @new_mtu : the new MTU size for the device.
6720 * Description: A driver entry point to change MTU size for the device.
6721 * Before changing the MTU the device must be stopped.
6722 * Return value:
6723 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6724 * file on failure.
6725 */
6726
ac1f60db 6727static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6728{
4cf1653a 6729 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6730 int ret = 0;
1da177e4
LT		 6731
6732 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6733 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6734 dev->name);
6735 return -EPERM;
6736 }
6737
1da177e4 6738 dev->mtu = new_mtu;
d8892c6e 6739 if (netif_running(dev)) {
3a3d5756 6740 s2io_stop_all_tx_queue(sp);
e6a8fee2 6741 s2io_card_down(sp);
9f74ffde
SH		 6742 ret = s2io_card_up(sp);
6743 if (ret) {
d8892c6e 6744 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6745 __func__);
9f74ffde 6746 return ret;
d8892c6e 6747 }
3a3d5756 6748 s2io_wake_all_tx_queue(sp);
d8892c6e 6749 } else { /* Device is down */
1ee6dd77 6750 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6751 u64 val64 = new_mtu;
6752
6753 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6754 }
1da177e4 6755
9f74ffde 6756 return ret;
1da177e4
LT		 6757}
6758
1da177e4
LT		 6759/**
6760 * s2io_set_link - Set the LInk status
6761 * @data: long pointer to device private structue
6762 * Description: Sets the link status for the adapter
6763 */
6764
c4028958 6765static void s2io_set_link(struct work_struct *work)
1da177e4 6766{
1ee6dd77 6767 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6768 struct net_device *dev = nic->dev;
1ee6dd77 6769 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6770 register u64 val64;
6771 u16 subid;
6772
22747d6b
FR		 6773 rtnl_lock();
6774
6775 if (!netif_running(dev))
6776 goto out_unlock;
6777
92b84437 6778 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6779 /* The card is being reset, no point doing anything */
22747d6b 6780 goto out_unlock;
1da177e4
LT		 6781 }
6782
6783 subid = nic->pdev->subsystem_device;
a371a07d
K		 6784 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6785 /*
6786 * Allow a small delay for the NICs self initiated
6787 * cleanup to complete.
6788 */
6789 msleep(100);
6790 }
1da177e4
LT		 6791
6792 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6793 if (LINK_IS_UP(val64)) {
6794 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6795 if (verify_xena_quiescence(nic)) {
6796 val64 = readq(&bar0->adapter_control);
6797 val64 |= ADAPTER_CNTL_EN;
1da177e4 6798 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6799 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6800 nic->device_type, subid)) {
6801 val64 = readq(&bar0->gpio_control);
6802 val64 |= GPIO_CTRL_GPIO_0;
6803 writeq(val64, &bar0->gpio_control);
6804 val64 = readq(&bar0->gpio_control);
6805 } else {
6806 val64 |= ADAPTER_LED_ON;
6807 writeq(val64, &bar0->adapter_control);
a371a07d 6808 }
f957bcf0 6809 nic->device_enabled_once = true;
19a60522
SS		 6810 } else {
6811 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6812 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6813 s2io_stop_all_tx_queue(nic);
1da177e4 6814 }
19a60522 6815 }
92c48799
SS		 6816 val64 = readq(&bar0->adapter_control);
6817 val64 |= ADAPTER_LED_ON;
6818 writeq(val64, &bar0->adapter_control);
6819 s2io_link(nic, LINK_UP);
19a60522
SS		 6820 } else {
6821 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6822 subid)) {
6823 val64 = readq(&bar0->gpio_control);
6824 val64 &= ~GPIO_CTRL_GPIO_0;
6825 writeq(val64, &bar0->gpio_control);
6826 val64 = readq(&bar0->gpio_control);
1da177e4 6827 }
92c48799
SS		 6828 /* turn off LED */
6829 val64 = readq(&bar0->adapter_control);
6830 val64 = val64 &(~ADAPTER_LED_ON);
6831 writeq(val64, &bar0->adapter_control);
19a60522 6832 s2io_link(nic, LINK_DOWN);
1da177e4 6833 }
92b84437 6834 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6835
6836out_unlock:
d8d70caf 6837 rtnl_unlock();
1da177e4
LT		 6838}
6839
1ee6dd77
RB		 6840static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6841 struct buffAdd *ba,
6842 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6843 u64 *temp2, int size)
5d3213cc
AR		 6844{
6845 struct net_device *dev = sp->dev;
491abf25 6846 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6847
6848 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6849 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6850 /* allocate skb */
6851 if (*skb) {
6852 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6853 /*
6854 * As Rx frame are not going to be processed,
6855 * using same mapped address for the Rxd
6856 * buffer pointer
6857 */
6d517a27 6858 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6859 } else {
6860 *skb = dev_alloc_skb(size);
6861 if (!(*skb)) {
0c61ed5f 6862 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6863 DBG_PRINT(INFO_DBG, "memory to allocate ");
6864 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6865 sp->mac_control.stats_info->sw_stat. \
6866 mem_alloc_fail_cnt++;
5d3213cc
AR		 6867 return -ENOMEM ;
6868 }
8a4bdbaa 6869 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6870 += (*skb)->truesize;
5d3213cc
AR		 6871 /* storing the mapped addr in a temp variable
6872 * such it will be used for next rxd whose
6873 * Host Control is NULL
6874 */
6d517a27 6875 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6876 pci_map_single( sp->pdev, (*skb)->data,
6877 size - NET_IP_ALIGN,
6878 PCI_DMA_FROMDEVICE);
8d8bb39b 6879 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6880 goto memalloc_failed;
5d3213cc
AR		 6881 rxdp->Host_Control = (unsigned long) (*skb);
6882 }
6883 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6884 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6885 /* Two buffer Mode */
6886 if (*skb) {
6d517a27
VP		 6887 rxdp3->Buffer2_ptr = *temp2;
6888 rxdp3->Buffer0_ptr = *temp0;
6889 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6890 } else {
6891 *skb = dev_alloc_skb(size);
2ceaac75 6892 if (!(*skb)) {
c53d4945
SH		 6893 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6894 DBG_PRINT(INFO_DBG, "memory to allocate ");
6895 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6896 sp->mac_control.stats_info->sw_stat. \
6897 mem_alloc_fail_cnt++;
2ceaac75
DR		 6898 return -ENOMEM;
6899 }
8a4bdbaa 6900 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6901 += (*skb)->truesize;
6d517a27 6902 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6903 pci_map_single(sp->pdev, (*skb)->data,
6904 dev->mtu + 4,
6905 PCI_DMA_FROMDEVICE);
8d8bb39b 6906 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6907 goto memalloc_failed;
6d517a27 6908 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6909 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6910 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 6911 if (pci_dma_mapping_error(sp->pdev,
6912 rxdp3->Buffer0_ptr)) {
491abf25 6913 pci_unmap_single (sp->pdev,
3e847423 6914 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6915 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6916 goto memalloc_failed;
6917 }
5d3213cc
AR		 6918 rxdp->Host_Control = (unsigned long) (*skb);
6919
6920 /* Buffer-1 will be dummy buffer not used */
6d517a27 6921 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6922 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6923 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 6924 if (pci_dma_mapping_error(sp->pdev,
6925 rxdp3->Buffer1_ptr)) {
491abf25 6926 pci_unmap_single (sp->pdev,
3e847423
AV		 6927 (dma_addr_t)rxdp3->Buffer0_ptr,
6928 BUF0_LEN, PCI_DMA_FROMDEVICE);
6929 pci_unmap_single (sp->pdev,
6930 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6931 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6932 goto memalloc_failed;
6933 }
5d3213cc
AR		 6934 }
6935 }
6936 return 0;
491abf25
VP		 6937 memalloc_failed:
6938 stats->pci_map_fail_cnt++;
6939 stats->mem_freed += (*skb)->truesize;
6940 dev_kfree_skb(*skb);
6941 return -ENOMEM;
5d3213cc 6942}
491abf25 6943
1ee6dd77
RB		 6944static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6945 int size)
5d3213cc
AR		 6946{
6947 struct net_device *dev = sp->dev;
6948 if (sp->rxd_mode == RXD_MODE_1) {
6949 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6950 } else if (sp->rxd_mode == RXD_MODE_3B) {
6951 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6952 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6953 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6954 }
6955}
6956
1ee6dd77 6957static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6958{
6959 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6960 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6961 struct config_param *config = &sp->config;
6962 struct net_device *dev = sp->dev;
1ee6dd77 6963 struct RxD_t *rxdp = NULL;
5d3213cc 6964 struct sk_buff *skb = NULL;
1ee6dd77 6965 struct buffAdd *ba = NULL;
5d3213cc
AR		 6966 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6967
6968 /* Calculate the size based on ring mode */
6969 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6970 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6971 if (sp->rxd_mode == RXD_MODE_1)
6972 size += NET_IP_ALIGN;
6973 else if (sp->rxd_mode == RXD_MODE_3B)
6974 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6975
6976 for (i = 0; i < config->rx_ring_num; i++) {
6977 blk_cnt = config->rx_cfg[i].num_rxd /
6978 (rxd_count[sp->rxd_mode] +1);
6979
6980 for (j = 0; j < blk_cnt; j++) {
6981 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6982 rxdp = mac_control->rings[i].
6983 rx_blocks[j].rxds[k].virt_addr;
6d517a27 6984 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 6985 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6986 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6987 &skb,(u64 *)&temp0_64,
6988 (u64 *)&temp1_64,
ac1f90d6 6989 (u64 *)&temp2_64,
20cbe73c 6990 size) == -ENOMEM) {
ac1f90d6
SS		 6991 return 0;
6992 }
5d3213cc
AR		 6993
6994 set_rxd_buffer_size(sp, rxdp, size);
6995 wmb();
6996 /* flip the Ownership bit to Hardware */
6997 rxdp->Control_1 |= RXD_OWN_XENA;
6998 }
6999 }
7000 }
7001 return 0;
7002
7003}
7004
1ee6dd77 7005static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 7006{
e6a8fee2 7007 int ret = 0;
c92ca04b 7008 struct net_device *dev = sp->dev;
e6a8fee2 7009 int err = 0;
1da177e4 7010
eaae7f72 7011 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7012 ret = s2io_enable_msi_x(sp);
7013 if (ret) {
7014 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7015 sp->config.intr_type = INTA;
20346722 7016 }
1da177e4 7017
1ee6dd77 7018 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 7019 store_xmsi_data(sp);
c92ca04b 7020
e6a8fee2 7021 /* After proper initialization of H/W, register ISR */
eaae7f72 7022 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7023 int i, msix_rx_cnt = 0;
7024
f61e0a35
SH		 7025 for (i = 0; i < sp->num_entries; i++) {
7026 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7027 if (sp->s2io_entries[i].type ==
ac731ab6
SH		 7028 MSIX_RING_TYPE) {
7029 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7030 dev->name, i);
7031 err = request_irq(sp->entries[i].vector,
7032 s2io_msix_ring_handle, 0,
7033 sp->desc[i],
7034 sp->s2io_entries[i].arg);
7035 } else if (sp->s2io_entries[i].type ==
7036 MSIX_ALARM_TYPE) {
7037 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
e6a8fee2 7038 dev->name, i);
ac731ab6
SH		 7039 err = request_irq(sp->entries[i].vector,
7040 s2io_msix_fifo_handle, 0,
7041 sp->desc[i],
7042 sp->s2io_entries[i].arg);
7043
fb6a825b 7044 }
ac731ab6
SH		 7045 /* if either data or addr is zero print it. */
7046 if (!(sp->msix_info[i].addr &&
fb6a825b 7047 sp->msix_info[i].data)) {
ac731ab6
SH		 7048 DBG_PRINT(ERR_DBG,
7049 "%s @Addr:0x%llx Data:0x%llx\n",
7050 sp->desc[i],
fb6a825b
SS		 7051 (unsigned long long)
7052 sp->msix_info[i].addr,
3459feb8 7053 (unsigned long long)
ac731ab6
SH		 7054 ntohl(sp->msix_info[i].data));
7055 } else
fb6a825b 7056 msix_rx_cnt++;
ac731ab6
SH		 7057 if (err) {
7058 remove_msix_isr(sp);
7059
7060 DBG_PRINT(ERR_DBG,
7061 "%s:MSI-X-%d registration "
7062 "failed\n", dev->name, i);
7063
7064 DBG_PRINT(ERR_DBG,
7065 "%s: Defaulting to INTA\n",
7066 dev->name);
7067 sp->config.intr_type = INTA;
7068 break;
fb6a825b 7069 }
ac731ab6
SH		 7070 sp->s2io_entries[i].in_use =
7071 MSIX_REGISTERED_SUCCESS;
c92ca04b 7072 }
e6a8fee2 7073 }
18b2b7bd 7074 if (!err) {
18b2b7bd 7075 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
ac731ab6
SH		 7076 --msix_rx_cnt);
7077 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7078 " through alarm vector\n");
18b2b7bd 7079 }
e6a8fee2 7080 }
eaae7f72 7081 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 7082 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7083 sp->name, dev);
7084 if (err) {
7085 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7086 dev->name);
7087 return -1;
7088 }
7089 }
7090 return 0;
7091}
1ee6dd77 7092static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 7093{
18b2b7bd
SH		 7094 if (sp->config.intr_type == MSI_X)
7095 remove_msix_isr(sp);
7096 else
7097 remove_inta_isr(sp);
e6a8fee2
AR		 7098}
7099
d796fdb7 7100static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 7101{
7102 int cnt = 0;
1ee6dd77 7103 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7104 register u64 val64 = 0;
5f490c96
SH		 7105 struct config_param *config;
7106 config = &sp->config;
e6a8fee2 7107
9f74ffde
SH		 7108 if (!is_s2io_card_up(sp))
7109 return;
7110
e6a8fee2
AR		 7111 del_timer_sync(&sp->alarm_timer);
7112 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 7113 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 7114 msleep(50);
7115 }
92b84437 7116 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7117
5f490c96 7118 /* Disable napi */
f61e0a35
SH		 7119 if (sp->config.napi) {
7120 int off = 0;
7121 if (config->intr_type == MSI_X) {
7122 for (; off < sp->config.rx_ring_num; off++)
7123 napi_disable(&sp->mac_control.rings[off].napi);
7124 }
7125 else
7126 napi_disable(&sp->napi);
7127 }
5f490c96 7128
e6a8fee2 7129 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7130 if (do_io)
7131 stop_nic(sp);
e6a8fee2
AR		 7132
7133 s2io_rem_isr(sp);
1da177e4 7134
01e16faa
SH		 7135 /* stop the tx queue, indicate link down */
7136 s2io_link(sp, LINK_DOWN);
7137
1da177e4 7138 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 7139 while(do_io) {
5d3213cc
AR		 7140 /* As per the HW requirement we need to replenish the
7141 * receive buffer to avoid the ring bump. Since there is
7142 * no intention of processing the Rx frame at this pointwe are
7143 * just settting the ownership bit of rxd in Each Rx
7144 * ring to HW and set the appropriate buffer size
7145 * based on the ring mode
7146 */
7147 rxd_owner_bit_reset(sp);
7148
1da177e4 7149 val64 = readq(&bar0->adapter_status);
19a60522
SS		 7150 if (verify_xena_quiescence(sp)) {
7151 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 7152 break;
7153 }
7154
7155 msleep(50);
7156 cnt++;
7157 if (cnt == 10) {
7158 DBG_PRINT(ERR_DBG,
7159 "s2io_close:Device not Quiescent ");
7160 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7161 (unsigned long long) val64);
7162 break;
7163 }
d796fdb7
LV		 7164 }
7165 if (do_io)
7166 s2io_reset(sp);
1da177e4 7167
7ba013ac 7168 /* Free all Tx buffers */
1da177e4 7169 free_tx_buffers(sp);
7ba013ac
K		 7170
7171 /* Free all Rx buffers */
1da177e4
LT		 7172 free_rx_buffers(sp);
7173
92b84437 7174 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7175}
7176
d796fdb7
LV		 7177static void s2io_card_down(struct s2io_nic * sp)
7178{
7179 do_s2io_card_down(sp, 1);
7180}
7181
1ee6dd77 7182static int s2io_card_up(struct s2io_nic * sp)
1da177e4 7183{
cc6e7c44 7184 int i, ret = 0;
1ee6dd77 7185 struct mac_info *mac_control;
1da177e4
LT		 7186 struct config_param *config;
7187 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 7188 u16 interruptible;
1da177e4
LT		 7189
7190 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7191 ret = init_nic(sp);
7192 if (ret != 0) {
1da177e4
LT		 7193 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7194 dev->name);
9f74ffde
SH		 7195 if (ret != -EIO)
7196 s2io_reset(sp);
7197 return ret;
1da177e4
LT		 7198 }
7199
20346722
K		 7200 /*
7201 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7202 * Rx ring and initializing buffers into 30 Rx blocks
7203 */
7204 mac_control = &sp->mac_control;
7205 config = &sp->config;
7206
7207 for (i = 0; i < config->rx_ring_num; i++) {
0425b46a 7208 mac_control->rings[i].mtu = dev->mtu;
8d8bb39b 7209 ret = fill_rx_buffers(sp, &mac_control->rings[i], 1);
0425b46a 7210 if (ret) {
1da177e4
LT		 7211 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7212 dev->name);
7213 s2io_reset(sp);
7214 free_rx_buffers(sp);
7215 return -ENOMEM;
7216 }
7217 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
0425b46a 7218 mac_control->rings[i].rx_bufs_left);
1da177e4 7219 }
5f490c96
SH		 7220
7221 /* Initialise napi */
f61e0a35 7222 if (config->napi) {
f61e0a35
SH		 7223 if (config->intr_type == MSI_X) {
7224 for (i = 0; i < sp->config.rx_ring_num; i++)
7225 napi_enable(&sp->mac_control.rings[i].napi);
7226 } else {
7227 napi_enable(&sp->napi);
7228 }
7229 }
5f490c96 7230
19a60522
SS		 7231 /* Maintain the state prior to the open */
7232 if (sp->promisc_flg)
7233 sp->promisc_flg = 0;
7234 if (sp->m_cast_flg) {
7235 sp->m_cast_flg = 0;
7236 sp->all_multi_pos= 0;
7237 }
1da177e4
LT		 7238
7239 /* Setting its receive mode */
7240 s2io_set_multicast(dev);
7241
7d3d0439 7242 if (sp->lro) {
b41477f3 7243 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 7244 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7245 /* Check if we can use(if specified) user provided value */
7246 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7247 sp->lro_max_aggr_per_sess = lro_max_pkts;
7248 }
7249
1da177e4
LT		 7250 /* Enable Rx Traffic and interrupts on the NIC */
7251 if (start_nic(sp)) {
7252 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7253 s2io_reset(sp);
e6a8fee2
AR		 7254 free_rx_buffers(sp);
7255 return -ENODEV;
7256 }
7257
7258 /* Add interrupt service routine */
7259 if (s2io_add_isr(sp) != 0) {
eaae7f72 7260 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7261 s2io_rem_isr(sp);
7262 s2io_reset(sp);
1da177e4
LT		 7263 free_rx_buffers(sp);
7264 return -ENODEV;
7265 }
7266
25fff88e
K		 7267 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7268
01e16faa
SH		 7269 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7270
e6a8fee2 7271 /* Enable select interrupts */
9caab458 7272 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7273 if (sp->config.intr_type != INTA) {
7274 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7275 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7276 } else {
e6a8fee2 7277 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7278 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7279 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7280 }
7281
1da177e4
LT		 7282 return 0;
7283}
7284
20346722 7285/**
1da177e4
LT		 7286 * s2io_restart_nic - Resets the NIC.
7287 * @data : long pointer to the device private structure
7288 * Description:
7289 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7290 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7291 * the run time of the watch dog routine which is run holding a
7292 * spin lock.
7293 */
7294
c4028958 7295static void s2io_restart_nic(struct work_struct *work)
1da177e4 7296{
1ee6dd77 7297 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7298 struct net_device *dev = sp->dev;
1da177e4 7299
22747d6b
FR		 7300 rtnl_lock();
7301
7302 if (!netif_running(dev))
7303 goto out_unlock;
7304
e6a8fee2 7305 s2io_card_down(sp);
1da177e4
LT		 7306 if (s2io_card_up(sp)) {
7307 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7308 dev->name);
7309 }
3a3d5756 7310 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7311 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7312 dev->name);
22747d6b
FR		 7313out_unlock:
7314 rtnl_unlock();
1da177e4
LT		 7315}
7316
20346722
K		 7317/**
7318 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7319 * @dev : Pointer to net device structure
7320 * Description:
7321 * This function is triggered if the Tx Queue is stopped
7322 * for a pre-defined amount of time when the Interface is still up.
7323 * If the Interface is jammed in such a situation, the hardware is
7324 * reset (by s2io_close) and restarted again (by s2io_open) to
7325 * overcome any problem that might have been caused in the hardware.
7326 * Return value:
7327 * void
7328 */
7329
7330static void s2io_tx_watchdog(struct net_device *dev)
7331{
4cf1653a 7332 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 7333
7334 if (netif_carrier_ok(dev)) {
c53d4945 7335 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7336 schedule_work(&sp->rst_timer_task);
bd1034f0 7337 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7338 }
7339}
7340
7341/**
7342 * rx_osm_handler - To perform some OS related operations on SKB.
7343 * @sp: private member of the device structure,pointer to s2io_nic structure.
7344 * @skb : the socket buffer pointer.
7345 * @len : length of the packet
7346 * @cksum : FCS checksum of the frame.
7347 * @ring_no : the ring from which this RxD was extracted.
20346722 7348 * Description:
b41477f3 7349 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7350 * some OS related operations on the SKB before passing it to the upper
7351 * layers. It mainly checks if the checksum is OK, if so adds it to the
7352 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7353 * to the upper layer. If the checksum is wrong, it increments the Rx
7354 * packet error count, frees the SKB and returns error.
7355 * Return value:
7356 * SUCCESS on success and -1 on failure.
7357 */
1ee6dd77 7358static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7359{
1ee6dd77 7360 struct s2io_nic *sp = ring_data->nic;
0425b46a 7361 struct net_device *dev = (struct net_device *) ring_data->dev;
20346722
K		 7362 struct sk_buff *skb = (struct sk_buff *)
7363 ((unsigned long) rxdp->Host_Control);
7364 int ring_no = ring_data->ring_no;
1da177e4 7365 u16 l3_csum, l4_csum;
863c11a9 7366 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7367 struct lro *uninitialized_var(lro);
f9046eb3 7368 u8 err_mask;
da6971d8 7369
20346722 7370 skb->dev = dev;
c92ca04b 7371
863c11a9 7372 if (err) {
bd1034f0
AR		 7373 /* Check for parity error */
7374 if (err & 0x1) {
7375 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7376 }
f9046eb3
OH		 7377 err_mask = err >> 48;
7378 switch(err_mask) {
491976b2
SH		 7379 case 1:
7380 sp->mac_control.stats_info->sw_stat.
7381 rx_parity_err_cnt++;
7382 break;
7383
7384 case 2:
7385 sp->mac_control.stats_info->sw_stat.
7386 rx_abort_cnt++;
7387 break;
7388
7389 case 3:
7390 sp->mac_control.stats_info->sw_stat.
7391 rx_parity_abort_cnt++;
7392 break;
7393
7394 case 4:
7395 sp->mac_control.stats_info->sw_stat.
7396 rx_rda_fail_cnt++;
7397 break;
7398
7399 case 5:
7400 sp->mac_control.stats_info->sw_stat.
7401 rx_unkn_prot_cnt++;
7402 break;
7403
7404 case 6:
7405 sp->mac_control.stats_info->sw_stat.
7406 rx_fcs_err_cnt++;
7407 break;
bd1034f0 7408
491976b2
SH		 7409 case 7:
7410 sp->mac_control.stats_info->sw_stat.
7411 rx_buf_size_err_cnt++;
7412 break;
7413
7414 case 8:
7415 sp->mac_control.stats_info->sw_stat.
7416 rx_rxd_corrupt_cnt++;
7417 break;
7418
7419 case 15:
7420 sp->mac_control.stats_info->sw_stat.
7421 rx_unkn_err_cnt++;
7422 break;
7423 }
863c11a9
AR		 7424 /*
7425 * Drop the packet if bad transfer code. Exception being
7426 * 0x5, which could be due to unsupported IPv6 extension header.
7427 * In this case, we let stack handle the packet.
7428 * Note that in this case, since checksum will be incorrect,
7429 * stack will validate the same.
7430 */
f9046eb3
OH		 7431 if (err_mask != 0x5) {
7432 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7433 dev->name, err_mask);
dc56e634 7434 dev->stats.rx_crc_errors++;
8a4bdbaa 7435 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7436 += skb->truesize;
863c11a9 7437 dev_kfree_skb(skb);
0425b46a 7438 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7439 rxdp->Host_Control = 0;
7440 return 0;
7441 }
20346722 7442 }
1da177e4 7443
20346722 7444 /* Updating statistics */
0425b46a 7445 ring_data->rx_packets++;
20346722 7446 rxdp->Host_Control = 0;
da6971d8
AR		 7447 if (sp->rxd_mode == RXD_MODE_1) {
7448 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7449
0425b46a 7450 ring_data->rx_bytes += len;
da6971d8
AR		 7451 skb_put(skb, len);
7452
6d517a27 7453 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7454 int get_block = ring_data->rx_curr_get_info.block_index;
7455 int get_off = ring_data->rx_curr_get_info.offset;
7456 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7457 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7458 unsigned char *buff = skb_push(skb, buf0_len);
7459
1ee6dd77 7460 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7461 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7462 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7463 skb_put(skb, buf2_len);
da6971d8 7464 }
20346722 7465
0425b46a
SH		 7466 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7467 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7468 (sp->rx_csum)) {
7469 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7470 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7471 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7472 /*
1da177e4
LT		 7473 * NIC verifies if the Checksum of the received
7474 * frame is Ok or not and accordingly returns
7475 * a flag in the RxD.
7476 */
7477 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7478 if (ring_data->lro) {
7d3d0439
RA		 7479 u32 tcp_len;
7480 u8 *tcp;
7481 int ret = 0;
7482
0425b46a
SH		 7483 ret = s2io_club_tcp_session(ring_data,
7484 skb->data, &tcp, &tcp_len, &lro,
7485 rxdp, sp);
7d3d0439
RA		 7486 switch (ret) {
7487 case 3: /* Begin anew */
7488 lro->parent = skb;
7489 goto aggregate;
7490 case 1: /* Aggregate */
7491 {
7492 lro_append_pkt(sp, lro,
7493 skb, tcp_len);
7494 goto aggregate;
7495 }
7496 case 4: /* Flush session */
7497 {
7498 lro_append_pkt(sp, lro,
7499 skb, tcp_len);
cdb5bf02
SH		 7500 queue_rx_frame(lro->parent,
7501 lro->vlan_tag);
7d3d0439
RA		 7502 clear_lro_session(lro);
7503 sp->mac_control.stats_info->
7504 sw_stat.flush_max_pkts++;
7505 goto aggregate;
7506 }
7507 case 2: /* Flush both */
7508 lro->parent->data_len =
7509 lro->frags_len;
7510 sp->mac_control.stats_info->
7511 sw_stat.sending_both++;
cdb5bf02
SH		 7512 queue_rx_frame(lro->parent,
7513 lro->vlan_tag);
7d3d0439
RA		 7514 clear_lro_session(lro);
7515 goto send_up;
7516 case 0: /* sessions exceeded */
c92ca04b
AR		 7517 case -1: /* non-TCP or not
7518 * L2 aggregatable
7519 */
7d3d0439
RA		 7520 case 5: /*
7521 * First pkt in session not
7522 * L3/L4 aggregatable
7523 */
7524 break;
7525 default:
7526 DBG_PRINT(ERR_DBG,
7527 "%s: Samadhana!!\n",
b39d66a8 7528 __func__);
7d3d0439
RA		 7529 BUG();
7530 }
7531 }
1da177e4 7532 } else {
20346722
K		 7533 /*
7534 * Packet with erroneous checksum, let the
1da177e4
LT		 7535 * upper layers deal with it.
7536 */
7537 skb->ip_summed = CHECKSUM_NONE;
7538 }
cdb5bf02 7539 } else
1da177e4 7540 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7541
491976b2 7542 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439 7543send_up:
0c8dfc83 7544 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7545 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7546aggregate:
0425b46a 7547 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7548 return SUCCESS;
7549}
7550
7551/**
7552 * s2io_link - stops/starts the Tx queue.
7553 * @sp : private member of the device structure, which is a pointer to the
7554 * s2io_nic structure.
7555 * @link : inidicates whether link is UP/DOWN.
7556 * Description:
7557 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7558 * status of the NIC is is down or up. This is called by the Alarm
7559 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7560 * Return value:
7561 * void.
7562 */
7563
1ee6dd77 7564static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7565{
7566 struct net_device *dev = (struct net_device *) sp->dev;
7567
7568 if (link != sp->last_link_state) {
b7c5678f 7569 init_tti(sp, link);
1da177e4
LT		 7570 if (link == LINK_DOWN) {
7571 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7572 s2io_stop_all_tx_queue(sp);
1da177e4 7573 netif_carrier_off(dev);
491976b2 7574 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7575 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7576 jiffies - sp->start_time;
7577 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7578 } else {
7579 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7580 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7581 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7582 jiffies - sp->start_time;
7583 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4 7584 netif_carrier_on(dev);
3a3d5756 7585 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7586 }
7587 }
7588 sp->last_link_state = link;
491976b2 7589 sp->start_time = jiffies;
1da177e4
LT		 7590}
7591
20346722
K		 7592/**
7593 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7594 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7595 * s2io_nic structure.
7596 * Description:
7597 * This function initializes a few of the PCI and PCI-X configuration registers
7598 * with recommended values.
7599 * Return value:
7600 * void
7601 */
7602
1ee6dd77 7603static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7604{
20346722 7605 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7606
7607 /* Enable Data Parity Error Recovery in PCI-X command register. */
7608 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7609 &(pcix_cmd));
1da177e4 7610 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7611 (pcix_cmd | 1));
1da177e4 7612 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7613 &(pcix_cmd));
1da177e4
LT		 7614
7615 /* Set the PErr Response bit in PCI command register. */
7616 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7617 pci_write_config_word(sp->pdev, PCI_COMMAND,
7618 (pci_cmd | PCI_COMMAND_PARITY));
7619 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7620}
7621
3a3d5756
SH		 7622static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7623 u8 *dev_multiq)
9dc737a7 7624{
2fda096d 7625 if ((tx_fifo_num > MAX_TX_FIFOS) ||
6cfc482b 7626 (tx_fifo_num < 1)) {
2fda096d
SR		 7627 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7628 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7629
7630 if (tx_fifo_num < 1)
7631 tx_fifo_num = 1;
7632 else
7633 tx_fifo_num = MAX_TX_FIFOS;
7634
2fda096d
SR		 7635 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7636 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7637 }
2fda096d 7638
6cfc482b 7639 if (multiq)
3a3d5756 7640 *dev_multiq = multiq;
6cfc482b
SH		 7641
7642 if (tx_steering_type && (1 == tx_fifo_num)) {
7643 if (tx_steering_type != TX_DEFAULT_STEERING)
7644 DBG_PRINT(ERR_DBG,
7645 "s2io: Tx steering is not supported with "
7646 "one fifo. Disabling Tx steering.\n");
7647 tx_steering_type = NO_STEERING;
7648 }
7649
7650 if ((tx_steering_type < NO_STEERING) ||
7651 (tx_steering_type > TX_DEFAULT_STEERING)) {
7652 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7653 "supported\n");
7654 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7655 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7656 }
7657
0425b46a
SH		 7658 if (rx_ring_num > MAX_RX_RINGS) {
7659 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
9dc737a7 7660 "supported\n");
0425b46a
SH		 7661 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7662 MAX_RX_RINGS);
7663 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7664 }
0425b46a 7665
eccb8628 7666 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7667 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7668 "Defaulting to INTA\n");
7669 *dev_intr_type = INTA;
7670 }
596c5c97 7671
9dc737a7
AR		 7672 if ((*dev_intr_type == MSI_X) &&
7673 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7674 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7675 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7676 "Defaulting to INTA\n");
7677 *dev_intr_type = INTA;
7678 }
fb6a825b 7679
6d517a27 7680 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7681 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7682 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7683 rx_ring_mode = 1;
9dc737a7
AR		 7684 }
7685 return SUCCESS;
7686}
7687
9fc93a41
SS		 7688/**
7689 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7690 * or Traffic class respectively.
b7c5678f 7691 * @nic: device private variable
9fc93a41
SS		 7692 * Description: The function configures the receive steering to
7693 * desired receive ring.
7694 * Return Value: SUCCESS on success and
7695 * '-1' on failure (endian settings incorrect).
7696 */
7697static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7698{
7699 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7700 register u64 val64 = 0;
7701
7702 if (ds_codepoint > 63)
7703 return FAILURE;
7704
7705 val64 = RTS_DS_MEM_DATA(ring);
7706 writeq(val64, &bar0->rts_ds_mem_data);
7707
7708 val64 = RTS_DS_MEM_CTRL_WE |
7709 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7710 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7711
7712 writeq(val64, &bar0->rts_ds_mem_ctrl);
7713
7714 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7715 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7716 S2IO_BIT_RESET);
7717}
7718
04025095
SH		 7719static const struct net_device_ops s2io_netdev_ops = {
7720 .ndo_open = s2io_open,
7721 .ndo_stop = s2io_close,
7722 .ndo_get_stats = s2io_get_stats,
7723 .ndo_start_xmit = s2io_xmit,
7724 .ndo_validate_addr = eth_validate_addr,
7725 .ndo_set_multicast_list = s2io_set_multicast,
7726 .ndo_do_ioctl = s2io_ioctl,
7727 .ndo_set_mac_address = s2io_set_mac_addr,
7728 .ndo_change_mtu = s2io_change_mtu,
7729 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7730 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7731 .ndo_tx_timeout = s2io_tx_watchdog,
7732#ifdef CONFIG_NET_POLL_CONTROLLER
7733 .ndo_poll_controller = s2io_netpoll,
7734#endif
7735};
7736
1da177e4 7737/**
20346722 7738 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7739 * @pdev : structure containing the PCI related information of the device.
7740 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7741 * Description:
7742 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7743 * All OS related initialization including memory and device structure and
7744 * initlaization of the device private variable is done. Also the swapper
7745 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7746 * registers of the device.
7747 * Return value:
7748 * returns 0 on success and negative on failure.
7749 */
7750
7751static int __devinit
7752s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7753{
1ee6dd77 7754 struct s2io_nic *sp;
1da177e4 7755 struct net_device *dev;
1da177e4 7756 int i, j, ret;
f957bcf0 7757 int dma_flag = false;
1da177e4
LT		 7758 u32 mac_up, mac_down;
7759 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7760 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7761 u16 subid;
1ee6dd77 7762 struct mac_info *mac_control;
1da177e4 7763 struct config_param *config;
541ae68f 7764 int mode;
cc6e7c44 7765 u8 dev_intr_type = intr_type;
3a3d5756 7766 u8 dev_multiq = 0;
1da177e4 7767
3a3d5756
SH		 7768 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7769 if (ret)
9dc737a7 7770 return ret;
1da177e4
LT		 7771
7772 if ((ret = pci_enable_device(pdev))) {
7773 DBG_PRINT(ERR_DBG,
7774 "s2io_init_nic: pci_enable_device failed\n");
7775 return ret;
7776 }
7777
6a35528a 7778 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7779 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
f957bcf0 7780 dma_flag = true;
1da177e4 7781 if (pci_set_consistent_dma_mask
6a35528a 7782 (pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 7783 DBG_PRINT(ERR_DBG,
7784 "Unable to obtain 64bit DMA for \
7785 consistent allocations\n");
7786 pci_disable_device(pdev);
7787 return -ENOMEM;
7788 }
284901a9 7789 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 7790 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7791 } else {
7792 pci_disable_device(pdev);
7793 return -ENOMEM;
7794 }
eccb8628 7795 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
b39d66a8 7796 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __func__, ret);
eccb8628
VP		 7797 pci_disable_device(pdev);
7798 return -ENODEV;
1da177e4 7799 }
3a3d5756 7800 if (dev_multiq)
6cfc482b 7801 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7802 else
b19fa1fa 7803 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7804 if (dev == NULL) {
7805 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7806 pci_disable_device(pdev);
7807 pci_release_regions(pdev);
7808 return -ENODEV;
7809 }
7810
7811 pci_set_master(pdev);
7812 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7813 SET_NETDEV_DEV(dev, &pdev->dev);
7814
7815 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7816 sp = netdev_priv(dev);
1ee6dd77 7817 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7818 sp->dev = dev;
7819 sp->pdev = pdev;
1da177e4 7820 sp->high_dma_flag = dma_flag;
f957bcf0 7821 sp->device_enabled_once = false;
da6971d8
AR		 7822 if (rx_ring_mode == 1)
7823 sp->rxd_mode = RXD_MODE_1;
7824 if (rx_ring_mode == 2)
7825 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7826
eaae7f72 7827 sp->config.intr_type = dev_intr_type;
1da177e4 7828
541ae68f
K		 7829 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7830 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7831 sp->device_type = XFRAME_II_DEVICE;
7832 else
7833 sp->device_type = XFRAME_I_DEVICE;
7834
43b7c451 7835 sp->lro = lro_enable;
6aa20a22 7836
1da177e4
LT		 7837 /* Initialize some PCI/PCI-X fields of the NIC. */
7838 s2io_init_pci(sp);
7839
20346722 7840 /*
1da177e4 7841 * Setting the device configuration parameters.
20346722
K		 7842 * Most of these parameters can be specified by the user during
7843 * module insertion as they are module loadable parameters. If
7844 * these parameters are not not specified during load time, they
1da177e4
LT		 7845 * are initialized with default values.
7846 */
7847 mac_control = &sp->mac_control;
7848 config = &sp->config;
7849
596c5c97 7850 config->napi = napi;
6cfc482b 7851 config->tx_steering_type = tx_steering_type;
596c5c97 7852
1da177e4 7853 /* Tx side parameters. */
6cfc482b
SH		 7854 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7855 config->tx_fifo_num = MAX_TX_FIFOS;
7856 else
7857 config->tx_fifo_num = tx_fifo_num;
7858
7859 /* Initialize the fifos used for tx steering */
7860 if (config->tx_fifo_num < 5) {
7861 if (config->tx_fifo_num == 1)
7862 sp->total_tcp_fifos = 1;
7863 else
7864 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7865 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7866 sp->total_udp_fifos = 1;
7867 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7868 } else {
7869 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7870 FIFO_OTHER_MAX_NUM);
7871 sp->udp_fifo_idx = sp->total_tcp_fifos;
7872 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7873 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7874 }
7875
3a3d5756 7876 config->multiq = dev_multiq;
6cfc482b 7877 for (i = 0; i < config->tx_fifo_num; i++) {
1da177e4
LT		 7878 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7879 config->tx_cfg[i].fifo_priority = i;
7880 }
7881
20346722
K		 7882 /* mapping the QoS priority to the configured fifos */
7883 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7884 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7885
6cfc482b
SH		 7886 /* map the hashing selector table to the configured fifos */
7887 for (i = 0; i < config->tx_fifo_num; i++)
7888 sp->fifo_selector[i] = fifo_selector[i];
7889
7890
1da177e4
LT		 7891 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7892 for (i = 0; i < config->tx_fifo_num; i++) {
7893 config->tx_cfg[i].f_no_snoop =
7894 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7895 if (config->tx_cfg[i].fifo_len < 65) {
7896 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7897 break;
7898 }
7899 }
fed5eccd
AR		 7900 /* + 2 because one Txd for skb->data and one Txd for UFO */
7901 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7902
7903 /* Rx side parameters. */
1da177e4 7904 config->rx_ring_num = rx_ring_num;
0425b46a 7905 for (i = 0; i < config->rx_ring_num; i++) {
1da177e4 7906 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7907 (rxd_count[sp->rxd_mode] + 1);
1da177e4 7908 config->rx_cfg[i].ring_priority = i;
0425b46a
SH		 7909 mac_control->rings[i].rx_bufs_left = 0;
7910 mac_control->rings[i].rxd_mode = sp->rxd_mode;
7911 mac_control->rings[i].rxd_count = rxd_count[sp->rxd_mode];
7912 mac_control->rings[i].pdev = sp->pdev;
7913 mac_control->rings[i].dev = sp->dev;
1da177e4
LT		 7914 }
7915
7916 for (i = 0; i < rx_ring_num; i++) {
7917 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7918 config->rx_cfg[i].f_no_snoop =
7919 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7920 }
7921
7922 /* Setting Mac Control parameters */
7923 mac_control->rmac_pause_time = rmac_pause_time;
7924 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7925 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7926
7927
1da177e4
LT		 7928 /* initialize the shared memory used by the NIC and the host */
7929 if (init_shared_mem(sp)) {
7930 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7931 dev->name);
1da177e4
LT		 7932 ret = -ENOMEM;
7933 goto mem_alloc_failed;
7934 }
7935
275f165f 7936 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7937 if (!sp->bar0) {
19a60522 7938 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7939 dev->name);
7940 ret = -ENOMEM;
7941 goto bar0_remap_failed;
7942 }
7943
275f165f 7944 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7945 if (!sp->bar1) {
19a60522 7946 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7947 dev->name);
7948 ret = -ENOMEM;
7949 goto bar1_remap_failed;
7950 }
7951
7952 dev->irq = pdev->irq;
7953 dev->base_addr = (unsigned long) sp->bar0;
7954
7955 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7956 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7957 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7958 (sp->bar1 + (j * 0x00020000));
7959 }
7960
7961 /* Driver entry points */
04025095 7962 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 7963 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 7964 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
612eff0e 7965
1da177e4 7966 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 7967 if (sp->high_dma_flag == true)
1da177e4 7968 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7969 dev->features |= NETIF_F_TSO;
f83ef8c0 7970 dev->features |= NETIF_F_TSO6;
db874e65 7971 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7972 dev->features |= NETIF_F_UFO;
7973 dev->features |= NETIF_F_HW_CSUM;
7974 }
1da177e4 7975 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7976 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7977 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7978
e960fc5c 7979 pci_save_state(sp->pdev);
1da177e4
LT		 7980
7981 /* Setting swapper control on the NIC, for proper reset operation */
7982 if (s2io_set_swapper(sp)) {
7983 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7984 dev->name);
7985 ret = -EAGAIN;
7986 goto set_swap_failed;
7987 }
7988
541ae68f
K		 7989 /* Verify if the Herc works on the slot its placed into */
7990 if (sp->device_type & XFRAME_II_DEVICE) {
7991 mode = s2io_verify_pci_mode(sp);
7992 if (mode < 0) {
b39d66a8 7993 DBG_PRINT(ERR_DBG, "%s: ", __func__);
541ae68f
K		 7994 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7995 ret = -EBADSLT;
7996 goto set_swap_failed;
7997 }
7998 }
7999
f61e0a35
SH		 8000 if (sp->config.intr_type == MSI_X) {
8001 sp->num_entries = config->rx_ring_num + 1;
8002 ret = s2io_enable_msi_x(sp);
8003
8004 if (!ret) {
8005 ret = s2io_test_msi(sp);
8006 /* rollback MSI-X, will re-enable during add_isr() */
8007 remove_msix_isr(sp);
8008 }
8009 if (ret) {
8010
8011 DBG_PRINT(ERR_DBG,
073a2436 8012 "s2io: MSI-X requested but failed to enable\n");
f61e0a35
SH		 8013 sp->config.intr_type = INTA;
8014 }
8015 }
8016
8017 if (config->intr_type == MSI_X) {
8018 for (i = 0; i < config->rx_ring_num ; i++)
8019 netif_napi_add(dev, &mac_control->rings[i].napi,
8020 s2io_poll_msix, 64);
8021 } else {
8022 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8023 }
8024
541ae68f
K		 8025 /* Not needed for Herc */
8026 if (sp->device_type & XFRAME_I_DEVICE) {
8027 /*
8028 * Fix for all "FFs" MAC address problems observed on
8029 * Alpha platforms
8030 */
8031 fix_mac_address(sp);
8032 s2io_reset(sp);
8033 }
1da177e4
LT		 8034
8035 /*
1da177e4
LT		 8036 * MAC address initialization.
8037 * For now only one mac address will be read and used.
8038 */
8039 bar0 = sp->bar0;
8040 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 8041 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8042 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8043 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 8044 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 8045 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8046 mac_down = (u32) tmp64;
8047 mac_up = (u32) (tmp64 >> 32);
8048
1da177e4
LT		 8049 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8050 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8051 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8052 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8053 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8054 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8055
1da177e4
LT		 8056 /* Set the factory defined MAC address initially */
8057 dev->addr_len = ETH_ALEN;
8058 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8059 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8060
faa4f796
SH		 8061 /* initialize number of multicast & unicast MAC entries variables */
8062 if (sp->device_type == XFRAME_I_DEVICE) {
8063 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8064 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8065 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8066 } else if (sp->device_type == XFRAME_II_DEVICE) {
8067 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8068 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8069 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8070 }
8071
8072 /* store mac addresses from CAM to s2io_nic structure */
8073 do_s2io_store_unicast_mc(sp);
8074
f61e0a35
SH		 8075 /* Configure MSIX vector for number of rings configured plus one */
8076 if ((sp->device_type == XFRAME_II_DEVICE) &&
8077 (config->intr_type == MSI_X))
8078 sp->num_entries = config->rx_ring_num + 1;
8079
c77dd43e
SS		 8080 /* Store the values of the MSIX table in the s2io_nic structure */
8081 store_xmsi_data(sp);
b41477f3
AR		 8082 /* reset Nic and bring it to known state */
8083 s2io_reset(sp);
8084
1da177e4 8085 /*
99993af6 8086 * Initialize link state flags
541ae68f 8087 * and the card state parameter
1da177e4 8088 */
92b84437 8089 sp->state = 0;
1da177e4 8090
1da177e4 8091 /* Initialize spinlocks */
2fda096d
SR		 8092 for (i = 0; i < sp->config.tx_fifo_num; i++)
8093 spin_lock_init(&mac_control->fifos[i].tx_lock);
db874e65 8094
20346722
K		 8095 /*
8096 * SXE-002: Configure link and activity LED to init state
8097 * on driver load.
1da177e4
LT		 8098 */
8099 subid = sp->pdev->subsystem_device;
8100 if ((subid & 0xFF) >= 0x07) {
8101 val64 = readq(&bar0->gpio_control);
8102 val64 |= 0x0000800000000000ULL;
8103 writeq(val64, &bar0->gpio_control);
8104 val64 = 0x0411040400000000ULL;
8105 writeq(val64, (void __iomem *) bar0 + 0x2700);
8106 val64 = readq(&bar0->gpio_control);
8107 }
8108
8109 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8110
8111 if (register_netdev(dev)) {
8112 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8113 ret = -ENODEV;
8114 goto register_failed;
8115 }
9dc737a7 8116 s2io_vpd_read(sp);
0c61ed5f 8117 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 8118 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 8119 sp->product_name, pdev->revision);
b41477f3
AR		 8120 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8121 s2io_driver_version);
e174961c 8122 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %pM\n", dev->name, dev->dev_addr);
19a60522 8123 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8124 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8125 mode = s2io_print_pci_mode(sp);
541ae68f 8126 if (mode < 0) {
9dc737a7 8127 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8128 ret = -EBADSLT;
9dc737a7 8129 unregister_netdev(dev);
541ae68f
K		 8130 goto set_swap_failed;
8131 }
541ae68f 8132 }
9dc737a7
AR		 8133 switch(sp->rxd_mode) {
8134 case RXD_MODE_1:
8135 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8136 dev->name);
8137 break;
8138 case RXD_MODE_3B:
8139 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8140 dev->name);
8141 break;
9dc737a7 8142 }
db874e65 8143
f61e0a35
SH		 8144 switch (sp->config.napi) {
8145 case 0:
8146 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8147 break;
8148 case 1:
db874e65 8149 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8150 break;
8151 }
3a3d5756
SH		 8152
8153 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8154 sp->config.tx_fifo_num);
8155
0425b46a
SH		 8156 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8157 sp->config.rx_ring_num);
8158
eaae7f72 8159 switch(sp->config.intr_type) {
9dc737a7
AR		 8160 case INTA:
8161 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8162 break;
9dc737a7
AR		 8163 case MSI_X:
8164 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8165 break;
8166 }
3a3d5756 8167 if (sp->config.multiq) {
a505f4ff
IJ		 8168 for (i = 0; i < sp->config.tx_fifo_num; i++)
8169 mac_control->fifos[i].multiq = config->multiq;
3a3d5756
SH		 8170 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8171 dev->name);
8172 } else
8173 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8174 dev->name);
8175
6cfc482b
SH		 8176 switch (sp->config.tx_steering_type) {
8177 case NO_STEERING:
8178 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8179 " transmit\n", dev->name);
8180 break;
8181 case TX_PRIORITY_STEERING:
8182 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8183 " transmit\n", dev->name);
8184 break;
8185 case TX_DEFAULT_STEERING:
8186 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8187 " transmit\n", dev->name);
8188 }
8189
7d3d0439
RA		 8190 if (sp->lro)
8191 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8192 dev->name);
db874e65
SS		 8193 if (ufo)
8194 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8195 " enabled\n", dev->name);
7ba013ac 8196 /* Initialize device name */
9dc737a7 8197 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8198
cd0fce03
BL		 8199 if (vlan_tag_strip)
8200 sp->vlan_strip_flag = 1;
8201 else
8202 sp->vlan_strip_flag = 0;
8203
20346722
K		 8204 /*
8205 * Make Link state as off at this point, when the Link change
8206 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8207 * the right state.
8208 */
8209 netif_carrier_off(dev);
1da177e4
LT		 8210
8211 return 0;
8212
8213 register_failed:
8214 set_swap_failed:
8215 iounmap(sp->bar1);
8216 bar1_remap_failed:
8217 iounmap(sp->bar0);
8218 bar0_remap_failed:
8219 mem_alloc_failed:
8220 free_shared_mem(sp);
8221 pci_disable_device(pdev);
eccb8628 8222 pci_release_regions(pdev);
1da177e4
LT		 8223 pci_set_drvdata(pdev, NULL);
8224 free_netdev(dev);
8225
8226 return ret;
8227}
8228
8229/**
20346722 8230 * s2io_rem_nic - Free the PCI device
1da177e4 8231 * @pdev: structure containing the PCI related information of the device.
20346722 8232 * Description: This function is called by the Pci subsystem to release a
1da177e4 8233 * PCI device and free up all resource held up by the device. This could
20346722 8234 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8235 * from memory.
8236 */
8237
8238static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8239{
8240 struct net_device *dev =
8241 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 8242 struct s2io_nic *sp;
1da177e4
LT		 8243
8244 if (dev == NULL) {
8245 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8246 return;
8247 }
8248
22747d6b
FR		 8249 flush_scheduled_work();
8250
4cf1653a 8251 sp = netdev_priv(dev);
1da177e4
LT		 8252 unregister_netdev(dev);
8253
8254 free_shared_mem(sp);
8255 iounmap(sp->bar0);
8256 iounmap(sp->bar1);
eccb8628 8257 pci_release_regions(pdev);
1da177e4 8258 pci_set_drvdata(pdev, NULL);
1da177e4 8259 free_netdev(dev);
19a60522 8260 pci_disable_device(pdev);
1da177e4
LT		 8261}
8262
8263/**
8264 * s2io_starter - Entry point for the driver
8265 * Description: This function is the entry point for the driver. It verifies
8266 * the module loadable parameters and initializes PCI configuration space.
8267 */
8268
43b7c451 8269static int __init s2io_starter(void)
1da177e4 8270{
29917620 8271 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8272}
8273
8274/**
20346722 8275 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8276 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8277 */
8278
372cc597 8279static __exit void s2io_closer(void)
1da177e4
LT		 8280{
8281 pci_unregister_driver(&s2io_driver);
8282 DBG_PRINT(INIT_DBG, "cleanup done\n");
8283}
8284
8285module_init(s2io_starter);
8286module_exit(s2io_closer);
7d3d0439 8287
6aa20a22 8288static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
cdb5bf02
SH		 8289 struct tcphdr **tcp, struct RxD_t *rxdp,
8290 struct s2io_nic *sp)
7d3d0439
RA		 8291{
8292 int ip_off;
8293 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8294
8295 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8296 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8297 __func__);
7d3d0439
RA		 8298 return -1;
8299 }
8300
cdb5bf02
SH		 8301 /* Checking for DIX type or DIX type with VLAN */
8302 if ((l2_type == 0)
8303 || (l2_type == 4)) {
8304 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8305 /*
8306 * If vlan stripping is disabled and the frame is VLAN tagged,
8307 * shift the offset by the VLAN header size bytes.
8308 */
cd0fce03 8309 if ((!sp->vlan_strip_flag) &&
cdb5bf02
SH		 8310 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8311 ip_off += HEADER_VLAN_SIZE;
8312 } else {
7d3d0439 8313 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8314 return -1;
7d3d0439
RA		 8315 }
8316
8317 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8318 ip_len = (u8)((*ip)->ihl);
8319 ip_len <<= 2;
8320 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8321
8322 return 0;
8323}
8324
1ee6dd77 8325static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8326 struct tcphdr *tcp)
8327{
b39d66a8 8328 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8329 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8330 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8331 return -1;
8332 return 0;
8333}
8334
8335static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8336{
8337 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8338}
8339
1ee6dd77 8340static void initiate_new_session(struct lro *lro, u8 *l2h,
cdb5bf02 8341 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8342{
b39d66a8 8343 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8344 lro->l2h = l2h;
8345 lro->iph = ip;
8346 lro->tcph = tcp;
8347 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8348 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8349 lro->sg_num = 1;
8350 lro->total_len = ntohs(ip->tot_len);
8351 lro->frags_len = 0;
cdb5bf02 8352 lro->vlan_tag = vlan_tag;
6aa20a22 8353 /*
7d3d0439
RA		 8354 * check if we saw TCP timestamp. Other consistency checks have
8355 * already been done.
8356 */
8357 if (tcp->doff == 8) {
c8855953
SR		 8358 __be32 *ptr;
8359 ptr = (__be32 *)(tcp+1);
7d3d0439 8360 lro->saw_ts = 1;
c8855953 8361 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8362 lro->cur_tsecr = *(ptr+2);
8363 }
8364 lro->in_use = 1;
8365}
8366
1ee6dd77 8367static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8368{
8369 struct iphdr *ip = lro->iph;
8370 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8371 __sum16 nchk;
1ee6dd77 8372 struct stat_block *statinfo = sp->mac_control.stats_info;
b39d66a8 8373 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8374
8375 /* Update L3 header */
8376 ip->tot_len = htons(lro->total_len);
8377 ip->check = 0;
8378 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8379 ip->check = nchk;
8380
8381 /* Update L4 header */
8382 tcp->ack_seq = lro->tcp_ack;
8383 tcp->window = lro->window;
8384
8385 /* Update tsecr field if this session has timestamps enabled */
8386 if (lro->saw_ts) {
c8855953 8387 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8388 *(ptr+2) = lro->cur_tsecr;
8389 }
8390
8391 /* Update counters required for calculation of
8392 * average no. of packets aggregated.
8393 */
8394 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8395 statinfo->sw_stat.num_aggregations++;
8396}
8397
1ee6dd77 8398static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8399 struct tcphdr *tcp, u32 l4_pyld)
8400{
b39d66a8 8401 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8402 lro->total_len += l4_pyld;
8403 lro->frags_len += l4_pyld;
8404 lro->tcp_next_seq += l4_pyld;
8405 lro->sg_num++;
8406
8407 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8408 lro->tcp_ack = tcp->ack_seq;
8409 lro->window = tcp->window;
6aa20a22 8410
7d3d0439 8411 if (lro->saw_ts) {
c8855953 8412 __be32 *ptr;
7d3d0439 8413 /* Update tsecr and tsval from this packet */
c8855953
SR		 8414 ptr = (__be32 *)(tcp+1);
8415 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8416 lro->cur_tsecr = *(ptr + 2);
8417 }
8418}
8419
1ee6dd77 8420static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8421 struct tcphdr *tcp, u32 tcp_pyld_len)
8422{
7d3d0439
RA		 8423 u8 *ptr;
8424
b39d66a8 8425 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
79dc1901 8426
7d3d0439
RA		 8427 if (!tcp_pyld_len) {
8428 /* Runt frame or a pure ack */
8429 return -1;
8430 }
8431
8432 if (ip->ihl != 5) /* IP has options */
8433 return -1;
8434
75c30b13
AR		 8435 /* If we see CE codepoint in IP header, packet is not mergeable */
8436 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8437 return -1;
8438
8439 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 8440 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 8441 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8442 /*
8443 * Currently recognize only the ack control word and
8444 * any other control field being set would result in
8445 * flushing the LRO session
8446 */
8447 return -1;
8448 }
8449
6aa20a22 8450 /*
7d3d0439
RA		 8451 * Allow only one TCP timestamp option. Don't aggregate if
8452 * any other options are detected.
8453 */
8454 if (tcp->doff != 5 && tcp->doff != 8)
8455 return -1;
8456
8457 if (tcp->doff == 8) {
6aa20a22 8458 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8459 while (*ptr == TCPOPT_NOP)
8460 ptr++;
8461 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8462 return -1;
8463
8464 /* Ensure timestamp value increases monotonically */
8465 if (l_lro)
c8855953 8466 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8467 return -1;
8468
8469 /* timestamp echo reply should be non-zero */
c8855953 8470 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8471 return -1;
8472 }
8473
8474 return 0;
8475}
8476
8477static int
0425b46a
SH		 8478s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8479 u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8480 struct s2io_nic *sp)
7d3d0439
RA		 8481{
8482 struct iphdr *ip;
8483 struct tcphdr *tcph;
8484 int ret = 0, i;
cdb5bf02 8485 u16 vlan_tag = 0;
7d3d0439
RA		 8486
8487 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
cdb5bf02 8488 rxdp, sp))) {
7d3d0439
RA		 8489 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8490 ip->saddr, ip->daddr);
cdb5bf02 8491 } else
7d3d0439 8492 return ret;
7d3d0439 8493
cdb5bf02 8494 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8495 tcph = (struct tcphdr *)*tcp;
8496 *tcp_len = get_l4_pyld_length(ip, tcph);
8497 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8498 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8499 if (l_lro->in_use) {
8500 if (check_for_socket_match(l_lro, ip, tcph))
8501 continue;
8502 /* Sock pair matched */
8503 *lro = l_lro;
8504
8505 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8506 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
b39d66a8 8507 "0x%x, actual 0x%x\n", __func__,
7d3d0439
RA		 8508 (*lro)->tcp_next_seq,
8509 ntohl(tcph->seq));
8510
8511 sp->mac_control.stats_info->
8512 sw_stat.outof_sequence_pkts++;
8513 ret = 2;
8514 break;
8515 }
8516
8517 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8518 ret = 1; /* Aggregate */
8519 else
8520 ret = 2; /* Flush both */
8521 break;
8522 }
8523 }
8524
8525 if (ret == 0) {
8526 /* Before searching for available LRO objects,
8527 * check if the pkt is L3/L4 aggregatable. If not
8528 * don't create new LRO session. Just send this
8529 * packet up.
8530 */
8531 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8532 return 5;
8533 }
8534
8535 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8536 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8537 if (!(l_lro->in_use)) {
8538 *lro = l_lro;
8539 ret = 3; /* Begin anew */
8540 break;
8541 }
8542 }
8543 }
8544
8545 if (ret == 0) { /* sessions exceeded */
8546 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
b39d66a8 8547 __func__);
7d3d0439
RA		 8548 *lro = NULL;
8549 return ret;
8550 }
8551
8552 switch (ret) {
8553 case 3:
cdb5bf02
SH		 8554 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8555 vlan_tag);
7d3d0439
RA		 8556 break;
8557 case 2:
8558 update_L3L4_header(sp, *lro);
8559 break;
8560 case 1:
8561 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8562 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8563 update_L3L4_header(sp, *lro);
8564 ret = 4; /* Flush the LRO */
8565 }
8566 break;
8567 default:
8568 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
b39d66a8 8569 __func__);
7d3d0439
RA		 8570 break;
8571 }
8572
8573 return ret;
8574}
8575
1ee6dd77 8576static void clear_lro_session(struct lro *lro)
7d3d0439 8577{
1ee6dd77 8578 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8579
8580 memset(lro, 0, lro_struct_size);
8581}
8582
cdb5bf02 8583static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8584{
8585 struct net_device *dev = skb->dev;
4cf1653a 8586 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8587
8588 skb->protocol = eth_type_trans(skb, dev);
cdb5bf02 8589 if (sp->vlgrp && vlan_tag
cd0fce03 8590 && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8591 /* Queueing the vlan frame to the upper layer */
8592 if (sp->config.napi)
8593 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8594 else
8595 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8596 } else {
8597 if (sp->config.napi)
8598 netif_receive_skb(skb);
8599 else
8600 netif_rx(skb);
8601 }
7d3d0439
RA		 8602}
8603
1ee6dd77
RB		 8604static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8605 struct sk_buff *skb,
7d3d0439
RA		 8606 u32 tcp_len)
8607{
75c30b13 8608 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8609
8610 first->len += tcp_len;
8611 first->data_len = lro->frags_len;
8612 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8613 if (skb_shinfo(first)->frag_list)
8614 lro->last_frag->next = skb;
7d3d0439
RA		 8615 else
8616 skb_shinfo(first)->frag_list = skb;
372cc597 8617 first->truesize += skb->truesize;
75c30b13 8618 lro->last_frag = skb;
7d3d0439
RA		 8619 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8620 return;
8621}
d796fdb7
LV		 8622
8623/**
8624 * s2io_io_error_detected - called when PCI error is detected
8625 * @pdev: Pointer to PCI device
8453d43f 8626 * @state: The current pci connection state
d796fdb7
LV		 8627 *
8628 * This function is called after a PCI bus error affecting
8629 * this device has been detected.
8630 */
8631static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8632 pci_channel_state_t state)
8633{
8634 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8635 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8636
8637 netif_device_detach(netdev);
8638
1e3c8bd6
DN		 8639 if (state == pci_channel_io_perm_failure)
8640 return PCI_ERS_RESULT_DISCONNECT;
8641
d796fdb7
LV		 8642 if (netif_running(netdev)) {
8643 /* Bring down the card, while avoiding PCI I/O */
8644 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8645 }
8646 pci_disable_device(pdev);
8647
8648 return PCI_ERS_RESULT_NEED_RESET;
8649}
8650
8651/**
8652 * s2io_io_slot_reset - called after the pci bus has been reset.
8653 * @pdev: Pointer to PCI device
8654 *
8655 * Restart the card from scratch, as if from a cold-boot.
8656 * At this point, the card has exprienced a hard reset,
8657 * followed by fixups by BIOS, and has its config space
8658 * set up identically to what it was at cold boot.
8659 */
8660static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8661{
8662 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8663 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8664
8665 if (pci_enable_device(pdev)) {
8666 printk(KERN_ERR "s2io: "
8667 "Cannot re-enable PCI device after reset.\n");
8668 return PCI_ERS_RESULT_DISCONNECT;
8669 }
8670
8671 pci_set_master(pdev);
8672 s2io_reset(sp);
8673
8674 return PCI_ERS_RESULT_RECOVERED;
8675}
8676
8677/**
8678 * s2io_io_resume - called when traffic can start flowing again.
8679 * @pdev: Pointer to PCI device
8680 *
8681 * This callback is called when the error recovery driver tells
8682 * us that its OK to resume normal operation.
8683 */
8684static void s2io_io_resume(struct pci_dev *pdev)
8685{
8686 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8687 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8688
8689 if (netif_running(netdev)) {
8690 if (s2io_card_up(sp)) {
8691 printk(KERN_ERR "s2io: "
8692 "Can't bring device back up after reset.\n");
8693 return;
8694 }
8695
8696 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8697 s2io_card_down(sp);
8698 printk(KERN_ERR "s2io: "
8699 "Can't resetore mac addr after reset.\n");
8700 return;
8701 }
8702 }
8703
8704 netif_device_attach(netdev);
fd2ea0a7 8705 netif_tx_wake_all_queues(netdev);
d796fdb7 8706}
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