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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * ALSA driver for ATI IXP 150/200/250 AC97 modem controllers | |
4 | * | |
5 | * Copyright (c) 2004 Takashi Iwai <[email protected]> | |
1da177e4 LT |
6 | */ |
7 | ||
6cbbfe1c | 8 | #include <linux/io.h> |
1da177e4 LT |
9 | #include <linux/delay.h> |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/slab.h> | |
65a77217 | 14 | #include <linux/module.h> |
62932df8 | 15 | #include <linux/mutex.h> |
1da177e4 LT |
16 | #include <sound/core.h> |
17 | #include <sound/pcm.h> | |
18 | #include <sound/pcm_params.h> | |
19 | #include <sound/info.h> | |
20 | #include <sound/ac97_codec.h> | |
21 | #include <sound/initval.h> | |
22 | ||
23 | MODULE_AUTHOR("Takashi Iwai <[email protected]>"); | |
24 | MODULE_DESCRIPTION("ATI IXP MC97 controller"); | |
25 | MODULE_LICENSE("GPL"); | |
1da177e4 | 26 | |
b7fe4622 CL |
27 | static int index = -2; /* Exclude the first card */ |
28 | static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ | |
29 | static int ac97_clock = 48000; | |
1da177e4 | 30 | |
b7fe4622 | 31 | module_param(index, int, 0444); |
1da177e4 | 32 | MODULE_PARM_DESC(index, "Index value for ATI IXP controller."); |
b7fe4622 | 33 | module_param(id, charp, 0444); |
1da177e4 | 34 | MODULE_PARM_DESC(id, "ID string for ATI IXP controller."); |
b7fe4622 | 35 | module_param(ac97_clock, int, 0444); |
1da177e4 LT |
36 | MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz)."); |
37 | ||
2b3e584b | 38 | /* just for backward compatibility */ |
a67ff6a5 | 39 | static bool enable; |
698444f3 | 40 | module_param(enable, bool, 0444); |
2b3e584b | 41 | |
1da177e4 LT |
42 | |
43 | /* | |
44 | */ | |
45 | ||
46 | #define ATI_REG_ISR 0x00 /* interrupt source */ | |
47 | #define ATI_REG_ISR_MODEM_IN_XRUN (1U<<0) | |
48 | #define ATI_REG_ISR_MODEM_IN_STATUS (1U<<1) | |
49 | #define ATI_REG_ISR_MODEM_OUT1_XRUN (1U<<2) | |
50 | #define ATI_REG_ISR_MODEM_OUT1_STATUS (1U<<3) | |
51 | #define ATI_REG_ISR_MODEM_OUT2_XRUN (1U<<4) | |
52 | #define ATI_REG_ISR_MODEM_OUT2_STATUS (1U<<5) | |
53 | #define ATI_REG_ISR_MODEM_OUT3_XRUN (1U<<6) | |
54 | #define ATI_REG_ISR_MODEM_OUT3_STATUS (1U<<7) | |
55 | #define ATI_REG_ISR_PHYS_INTR (1U<<8) | |
56 | #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9) | |
57 | #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10) | |
58 | #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11) | |
59 | #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12) | |
60 | #define ATI_REG_ISR_NEW_FRAME (1U<<13) | |
61 | #define ATI_REG_ISR_MODEM_GPIO_DATA (1U<<14) | |
62 | ||
63 | #define ATI_REG_IER 0x04 /* interrupt enable */ | |
64 | #define ATI_REG_IER_MODEM_IN_XRUN_EN (1U<<0) | |
65 | #define ATI_REG_IER_MODEM_STATUS_EN (1U<<1) | |
66 | #define ATI_REG_IER_MODEM_OUT1_XRUN_EN (1U<<2) | |
67 | #define ATI_REG_IER_MODEM_OUT2_XRUN_EN (1U<<4) | |
68 | #define ATI_REG_IER_MODEM_OUT3_XRUN_EN (1U<<6) | |
69 | #define ATI_REG_IER_PHYS_INTR_EN (1U<<8) | |
70 | #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9) | |
71 | #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10) | |
72 | #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11) | |
73 | #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12) | |
74 | #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */ | |
75 | #define ATI_REG_IER_MODEM_GPIO_DATA_EN (1U<<14) /* (WO) modem is running */ | |
76 | #define ATI_REG_IER_MODEM_SET_BUS_BUSY (1U<<15) | |
77 | ||
78 | #define ATI_REG_CMD 0x08 /* command */ | |
79 | #define ATI_REG_CMD_POWERDOWN (1U<<0) | |
80 | #define ATI_REG_CMD_MODEM_RECEIVE_EN (1U<<1) /* modem only */ | |
81 | #define ATI_REG_CMD_MODEM_SEND1_EN (1U<<2) /* modem only */ | |
82 | #define ATI_REG_CMD_MODEM_SEND2_EN (1U<<3) /* modem only */ | |
83 | #define ATI_REG_CMD_MODEM_SEND3_EN (1U<<4) /* modem only */ | |
84 | #define ATI_REG_CMD_MODEM_STATUS_MEM (1U<<5) /* modem only */ | |
85 | #define ATI_REG_CMD_MODEM_IN_DMA_EN (1U<<8) /* modem only */ | |
86 | #define ATI_REG_CMD_MODEM_OUT_DMA1_EN (1U<<9) /* modem only */ | |
87 | #define ATI_REG_CMD_MODEM_OUT_DMA2_EN (1U<<10) /* modem only */ | |
88 | #define ATI_REG_CMD_MODEM_OUT_DMA3_EN (1U<<11) /* modem only */ | |
89 | #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20) | |
90 | #define ATI_REG_CMD_MODEM_GPIO_THRU_DMA (1U<<22) /* modem only */ | |
91 | #define ATI_REG_CMD_LOOPBACK_EN (1U<<23) | |
92 | #define ATI_REG_CMD_PACKED_DIS (1U<<24) | |
93 | #define ATI_REG_CMD_BURST_EN (1U<<25) | |
94 | #define ATI_REG_CMD_PANIC_EN (1U<<26) | |
95 | #define ATI_REG_CMD_MODEM_PRESENT (1U<<27) | |
96 | #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28) | |
97 | #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29) | |
98 | #define ATI_REG_CMD_AC_SYNC (1U<<30) | |
99 | #define ATI_REG_CMD_AC_RESET (1U<<31) | |
100 | ||
101 | #define ATI_REG_PHYS_OUT_ADDR 0x0c | |
102 | #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0) | |
103 | #define ATI_REG_PHYS_OUT_RW (1U<<2) | |
104 | #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8) | |
105 | #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9 | |
106 | #define ATI_REG_PHYS_OUT_DATA_SHIFT 16 | |
107 | ||
108 | #define ATI_REG_PHYS_IN_ADDR 0x10 | |
109 | #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8) | |
110 | #define ATI_REG_PHYS_IN_ADDR_SHIFT 9 | |
111 | #define ATI_REG_PHYS_IN_DATA_SHIFT 16 | |
112 | ||
113 | #define ATI_REG_SLOTREQ 0x14 | |
114 | ||
115 | #define ATI_REG_COUNTER 0x18 | |
116 | #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */ | |
117 | #define ATI_REG_COUNTER_BITCLOCK (31U<<8) | |
118 | ||
119 | #define ATI_REG_IN_FIFO_THRESHOLD 0x1c | |
120 | ||
121 | #define ATI_REG_MODEM_IN_DMA_LINKPTR 0x20 | |
122 | #define ATI_REG_MODEM_IN_DMA_DT_START 0x24 /* RO */ | |
123 | #define ATI_REG_MODEM_IN_DMA_DT_NEXT 0x28 /* RO */ | |
124 | #define ATI_REG_MODEM_IN_DMA_DT_CUR 0x2c /* RO */ | |
125 | #define ATI_REG_MODEM_IN_DMA_DT_SIZE 0x30 | |
126 | #define ATI_REG_MODEM_OUT_FIFO 0x34 /* output threshold */ | |
127 | #define ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK (0xf<<16) | |
128 | #define ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT 16 | |
129 | #define ATI_REG_MODEM_OUT_DMA1_LINKPTR 0x38 | |
130 | #define ATI_REG_MODEM_OUT_DMA2_LINKPTR 0x3c | |
131 | #define ATI_REG_MODEM_OUT_DMA3_LINKPTR 0x40 | |
132 | #define ATI_REG_MODEM_OUT_DMA1_DT_START 0x44 | |
133 | #define ATI_REG_MODEM_OUT_DMA1_DT_NEXT 0x48 | |
134 | #define ATI_REG_MODEM_OUT_DMA1_DT_CUR 0x4c | |
135 | #define ATI_REG_MODEM_OUT_DMA2_DT_START 0x50 | |
136 | #define ATI_REG_MODEM_OUT_DMA2_DT_NEXT 0x54 | |
137 | #define ATI_REG_MODEM_OUT_DMA2_DT_CUR 0x58 | |
138 | #define ATI_REG_MODEM_OUT_DMA3_DT_START 0x5c | |
139 | #define ATI_REG_MODEM_OUT_DMA3_DT_NEXT 0x60 | |
140 | #define ATI_REG_MODEM_OUT_DMA3_DT_CUR 0x64 | |
141 | #define ATI_REG_MODEM_OUT_DMA12_DT_SIZE 0x68 | |
142 | #define ATI_REG_MODEM_OUT_DMA3_DT_SIZE 0x6c | |
143 | #define ATI_REG_MODEM_OUT_FIFO_USED 0x70 | |
144 | #define ATI_REG_MODEM_OUT_GPIO 0x74 | |
145 | #define ATI_REG_MODEM_OUT_GPIO_EN 1 | |
146 | #define ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT 5 | |
147 | #define ATI_REG_MODEM_IN_GPIO 0x78 | |
148 | ||
149 | #define ATI_REG_MODEM_MIRROR 0x7c | |
150 | #define ATI_REG_AUDIO_MIRROR 0x80 | |
151 | ||
152 | #define ATI_REG_MODEM_FIFO_FLUSH 0x88 | |
153 | #define ATI_REG_MODEM_FIFO_OUT1_FLUSH (1U<<0) | |
154 | #define ATI_REG_MODEM_FIFO_OUT2_FLUSH (1U<<1) | |
155 | #define ATI_REG_MODEM_FIFO_OUT3_FLUSH (1U<<2) | |
156 | #define ATI_REG_MODEM_FIFO_IN_FLUSH (1U<<3) | |
157 | ||
158 | /* LINKPTR */ | |
159 | #define ATI_REG_LINKPTR_EN (1U<<0) | |
160 | ||
161 | #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */ | |
162 | ||
163 | ||
74ee4ff1 | 164 | struct atiixp_modem; |
1da177e4 LT |
165 | |
166 | /* | |
167 | * DMA packate descriptor | |
168 | */ | |
169 | ||
74ee4ff1 | 170 | struct atiixp_dma_desc { |
7e49aadf | 171 | __le32 addr; /* DMA buffer address */ |
1da177e4 LT |
172 | u16 status; /* status bits */ |
173 | u16 size; /* size of the packet in dwords */ | |
7e49aadf | 174 | __le32 next; /* address of the next packet descriptor */ |
74ee4ff1 | 175 | }; |
1da177e4 LT |
176 | |
177 | /* | |
178 | * stream enum | |
179 | */ | |
180 | enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, NUM_ATI_DMAS }; /* DMAs */ | |
181 | enum { ATI_PCM_OUT, ATI_PCM_IN, NUM_ATI_PCMS }; /* AC97 pcm slots */ | |
182 | enum { ATI_PCMDEV_ANALOG, NUM_ATI_PCMDEVS }; /* pcm devices */ | |
183 | ||
184 | #define NUM_ATI_CODECS 3 | |
185 | ||
186 | ||
187 | /* | |
188 | * constants and callbacks for each DMA type | |
189 | */ | |
74ee4ff1 | 190 | struct atiixp_dma_ops { |
1da177e4 LT |
191 | int type; /* ATI_DMA_XXX */ |
192 | unsigned int llp_offset; /* LINKPTR offset */ | |
193 | unsigned int dt_cur; /* DT_CUR offset */ | |
74ee4ff1 TI |
194 | /* called from open callback */ |
195 | void (*enable_dma)(struct atiixp_modem *chip, int on); | |
196 | /* called from trigger (START/STOP) */ | |
197 | void (*enable_transfer)(struct atiixp_modem *chip, int on); | |
198 | /* called from trigger (STOP only) */ | |
199 | void (*flush_dma)(struct atiixp_modem *chip); | |
1da177e4 LT |
200 | }; |
201 | ||
202 | /* | |
203 | * DMA stream | |
204 | */ | |
74ee4ff1 TI |
205 | struct atiixp_dma { |
206 | const struct atiixp_dma_ops *ops; | |
1da177e4 | 207 | struct snd_dma_buffer desc_buf; |
74ee4ff1 | 208 | struct snd_pcm_substream *substream; /* assigned PCM substream */ |
1da177e4 LT |
209 | unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */ |
210 | unsigned int period_bytes, periods; | |
211 | int opened; | |
212 | int running; | |
213 | int pcm_open_flag; | |
214 | int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */ | |
215 | }; | |
216 | ||
217 | /* | |
218 | * ATI IXP chip | |
219 | */ | |
74ee4ff1 TI |
220 | struct atiixp_modem { |
221 | struct snd_card *card; | |
1da177e4 LT |
222 | struct pci_dev *pci; |
223 | ||
224 | struct resource *res; /* memory i/o */ | |
225 | unsigned long addr; | |
226 | void __iomem *remap_addr; | |
227 | int irq; | |
228 | ||
74ee4ff1 TI |
229 | struct snd_ac97_bus *ac97_bus; |
230 | struct snd_ac97 *ac97[NUM_ATI_CODECS]; | |
1da177e4 LT |
231 | |
232 | spinlock_t reg_lock; | |
233 | ||
74ee4ff1 | 234 | struct atiixp_dma dmas[NUM_ATI_DMAS]; |
1da177e4 | 235 | struct ac97_pcm *pcms[NUM_ATI_PCMS]; |
74ee4ff1 | 236 | struct snd_pcm *pcmdevs[NUM_ATI_PCMDEVS]; |
1da177e4 LT |
237 | |
238 | int max_channels; /* max. channels for PCM out */ | |
239 | ||
240 | unsigned int codec_not_ready_bits; /* for codec detection */ | |
241 | ||
242 | int spdif_over_aclink; /* passed from the module option */ | |
62932df8 | 243 | struct mutex open_mutex; /* playback open mutex */ |
1da177e4 LT |
244 | }; |
245 | ||
246 | ||
247 | /* | |
248 | */ | |
9baa3c34 | 249 | static const struct pci_device_id snd_atiixp_ids[] = { |
28d27aae JP |
250 | { PCI_VDEVICE(ATI, 0x434d), 0 }, /* SB200 */ |
251 | { PCI_VDEVICE(ATI, 0x4378), 0 }, /* SB400 */ | |
1da177e4 LT |
252 | { 0, } |
253 | }; | |
254 | ||
255 | MODULE_DEVICE_TABLE(pci, snd_atiixp_ids); | |
256 | ||
257 | ||
258 | /* | |
259 | * lowlevel functions | |
260 | */ | |
261 | ||
262 | /* | |
263 | * update the bits of the given register. | |
264 | * return 1 if the bits changed. | |
265 | */ | |
74ee4ff1 TI |
266 | static int snd_atiixp_update_bits(struct atiixp_modem *chip, unsigned int reg, |
267 | unsigned int mask, unsigned int value) | |
1da177e4 LT |
268 | { |
269 | void __iomem *addr = chip->remap_addr + reg; | |
270 | unsigned int data, old_data; | |
271 | old_data = data = readl(addr); | |
272 | data &= ~mask; | |
273 | data |= value; | |
274 | if (old_data == data) | |
275 | return 0; | |
276 | writel(data, addr); | |
277 | return 1; | |
278 | } | |
279 | ||
280 | /* | |
281 | * macros for easy use | |
282 | */ | |
283 | #define atiixp_write(chip,reg,value) \ | |
284 | writel(value, chip->remap_addr + ATI_REG_##reg) | |
285 | #define atiixp_read(chip,reg) \ | |
286 | readl(chip->remap_addr + ATI_REG_##reg) | |
287 | #define atiixp_update(chip,reg,mask,val) \ | |
288 | snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val) | |
289 | ||
1da177e4 LT |
290 | /* |
291 | * handling DMA packets | |
292 | * | |
293 | * we allocate a linear buffer for the DMA, and split it to each packet. | |
294 | * in a future version, a scatter-gather buffer should be implemented. | |
295 | */ | |
296 | ||
297 | #define ATI_DESC_LIST_SIZE \ | |
74ee4ff1 | 298 | PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(struct atiixp_dma_desc)) |
1da177e4 LT |
299 | |
300 | /* | |
301 | * build packets ring for the given buffer size. | |
302 | * | |
303 | * IXP handles the buffer descriptors, which are connected as a linked | |
304 | * list. although we can change the list dynamically, in this version, | |
305 | * a static RING of buffer descriptors is used. | |
306 | * | |
307 | * the ring is built in this function, and is set up to the hardware. | |
308 | */ | |
74ee4ff1 TI |
309 | static int atiixp_build_dma_packets(struct atiixp_modem *chip, |
310 | struct atiixp_dma *dma, | |
311 | struct snd_pcm_substream *substream, | |
312 | unsigned int periods, | |
313 | unsigned int period_bytes) | |
1da177e4 LT |
314 | { |
315 | unsigned int i; | |
316 | u32 addr, desc_addr; | |
317 | unsigned long flags; | |
318 | ||
319 | if (periods > ATI_MAX_DESCRIPTORS) | |
320 | return -ENOMEM; | |
321 | ||
322 | if (dma->desc_buf.area == NULL) { | |
6974f8ad | 323 | if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev, |
1da177e4 LT |
324 | ATI_DESC_LIST_SIZE, &dma->desc_buf) < 0) |
325 | return -ENOMEM; | |
326 | dma->period_bytes = dma->periods = 0; /* clear */ | |
327 | } | |
328 | ||
329 | if (dma->periods == periods && dma->period_bytes == period_bytes) | |
330 | return 0; | |
331 | ||
332 | /* reset DMA before changing the descriptor table */ | |
333 | spin_lock_irqsave(&chip->reg_lock, flags); | |
334 | writel(0, chip->remap_addr + dma->ops->llp_offset); | |
335 | dma->ops->enable_dma(chip, 0); | |
336 | dma->ops->enable_dma(chip, 1); | |
337 | spin_unlock_irqrestore(&chip->reg_lock, flags); | |
338 | ||
339 | /* fill the entries */ | |
340 | addr = (u32)substream->runtime->dma_addr; | |
341 | desc_addr = (u32)dma->desc_buf.addr; | |
342 | for (i = 0; i < periods; i++) { | |
74ee4ff1 TI |
343 | struct atiixp_dma_desc *desc; |
344 | desc = &((struct atiixp_dma_desc *)dma->desc_buf.area)[i]; | |
1da177e4 LT |
345 | desc->addr = cpu_to_le32(addr); |
346 | desc->status = 0; | |
347 | desc->size = period_bytes >> 2; /* in dwords */ | |
74ee4ff1 | 348 | desc_addr += sizeof(struct atiixp_dma_desc); |
1da177e4 LT |
349 | if (i == periods - 1) |
350 | desc->next = cpu_to_le32((u32)dma->desc_buf.addr); | |
351 | else | |
352 | desc->next = cpu_to_le32(desc_addr); | |
353 | addr += period_bytes; | |
354 | } | |
355 | ||
356 | writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN, | |
357 | chip->remap_addr + dma->ops->llp_offset); | |
358 | ||
359 | dma->period_bytes = period_bytes; | |
360 | dma->periods = periods; | |
361 | ||
362 | return 0; | |
363 | } | |
364 | ||
365 | /* | |
366 | * remove the ring buffer and release it if assigned | |
367 | */ | |
74ee4ff1 TI |
368 | static void atiixp_clear_dma_packets(struct atiixp_modem *chip, |
369 | struct atiixp_dma *dma, | |
370 | struct snd_pcm_substream *substream) | |
1da177e4 LT |
371 | { |
372 | if (dma->desc_buf.area) { | |
373 | writel(0, chip->remap_addr + dma->ops->llp_offset); | |
374 | snd_dma_free_pages(&dma->desc_buf); | |
375 | dma->desc_buf.area = NULL; | |
376 | } | |
377 | } | |
378 | ||
379 | /* | |
380 | * AC97 interface | |
381 | */ | |
74ee4ff1 | 382 | static int snd_atiixp_acquire_codec(struct atiixp_modem *chip) |
1da177e4 LT |
383 | { |
384 | int timeout = 1000; | |
385 | ||
386 | while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) { | |
387 | if (! timeout--) { | |
ca6aafd8 | 388 | dev_warn(chip->card->dev, "codec acquire timeout\n"); |
1da177e4 LT |
389 | return -EBUSY; |
390 | } | |
391 | udelay(1); | |
392 | } | |
393 | return 0; | |
394 | } | |
395 | ||
74ee4ff1 TI |
396 | static unsigned short snd_atiixp_codec_read(struct atiixp_modem *chip, |
397 | unsigned short codec, | |
398 | unsigned short reg) | |
1da177e4 LT |
399 | { |
400 | unsigned int data; | |
401 | int timeout; | |
402 | ||
403 | if (snd_atiixp_acquire_codec(chip) < 0) | |
404 | return 0xffff; | |
405 | data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | | |
406 | ATI_REG_PHYS_OUT_ADDR_EN | | |
407 | ATI_REG_PHYS_OUT_RW | | |
408 | codec; | |
409 | atiixp_write(chip, PHYS_OUT_ADDR, data); | |
410 | if (snd_atiixp_acquire_codec(chip) < 0) | |
411 | return 0xffff; | |
412 | timeout = 1000; | |
413 | do { | |
414 | data = atiixp_read(chip, PHYS_IN_ADDR); | |
415 | if (data & ATI_REG_PHYS_IN_READ_FLAG) | |
416 | return data >> ATI_REG_PHYS_IN_DATA_SHIFT; | |
417 | udelay(1); | |
418 | } while (--timeout); | |
419 | /* time out may happen during reset */ | |
420 | if (reg < 0x7c) | |
ca6aafd8 | 421 | dev_warn(chip->card->dev, "codec read timeout (reg %x)\n", reg); |
1da177e4 LT |
422 | return 0xffff; |
423 | } | |
424 | ||
425 | ||
74ee4ff1 TI |
426 | static void snd_atiixp_codec_write(struct atiixp_modem *chip, |
427 | unsigned short codec, | |
428 | unsigned short reg, unsigned short val) | |
1da177e4 LT |
429 | { |
430 | unsigned int data; | |
431 | ||
432 | if (snd_atiixp_acquire_codec(chip) < 0) | |
433 | return; | |
434 | data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) | | |
435 | ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) | | |
436 | ATI_REG_PHYS_OUT_ADDR_EN | codec; | |
437 | atiixp_write(chip, PHYS_OUT_ADDR, data); | |
438 | } | |
439 | ||
440 | ||
74ee4ff1 TI |
441 | static unsigned short snd_atiixp_ac97_read(struct snd_ac97 *ac97, |
442 | unsigned short reg) | |
1da177e4 | 443 | { |
74ee4ff1 | 444 | struct atiixp_modem *chip = ac97->private_data; |
1da177e4 LT |
445 | return snd_atiixp_codec_read(chip, ac97->num, reg); |
446 | ||
447 | } | |
448 | ||
74ee4ff1 TI |
449 | static void snd_atiixp_ac97_write(struct snd_ac97 *ac97, unsigned short reg, |
450 | unsigned short val) | |
1da177e4 | 451 | { |
74ee4ff1 | 452 | struct atiixp_modem *chip = ac97->private_data; |
83a5b72a SK |
453 | if (reg == AC97_GPIO_STATUS) { |
454 | atiixp_write(chip, MODEM_OUT_GPIO, | |
455 | (val << ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT) | ATI_REG_MODEM_OUT_GPIO_EN); | |
456 | return; | |
457 | } | |
1da177e4 LT |
458 | snd_atiixp_codec_write(chip, ac97->num, reg, val); |
459 | } | |
460 | ||
461 | /* | |
462 | * reset AC link | |
463 | */ | |
74ee4ff1 | 464 | static int snd_atiixp_aclink_reset(struct atiixp_modem *chip) |
1da177e4 LT |
465 | { |
466 | int timeout; | |
467 | ||
468 | /* reset powerdoewn */ | |
469 | if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0)) | |
470 | udelay(10); | |
471 | ||
472 | /* perform a software reset */ | |
473 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET); | |
474 | atiixp_read(chip, CMD); | |
475 | udelay(10); | |
476 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0); | |
477 | ||
478 | timeout = 10; | |
479 | while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) { | |
480 | /* do a hard reset */ | |
481 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, | |
482 | ATI_REG_CMD_AC_SYNC); | |
483 | atiixp_read(chip, CMD); | |
bfdcbace | 484 | msleep(1); |
1da177e4 | 485 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET); |
7e79443c | 486 | if (!--timeout) { |
ca6aafd8 | 487 | dev_err(chip->card->dev, "codec reset timeout\n"); |
1da177e4 LT |
488 | break; |
489 | } | |
490 | } | |
491 | ||
492 | /* deassert RESET and assert SYNC to make sure */ | |
493 | atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET, | |
494 | ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
c7561cd8 | 499 | #ifdef CONFIG_PM_SLEEP |
74ee4ff1 | 500 | static int snd_atiixp_aclink_down(struct atiixp_modem *chip) |
1da177e4 LT |
501 | { |
502 | // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */ | |
503 | // return -EBUSY; | |
504 | atiixp_update(chip, CMD, | |
505 | ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET, | |
506 | ATI_REG_CMD_POWERDOWN); | |
507 | return 0; | |
508 | } | |
509 | #endif | |
510 | ||
511 | /* | |
512 | * auto-detection of codecs | |
513 | * | |
514 | * the IXP chip can generate interrupts for the non-existing codecs. | |
515 | * NEW_FRAME interrupt is used to make sure that the interrupt is generated | |
516 | * even if all three codecs are connected. | |
517 | */ | |
518 | ||
519 | #define ALL_CODEC_NOT_READY \ | |
520 | (ATI_REG_ISR_CODEC0_NOT_READY |\ | |
521 | ATI_REG_ISR_CODEC1_NOT_READY |\ | |
522 | ATI_REG_ISR_CODEC2_NOT_READY) | |
523 | #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME) | |
524 | ||
74ee4ff1 | 525 | static int snd_atiixp_codec_detect(struct atiixp_modem *chip) |
1da177e4 LT |
526 | { |
527 | int timeout; | |
528 | ||
529 | chip->codec_not_ready_bits = 0; | |
530 | atiixp_write(chip, IER, CODEC_CHECK_BITS); | |
531 | /* wait for the interrupts */ | |
bfdcbace | 532 | timeout = 50; |
1da177e4 | 533 | while (timeout-- > 0) { |
bfdcbace | 534 | msleep(1); |
1da177e4 LT |
535 | if (chip->codec_not_ready_bits) |
536 | break; | |
537 | } | |
538 | atiixp_write(chip, IER, 0); /* disable irqs */ | |
539 | ||
540 | if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) { | |
ca6aafd8 | 541 | dev_err(chip->card->dev, "no codec detected!\n"); |
1da177e4 LT |
542 | return -ENXIO; |
543 | } | |
544 | return 0; | |
545 | } | |
546 | ||
547 | ||
548 | /* | |
549 | * enable DMA and irqs | |
550 | */ | |
74ee4ff1 | 551 | static int snd_atiixp_chip_start(struct atiixp_modem *chip) |
1da177e4 LT |
552 | { |
553 | unsigned int reg; | |
554 | ||
555 | /* set up spdif, enable burst mode */ | |
556 | reg = atiixp_read(chip, CMD); | |
557 | reg |= ATI_REG_CMD_BURST_EN; | |
558 | if(!(reg & ATI_REG_CMD_MODEM_PRESENT)) | |
559 | reg |= ATI_REG_CMD_MODEM_PRESENT; | |
560 | atiixp_write(chip, CMD, reg); | |
561 | ||
562 | /* clear all interrupt source */ | |
563 | atiixp_write(chip, ISR, 0xffffffff); | |
564 | /* enable irqs */ | |
565 | atiixp_write(chip, IER, | |
566 | ATI_REG_IER_MODEM_STATUS_EN | | |
567 | ATI_REG_IER_MODEM_IN_XRUN_EN | | |
568 | ATI_REG_IER_MODEM_OUT1_XRUN_EN); | |
569 | return 0; | |
570 | } | |
571 | ||
572 | ||
573 | /* | |
574 | * disable DMA and IRQs | |
575 | */ | |
74ee4ff1 | 576 | static int snd_atiixp_chip_stop(struct atiixp_modem *chip) |
1da177e4 LT |
577 | { |
578 | /* clear interrupt source */ | |
579 | atiixp_write(chip, ISR, atiixp_read(chip, ISR)); | |
580 | /* disable irqs */ | |
581 | atiixp_write(chip, IER, 0); | |
582 | return 0; | |
583 | } | |
584 | ||
585 | ||
586 | /* | |
587 | * PCM section | |
588 | */ | |
589 | ||
590 | /* | |
591 | * pointer callback simplly reads XXX_DMA_DT_CUR register as the current | |
592 | * position. when SG-buffer is implemented, the offset must be calculated | |
593 | * correctly... | |
594 | */ | |
74ee4ff1 | 595 | static snd_pcm_uframes_t snd_atiixp_pcm_pointer(struct snd_pcm_substream *substream) |
1da177e4 | 596 | { |
74ee4ff1 TI |
597 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
598 | struct snd_pcm_runtime *runtime = substream->runtime; | |
599 | struct atiixp_dma *dma = runtime->private_data; | |
1da177e4 LT |
600 | unsigned int curptr; |
601 | int timeout = 1000; | |
602 | ||
603 | while (timeout--) { | |
604 | curptr = readl(chip->remap_addr + dma->ops->dt_cur); | |
605 | if (curptr < dma->buf_addr) | |
606 | continue; | |
607 | curptr -= dma->buf_addr; | |
608 | if (curptr >= dma->buf_bytes) | |
609 | continue; | |
610 | return bytes_to_frames(runtime, curptr); | |
611 | } | |
ca6aafd8 | 612 | dev_dbg(chip->card->dev, "invalid DMA pointer read 0x%x (buf=%x)\n", |
1da177e4 LT |
613 | readl(chip->remap_addr + dma->ops->dt_cur), dma->buf_addr); |
614 | return 0; | |
615 | } | |
616 | ||
617 | /* | |
618 | * XRUN detected, and stop the PCM substream | |
619 | */ | |
74ee4ff1 TI |
620 | static void snd_atiixp_xrun_dma(struct atiixp_modem *chip, |
621 | struct atiixp_dma *dma) | |
1da177e4 LT |
622 | { |
623 | if (! dma->substream || ! dma->running) | |
624 | return; | |
ca6aafd8 | 625 | dev_dbg(chip->card->dev, "XRUN detected (DMA %d)\n", dma->ops->type); |
1fb8510c | 626 | snd_pcm_stop_xrun(dma->substream); |
1da177e4 LT |
627 | } |
628 | ||
629 | /* | |
630 | * the period ack. update the substream. | |
631 | */ | |
74ee4ff1 TI |
632 | static void snd_atiixp_update_dma(struct atiixp_modem *chip, |
633 | struct atiixp_dma *dma) | |
1da177e4 LT |
634 | { |
635 | if (! dma->substream || ! dma->running) | |
636 | return; | |
637 | snd_pcm_period_elapsed(dma->substream); | |
638 | } | |
639 | ||
640 | /* set BUS_BUSY interrupt bit if any DMA is running */ | |
641 | /* call with spinlock held */ | |
74ee4ff1 | 642 | static void snd_atiixp_check_bus_busy(struct atiixp_modem *chip) |
1da177e4 LT |
643 | { |
644 | unsigned int bus_busy; | |
645 | if (atiixp_read(chip, CMD) & (ATI_REG_CMD_MODEM_SEND1_EN | | |
646 | ATI_REG_CMD_MODEM_RECEIVE_EN)) | |
647 | bus_busy = ATI_REG_IER_MODEM_SET_BUS_BUSY; | |
648 | else | |
649 | bus_busy = 0; | |
650 | atiixp_update(chip, IER, ATI_REG_IER_MODEM_SET_BUS_BUSY, bus_busy); | |
651 | } | |
652 | ||
653 | /* common trigger callback | |
654 | * calling the lowlevel callbacks in it | |
655 | */ | |
74ee4ff1 | 656 | static int snd_atiixp_pcm_trigger(struct snd_pcm_substream *substream, int cmd) |
1da177e4 | 657 | { |
74ee4ff1 TI |
658 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
659 | struct atiixp_dma *dma = substream->runtime->private_data; | |
83a5b72a | 660 | int err = 0; |
1da177e4 | 661 | |
da3cec35 TI |
662 | if (snd_BUG_ON(!dma->ops->enable_transfer || |
663 | !dma->ops->flush_dma)) | |
664 | return -EINVAL; | |
1da177e4 | 665 | |
1da177e4 | 666 | spin_lock(&chip->reg_lock); |
83a5b72a SK |
667 | switch(cmd) { |
668 | case SNDRV_PCM_TRIGGER_START: | |
1da177e4 LT |
669 | dma->ops->enable_transfer(chip, 1); |
670 | dma->running = 1; | |
83a5b72a SK |
671 | break; |
672 | case SNDRV_PCM_TRIGGER_STOP: | |
1da177e4 LT |
673 | dma->ops->enable_transfer(chip, 0); |
674 | dma->running = 0; | |
83a5b72a SK |
675 | break; |
676 | default: | |
677 | err = -EINVAL; | |
678 | break; | |
1da177e4 | 679 | } |
83a5b72a | 680 | if (! err) { |
1da177e4 LT |
681 | snd_atiixp_check_bus_busy(chip); |
682 | if (cmd == SNDRV_PCM_TRIGGER_STOP) { | |
683 | dma->ops->flush_dma(chip); | |
684 | snd_atiixp_check_bus_busy(chip); | |
685 | } | |
83a5b72a | 686 | } |
1da177e4 | 687 | spin_unlock(&chip->reg_lock); |
83a5b72a | 688 | return err; |
1da177e4 LT |
689 | } |
690 | ||
691 | ||
692 | /* | |
693 | * lowlevel callbacks for each DMA type | |
694 | * | |
695 | * every callback is supposed to be called in chip->reg_lock spinlock | |
696 | */ | |
697 | ||
698 | /* flush FIFO of analog OUT DMA */ | |
74ee4ff1 | 699 | static void atiixp_out_flush_dma(struct atiixp_modem *chip) |
1da177e4 LT |
700 | { |
701 | atiixp_write(chip, MODEM_FIFO_FLUSH, ATI_REG_MODEM_FIFO_OUT1_FLUSH); | |
702 | } | |
703 | ||
704 | /* enable/disable analog OUT DMA */ | |
74ee4ff1 | 705 | static void atiixp_out_enable_dma(struct atiixp_modem *chip, int on) |
1da177e4 LT |
706 | { |
707 | unsigned int data; | |
708 | data = atiixp_read(chip, CMD); | |
709 | if (on) { | |
710 | if (data & ATI_REG_CMD_MODEM_OUT_DMA1_EN) | |
711 | return; | |
712 | atiixp_out_flush_dma(chip); | |
713 | data |= ATI_REG_CMD_MODEM_OUT_DMA1_EN; | |
714 | } else | |
715 | data &= ~ATI_REG_CMD_MODEM_OUT_DMA1_EN; | |
716 | atiixp_write(chip, CMD, data); | |
717 | } | |
718 | ||
719 | /* start/stop transfer over OUT DMA */ | |
74ee4ff1 | 720 | static void atiixp_out_enable_transfer(struct atiixp_modem *chip, int on) |
1da177e4 LT |
721 | { |
722 | atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_SEND1_EN, | |
723 | on ? ATI_REG_CMD_MODEM_SEND1_EN : 0); | |
724 | } | |
725 | ||
726 | /* enable/disable analog IN DMA */ | |
74ee4ff1 | 727 | static void atiixp_in_enable_dma(struct atiixp_modem *chip, int on) |
1da177e4 LT |
728 | { |
729 | atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_IN_DMA_EN, | |
730 | on ? ATI_REG_CMD_MODEM_IN_DMA_EN : 0); | |
731 | } | |
732 | ||
733 | /* start/stop analog IN DMA */ | |
74ee4ff1 | 734 | static void atiixp_in_enable_transfer(struct atiixp_modem *chip, int on) |
1da177e4 LT |
735 | { |
736 | if (on) { | |
737 | unsigned int data = atiixp_read(chip, CMD); | |
738 | if (! (data & ATI_REG_CMD_MODEM_RECEIVE_EN)) { | |
739 | data |= ATI_REG_CMD_MODEM_RECEIVE_EN; | |
740 | atiixp_write(chip, CMD, data); | |
741 | } | |
742 | } else | |
743 | atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_RECEIVE_EN, 0); | |
744 | } | |
745 | ||
746 | /* flush FIFO of analog IN DMA */ | |
74ee4ff1 | 747 | static void atiixp_in_flush_dma(struct atiixp_modem *chip) |
1da177e4 LT |
748 | { |
749 | atiixp_write(chip, MODEM_FIFO_FLUSH, ATI_REG_MODEM_FIFO_IN_FLUSH); | |
750 | } | |
751 | ||
752 | /* set up slots and formats for analog OUT */ | |
74ee4ff1 | 753 | static int snd_atiixp_playback_prepare(struct snd_pcm_substream *substream) |
1da177e4 | 754 | { |
74ee4ff1 | 755 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
756 | unsigned int data; |
757 | ||
758 | spin_lock_irq(&chip->reg_lock); | |
759 | /* set output threshold */ | |
760 | data = atiixp_read(chip, MODEM_OUT_FIFO); | |
761 | data &= ~ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK; | |
762 | data |= 0x04 << ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT; | |
763 | atiixp_write(chip, MODEM_OUT_FIFO, data); | |
764 | spin_unlock_irq(&chip->reg_lock); | |
765 | return 0; | |
766 | } | |
767 | ||
768 | /* set up slots and formats for analog IN */ | |
74ee4ff1 | 769 | static int snd_atiixp_capture_prepare(struct snd_pcm_substream *substream) |
1da177e4 LT |
770 | { |
771 | return 0; | |
772 | } | |
773 | ||
774 | /* | |
775 | * hw_params - allocate the buffer and set up buffer descriptors | |
776 | */ | |
74ee4ff1 TI |
777 | static int snd_atiixp_pcm_hw_params(struct snd_pcm_substream *substream, |
778 | struct snd_pcm_hw_params *hw_params) | |
1da177e4 | 779 | { |
74ee4ff1 TI |
780 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
781 | struct atiixp_dma *dma = substream->runtime->private_data; | |
1da177e4 LT |
782 | int err; |
783 | int i; | |
784 | ||
1da177e4 LT |
785 | dma->buf_addr = substream->runtime->dma_addr; |
786 | dma->buf_bytes = params_buffer_bytes(hw_params); | |
787 | ||
788 | err = atiixp_build_dma_packets(chip, dma, substream, | |
789 | params_periods(hw_params), | |
790 | params_period_bytes(hw_params)); | |
791 | if (err < 0) | |
792 | return err; | |
793 | ||
794 | /* set up modem rate */ | |
795 | for (i = 0; i < NUM_ATI_CODECS; i++) { | |
796 | if (! chip->ac97[i]) | |
797 | continue; | |
798 | snd_ac97_write(chip->ac97[i], AC97_LINE1_RATE, params_rate(hw_params)); | |
799 | snd_ac97_write(chip->ac97[i], AC97_LINE1_LEVEL, 0); | |
800 | } | |
801 | ||
802 | return err; | |
803 | } | |
804 | ||
74ee4ff1 | 805 | static int snd_atiixp_pcm_hw_free(struct snd_pcm_substream *substream) |
1da177e4 | 806 | { |
74ee4ff1 TI |
807 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
808 | struct atiixp_dma *dma = substream->runtime->private_data; | |
1da177e4 LT |
809 | |
810 | atiixp_clear_dma_packets(chip, dma, substream); | |
1da177e4 LT |
811 | return 0; |
812 | } | |
813 | ||
814 | ||
815 | /* | |
816 | * pcm hardware definition, identical for all DMA types | |
817 | */ | |
dee49895 | 818 | static const struct snd_pcm_hardware snd_atiixp_pcm_hw = |
1da177e4 LT |
819 | { |
820 | .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | | |
821 | SNDRV_PCM_INFO_BLOCK_TRANSFER | | |
822 | SNDRV_PCM_INFO_MMAP_VALID), | |
823 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
74ee4ff1 TI |
824 | .rates = (SNDRV_PCM_RATE_8000 | |
825 | SNDRV_PCM_RATE_16000 | | |
826 | SNDRV_PCM_RATE_KNOT), | |
1da177e4 LT |
827 | .rate_min = 8000, |
828 | .rate_max = 16000, | |
829 | .channels_min = 2, | |
830 | .channels_max = 2, | |
831 | .buffer_bytes_max = 256 * 1024, | |
832 | .period_bytes_min = 32, | |
833 | .period_bytes_max = 128 * 1024, | |
834 | .periods_min = 2, | |
835 | .periods_max = ATI_MAX_DESCRIPTORS, | |
836 | }; | |
837 | ||
74ee4ff1 TI |
838 | static int snd_atiixp_pcm_open(struct snd_pcm_substream *substream, |
839 | struct atiixp_dma *dma, int pcm_type) | |
1da177e4 | 840 | { |
74ee4ff1 TI |
841 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
842 | struct snd_pcm_runtime *runtime = substream->runtime; | |
1da177e4 | 843 | int err; |
c15ec07b TI |
844 | static const unsigned int rates[] = { 8000, 9600, 12000, 16000 }; |
845 | static const struct snd_pcm_hw_constraint_list hw_constraints_rates = { | |
1da177e4 LT |
846 | .count = ARRAY_SIZE(rates), |
847 | .list = rates, | |
848 | .mask = 0, | |
849 | }; | |
850 | ||
da3cec35 TI |
851 | if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) |
852 | return -EINVAL; | |
1da177e4 LT |
853 | |
854 | if (dma->opened) | |
855 | return -EBUSY; | |
856 | dma->substream = substream; | |
857 | runtime->hw = snd_atiixp_pcm_hw; | |
858 | dma->ac97_pcm_type = pcm_type; | |
b83bea38 TI |
859 | err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, |
860 | &hw_constraints_rates); | |
861 | if (err < 0) | |
1da177e4 | 862 | return err; |
b83bea38 TI |
863 | err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); |
864 | if (err < 0) | |
1da177e4 LT |
865 | return err; |
866 | runtime->private_data = dma; | |
867 | ||
868 | /* enable DMA bits */ | |
869 | spin_lock_irq(&chip->reg_lock); | |
870 | dma->ops->enable_dma(chip, 1); | |
871 | spin_unlock_irq(&chip->reg_lock); | |
872 | dma->opened = 1; | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
74ee4ff1 TI |
877 | static int snd_atiixp_pcm_close(struct snd_pcm_substream *substream, |
878 | struct atiixp_dma *dma) | |
1da177e4 | 879 | { |
74ee4ff1 | 880 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 881 | /* disable DMA bits */ |
da3cec35 TI |
882 | if (snd_BUG_ON(!dma->ops || !dma->ops->enable_dma)) |
883 | return -EINVAL; | |
1da177e4 LT |
884 | spin_lock_irq(&chip->reg_lock); |
885 | dma->ops->enable_dma(chip, 0); | |
886 | spin_unlock_irq(&chip->reg_lock); | |
887 | dma->substream = NULL; | |
888 | dma->opened = 0; | |
889 | return 0; | |
890 | } | |
891 | ||
892 | /* | |
893 | */ | |
74ee4ff1 | 894 | static int snd_atiixp_playback_open(struct snd_pcm_substream *substream) |
1da177e4 | 895 | { |
74ee4ff1 | 896 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
897 | int err; |
898 | ||
62932df8 | 899 | mutex_lock(&chip->open_mutex); |
1da177e4 | 900 | err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0); |
62932df8 | 901 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
902 | if (err < 0) |
903 | return err; | |
904 | return 0; | |
905 | } | |
906 | ||
74ee4ff1 | 907 | static int snd_atiixp_playback_close(struct snd_pcm_substream *substream) |
1da177e4 | 908 | { |
74ee4ff1 | 909 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
1da177e4 | 910 | int err; |
62932df8 | 911 | mutex_lock(&chip->open_mutex); |
1da177e4 | 912 | err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]); |
62932df8 | 913 | mutex_unlock(&chip->open_mutex); |
1da177e4 LT |
914 | return err; |
915 | } | |
916 | ||
74ee4ff1 | 917 | static int snd_atiixp_capture_open(struct snd_pcm_substream *substream) |
1da177e4 | 918 | { |
74ee4ff1 | 919 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
920 | return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1); |
921 | } | |
922 | ||
74ee4ff1 | 923 | static int snd_atiixp_capture_close(struct snd_pcm_substream *substream) |
1da177e4 | 924 | { |
74ee4ff1 | 925 | struct atiixp_modem *chip = snd_pcm_substream_chip(substream); |
1da177e4 LT |
926 | return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]); |
927 | } | |
928 | ||
929 | ||
930 | /* AC97 playback */ | |
6769e988 | 931 | static const struct snd_pcm_ops snd_atiixp_playback_ops = { |
1da177e4 LT |
932 | .open = snd_atiixp_playback_open, |
933 | .close = snd_atiixp_playback_close, | |
1da177e4 LT |
934 | .hw_params = snd_atiixp_pcm_hw_params, |
935 | .hw_free = snd_atiixp_pcm_hw_free, | |
936 | .prepare = snd_atiixp_playback_prepare, | |
937 | .trigger = snd_atiixp_pcm_trigger, | |
938 | .pointer = snd_atiixp_pcm_pointer, | |
939 | }; | |
940 | ||
941 | /* AC97 capture */ | |
6769e988 | 942 | static const struct snd_pcm_ops snd_atiixp_capture_ops = { |
1da177e4 LT |
943 | .open = snd_atiixp_capture_open, |
944 | .close = snd_atiixp_capture_close, | |
1da177e4 LT |
945 | .hw_params = snd_atiixp_pcm_hw_params, |
946 | .hw_free = snd_atiixp_pcm_hw_free, | |
947 | .prepare = snd_atiixp_capture_prepare, | |
948 | .trigger = snd_atiixp_pcm_trigger, | |
949 | .pointer = snd_atiixp_pcm_pointer, | |
950 | }; | |
951 | ||
064e186f | 952 | static const struct atiixp_dma_ops snd_atiixp_playback_dma_ops = { |
1da177e4 LT |
953 | .type = ATI_DMA_PLAYBACK, |
954 | .llp_offset = ATI_REG_MODEM_OUT_DMA1_LINKPTR, | |
955 | .dt_cur = ATI_REG_MODEM_OUT_DMA1_DT_CUR, | |
956 | .enable_dma = atiixp_out_enable_dma, | |
957 | .enable_transfer = atiixp_out_enable_transfer, | |
958 | .flush_dma = atiixp_out_flush_dma, | |
959 | }; | |
960 | ||
064e186f | 961 | static const struct atiixp_dma_ops snd_atiixp_capture_dma_ops = { |
1da177e4 LT |
962 | .type = ATI_DMA_CAPTURE, |
963 | .llp_offset = ATI_REG_MODEM_IN_DMA_LINKPTR, | |
964 | .dt_cur = ATI_REG_MODEM_IN_DMA_DT_CUR, | |
965 | .enable_dma = atiixp_in_enable_dma, | |
966 | .enable_transfer = atiixp_in_enable_transfer, | |
967 | .flush_dma = atiixp_in_flush_dma, | |
968 | }; | |
969 | ||
e23e7a14 | 970 | static int snd_atiixp_pcm_new(struct atiixp_modem *chip) |
1da177e4 | 971 | { |
74ee4ff1 | 972 | struct snd_pcm *pcm; |
1da177e4 LT |
973 | int err; |
974 | ||
975 | /* initialize constants */ | |
976 | chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops; | |
977 | chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops; | |
978 | ||
979 | /* PCM #0: analog I/O */ | |
980 | err = snd_pcm_new(chip->card, "ATI IXP MC97", ATI_PCMDEV_ANALOG, 1, 1, &pcm); | |
981 | if (err < 0) | |
982 | return err; | |
983 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops); | |
984 | snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops); | |
6632d198 | 985 | pcm->dev_class = SNDRV_PCM_CLASS_MODEM; |
1da177e4 LT |
986 | pcm->private_data = chip; |
987 | strcpy(pcm->name, "ATI IXP MC97"); | |
988 | chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm; | |
989 | ||
801bf057 TI |
990 | snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, |
991 | &chip->pci->dev, 64*1024, 128*1024); | |
1da177e4 LT |
992 | |
993 | return 0; | |
994 | } | |
995 | ||
996 | ||
997 | ||
998 | /* | |
999 | * interrupt handler | |
1000 | */ | |
7d12e780 | 1001 | static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id) |
1da177e4 | 1002 | { |
74ee4ff1 | 1003 | struct atiixp_modem *chip = dev_id; |
1da177e4 LT |
1004 | unsigned int status; |
1005 | ||
1006 | status = atiixp_read(chip, ISR); | |
1007 | ||
1008 | if (! status) | |
1009 | return IRQ_NONE; | |
1010 | ||
1011 | /* process audio DMA */ | |
1012 | if (status & ATI_REG_ISR_MODEM_OUT1_XRUN) | |
1013 | snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1014 | else if (status & ATI_REG_ISR_MODEM_OUT1_STATUS) | |
1015 | snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]); | |
1016 | if (status & ATI_REG_ISR_MODEM_IN_XRUN) | |
1017 | snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); | |
1018 | else if (status & ATI_REG_ISR_MODEM_IN_STATUS) | |
1019 | snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]); | |
1020 | ||
1021 | /* for codec detection */ | |
1022 | if (status & CODEC_CHECK_BITS) { | |
1023 | unsigned int detected; | |
1024 | detected = status & CODEC_CHECK_BITS; | |
1025 | spin_lock(&chip->reg_lock); | |
1026 | chip->codec_not_ready_bits |= detected; | |
1027 | atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */ | |
1028 | spin_unlock(&chip->reg_lock); | |
1029 | } | |
1030 | ||
1031 | /* ack */ | |
1032 | atiixp_write(chip, ISR, status); | |
1033 | ||
1034 | return IRQ_HANDLED; | |
1035 | } | |
1036 | ||
1037 | ||
1038 | /* | |
1039 | * ac97 mixer section | |
1040 | */ | |
1041 | ||
e23e7a14 | 1042 | static int snd_atiixp_mixer_new(struct atiixp_modem *chip, int clock) |
1da177e4 | 1043 | { |
74ee4ff1 TI |
1044 | struct snd_ac97_bus *pbus; |
1045 | struct snd_ac97_template ac97; | |
1da177e4 LT |
1046 | int i, err; |
1047 | int codec_count; | |
51055da5 | 1048 | static const struct snd_ac97_bus_ops ops = { |
1da177e4 LT |
1049 | .write = snd_atiixp_ac97_write, |
1050 | .read = snd_atiixp_ac97_read, | |
1051 | }; | |
066c044b | 1052 | static const unsigned int codec_skip[NUM_ATI_CODECS] = { |
1da177e4 LT |
1053 | ATI_REG_ISR_CODEC0_NOT_READY, |
1054 | ATI_REG_ISR_CODEC1_NOT_READY, | |
1055 | ATI_REG_ISR_CODEC2_NOT_READY, | |
1056 | }; | |
1057 | ||
1058 | if (snd_atiixp_codec_detect(chip) < 0) | |
1059 | return -ENXIO; | |
1060 | ||
b83bea38 TI |
1061 | err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus); |
1062 | if (err < 0) | |
1da177e4 LT |
1063 | return err; |
1064 | pbus->clock = clock; | |
1da177e4 LT |
1065 | chip->ac97_bus = pbus; |
1066 | ||
1067 | codec_count = 0; | |
1068 | for (i = 0; i < NUM_ATI_CODECS; i++) { | |
1069 | if (chip->codec_not_ready_bits & codec_skip[i]) | |
1070 | continue; | |
1071 | memset(&ac97, 0, sizeof(ac97)); | |
1072 | ac97.private_data = chip; | |
1073 | ac97.pci = chip->pci; | |
1074 | ac97.num = i; | |
f1a63a38 | 1075 | ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE; |
b83bea38 TI |
1076 | err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i]); |
1077 | if (err < 0) { | |
1da177e4 | 1078 | chip->ac97[i] = NULL; /* to be sure */ |
ca6aafd8 TI |
1079 | dev_dbg(chip->card->dev, |
1080 | "codec %d not available for modem\n", i); | |
1da177e4 LT |
1081 | continue; |
1082 | } | |
1083 | codec_count++; | |
1084 | } | |
1085 | ||
1086 | if (! codec_count) { | |
ca6aafd8 | 1087 | dev_err(chip->card->dev, "no codec available\n"); |
1da177e4 LT |
1088 | return -ENODEV; |
1089 | } | |
1090 | ||
1091 | /* snd_ac97_tune_hardware(chip->ac97, ac97_quirks); */ | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | ||
c7561cd8 | 1097 | #ifdef CONFIG_PM_SLEEP |
1da177e4 LT |
1098 | /* |
1099 | * power management | |
1100 | */ | |
68cb2b55 | 1101 | static int snd_atiixp_suspend(struct device *dev) |
1da177e4 | 1102 | { |
68cb2b55 | 1103 | struct snd_card *card = dev_get_drvdata(dev); |
92304cc7 | 1104 | struct atiixp_modem *chip = card->private_data; |
1da177e4 LT |
1105 | int i; |
1106 | ||
92304cc7 | 1107 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
1da177e4 | 1108 | for (i = 0; i < NUM_ATI_CODECS; i++) |
92304cc7 | 1109 | snd_ac97_suspend(chip->ac97[i]); |
1da177e4 LT |
1110 | snd_atiixp_aclink_down(chip); |
1111 | snd_atiixp_chip_stop(chip); | |
1da177e4 LT |
1112 | return 0; |
1113 | } | |
1114 | ||
68cb2b55 | 1115 | static int snd_atiixp_resume(struct device *dev) |
1da177e4 | 1116 | { |
68cb2b55 | 1117 | struct snd_card *card = dev_get_drvdata(dev); |
92304cc7 | 1118 | struct atiixp_modem *chip = card->private_data; |
1da177e4 LT |
1119 | int i; |
1120 | ||
1da177e4 LT |
1121 | snd_atiixp_aclink_reset(chip); |
1122 | snd_atiixp_chip_start(chip); | |
1123 | ||
1124 | for (i = 0; i < NUM_ATI_CODECS; i++) | |
92304cc7 | 1125 | snd_ac97_resume(chip->ac97[i]); |
1da177e4 | 1126 | |
92304cc7 | 1127 | snd_power_change_state(card, SNDRV_CTL_POWER_D0); |
1da177e4 LT |
1128 | return 0; |
1129 | } | |
1da177e4 | 1130 | |
68cb2b55 TI |
1131 | static SIMPLE_DEV_PM_OPS(snd_atiixp_pm, snd_atiixp_suspend, snd_atiixp_resume); |
1132 | #define SND_ATIIXP_PM_OPS &snd_atiixp_pm | |
1133 | #else | |
1134 | #define SND_ATIIXP_PM_OPS NULL | |
c7561cd8 | 1135 | #endif /* CONFIG_PM_SLEEP */ |
1da177e4 LT |
1136 | |
1137 | /* | |
1138 | * proc interface for register dump | |
1139 | */ | |
1140 | ||
74ee4ff1 TI |
1141 | static void snd_atiixp_proc_read(struct snd_info_entry *entry, |
1142 | struct snd_info_buffer *buffer) | |
1da177e4 | 1143 | { |
74ee4ff1 | 1144 | struct atiixp_modem *chip = entry->private_data; |
1da177e4 LT |
1145 | int i; |
1146 | ||
1147 | for (i = 0; i < 256; i += 4) | |
1148 | snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i)); | |
1149 | } | |
1150 | ||
e23e7a14 | 1151 | static void snd_atiixp_proc_init(struct atiixp_modem *chip) |
1da177e4 | 1152 | { |
47f2769b TI |
1153 | snd_card_ro_proc_new(chip->card, "atiixp-modem", chip, |
1154 | snd_atiixp_proc_read); | |
1da177e4 | 1155 | } |
1da177e4 LT |
1156 | |
1157 | ||
1158 | /* | |
1159 | * destructor | |
1160 | */ | |
1161 | ||
86bde74d | 1162 | static void snd_atiixp_free(struct snd_card *card) |
1da177e4 | 1163 | { |
86bde74d | 1164 | snd_atiixp_chip_stop(card->private_data); |
1da177e4 LT |
1165 | } |
1166 | ||
1167 | /* | |
1168 | * constructor for chip instance | |
1169 | */ | |
86bde74d | 1170 | static int snd_atiixp_init(struct snd_card *card, struct pci_dev *pci) |
1da177e4 | 1171 | { |
86bde74d | 1172 | struct atiixp_modem *chip = card->private_data; |
1da177e4 LT |
1173 | int err; |
1174 | ||
86bde74d | 1175 | err = pcim_enable_device(pci); |
b83bea38 | 1176 | if (err < 0) |
1da177e4 LT |
1177 | return err; |
1178 | ||
1da177e4 | 1179 | spin_lock_init(&chip->reg_lock); |
62932df8 | 1180 | mutex_init(&chip->open_mutex); |
1da177e4 LT |
1181 | chip->card = card; |
1182 | chip->pci = pci; | |
1183 | chip->irq = -1; | |
86bde74d TI |
1184 | err = pcim_iomap_regions(pci, 1 << 0, "ATI IXP MC97"); |
1185 | if (err < 0) | |
1da177e4 | 1186 | return err; |
1da177e4 | 1187 | chip->addr = pci_resource_start(pci, 0); |
86bde74d | 1188 | chip->remap_addr = pcim_iomap_table(pci)[0]; |
1da177e4 | 1189 | |
86bde74d TI |
1190 | if (devm_request_irq(&pci->dev, pci->irq, snd_atiixp_interrupt, |
1191 | IRQF_SHARED, KBUILD_MODNAME, chip)) { | |
ca6aafd8 | 1192 | dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); |
1da177e4 LT |
1193 | return -EBUSY; |
1194 | } | |
1195 | chip->irq = pci->irq; | |
4504487d | 1196 | card->sync_irq = chip->irq; |
86bde74d | 1197 | card->private_free = snd_atiixp_free; |
1da177e4 | 1198 | pci_set_master(pci); |
1da177e4 | 1199 | |
1da177e4 LT |
1200 | return 0; |
1201 | } | |
1202 | ||
1203 | ||
48e8adde TI |
1204 | static int __snd_atiixp_probe(struct pci_dev *pci, |
1205 | const struct pci_device_id *pci_id) | |
1da177e4 | 1206 | { |
74ee4ff1 TI |
1207 | struct snd_card *card; |
1208 | struct atiixp_modem *chip; | |
1da177e4 LT |
1209 | int err; |
1210 | ||
86bde74d TI |
1211 | err = snd_devm_card_new(&pci->dev, index, id, THIS_MODULE, |
1212 | sizeof(*chip), &card); | |
e58de7ba TI |
1213 | if (err < 0) |
1214 | return err; | |
86bde74d | 1215 | chip = card->private_data; |
1da177e4 | 1216 | |
1da177e4 LT |
1217 | strcpy(card->driver, "ATIIXP-MODEM"); |
1218 | strcpy(card->shortname, "ATI IXP Modem"); | |
86bde74d | 1219 | err = snd_atiixp_init(card, pci); |
b83bea38 | 1220 | if (err < 0) |
86bde74d | 1221 | return err; |
1da177e4 | 1222 | |
b83bea38 TI |
1223 | err = snd_atiixp_aclink_reset(chip); |
1224 | if (err < 0) | |
86bde74d | 1225 | return err; |
1da177e4 | 1226 | |
b83bea38 TI |
1227 | err = snd_atiixp_mixer_new(chip, ac97_clock); |
1228 | if (err < 0) | |
86bde74d | 1229 | return err; |
1da177e4 | 1230 | |
b83bea38 TI |
1231 | err = snd_atiixp_pcm_new(chip); |
1232 | if (err < 0) | |
86bde74d | 1233 | return err; |
1da177e4 LT |
1234 | |
1235 | snd_atiixp_proc_init(chip); | |
1236 | ||
1237 | snd_atiixp_chip_start(chip); | |
1238 | ||
1239 | sprintf(card->longname, "%s rev %x at 0x%lx, irq %i", | |
44c10138 | 1240 | card->shortname, pci->revision, chip->addr, chip->irq); |
1da177e4 | 1241 | |
b83bea38 TI |
1242 | err = snd_card_register(card); |
1243 | if (err < 0) | |
86bde74d | 1244 | return err; |
1da177e4 LT |
1245 | |
1246 | pci_set_drvdata(pci, card); | |
1da177e4 | 1247 | return 0; |
1da177e4 LT |
1248 | } |
1249 | ||
48e8adde TI |
1250 | static int snd_atiixp_probe(struct pci_dev *pci, |
1251 | const struct pci_device_id *pci_id) | |
1252 | { | |
1253 | return snd_card_free_on_error(&pci->dev, __snd_atiixp_probe(pci, pci_id)); | |
1254 | } | |
1255 | ||
e9f66d9b | 1256 | static struct pci_driver atiixp_modem_driver = { |
3733e424 | 1257 | .name = KBUILD_MODNAME, |
1da177e4 LT |
1258 | .id_table = snd_atiixp_ids, |
1259 | .probe = snd_atiixp_probe, | |
68cb2b55 TI |
1260 | .driver = { |
1261 | .pm = SND_ATIIXP_PM_OPS, | |
1262 | }, | |
1da177e4 LT |
1263 | }; |
1264 | ||
e9f66d9b | 1265 | module_pci_driver(atiixp_modem_driver); |