[linux.git] / drivers / ssb / driver_mipscore.c

/*
 * Sonics Silicon Backplane
 * Broadcom MIPS core driver
 *
 * Copyright 2005, Broadcom Corporation
 * Copyright 2006, 2007, Michael Buesch <[email protected]>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/ssb/ssb.h>

#include <linux/mtd/physmap.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/time.h>
#ifdef CONFIG_BCM47XX
#include <linux/bcm47xx_nvram.h>
#endif

#include "ssb_private.h"

static const char * const part_probes[] = { "bcm47xxpart", NULL };

static struct physmap_flash_data ssb_pflash_data = {
	.part_probe_types	= part_probes,
};

static struct resource ssb_pflash_resource = {
	.name	= "ssb_pflash",
	.flags  = IORESOURCE_MEM,
};

struct platform_device ssb_pflash_dev = {
	.name		= "physmap-flash",
	.dev		= {
		.platform_data  = &ssb_pflash_data,
	},
	.resource	= &ssb_pflash_resource,
	.num_resources	= 1,
};

static inline u32 mips_read32(struct ssb_mipscore *mcore,
			      u16 offset)
{
	return ssb_read32(mcore->dev, offset);
}

static inline void mips_write32(struct ssb_mipscore *mcore,
				u16 offset,
				u32 value)
{
	ssb_write32(mcore->dev, offset, value);
}

static const u32 ipsflag_irq_mask[] = {
	0,
	SSB_IPSFLAG_IRQ1,
	SSB_IPSFLAG_IRQ2,
	SSB_IPSFLAG_IRQ3,
	SSB_IPSFLAG_IRQ4,
};

static const u32 ipsflag_irq_shift[] = {
	0,
	SSB_IPSFLAG_IRQ1_SHIFT,
	SSB_IPSFLAG_IRQ2_SHIFT,
	SSB_IPSFLAG_IRQ3_SHIFT,
	SSB_IPSFLAG_IRQ4_SHIFT,
};

static inline u32 ssb_irqflag(struct ssb_device *dev)
{
	u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
	if (tpsflag)
		return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
	else
		/* not irq supported */
		return 0x3f;
}

static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
{
	struct ssb_bus *bus = rdev->bus;
	int i;
	for (i = 0; i < bus->nr_devices; i++) {
		struct ssb_device *dev;
		dev = &(bus->devices[i]);
		if (ssb_irqflag(dev) == irqflag)
			return dev;
	}
	return NULL;
}

/* Get the MIPS IRQ assignment for a specified device.
 * If unassigned, 0 is returned.
 * If disabled, 5 is returned.
 * If not supported, 6 is returned.
 */
unsigned int ssb_mips_irq(struct ssb_device *dev)
{
	struct ssb_bus *bus = dev->bus;
	struct ssb_device *mdev = bus->mipscore.dev;
	u32 irqflag;
	u32 ipsflag;
	u32 tmp;
	unsigned int irq;

	irqflag = ssb_irqflag(dev);
	if (irqflag == 0x3f)
		return 6;
	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
	for (irq = 1; irq <= 4; irq++) {
		tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
		if (tmp == irqflag)
			break;
	}
	if (irq	== 5) {
		if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
			irq = 0;
	}

	return irq;
}

static void clear_irq(struct ssb_bus *bus, unsigned int irq)
{
	struct ssb_device *dev = bus->mipscore.dev;

	/* Clear the IRQ in the MIPScore backplane registers */
	if (irq == 0) {
		ssb_write32(dev, SSB_INTVEC, 0);
	} else {
		ssb_write32(dev, SSB_IPSFLAG,
			    ssb_read32(dev, SSB_IPSFLAG) |
			    ipsflag_irq_mask[irq]);
	}
}

static void set_irq(struct ssb_device *dev, unsigned int irq)
{
	unsigned int oldirq = ssb_mips_irq(dev);
	struct ssb_bus *bus = dev->bus;
	struct ssb_device *mdev = bus->mipscore.dev;
	u32 irqflag = ssb_irqflag(dev);

	BUG_ON(oldirq == 6);

	dev->irq = irq + 2;

	/* clear the old irq */
	if (oldirq == 0)
		ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
	else if (oldirq != 5)
		clear_irq(bus, oldirq);

	/* assign the new one */
	if (irq == 0) {
		ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
	} else {
		u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
		if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
			u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
			struct ssb_device *olddev = find_device(dev, oldipsflag);
			if (olddev)
				set_irq(olddev, 0);
		}
		irqflag <<= ipsflag_irq_shift[irq];
		irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
		ssb_write32(mdev, SSB_IPSFLAG, irqflag);
	}
	ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
		dev->id.coreid, oldirq+2, irq+2);
}

static void print_irq(struct ssb_device *dev, unsigned int irq)
{
	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
	ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
		dev->id.coreid,
		irq_name[0], irq == 0 ? "*" : " ",
		irq_name[1], irq == 1 ? "*" : " ",
		irq_name[2], irq == 2 ? "*" : " ",
		irq_name[3], irq == 3 ? "*" : " ",
		irq_name[4], irq == 4 ? "*" : " ",
		irq_name[5], irq == 5 ? "*" : " ",
		irq_name[6], irq == 6 ? "*" : " ");
}

static void dump_irq(struct ssb_bus *bus)
{
	int i;
	for (i = 0; i < bus->nr_devices; i++) {
		struct ssb_device *dev;
		dev = &(bus->devices[i]);
		print_irq(dev, ssb_mips_irq(dev));
	}
}

static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;

	if (ssb_extif_available(&bus->extif))
		mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
	else if (ssb_chipco_available(&bus->chipco))
		mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
	else
		mcore->nr_serial_ports = 0;
}

static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;
	struct ssb_sflash *sflash = &mcore->sflash;
	struct ssb_pflash *pflash = &mcore->pflash;

	/* When there is no chipcommon on the bus there is 4MB flash */
	if (!ssb_chipco_available(&bus->chipco)) {
		pflash->present = true;
		pflash->buswidth = 2;
		pflash->window = SSB_FLASH1;
		pflash->window_size = SSB_FLASH1_SZ;
		goto ssb_pflash;
	}

	/* There is ChipCommon, so use it to read info about flash */
	switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
	case SSB_CHIPCO_FLASHT_STSER:
	case SSB_CHIPCO_FLASHT_ATSER:
		pr_debug("Found serial flash\n");
		ssb_sflash_init(&bus->chipco);
		break;
	case SSB_CHIPCO_FLASHT_PARA:
		pr_debug("Found parallel flash\n");
		pflash->present = true;
		pflash->window = SSB_FLASH2;
		pflash->window_size = SSB_FLASH2_SZ;
		if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
		               & SSB_CHIPCO_CFG_DS16) == 0)
			pflash->buswidth = 1;
		else
			pflash->buswidth = 2;
		break;
	}

ssb_pflash:
	if (sflash->present) {
#ifdef CONFIG_BCM47XX
		bcm47xx_nvram_init_from_mem(sflash->window, sflash->size);
#endif
	} else if (pflash->present) {
#ifdef CONFIG_BCM47XX
		bcm47xx_nvram_init_from_mem(pflash->window, pflash->window_size);
#endif

		ssb_pflash_data.width = pflash->buswidth;
		ssb_pflash_resource.start = pflash->window;
		ssb_pflash_resource.end = pflash->window + pflash->window_size;
	}
}

u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus = mcore->dev->bus;
	u32 pll_type, n, m, rate = 0;

	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
		return ssb_pmu_get_cpu_clock(&bus->chipco);

	if (ssb_extif_available(&bus->extif)) {
		ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
	} else if (ssb_chipco_available(&bus->chipco)) {
		ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
	} else
		return 0;

	if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) {
		rate = 200000000;
	} else {
		rate = ssb_calc_clock_rate(pll_type, n, m);
	}

	if (pll_type == SSB_PLLTYPE_6) {
		rate *= 2;
	}

	return rate;
}

void ssb_mipscore_init(struct ssb_mipscore *mcore)
{
	struct ssb_bus *bus;
	struct ssb_device *dev;
	unsigned long hz, ns;
	unsigned int irq, i;

	if (!mcore->dev)
		return; /* We don't have a MIPS core */

	ssb_dbg("Initializing MIPS core...\n");

	bus = mcore->dev->bus;
	hz = ssb_clockspeed(bus);
	if (!hz)
		hz = 100000000;
	ns = 1000000000 / hz;

	if (ssb_extif_available(&bus->extif))
		ssb_extif_timing_init(&bus->extif, ns);
	else if (ssb_chipco_available(&bus->chipco))
		ssb_chipco_timing_init(&bus->chipco, ns);

	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
		int mips_irq;
		dev = &(bus->devices[i]);
		mips_irq = ssb_mips_irq(dev);
		if (mips_irq > 4)
			dev->irq = 0;
		else
			dev->irq = mips_irq + 2;
		if (dev->irq > 5)
			continue;
		switch (dev->id.coreid) {
		case SSB_DEV_USB11_HOST:
			/* shouldn't need a separate irq line for non-4710, most of them have a proper
			 * external usb controller on the pci */
			if ((bus->chip_id == 0x4710) && (irq <= 4)) {
				set_irq(dev, irq++);
			}
			break;
		case SSB_DEV_PCI:
		case SSB_DEV_ETHERNET:
		case SSB_DEV_ETHERNET_GBIT:
		case SSB_DEV_80211:
		case SSB_DEV_USB20_HOST:
			/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
			if (irq <= 4) {
				set_irq(dev, irq++);
				break;
			}
			/* fallthrough */
		case SSB_DEV_EXTIF:
			set_irq(dev, 0);
			break;
		}
	}
	ssb_dbg("after irq reconfiguration\n");
	dump_irq(bus);

	ssb_mips_serial_init(mcore);
	ssb_mips_flash_detect(mcore);
}
Commit	Line	Data
61e115a5 MB	1	/*
	2	* Sonics Silicon Backplane
	3	* Broadcom MIPS core driver
	4	*
	5	* Copyright 2005, Broadcom Corporation
eb032b98	6	* Copyright 2006, 2007, Michael Buesch <[email protected]>
61e115a5 MB	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
	11	#include <linux/ssb/ssb.h>
	12
c7a4a9e3	13	#include <linux/mtd/physmap.h>
61e115a5 MB	14	#include <linux/serial.h>
	15	#include <linux/serial_core.h>
	16	#include <linux/serial_reg.h>
	17	#include <linux/time.h>
21400f25	18	#ifdef CONFIG_BCM47XX
138173d4	19	#include <linux/bcm47xx_nvram.h>
21400f25	20	#endif
61e115a5 MB	21
	22	#include "ssb_private.h"
	23
255e9fd4	24	static const char * const part_probes[] = { "bcm47xxpart", NULL };
c7a4a9e3 RM	25
	26	static struct physmap_flash_data ssb_pflash_data = {
	27	.part_probe_types = part_probes,
	28	};
	29
	30	static struct resource ssb_pflash_resource = {
	31	.name = "ssb_pflash",
	32	.flags = IORESOURCE_MEM,
	33	};
	34
	35	struct platform_device ssb_pflash_dev = {
	36	.name = "physmap-flash",
	37	.dev = {
	38	.platform_data = &ssb_pflash_data,
	39	},
	40	.resource = &ssb_pflash_resource,
	41	.num_resources = 1,
	42	};
61e115a5 MB	43
	44	static inline u32 mips_read32(struct ssb_mipscore *mcore,
	45	u16 offset)
	46	{
	47	return ssb_read32(mcore->dev, offset);
	48	}
	49
	50	static inline void mips_write32(struct ssb_mipscore *mcore,
	51	u16 offset,
	52	u32 value)
	53	{
	54	ssb_write32(mcore->dev, offset, value);
	55	}
	56
	57	static const u32 ipsflag_irq_mask[] = {
	58	0,
	59	SSB_IPSFLAG_IRQ1,
	60	SSB_IPSFLAG_IRQ2,
	61	SSB_IPSFLAG_IRQ3,
	62	SSB_IPSFLAG_IRQ4,
	63	};
	64
	65	static const u32 ipsflag_irq_shift[] = {
	66	0,
	67	SSB_IPSFLAG_IRQ1_SHIFT,
	68	SSB_IPSFLAG_IRQ2_SHIFT,
	69	SSB_IPSFLAG_IRQ3_SHIFT,
	70	SSB_IPSFLAG_IRQ4_SHIFT,
	71	};
	72
	73	static inline u32 ssb_irqflag(struct ssb_device *dev)
	74	{
ea4bbfd0 MC	75	u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
	76	if (tpsflag)
	77	return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
	78	else
	79	/* not irq supported */
	80	return 0x3f;
	81	}
	82
	83	static struct ssb_device find_device(struct ssb_device rdev, int irqflag)
	84	{
	85	struct ssb_bus *bus = rdev->bus;
	86	int i;
	87	for (i = 0; i < bus->nr_devices; i++) {
	88	struct ssb_device *dev;
	89	dev = &(bus->devices[i]);
	90	if (ssb_irqflag(dev) == irqflag)
	91	return dev;
	92	}
	93	return NULL;
61e115a5 MB	94	}
	95
	96	/* Get the MIPS IRQ assignment for a specified device.
	97	* If unassigned, 0 is returned.
ea4bbfd0 MC	98	* If disabled, 5 is returned.
ea4bbfd0 MC	99	* If not supported, 6 is returned.
61e115a5 MB	100	*/
	101	unsigned int ssb_mips_irq(struct ssb_device *dev)
	102	{
	103	struct ssb_bus *bus = dev->bus;
ea4bbfd0	104	struct ssb_device *mdev = bus->mipscore.dev;
61e115a5 MB	105	u32 irqflag;
	106	u32 ipsflag;
	107	u32 tmp;
	108	unsigned int irq;
	109
	110	irqflag = ssb_irqflag(dev);
ea4bbfd0 MC	111	if (irqflag == 0x3f)
ea4bbfd0 MC	112	return 6;
61e115a5 MB	113	ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
	114	for (irq = 1; irq <= 4; irq++) {
	115	tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
	116	if (tmp == irqflag)
	117	break;
	118	}
ea4bbfd0 MC	119	if (irq == 5) {
	120	if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
	121	irq = 0;
	122	}
61e115a5 MB	123
	124	return irq;
	125	}
	126
	127	static void clear_irq(struct ssb_bus *bus, unsigned int irq)
	128	{
	129	struct ssb_device *dev = bus->mipscore.dev;
	130
	131	/* Clear the IRQ in the MIPScore backplane registers */
	132	if (irq == 0) {
	133	ssb_write32(dev, SSB_INTVEC, 0);
	134	} else {
	135	ssb_write32(dev, SSB_IPSFLAG,
	136	ssb_read32(dev, SSB_IPSFLAG) \|
	137	ipsflag_irq_mask[irq]);
	138	}
	139	}
	140
	141	static void set_irq(struct ssb_device *dev, unsigned int irq)
	142	{
	143	unsigned int oldirq = ssb_mips_irq(dev);
	144	struct ssb_bus *bus = dev->bus;
	145	struct ssb_device *mdev = bus->mipscore.dev;
	146	u32 irqflag = ssb_irqflag(dev);
	147
ea4bbfd0 MC	148	BUG_ON(oldirq == 6);
ea4bbfd0 MC	149
61e115a5 MB	150	dev->irq = irq + 2;
61e115a5 MB	151
61e115a5 MB	152	/* clear the old irq */
	153	if (oldirq == 0)
	154	ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
ea4bbfd0	155	else if (oldirq != 5)
61e115a5 MB	156	clear_irq(bus, oldirq);
	157
	158	/* assign the new one */
2633da23 MB	159	if (irq == 0) {
	160	ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) \| ssb_read32(mdev, SSB_INTVEC)));
	161	} else {
ea4bbfd0 MC	162	u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
	163	if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
	164	u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
	165	struct ssb_device *olddev = find_device(dev, oldipsflag);
	166	if (olddev)
	167	set_irq(olddev, 0);
	168	}
2633da23	169	irqflag <<= ipsflag_irq_shift[irq];
ea4bbfd0	170	irqflag \|= (ipsflag & ~ipsflag_irq_mask[irq]);
2633da23 MB	171	ssb_write32(mdev, SSB_IPSFLAG, irqflag);
2633da23 MB	172	}
33a606ac JP	173	ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
33a606ac JP	174	dev->id.coreid, oldirq+2, irq+2);
ea4bbfd0 MC	175	}
	176
	177	static void print_irq(struct ssb_device *dev, unsigned int irq)
	178	{
ea4bbfd0	179	static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
33a606ac JP	180	ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
	181	dev->id.coreid,
	182	irq_name[0], irq == 0 ? "*" : " ",
	183	irq_name[1], irq == 1 ? "*" : " ",
	184	irq_name[2], irq == 2 ? "*" : " ",
	185	irq_name[3], irq == 3 ? "*" : " ",
	186	irq_name[4], irq == 4 ? "*" : " ",
	187	irq_name[5], irq == 5 ? "*" : " ",
	188	irq_name[6], irq == 6 ? "*" : " ");
ea4bbfd0 MC	189	}
	190
	191	static void dump_irq(struct ssb_bus *bus)
	192	{
	193	int i;
	194	for (i = 0; i < bus->nr_devices; i++) {
	195	struct ssb_device *dev;
	196	dev = &(bus->devices[i]);
	197	print_irq(dev, ssb_mips_irq(dev));
	198	}
61e115a5 MB	199	}
	200
	201	static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
	202	{
	203	struct ssb_bus *bus = mcore->dev->bus;
	204
0362063b	205	if (ssb_extif_available(&bus->extif))
61e115a5	206	mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
0362063b	207	else if (ssb_chipco_available(&bus->chipco))
61e115a5 MB	208	mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
	209	else
	210	mcore->nr_serial_ports = 0;
	211	}
	212
	213	static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
	214	{
	215	struct ssb_bus *bus = mcore->dev->bus;
21400f25	216	struct ssb_sflash *sflash = &mcore->sflash;
f1ab57e3	217	struct ssb_pflash *pflash = &mcore->pflash;
61e115a5	218
902d9e0f	219	/* When there is no chipcommon on the bus there is 4MB flash */
0362063b	220	if (!ssb_chipco_available(&bus->chipco)) {
f1ab57e3 RM	221	pflash->present = true;
	222	pflash->buswidth = 2;
	223	pflash->window = SSB_FLASH1;
	224	pflash->window_size = SSB_FLASH1_SZ;
c7a4a9e3	225	goto ssb_pflash;
902d9e0f RM	226	}
	227
	228	/* There is ChipCommon, so use it to read info about flash */
	229	switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
	230	case SSB_CHIPCO_FLASHT_STSER:
	231	case SSB_CHIPCO_FLASHT_ATSER:
72a525cb RM	232	pr_debug("Found serial flash\n");
72a525cb RM	233	ssb_sflash_init(&bus->chipco);
902d9e0f RM	234	break;
	235	case SSB_CHIPCO_FLASHT_PARA:
	236	pr_debug("Found parallel flash\n");
f1ab57e3 RM	237	pflash->present = true;
	238	pflash->window = SSB_FLASH2;
	239	pflash->window_size = SSB_FLASH2_SZ;
61e115a5 MB	240	if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
61e115a5 MB	241	& SSB_CHIPCO_CFG_DS16) == 0)
f1ab57e3	242	pflash->buswidth = 1;
902d9e0f	243	else
f1ab57e3	244	pflash->buswidth = 2;
902d9e0f	245	break;
61e115a5	246	}
c7a4a9e3 RM	247
c7a4a9e3 RM	248	ssb_pflash:
21400f25 RM	249	if (sflash->present) {
	250	#ifdef CONFIG_BCM47XX
	251	bcm47xx_nvram_init_from_mem(sflash->window, sflash->size);
	252	#endif
	253	} else if (pflash->present) {
	254	#ifdef CONFIG_BCM47XX
	255	bcm47xx_nvram_init_from_mem(pflash->window, pflash->window_size);
	256	#endif
	257
c7a4a9e3 RM	258	ssb_pflash_data.width = pflash->buswidth;
	259	ssb_pflash_resource.start = pflash->window;
	260	ssb_pflash_resource.end = pflash->window + pflash->window_size;
	261	}
61e115a5 MB	262	}
	263
	264	u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
	265	{
	266	struct ssb_bus *bus = mcore->dev->bus;
	267	u32 pll_type, n, m, rate = 0;
	268
d486a5b4 HM	269	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
	270	return ssb_pmu_get_cpu_clock(&bus->chipco);
	271
0362063b	272	if (ssb_extif_available(&bus->extif)) {
61e115a5	273	ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
0362063b	274	} else if (ssb_chipco_available(&bus->chipco)) {
61e115a5 MB	275	ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
	276	} else
	277	return 0;
	278
	279	if ((pll_type == SSB_PLLTYPE_5) \|\| (bus->chip_id == 0x5365)) {
	280	rate = 200000000;
	281	} else {
	282	rate = ssb_calc_clock_rate(pll_type, n, m);
	283	}
	284
	285	if (pll_type == SSB_PLLTYPE_6) {
	286	rate *= 2;
	287	}
	288
	289	return rate;
	290	}
	291
	292	void ssb_mipscore_init(struct ssb_mipscore *mcore)
	293	{
7007d00c	294	struct ssb_bus *bus;
61e115a5 MB	295	struct ssb_device *dev;
	296	unsigned long hz, ns;
	297	unsigned int irq, i;
	298
	299	if (!mcore->dev)
	300	return; /* We don't have a MIPS core */
	301
33a606ac	302	ssb_dbg("Initializing MIPS core...\n");
61e115a5	303
7007d00c	304	bus = mcore->dev->bus;
61e115a5 MB	305	hz = ssb_clockspeed(bus);
	306	if (!hz)
	307	hz = 100000000;
	308	ns = 1000000000 / hz;
	309
0362063b	310	if (ssb_extif_available(&bus->extif))
61e115a5	311	ssb_extif_timing_init(&bus->extif, ns);
0362063b	312	else if (ssb_chipco_available(&bus->chipco))
61e115a5 MB	313	ssb_chipco_timing_init(&bus->chipco, ns);
	314
	315	/* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
	316	for (irq = 2, i = 0; i < bus->nr_devices; i++) {
ea4bbfd0	317	int mips_irq;
61e115a5	318	dev = &(bus->devices[i]);
ea4bbfd0 MC	319	mips_irq = ssb_mips_irq(dev);
	320	if (mips_irq > 4)
	321	dev->irq = 0;
	322	else
	323	dev->irq = mips_irq + 2;
	324	if (dev->irq > 5)
	325	continue;
61e115a5 MB	326	switch (dev->id.coreid) {
	327	case SSB_DEV_USB11_HOST:
	328	/* shouldn't need a separate irq line for non-4710, most of them have a proper
	329	* external usb controller on the pci */
	330	if ((bus->chip_id == 0x4710) && (irq <= 4)) {
	331	set_irq(dev, irq++);
61e115a5	332	}
ea4bbfd0	333	break;
61e115a5 MB	334	case SSB_DEV_PCI:
61e115a5 MB	335	case SSB_DEV_ETHERNET:
aab547ce	336	case SSB_DEV_ETHERNET_GBIT:
61e115a5 MB	337	case SSB_DEV_80211:
	338	case SSB_DEV_USB20_HOST:
	339	/* These devices get their own IRQ line if available, the rest goes on IRQ0 */
	340	if (irq <= 4) {
	341	set_irq(dev, irq++);
	342	break;
	343	}
83e34f03 JF	344	/* fallthrough */
	345	case SSB_DEV_EXTIF:
	346	set_irq(dev, 0);
	347	break;
61e115a5 MB	348	}
61e115a5 MB	349	}
33a606ac	350	ssb_dbg("after irq reconfiguration\n");
ea4bbfd0	351	dump_irq(bus);
61e115a5 MB	352
	353	ssb_mips_serial_init(mcore);
	354	ssb_mips_flash_detect(mcore);
	355	}