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a1365275 SH |
1 | /* |
2 | * dm9000.c: Version 1.2 03/18/2003 | |
3 | * | |
4 | * A Davicom DM9000 ISA NIC fast Ethernet driver for Linux. | |
5 | * Copyright (C) 1997 Sten Wang | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version 2 | |
10 | * of the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved. | |
18 | * | |
19 | * V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match | |
20 | * 06/22/2001 Support DM9801 progrmming | |
21 | * E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000 | |
22 | * E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200 | |
23 | * R17 = (R17 & 0xfff0) | NF + 3 | |
24 | * E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200 | |
25 | * R17 = (R17 & 0xfff0) | NF | |
26 | * | |
27 | * v1.00 modify by simon 2001.9.5 | |
28 | * change for kernel 2.4.x | |
29 | * | |
30 | * v1.1 11/09/2001 fix force mode bug | |
31 | * | |
32 | * v1.2 03/18/2003 Weilun Huang <[email protected]>: | |
33 | * Fixed phy reset. | |
34 | * Added tx/rx 32 bit mode. | |
35 | * Cleaned up for kernel merge. | |
36 | * | |
37 | * 03/03/2004 Sascha Hauer <[email protected]> | |
38 | * Port to 2.6 kernel | |
39 | * | |
40 | * 24-Sep-2004 Ben Dooks <[email protected]> | |
41 | * Cleanup of code to remove ifdefs | |
42 | * Allowed platform device data to influence access width | |
43 | * Reformatting areas of code | |
44 | * | |
45 | * 17-Mar-2005 Sascha Hauer <[email protected]> | |
46 | * * removed 2.4 style module parameters | |
47 | * * removed removed unused stat counter and fixed | |
48 | * net_device_stats | |
49 | * * introduced tx_timeout function | |
50 | * * reworked locking | |
9ef9ac51 BD |
51 | * |
52 | * 01-Jul-2005 Ben Dooks <[email protected]> | |
53 | * * fixed spinlock call without pointer | |
54 | * * ensure spinlock is initialised | |
a1365275 SH |
55 | */ |
56 | ||
57 | #include <linux/module.h> | |
58 | #include <linux/ioport.h> | |
59 | #include <linux/netdevice.h> | |
60 | #include <linux/etherdevice.h> | |
61 | #include <linux/init.h> | |
62 | #include <linux/skbuff.h> | |
a1365275 SH |
63 | #include <linux/spinlock.h> |
64 | #include <linux/crc32.h> | |
65 | #include <linux/mii.h> | |
7da99859 | 66 | #include <linux/ethtool.h> |
a1365275 SH |
67 | #include <linux/dm9000.h> |
68 | #include <linux/delay.h> | |
d052d1be | 69 | #include <linux/platform_device.h> |
4e4fc05a | 70 | #include <linux/irq.h> |
a1365275 SH |
71 | |
72 | #include <asm/delay.h> | |
73 | #include <asm/irq.h> | |
74 | #include <asm/io.h> | |
75 | ||
76 | #include "dm9000.h" | |
77 | ||
78 | /* Board/System/Debug information/definition ---------------- */ | |
79 | ||
80 | #define DM9000_PHY 0x40 /* PHY address 0x01 */ | |
81 | ||
a1365275 SH |
82 | #define CARDNAME "dm9000" |
83 | #define PFX CARDNAME ": " | |
7da99859 | 84 | #define DRV_VERSION "1.30" |
a1365275 | 85 | |
f40d24d9 AL |
86 | #ifdef CONFIG_BLACKFIN |
87 | #define readsb insb | |
88 | #define readsw insw | |
89 | #define readsl insl | |
90 | #define writesb outsb | |
91 | #define writesw outsw | |
92 | #define writesl outsl | |
1a5f1c4f | 93 | #define DEFAULT_TRIGGER IRQF_TRIGGER_HIGH |
f40d24d9 | 94 | #else |
1a5f1c4f | 95 | #define DEFAULT_TRIGGER (0) |
f40d24d9 AL |
96 | #endif |
97 | ||
a1365275 SH |
98 | /* |
99 | * Transmit timeout, default 5 seconds. | |
100 | */ | |
101 | static int watchdog = 5000; | |
102 | module_param(watchdog, int, 0400); | |
103 | MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); | |
104 | ||
9a2f037c BD |
105 | /* DM9000 register address locking. |
106 | * | |
107 | * The DM9000 uses an address register to control where data written | |
108 | * to the data register goes. This means that the address register | |
109 | * must be preserved over interrupts or similar calls. | |
110 | * | |
111 | * During interrupt and other critical calls, a spinlock is used to | |
112 | * protect the system, but the calls themselves save the address | |
113 | * in the address register in case they are interrupting another | |
114 | * access to the device. | |
115 | * | |
116 | * For general accesses a lock is provided so that calls which are | |
117 | * allowed to sleep are serialised so that the address register does | |
118 | * not need to be saved. This lock also serves to serialise access | |
119 | * to the EEPROM and PHY access registers which are shared between | |
120 | * these two devices. | |
121 | */ | |
122 | ||
a1365275 SH |
123 | /* Structure/enum declaration ------------------------------- */ |
124 | typedef struct board_info { | |
125 | ||
126 | void __iomem *io_addr; /* Register I/O base address */ | |
127 | void __iomem *io_data; /* Data I/O address */ | |
128 | u16 irq; /* IRQ */ | |
129 | ||
130 | u16 tx_pkt_cnt; | |
131 | u16 queue_pkt_len; | |
132 | u16 queue_start_addr; | |
133 | u16 dbug_cnt; | |
134 | u8 io_mode; /* 0:word, 2:byte */ | |
135 | u8 phy_addr; | |
33ba5091 | 136 | unsigned int flags; |
321f69a4 | 137 | unsigned int in_suspend :1; |
a1365275 | 138 | |
5b2b4ff0 BD |
139 | int debug_level; |
140 | ||
a1365275 SH |
141 | void (*inblk)(void __iomem *port, void *data, int length); |
142 | void (*outblk)(void __iomem *port, void *data, int length); | |
143 | void (*dumpblk)(void __iomem *port, int length); | |
144 | ||
a76836f9 BD |
145 | struct device *dev; /* parent device */ |
146 | ||
a1365275 SH |
147 | struct resource *addr_res; /* resources found */ |
148 | struct resource *data_res; | |
149 | struct resource *addr_req; /* resources requested */ | |
150 | struct resource *data_req; | |
151 | struct resource *irq_res; | |
152 | ||
9a2f037c BD |
153 | struct mutex addr_lock; /* phy and eeprom access lock */ |
154 | ||
a1365275 SH |
155 | spinlock_t lock; |
156 | ||
157 | struct mii_if_info mii; | |
158 | u32 msg_enable; | |
159 | } board_info_t; | |
160 | ||
5b2b4ff0 BD |
161 | /* debug code */ |
162 | ||
163 | #define dm9000_dbg(db, lev, msg...) do { \ | |
164 | if ((lev) < CONFIG_DM9000_DEBUGLEVEL && \ | |
165 | (lev) < db->debug_level) { \ | |
166 | dev_dbg(db->dev, msg); \ | |
167 | } \ | |
168 | } while (0) | |
169 | ||
7da99859 BD |
170 | static inline board_info_t *to_dm9000_board(struct net_device *dev) |
171 | { | |
172 | return dev->priv; | |
173 | } | |
174 | ||
a1365275 | 175 | /* function declaration ------------------------------------- */ |
3ae5eaec | 176 | static int dm9000_probe(struct platform_device *); |
a1365275 SH |
177 | static int dm9000_open(struct net_device *); |
178 | static int dm9000_start_xmit(struct sk_buff *, struct net_device *); | |
179 | static int dm9000_stop(struct net_device *); | |
a1365275 | 180 | |
a1365275 SH |
181 | static void dm9000_init_dm9000(struct net_device *); |
182 | ||
7d12e780 | 183 | static irqreturn_t dm9000_interrupt(int, void *); |
a1365275 SH |
184 | |
185 | static int dm9000_phy_read(struct net_device *dev, int phyaddr_unsused, int reg); | |
186 | static void dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, | |
187 | int value); | |
86c62fab BD |
188 | |
189 | static void dm9000_read_eeprom(board_info_t *, int addr, unsigned char *to); | |
a1365275 SH |
190 | static void dm9000_rx(struct net_device *); |
191 | static void dm9000_hash_table(struct net_device *); | |
192 | ||
193 | //#define DM9000_PROGRAM_EEPROM | |
194 | #ifdef DM9000_PROGRAM_EEPROM | |
195 | static void program_eeprom(board_info_t * db); | |
196 | #endif | |
197 | /* DM9000 network board routine ---------------------------- */ | |
198 | ||
199 | static void | |
200 | dm9000_reset(board_info_t * db) | |
201 | { | |
a76836f9 BD |
202 | dev_dbg(db->dev, "resetting device\n"); |
203 | ||
a1365275 SH |
204 | /* RESET device */ |
205 | writeb(DM9000_NCR, db->io_addr); | |
206 | udelay(200); | |
207 | writeb(NCR_RST, db->io_data); | |
208 | udelay(200); | |
209 | } | |
210 | ||
211 | /* | |
212 | * Read a byte from I/O port | |
213 | */ | |
214 | static u8 | |
215 | ior(board_info_t * db, int reg) | |
216 | { | |
217 | writeb(reg, db->io_addr); | |
218 | return readb(db->io_data); | |
219 | } | |
220 | ||
221 | /* | |
222 | * Write a byte to I/O port | |
223 | */ | |
224 | ||
225 | static void | |
226 | iow(board_info_t * db, int reg, int value) | |
227 | { | |
228 | writeb(reg, db->io_addr); | |
229 | writeb(value, db->io_data); | |
230 | } | |
231 | ||
232 | /* routines for sending block to chip */ | |
233 | ||
234 | static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count) | |
235 | { | |
236 | writesb(reg, data, count); | |
237 | } | |
238 | ||
239 | static void dm9000_outblk_16bit(void __iomem *reg, void *data, int count) | |
240 | { | |
241 | writesw(reg, data, (count+1) >> 1); | |
242 | } | |
243 | ||
244 | static void dm9000_outblk_32bit(void __iomem *reg, void *data, int count) | |
245 | { | |
246 | writesl(reg, data, (count+3) >> 2); | |
247 | } | |
248 | ||
249 | /* input block from chip to memory */ | |
250 | ||
251 | static void dm9000_inblk_8bit(void __iomem *reg, void *data, int count) | |
252 | { | |
5f6b5517 | 253 | readsb(reg, data, count); |
a1365275 SH |
254 | } |
255 | ||
256 | ||
257 | static void dm9000_inblk_16bit(void __iomem *reg, void *data, int count) | |
258 | { | |
259 | readsw(reg, data, (count+1) >> 1); | |
260 | } | |
261 | ||
262 | static void dm9000_inblk_32bit(void __iomem *reg, void *data, int count) | |
263 | { | |
264 | readsl(reg, data, (count+3) >> 2); | |
265 | } | |
266 | ||
267 | /* dump block from chip to null */ | |
268 | ||
269 | static void dm9000_dumpblk_8bit(void __iomem *reg, int count) | |
270 | { | |
271 | int i; | |
272 | int tmp; | |
273 | ||
274 | for (i = 0; i < count; i++) | |
275 | tmp = readb(reg); | |
276 | } | |
277 | ||
278 | static void dm9000_dumpblk_16bit(void __iomem *reg, int count) | |
279 | { | |
280 | int i; | |
281 | int tmp; | |
282 | ||
283 | count = (count + 1) >> 1; | |
284 | ||
285 | for (i = 0; i < count; i++) | |
286 | tmp = readw(reg); | |
287 | } | |
288 | ||
289 | static void dm9000_dumpblk_32bit(void __iomem *reg, int count) | |
290 | { | |
291 | int i; | |
292 | int tmp; | |
293 | ||
294 | count = (count + 3) >> 2; | |
295 | ||
296 | for (i = 0; i < count; i++) | |
297 | tmp = readl(reg); | |
298 | } | |
299 | ||
300 | /* dm9000_set_io | |
301 | * | |
302 | * select the specified set of io routines to use with the | |
303 | * device | |
304 | */ | |
305 | ||
306 | static void dm9000_set_io(struct board_info *db, int byte_width) | |
307 | { | |
308 | /* use the size of the data resource to work out what IO | |
309 | * routines we want to use | |
310 | */ | |
311 | ||
312 | switch (byte_width) { | |
313 | case 1: | |
314 | db->dumpblk = dm9000_dumpblk_8bit; | |
315 | db->outblk = dm9000_outblk_8bit; | |
316 | db->inblk = dm9000_inblk_8bit; | |
317 | break; | |
318 | ||
a1365275 SH |
319 | |
320 | case 3: | |
a76836f9 BD |
321 | dev_dbg(db->dev, ": 3 byte IO, falling back to 16bit\n"); |
322 | case 2: | |
a1365275 SH |
323 | db->dumpblk = dm9000_dumpblk_16bit; |
324 | db->outblk = dm9000_outblk_16bit; | |
325 | db->inblk = dm9000_inblk_16bit; | |
326 | break; | |
327 | ||
328 | case 4: | |
329 | default: | |
330 | db->dumpblk = dm9000_dumpblk_32bit; | |
331 | db->outblk = dm9000_outblk_32bit; | |
332 | db->inblk = dm9000_inblk_32bit; | |
333 | break; | |
334 | } | |
335 | } | |
336 | ||
337 | ||
338 | /* Our watchdog timed out. Called by the networking layer */ | |
339 | static void dm9000_timeout(struct net_device *dev) | |
340 | { | |
341 | board_info_t *db = (board_info_t *) dev->priv; | |
342 | u8 reg_save; | |
343 | unsigned long flags; | |
344 | ||
345 | /* Save previous register address */ | |
346 | reg_save = readb(db->io_addr); | |
9ef9ac51 | 347 | spin_lock_irqsave(&db->lock,flags); |
a1365275 SH |
348 | |
349 | netif_stop_queue(dev); | |
350 | dm9000_reset(db); | |
351 | dm9000_init_dm9000(dev); | |
352 | /* We can accept TX packets again */ | |
353 | dev->trans_start = jiffies; | |
354 | netif_wake_queue(dev); | |
355 | ||
356 | /* Restore previous register address */ | |
357 | writeb(reg_save, db->io_addr); | |
9ef9ac51 | 358 | spin_unlock_irqrestore(&db->lock,flags); |
a1365275 SH |
359 | } |
360 | ||
2fd0e33f KH |
361 | #ifdef CONFIG_NET_POLL_CONTROLLER |
362 | /* | |
363 | *Used by netconsole | |
364 | */ | |
365 | static void dm9000_poll_controller(struct net_device *dev) | |
366 | { | |
367 | disable_irq(dev->irq); | |
28431146 | 368 | dm9000_interrupt(dev->irq,dev); |
2fd0e33f KH |
369 | enable_irq(dev->irq); |
370 | } | |
371 | #endif | |
a1365275 | 372 | |
7da99859 BD |
373 | /* ethtool ops */ |
374 | ||
375 | static void dm9000_get_drvinfo(struct net_device *dev, | |
376 | struct ethtool_drvinfo *info) | |
377 | { | |
378 | board_info_t *dm = to_dm9000_board(dev); | |
379 | ||
380 | strcpy(info->driver, CARDNAME); | |
381 | strcpy(info->version, DRV_VERSION); | |
382 | strcpy(info->bus_info, to_platform_device(dm->dev)->name); | |
383 | } | |
384 | ||
385 | static int dm9000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
386 | { | |
387 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 388 | |
7da99859 | 389 | mii_ethtool_gset(&dm->mii, cmd); |
7da99859 BD |
390 | return 0; |
391 | } | |
392 | ||
393 | static int dm9000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
394 | { | |
395 | board_info_t *dm = to_dm9000_board(dev); | |
7da99859 | 396 | |
9a2f037c | 397 | return mii_ethtool_sset(&dm->mii, cmd); |
7da99859 BD |
398 | } |
399 | ||
400 | static int dm9000_nway_reset(struct net_device *dev) | |
401 | { | |
402 | board_info_t *dm = to_dm9000_board(dev); | |
403 | return mii_nway_restart(&dm->mii); | |
404 | } | |
405 | ||
406 | static u32 dm9000_get_link(struct net_device *dev) | |
407 | { | |
408 | board_info_t *dm = to_dm9000_board(dev); | |
409 | return mii_link_ok(&dm->mii); | |
410 | } | |
411 | ||
412 | static const struct ethtool_ops dm9000_ethtool_ops = { | |
413 | .get_drvinfo = dm9000_get_drvinfo, | |
414 | .get_settings = dm9000_get_settings, | |
415 | .set_settings = dm9000_set_settings, | |
416 | .nway_reset = dm9000_nway_reset, | |
417 | .get_link = dm9000_get_link, | |
418 | }; | |
419 | ||
420 | ||
a1365275 SH |
421 | /* dm9000_release_board |
422 | * | |
423 | * release a board, and any mapped resources | |
424 | */ | |
425 | ||
426 | static void | |
427 | dm9000_release_board(struct platform_device *pdev, struct board_info *db) | |
428 | { | |
429 | if (db->data_res == NULL) { | |
430 | if (db->addr_res != NULL) | |
431 | release_mem_region((unsigned long)db->io_addr, 4); | |
432 | return; | |
433 | } | |
434 | ||
435 | /* unmap our resources */ | |
436 | ||
437 | iounmap(db->io_addr); | |
438 | iounmap(db->io_data); | |
439 | ||
440 | /* release the resources */ | |
441 | ||
442 | if (db->data_req != NULL) { | |
443 | release_resource(db->data_req); | |
444 | kfree(db->data_req); | |
445 | } | |
446 | ||
51985487 DO |
447 | if (db->addr_req != NULL) { |
448 | release_resource(db->addr_req); | |
a1365275 SH |
449 | kfree(db->addr_req); |
450 | } | |
451 | } | |
452 | ||
453 | #define res_size(_r) (((_r)->end - (_r)->start) + 1) | |
454 | ||
455 | /* | |
456 | * Search DM9000 board, allocate space and register it | |
457 | */ | |
458 | static int | |
3ae5eaec | 459 | dm9000_probe(struct platform_device *pdev) |
a1365275 | 460 | { |
a1365275 SH |
461 | struct dm9000_plat_data *pdata = pdev->dev.platform_data; |
462 | struct board_info *db; /* Point a board information structure */ | |
463 | struct net_device *ndev; | |
464 | unsigned long base; | |
465 | int ret = 0; | |
466 | int iosize; | |
467 | int i; | |
468 | u32 id_val; | |
469 | ||
a1365275 SH |
470 | /* Init network device */ |
471 | ndev = alloc_etherdev(sizeof (struct board_info)); | |
472 | if (!ndev) { | |
a76836f9 | 473 | dev_err(&pdev->dev, "could not allocate device.\n"); |
a1365275 SH |
474 | return -ENOMEM; |
475 | } | |
476 | ||
3ae5eaec | 477 | SET_NETDEV_DEV(ndev, &pdev->dev); |
a1365275 | 478 | |
a76836f9 | 479 | dev_dbg(&pdev->dev, "dm9000_probe()"); |
a1365275 SH |
480 | |
481 | /* setup board info structure */ | |
482 | db = (struct board_info *) ndev->priv; | |
483 | memset(db, 0, sizeof (*db)); | |
484 | ||
a76836f9 BD |
485 | db->dev = &pdev->dev; |
486 | ||
9ef9ac51 | 487 | spin_lock_init(&db->lock); |
9a2f037c | 488 | mutex_init(&db->addr_lock); |
9ef9ac51 | 489 | |
a1365275 SH |
490 | if (pdev->num_resources < 2) { |
491 | ret = -ENODEV; | |
492 | goto out; | |
b4ed03ff | 493 | } else if (pdev->num_resources == 2) { |
a1365275 SH |
494 | base = pdev->resource[0].start; |
495 | ||
496 | if (!request_mem_region(base, 4, ndev->name)) { | |
497 | ret = -EBUSY; | |
498 | goto out; | |
499 | } | |
500 | ||
501 | ndev->base_addr = base; | |
502 | ndev->irq = pdev->resource[1].start; | |
b4ed03ff BD |
503 | db->io_addr = (void __iomem *)base; |
504 | db->io_data = (void __iomem *)(base + 4); | |
a1365275 | 505 | |
f40d24d9 AL |
506 | /* ensure at least we have a default set of IO routines */ |
507 | dm9000_set_io(db, 2); | |
508 | ||
b4ed03ff | 509 | } else { |
a1365275 SH |
510 | db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
511 | db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
512 | db->irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
513 | ||
b4ed03ff BD |
514 | if (db->addr_res == NULL || db->data_res == NULL || |
515 | db->irq_res == NULL) { | |
a76836f9 | 516 | dev_err(db->dev, "insufficient resources\n"); |
a1365275 SH |
517 | ret = -ENOENT; |
518 | goto out; | |
519 | } | |
520 | ||
521 | i = res_size(db->addr_res); | |
522 | db->addr_req = request_mem_region(db->addr_res->start, i, | |
523 | pdev->name); | |
524 | ||
525 | if (db->addr_req == NULL) { | |
a76836f9 | 526 | dev_err(db->dev, "cannot claim address reg area\n"); |
a1365275 SH |
527 | ret = -EIO; |
528 | goto out; | |
529 | } | |
530 | ||
531 | db->io_addr = ioremap(db->addr_res->start, i); | |
532 | ||
533 | if (db->io_addr == NULL) { | |
a76836f9 | 534 | dev_err(db->dev, "failed to ioremap address reg\n"); |
a1365275 SH |
535 | ret = -EINVAL; |
536 | goto out; | |
537 | } | |
538 | ||
539 | iosize = res_size(db->data_res); | |
540 | db->data_req = request_mem_region(db->data_res->start, iosize, | |
541 | pdev->name); | |
542 | ||
543 | if (db->data_req == NULL) { | |
a76836f9 | 544 | dev_err(db->dev, "cannot claim data reg area\n"); |
a1365275 SH |
545 | ret = -EIO; |
546 | goto out; | |
547 | } | |
548 | ||
549 | db->io_data = ioremap(db->data_res->start, iosize); | |
550 | ||
551 | if (db->io_data == NULL) { | |
a76836f9 | 552 | dev_err(db->dev,"failed to ioremap data reg\n"); |
a1365275 SH |
553 | ret = -EINVAL; |
554 | goto out; | |
555 | } | |
556 | ||
557 | /* fill in parameters for net-dev structure */ | |
558 | ||
559 | ndev->base_addr = (unsigned long)db->io_addr; | |
560 | ndev->irq = db->irq_res->start; | |
561 | ||
562 | /* ensure at least we have a default set of IO routines */ | |
563 | dm9000_set_io(db, iosize); | |
a1365275 SH |
564 | } |
565 | ||
566 | /* check to see if anything is being over-ridden */ | |
567 | if (pdata != NULL) { | |
568 | /* check to see if the driver wants to over-ride the | |
569 | * default IO width */ | |
570 | ||
571 | if (pdata->flags & DM9000_PLATF_8BITONLY) | |
572 | dm9000_set_io(db, 1); | |
573 | ||
574 | if (pdata->flags & DM9000_PLATF_16BITONLY) | |
575 | dm9000_set_io(db, 2); | |
576 | ||
577 | if (pdata->flags & DM9000_PLATF_32BITONLY) | |
578 | dm9000_set_io(db, 4); | |
579 | ||
580 | /* check to see if there are any IO routine | |
581 | * over-rides */ | |
582 | ||
583 | if (pdata->inblk != NULL) | |
584 | db->inblk = pdata->inblk; | |
585 | ||
586 | if (pdata->outblk != NULL) | |
587 | db->outblk = pdata->outblk; | |
588 | ||
589 | if (pdata->dumpblk != NULL) | |
590 | db->dumpblk = pdata->dumpblk; | |
33ba5091 BD |
591 | |
592 | db->flags = pdata->flags; | |
a1365275 SH |
593 | } |
594 | ||
595 | dm9000_reset(db); | |
596 | ||
597 | /* try two times, DM9000 sometimes gets the first read wrong */ | |
598 | for (i = 0; i < 2; i++) { | |
599 | id_val = ior(db, DM9000_VIDL); | |
600 | id_val |= (u32)ior(db, DM9000_VIDH) << 8; | |
601 | id_val |= (u32)ior(db, DM9000_PIDL) << 16; | |
602 | id_val |= (u32)ior(db, DM9000_PIDH) << 24; | |
603 | ||
604 | if (id_val == DM9000_ID) | |
605 | break; | |
a76836f9 | 606 | dev_err(db->dev, "read wrong id 0x%08x\n", id_val); |
a1365275 SH |
607 | } |
608 | ||
609 | if (id_val != DM9000_ID) { | |
a76836f9 | 610 | dev_err(db->dev, "wrong id: 0x%08x\n", id_val); |
418d6f87 MR |
611 | ret = -ENODEV; |
612 | goto out; | |
a1365275 SH |
613 | } |
614 | ||
615 | /* from this point we assume that we have found a DM9000 */ | |
616 | ||
617 | /* driver system function */ | |
618 | ether_setup(ndev); | |
619 | ||
620 | ndev->open = &dm9000_open; | |
621 | ndev->hard_start_xmit = &dm9000_start_xmit; | |
622 | ndev->tx_timeout = &dm9000_timeout; | |
623 | ndev->watchdog_timeo = msecs_to_jiffies(watchdog); | |
624 | ndev->stop = &dm9000_stop; | |
a1365275 | 625 | ndev->set_multicast_list = &dm9000_hash_table; |
7da99859 BD |
626 | ndev->ethtool_ops = &dm9000_ethtool_ops; |
627 | ||
2fd0e33f KH |
628 | #ifdef CONFIG_NET_POLL_CONTROLLER |
629 | ndev->poll_controller = &dm9000_poll_controller; | |
630 | #endif | |
a1365275 SH |
631 | |
632 | #ifdef DM9000_PROGRAM_EEPROM | |
633 | program_eeprom(db); | |
634 | #endif | |
635 | db->msg_enable = NETIF_MSG_LINK; | |
636 | db->mii.phy_id_mask = 0x1f; | |
637 | db->mii.reg_num_mask = 0x1f; | |
638 | db->mii.force_media = 0; | |
639 | db->mii.full_duplex = 0; | |
640 | db->mii.dev = ndev; | |
641 | db->mii.mdio_read = dm9000_phy_read; | |
642 | db->mii.mdio_write = dm9000_phy_write; | |
643 | ||
86c62fab BD |
644 | /* try reading the node address from the attached EEPROM */ |
645 | for (i = 0; i < 6; i += 2) | |
646 | dm9000_read_eeprom(db, i / 2, ndev->dev_addr+i); | |
a1365275 | 647 | |
5b55dda6 BD |
648 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
649 | /* try reading from mac */ | |
650 | ||
651 | for (i = 0; i < 6; i++) | |
652 | ndev->dev_addr[i] = ior(db, i+DM9000_PAR); | |
653 | } | |
654 | ||
a1365275 | 655 | if (!is_valid_ether_addr(ndev->dev_addr)) |
a76836f9 BD |
656 | dev_warn(db->dev, "%s: Invalid ethernet MAC address. Please " |
657 | "set using ifconfig\n", ndev->name); | |
a1365275 | 658 | |
3ae5eaec | 659 | platform_set_drvdata(pdev, ndev); |
a1365275 SH |
660 | ret = register_netdev(ndev); |
661 | ||
662 | if (ret == 0) { | |
0795af57 JP |
663 | DECLARE_MAC_BUF(mac); |
664 | printk("%s: dm9000 at %p,%p IRQ %d MAC: %s\n", | |
665 | ndev->name, db->io_addr, db->io_data, ndev->irq, | |
666 | print_mac(mac, ndev->dev_addr)); | |
a1365275 SH |
667 | } |
668 | return 0; | |
669 | ||
418d6f87 | 670 | out: |
a76836f9 | 671 | dev_err(db->dev, "not found (%d).\n", ret); |
a1365275 SH |
672 | |
673 | dm9000_release_board(pdev, db); | |
9fd9f9b6 | 674 | free_netdev(ndev); |
a1365275 SH |
675 | |
676 | return ret; | |
677 | } | |
678 | ||
679 | /* | |
680 | * Open the interface. | |
681 | * The interface is opened whenever "ifconfig" actives it. | |
682 | */ | |
683 | static int | |
684 | dm9000_open(struct net_device *dev) | |
685 | { | |
686 | board_info_t *db = (board_info_t *) dev->priv; | |
1a5f1c4f | 687 | unsigned long irqflags = db->irq_res->flags & IRQF_TRIGGER_MASK; |
a1365275 | 688 | |
a76836f9 | 689 | dev_dbg(db->dev, "entering %s\n", __func__); |
a1365275 | 690 | |
1a5f1c4f BD |
691 | /* If there is no IRQ type specified, default to something that |
692 | * may work, and tell the user that this is a problem */ | |
693 | ||
694 | if (irqflags == IRQF_TRIGGER_NONE) { | |
695 | dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); | |
696 | irqflags = DEFAULT_TRIGGER; | |
697 | } | |
698 | ||
699 | irqflags |= IRQF_SHARED; | |
700 | ||
701 | if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev)) | |
a1365275 SH |
702 | return -EAGAIN; |
703 | ||
704 | /* Initialize DM9000 board */ | |
705 | dm9000_reset(db); | |
706 | dm9000_init_dm9000(dev); | |
707 | ||
708 | /* Init driver variable */ | |
709 | db->dbug_cnt = 0; | |
710 | ||
a1365275 SH |
711 | mii_check_media(&db->mii, netif_msg_link(db), 1); |
712 | netif_start_queue(dev); | |
713 | ||
714 | return 0; | |
715 | } | |
716 | ||
717 | /* | |
718 | * Initilize dm9000 board | |
719 | */ | |
720 | static void | |
721 | dm9000_init_dm9000(struct net_device *dev) | |
722 | { | |
723 | board_info_t *db = (board_info_t *) dev->priv; | |
724 | ||
5b2b4ff0 | 725 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 SH |
726 | |
727 | /* I/O mode */ | |
728 | db->io_mode = ior(db, DM9000_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ | |
729 | ||
730 | /* GPIO0 on pre-activate PHY */ | |
731 | iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ | |
732 | iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */ | |
733 | iow(db, DM9000_GPR, 0); /* Enable PHY */ | |
734 | ||
33ba5091 BD |
735 | if (db->flags & DM9000_PLATF_EXT_PHY) |
736 | iow(db, DM9000_NCR, NCR_EXT_PHY); | |
737 | ||
a1365275 SH |
738 | /* Program operating register */ |
739 | iow(db, DM9000_TCR, 0); /* TX Polling clear */ | |
740 | iow(db, DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */ | |
741 | iow(db, DM9000_FCR, 0xff); /* Flow Control */ | |
742 | iow(db, DM9000_SMCR, 0); /* Special Mode */ | |
743 | /* clear TX status */ | |
744 | iow(db, DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); | |
745 | iow(db, DM9000_ISR, ISR_CLR_STATUS); /* Clear interrupt status */ | |
746 | ||
747 | /* Set address filter table */ | |
748 | dm9000_hash_table(dev); | |
749 | ||
750 | /* Activate DM9000 */ | |
751 | iow(db, DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); | |
752 | /* Enable TX/RX interrupt mask */ | |
753 | iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); | |
754 | ||
755 | /* Init Driver variable */ | |
756 | db->tx_pkt_cnt = 0; | |
757 | db->queue_pkt_len = 0; | |
758 | dev->trans_start = 0; | |
a1365275 SH |
759 | } |
760 | ||
761 | /* | |
762 | * Hardware start transmission. | |
763 | * Send a packet to media from the upper layer. | |
764 | */ | |
765 | static int | |
766 | dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
767 | { | |
c46ac946 | 768 | unsigned long flags; |
a1365275 SH |
769 | board_info_t *db = (board_info_t *) dev->priv; |
770 | ||
5b2b4ff0 | 771 | dm9000_dbg(db, 3, "%s:\n", __func__); |
a1365275 SH |
772 | |
773 | if (db->tx_pkt_cnt > 1) | |
774 | return 1; | |
775 | ||
c46ac946 | 776 | spin_lock_irqsave(&db->lock, flags); |
a1365275 SH |
777 | |
778 | /* Move data to DM9000 TX RAM */ | |
779 | writeb(DM9000_MWCMD, db->io_addr); | |
780 | ||
781 | (db->outblk)(db->io_data, skb->data, skb->len); | |
09f75cd7 | 782 | dev->stats.tx_bytes += skb->len; |
a1365275 | 783 | |
c46ac946 | 784 | db->tx_pkt_cnt++; |
a1365275 | 785 | /* TX control: First packet immediately send, second packet queue */ |
c46ac946 | 786 | if (db->tx_pkt_cnt == 1) { |
a1365275 SH |
787 | /* Set TX length to DM9000 */ |
788 | iow(db, DM9000_TXPLL, skb->len & 0xff); | |
789 | iow(db, DM9000_TXPLH, (skb->len >> 8) & 0xff); | |
790 | ||
791 | /* Issue TX polling command */ | |
792 | iow(db, DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */ | |
793 | ||
794 | dev->trans_start = jiffies; /* save the time stamp */ | |
a1365275 SH |
795 | } else { |
796 | /* Second packet */ | |
a1365275 | 797 | db->queue_pkt_len = skb->len; |
c46ac946 | 798 | netif_stop_queue(dev); |
a1365275 SH |
799 | } |
800 | ||
c46ac946 FW |
801 | spin_unlock_irqrestore(&db->lock, flags); |
802 | ||
a1365275 SH |
803 | /* free this SKB */ |
804 | dev_kfree_skb(skb); | |
805 | ||
a1365275 SH |
806 | return 0; |
807 | } | |
808 | ||
809 | static void | |
810 | dm9000_shutdown(struct net_device *dev) | |
811 | { | |
812 | board_info_t *db = (board_info_t *) dev->priv; | |
813 | ||
814 | /* RESET device */ | |
815 | dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */ | |
816 | iow(db, DM9000_GPR, 0x01); /* Power-Down PHY */ | |
817 | iow(db, DM9000_IMR, IMR_PAR); /* Disable all interrupt */ | |
818 | iow(db, DM9000_RCR, 0x00); /* Disable RX */ | |
819 | } | |
820 | ||
821 | /* | |
822 | * Stop the interface. | |
823 | * The interface is stopped when it is brought. | |
824 | */ | |
825 | static int | |
826 | dm9000_stop(struct net_device *ndev) | |
827 | { | |
828 | board_info_t *db = (board_info_t *) ndev->priv; | |
829 | ||
5b2b4ff0 | 830 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 | 831 | |
a1365275 SH |
832 | netif_stop_queue(ndev); |
833 | netif_carrier_off(ndev); | |
834 | ||
835 | /* free interrupt */ | |
836 | free_irq(ndev->irq, ndev); | |
837 | ||
838 | dm9000_shutdown(ndev); | |
839 | ||
840 | return 0; | |
841 | } | |
842 | ||
843 | /* | |
844 | * DM9000 interrupt handler | |
845 | * receive the packet to upper layer, free the transmitted packet | |
846 | */ | |
847 | ||
5d22a312 | 848 | static void |
a1365275 SH |
849 | dm9000_tx_done(struct net_device *dev, board_info_t * db) |
850 | { | |
851 | int tx_status = ior(db, DM9000_NSR); /* Got TX status */ | |
852 | ||
853 | if (tx_status & (NSR_TX2END | NSR_TX1END)) { | |
854 | /* One packet sent complete */ | |
855 | db->tx_pkt_cnt--; | |
09f75cd7 | 856 | dev->stats.tx_packets++; |
a1365275 SH |
857 | |
858 | /* Queue packet check & send */ | |
859 | if (db->tx_pkt_cnt > 0) { | |
860 | iow(db, DM9000_TXPLL, db->queue_pkt_len & 0xff); | |
861 | iow(db, DM9000_TXPLH, (db->queue_pkt_len >> 8) & 0xff); | |
862 | iow(db, DM9000_TCR, TCR_TXREQ); | |
863 | dev->trans_start = jiffies; | |
864 | } | |
865 | netif_wake_queue(dev); | |
866 | } | |
867 | } | |
868 | ||
869 | static irqreturn_t | |
7d12e780 | 870 | dm9000_interrupt(int irq, void *dev_id) |
a1365275 SH |
871 | { |
872 | struct net_device *dev = dev_id; | |
5b2b4ff0 | 873 | board_info_t *db = (board_info_t *) dev->priv; |
a1365275 SH |
874 | int int_status; |
875 | u8 reg_save; | |
876 | ||
5b2b4ff0 | 877 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
a1365275 SH |
878 | |
879 | /* A real interrupt coming */ | |
5b2b4ff0 | 880 | |
a1365275 SH |
881 | spin_lock(&db->lock); |
882 | ||
883 | /* Save previous register address */ | |
884 | reg_save = readb(db->io_addr); | |
885 | ||
886 | /* Disable all interrupts */ | |
887 | iow(db, DM9000_IMR, IMR_PAR); | |
888 | ||
889 | /* Got DM9000 interrupt status */ | |
890 | int_status = ior(db, DM9000_ISR); /* Got ISR */ | |
891 | iow(db, DM9000_ISR, int_status); /* Clear ISR status */ | |
892 | ||
893 | /* Received the coming packet */ | |
894 | if (int_status & ISR_PRS) | |
895 | dm9000_rx(dev); | |
896 | ||
897 | /* Trnasmit Interrupt check */ | |
898 | if (int_status & ISR_PTS) | |
899 | dm9000_tx_done(dev, db); | |
900 | ||
901 | /* Re-enable interrupt mask */ | |
902 | iow(db, DM9000_IMR, IMR_PAR | IMR_PTM | IMR_PRM); | |
903 | ||
904 | /* Restore previous register address */ | |
905 | writeb(reg_save, db->io_addr); | |
906 | ||
907 | spin_unlock(&db->lock); | |
908 | ||
909 | return IRQ_HANDLED; | |
910 | } | |
911 | ||
a1365275 | 912 | struct dm9000_rxhdr { |
93116573 BD |
913 | u8 RxPktReady; |
914 | u8 RxStatus; | |
a1365275 SH |
915 | u16 RxLen; |
916 | } __attribute__((__packed__)); | |
917 | ||
918 | /* | |
919 | * Received a packet and pass to upper layer | |
920 | */ | |
921 | static void | |
922 | dm9000_rx(struct net_device *dev) | |
923 | { | |
924 | board_info_t *db = (board_info_t *) dev->priv; | |
925 | struct dm9000_rxhdr rxhdr; | |
926 | struct sk_buff *skb; | |
927 | u8 rxbyte, *rdptr; | |
6478fac6 | 928 | bool GoodPacket; |
a1365275 SH |
929 | int RxLen; |
930 | ||
931 | /* Check packet ready or not */ | |
932 | do { | |
933 | ior(db, DM9000_MRCMDX); /* Dummy read */ | |
934 | ||
935 | /* Get most updated data */ | |
936 | rxbyte = readb(db->io_data); | |
937 | ||
938 | /* Status check: this byte must be 0 or 1 */ | |
939 | if (rxbyte > DM9000_PKT_RDY) { | |
a76836f9 | 940 | dev_warn(db->dev, "status check fail: %d\n", rxbyte); |
a1365275 SH |
941 | iow(db, DM9000_RCR, 0x00); /* Stop Device */ |
942 | iow(db, DM9000_ISR, IMR_PAR); /* Stop INT request */ | |
943 | return; | |
944 | } | |
945 | ||
946 | if (rxbyte != DM9000_PKT_RDY) | |
947 | return; | |
948 | ||
949 | /* A packet ready now & Get status/length */ | |
6478fac6 | 950 | GoodPacket = true; |
a1365275 SH |
951 | writeb(DM9000_MRCMD, db->io_addr); |
952 | ||
953 | (db->inblk)(db->io_data, &rxhdr, sizeof(rxhdr)); | |
954 | ||
93116573 | 955 | RxLen = le16_to_cpu(rxhdr.RxLen); |
a1365275 SH |
956 | |
957 | /* Packet Status check */ | |
958 | if (RxLen < 0x40) { | |
6478fac6 | 959 | GoodPacket = false; |
a76836f9 | 960 | dev_dbg(db->dev, "Bad Packet received (runt)\n"); |
a1365275 SH |
961 | } |
962 | ||
963 | if (RxLen > DM9000_PKT_MAX) { | |
a76836f9 | 964 | dev_dbg(db->dev, "RST: RX Len:%x\n", RxLen); |
a1365275 SH |
965 | } |
966 | ||
93116573 | 967 | if (rxhdr.RxStatus & 0xbf) { |
6478fac6 | 968 | GoodPacket = false; |
93116573 | 969 | if (rxhdr.RxStatus & 0x01) { |
a76836f9 | 970 | dev_dbg(db->dev, "fifo error\n"); |
09f75cd7 | 971 | dev->stats.rx_fifo_errors++; |
a1365275 | 972 | } |
93116573 | 973 | if (rxhdr.RxStatus & 0x02) { |
a76836f9 | 974 | dev_dbg(db->dev, "crc error\n"); |
09f75cd7 | 975 | dev->stats.rx_crc_errors++; |
a1365275 | 976 | } |
93116573 | 977 | if (rxhdr.RxStatus & 0x80) { |
a76836f9 | 978 | dev_dbg(db->dev, "length error\n"); |
09f75cd7 | 979 | dev->stats.rx_length_errors++; |
a1365275 SH |
980 | } |
981 | } | |
982 | ||
983 | /* Move data from DM9000 */ | |
984 | if (GoodPacket | |
985 | && ((skb = dev_alloc_skb(RxLen + 4)) != NULL)) { | |
a1365275 SH |
986 | skb_reserve(skb, 2); |
987 | rdptr = (u8 *) skb_put(skb, RxLen - 4); | |
988 | ||
989 | /* Read received packet from RX SRAM */ | |
990 | ||
991 | (db->inblk)(db->io_data, rdptr, RxLen); | |
09f75cd7 | 992 | dev->stats.rx_bytes += RxLen; |
a1365275 SH |
993 | |
994 | /* Pass to upper layer */ | |
995 | skb->protocol = eth_type_trans(skb, dev); | |
996 | netif_rx(skb); | |
09f75cd7 | 997 | dev->stats.rx_packets++; |
a1365275 SH |
998 | |
999 | } else { | |
1000 | /* need to dump the packet's data */ | |
1001 | ||
1002 | (db->dumpblk)(db->io_data, RxLen); | |
1003 | } | |
1004 | } while (rxbyte == DM9000_PKT_RDY); | |
1005 | } | |
1006 | ||
1007 | /* | |
86c62fab | 1008 | * Read a word data from EEPROM |
a1365275 | 1009 | */ |
86c62fab | 1010 | static void |
9a2f037c | 1011 | dm9000_read_eeprom(board_info_t *db, int offset, unsigned char *to) |
a1365275 | 1012 | { |
9a2f037c BD |
1013 | mutex_lock(&db->addr_lock); |
1014 | ||
a1365275 SH |
1015 | iow(db, DM9000_EPAR, offset); |
1016 | iow(db, DM9000_EPCR, EPCR_ERPRR); | |
1017 | mdelay(8); /* according to the datasheet 200us should be enough, | |
1018 | but it doesn't work */ | |
1019 | iow(db, DM9000_EPCR, 0x0); | |
86c62fab BD |
1020 | |
1021 | to[0] = ior(db, DM9000_EPDRL); | |
1022 | to[1] = ior(db, DM9000_EPDRH); | |
9a2f037c BD |
1023 | |
1024 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1025 | } |
1026 | ||
1027 | #ifdef DM9000_PROGRAM_EEPROM | |
1028 | /* | |
1029 | * Write a word data to SROM | |
1030 | */ | |
1031 | static void | |
1032 | write_srom_word(board_info_t * db, int offset, u16 val) | |
1033 | { | |
9a2f037c BD |
1034 | mutex_lock(&db->addr_lock); |
1035 | ||
a1365275 SH |
1036 | iow(db, DM9000_EPAR, offset); |
1037 | iow(db, DM9000_EPDRH, ((val >> 8) & 0xff)); | |
1038 | iow(db, DM9000_EPDRL, (val & 0xff)); | |
1039 | iow(db, DM9000_EPCR, EPCR_WEP | EPCR_ERPRW); | |
1040 | mdelay(8); /* same shit */ | |
1041 | iow(db, DM9000_EPCR, 0); | |
9a2f037c BD |
1042 | |
1043 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1044 | } |
1045 | ||
1046 | /* | |
1047 | * Only for development: | |
1048 | * Here we write static data to the eeprom in case | |
1049 | * we don't have valid content on a new board | |
1050 | */ | |
1051 | static void | |
1052 | program_eeprom(board_info_t * db) | |
1053 | { | |
1054 | u16 eeprom[] = { 0x0c00, 0x007f, 0x1300, /* MAC Address */ | |
1055 | 0x0000, /* Autoload: accept nothing */ | |
1056 | 0x0a46, 0x9000, /* Vendor / Product ID */ | |
1057 | 0x0000, /* pin control */ | |
1058 | 0x0000, | |
1059 | }; /* Wake-up mode control */ | |
1060 | int i; | |
1061 | for (i = 0; i < 8; i++) | |
1062 | write_srom_word(db, i, eeprom[i]); | |
1063 | } | |
1064 | #endif | |
1065 | ||
1066 | ||
1067 | /* | |
1068 | * Calculate the CRC valude of the Rx packet | |
1069 | * flag = 1 : return the reverse CRC (for the received packet CRC) | |
1070 | * 0 : return the normal CRC (for Hash Table index) | |
1071 | */ | |
1072 | ||
1073 | static unsigned long | |
1074 | cal_CRC(unsigned char *Data, unsigned int Len, u8 flag) | |
1075 | { | |
1076 | ||
1077 | u32 crc = ether_crc_le(Len, Data); | |
1078 | ||
1079 | if (flag) | |
1080 | return ~crc; | |
1081 | ||
1082 | return crc; | |
1083 | } | |
1084 | ||
1085 | /* | |
1086 | * Set DM9000 multicast address | |
1087 | */ | |
1088 | static void | |
1089 | dm9000_hash_table(struct net_device *dev) | |
1090 | { | |
1091 | board_info_t *db = (board_info_t *) dev->priv; | |
1092 | struct dev_mc_list *mcptr = dev->mc_list; | |
1093 | int mc_cnt = dev->mc_count; | |
1094 | u32 hash_val; | |
1095 | u16 i, oft, hash_table[4]; | |
1096 | unsigned long flags; | |
1097 | ||
5b2b4ff0 | 1098 | dm9000_dbg(db, 1, "entering %s\n", __func__); |
a1365275 SH |
1099 | |
1100 | spin_lock_irqsave(&db->lock,flags); | |
1101 | ||
1102 | for (i = 0, oft = 0x10; i < 6; i++, oft++) | |
1103 | iow(db, oft, dev->dev_addr[i]); | |
1104 | ||
1105 | /* Clear Hash Table */ | |
1106 | for (i = 0; i < 4; i++) | |
1107 | hash_table[i] = 0x0; | |
1108 | ||
1109 | /* broadcast address */ | |
1110 | hash_table[3] = 0x8000; | |
1111 | ||
1112 | /* the multicast address in Hash Table : 64 bits */ | |
1113 | for (i = 0; i < mc_cnt; i++, mcptr = mcptr->next) { | |
1114 | hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f; | |
1115 | hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16); | |
1116 | } | |
1117 | ||
1118 | /* Write the hash table to MAC MD table */ | |
1119 | for (i = 0, oft = 0x16; i < 4; i++) { | |
1120 | iow(db, oft++, hash_table[i] & 0xff); | |
1121 | iow(db, oft++, (hash_table[i] >> 8) & 0xff); | |
1122 | } | |
1123 | ||
1124 | spin_unlock_irqrestore(&db->lock,flags); | |
1125 | } | |
1126 | ||
1127 | ||
321f69a4 BD |
1128 | /* |
1129 | * Sleep, either by using msleep() or if we are suspending, then | |
1130 | * use mdelay() to sleep. | |
1131 | */ | |
1132 | static void dm9000_msleep(board_info_t *db, unsigned int ms) | |
1133 | { | |
1134 | if (db->in_suspend) | |
1135 | mdelay(ms); | |
1136 | else | |
1137 | msleep(ms); | |
1138 | } | |
1139 | ||
a1365275 SH |
1140 | /* |
1141 | * Read a word from phyxcer | |
1142 | */ | |
1143 | static int | |
1144 | dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg) | |
1145 | { | |
1146 | board_info_t *db = (board_info_t *) dev->priv; | |
1147 | unsigned long flags; | |
9ef9ac51 | 1148 | unsigned int reg_save; |
a1365275 SH |
1149 | int ret; |
1150 | ||
9a2f037c BD |
1151 | mutex_lock(&db->addr_lock); |
1152 | ||
a1365275 | 1153 | spin_lock_irqsave(&db->lock,flags); |
9ef9ac51 BD |
1154 | |
1155 | /* Save previous register address */ | |
1156 | reg_save = readb(db->io_addr); | |
1157 | ||
a1365275 SH |
1158 | /* Fill the phyxcer register into REG_0C */ |
1159 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1160 | ||
1161 | iow(db, DM9000_EPCR, 0xc); /* Issue phyxcer read command */ | |
89c8b0e6 BD |
1162 | |
1163 | writeb(reg_save, db->io_addr); | |
1164 | spin_unlock_irqrestore(&db->lock,flags); | |
1165 | ||
321f69a4 | 1166 | dm9000_msleep(db, 1); /* Wait read complete */ |
89c8b0e6 BD |
1167 | |
1168 | spin_lock_irqsave(&db->lock,flags); | |
1169 | reg_save = readb(db->io_addr); | |
1170 | ||
a1365275 SH |
1171 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer read command */ |
1172 | ||
1173 | /* The read data keeps on REG_0D & REG_0E */ | |
1174 | ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL); | |
1175 | ||
9ef9ac51 BD |
1176 | /* restore the previous address */ |
1177 | writeb(reg_save, db->io_addr); | |
a1365275 SH |
1178 | spin_unlock_irqrestore(&db->lock,flags); |
1179 | ||
9a2f037c | 1180 | mutex_unlock(&db->addr_lock); |
a1365275 SH |
1181 | return ret; |
1182 | } | |
1183 | ||
1184 | /* | |
1185 | * Write a word to phyxcer | |
1186 | */ | |
1187 | static void | |
1188 | dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value) | |
1189 | { | |
1190 | board_info_t *db = (board_info_t *) dev->priv; | |
1191 | unsigned long flags; | |
9ef9ac51 | 1192 | unsigned long reg_save; |
a1365275 | 1193 | |
9a2f037c BD |
1194 | mutex_lock(&db->addr_lock); |
1195 | ||
a1365275 SH |
1196 | spin_lock_irqsave(&db->lock,flags); |
1197 | ||
9ef9ac51 BD |
1198 | /* Save previous register address */ |
1199 | reg_save = readb(db->io_addr); | |
1200 | ||
a1365275 SH |
1201 | /* Fill the phyxcer register into REG_0C */ |
1202 | iow(db, DM9000_EPAR, DM9000_PHY | reg); | |
1203 | ||
1204 | /* Fill the written data into REG_0D & REG_0E */ | |
1205 | iow(db, DM9000_EPDRL, (value & 0xff)); | |
1206 | iow(db, DM9000_EPDRH, ((value >> 8) & 0xff)); | |
1207 | ||
1208 | iow(db, DM9000_EPCR, 0xa); /* Issue phyxcer write command */ | |
89c8b0e6 BD |
1209 | |
1210 | writeb(reg_save, db->io_addr); | |
9a2f037c | 1211 | spin_unlock_irqrestore(&db->lock, flags); |
89c8b0e6 | 1212 | |
321f69a4 | 1213 | dm9000_msleep(db, 1); /* Wait write complete */ |
89c8b0e6 BD |
1214 | |
1215 | spin_lock_irqsave(&db->lock,flags); | |
1216 | reg_save = readb(db->io_addr); | |
1217 | ||
a1365275 SH |
1218 | iow(db, DM9000_EPCR, 0x0); /* Clear phyxcer write command */ |
1219 | ||
9ef9ac51 BD |
1220 | /* restore the previous address */ |
1221 | writeb(reg_save, db->io_addr); | |
1222 | ||
9a2f037c BD |
1223 | spin_unlock_irqrestore(&db->lock, flags); |
1224 | mutex_unlock(&db->addr_lock); | |
a1365275 SH |
1225 | } |
1226 | ||
1227 | static int | |
3ae5eaec | 1228 | dm9000_drv_suspend(struct platform_device *dev, pm_message_t state) |
a1365275 | 1229 | { |
3ae5eaec | 1230 | struct net_device *ndev = platform_get_drvdata(dev); |
321f69a4 | 1231 | board_info_t *db; |
a1365275 | 1232 | |
9480e307 | 1233 | if (ndev) { |
321f69a4 BD |
1234 | db = (board_info_t *) ndev->priv; |
1235 | db->in_suspend = 1; | |
1236 | ||
a1365275 SH |
1237 | if (netif_running(ndev)) { |
1238 | netif_device_detach(ndev); | |
1239 | dm9000_shutdown(ndev); | |
1240 | } | |
1241 | } | |
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | static int | |
3ae5eaec | 1246 | dm9000_drv_resume(struct platform_device *dev) |
a1365275 | 1247 | { |
3ae5eaec | 1248 | struct net_device *ndev = platform_get_drvdata(dev); |
a1365275 SH |
1249 | board_info_t *db = (board_info_t *) ndev->priv; |
1250 | ||
9480e307 | 1251 | if (ndev) { |
a1365275 SH |
1252 | |
1253 | if (netif_running(ndev)) { | |
1254 | dm9000_reset(db); | |
1255 | dm9000_init_dm9000(ndev); | |
1256 | ||
1257 | netif_device_attach(ndev); | |
1258 | } | |
321f69a4 BD |
1259 | |
1260 | db->in_suspend = 0; | |
a1365275 SH |
1261 | } |
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | static int | |
3ae5eaec | 1266 | dm9000_drv_remove(struct platform_device *pdev) |
a1365275 | 1267 | { |
3ae5eaec | 1268 | struct net_device *ndev = platform_get_drvdata(pdev); |
a1365275 | 1269 | |
3ae5eaec | 1270 | platform_set_drvdata(pdev, NULL); |
a1365275 SH |
1271 | |
1272 | unregister_netdev(ndev); | |
1273 | dm9000_release_board(pdev, (board_info_t *) ndev->priv); | |
9fd9f9b6 | 1274 | free_netdev(ndev); /* free device structure */ |
a1365275 | 1275 | |
a76836f9 | 1276 | dev_dbg(&pdev->dev, "released and freed device\n"); |
a1365275 SH |
1277 | return 0; |
1278 | } | |
1279 | ||
3ae5eaec | 1280 | static struct platform_driver dm9000_driver = { |
5d22a312 BD |
1281 | .driver = { |
1282 | .name = "dm9000", | |
1283 | .owner = THIS_MODULE, | |
1284 | }, | |
a1365275 SH |
1285 | .probe = dm9000_probe, |
1286 | .remove = dm9000_drv_remove, | |
1287 | .suspend = dm9000_drv_suspend, | |
1288 | .resume = dm9000_drv_resume, | |
1289 | }; | |
1290 | ||
1291 | static int __init | |
1292 | dm9000_init(void) | |
1293 | { | |
7da99859 | 1294 | printk(KERN_INFO "%s Ethernet Driver, V%s\n", CARDNAME, DRV_VERSION); |
2ae2d77c | 1295 | |
3ae5eaec | 1296 | return platform_driver_register(&dm9000_driver); /* search board and register */ |
a1365275 SH |
1297 | } |
1298 | ||
1299 | static void __exit | |
1300 | dm9000_cleanup(void) | |
1301 | { | |
3ae5eaec | 1302 | platform_driver_unregister(&dm9000_driver); |
a1365275 SH |
1303 | } |
1304 | ||
1305 | module_init(dm9000_init); | |
1306 | module_exit(dm9000_cleanup); | |
1307 | ||
1308 | MODULE_AUTHOR("Sascha Hauer, Ben Dooks"); | |
1309 | MODULE_DESCRIPTION("Davicom DM9000 network driver"); | |
1310 | MODULE_LICENSE("GPL"); |