[linux.git] / drivers / ata / pata_artop.c

/*
 *    pata_artop.c - ARTOP ATA controller driver
 *
 *	(C) 2006 Red Hat
 *	(C) 2007,2011 Bartlomiej Zolnierkiewicz
 *
 *    Based in part on drivers/ide/pci/aec62xx.c
 *	Copyright (C) 1999-2002	Andre Hedrick <[email protected]>
 *	865/865R fixes for Macintosh card version from a patch to the old
 *		driver by Thibaut VARENE <[email protected]>
 *	When setting the PCI latency we must set 0x80 or higher for burst
 *		performance Alessandro Zummo <[email protected]>
 *
 *	TODO
 *	Investigate no_dsc on 850R
 *	Clock detect
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_artop"
#define DRV_VERSION	"0.4.6"

/*
 *	The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
 *	get PCI bus speed functionality we leave this as 0. Its a variable
 *	for when we get the functionality and also for folks wanting to
 *	test stuff.
 */

static int clock = 0;

/**
 *	artop62x0_pre_reset	-	probe begin
 *	@link: link
 *	@deadline: deadline jiffies for the operation
 *
 *	Nothing complicated needed here.
 */

static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits artop_enable_bits[] = {
		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
	};

	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	/* Odd numbered device ids are the units with enable bits. */
	if ((pdev->device & 1) &&
	    !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	artop6260_cable_detect	-	identify cable type
 *	@ap: Port
 *
 *	Identify the cable type for the ARTOP interface in question
 */

static int artop6260_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;
	pci_read_config_byte(pdev, 0x49, &tmp);
	if (tmp & (1 << ap->port_no))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

/**
 *	artop6210_load_piomode - Load a set of PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. This
 *	is used both to set PIO timings in PIO mode and also to set the
 *	matching PIO clocking for UDMA, as well as the MWDMA timings.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u16 timing[2][5] = {
		{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
		{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
}

/**
 *	artop6210_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_load_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u8 timing[2][5] = {
		{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
		{ 0x70, 0x7A, 0x78, 0x43, 0x41 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
}

/**
 *	artop6260_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

/**
 *	artop6210_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device whose timings we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6210_load_piomode(ap, adev, pio);

	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));

	/* Add ultra DMA bits if in UDMA mode */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (2 * dn));
	}
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6260_load_piomode(ap, adev, pio);

	/* Add ultra DMA bits if in UDMA mode */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (4 * adev->devno));
	}
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

/**
 *	artop_6210_qc_defer	-	implement serialization
 *	@qc: command
 *
 *	Issue commands per host on this chip.
 */

static int artop6210_qc_defer(struct ata_queued_cmd *qc)
{
	struct ata_host *host = qc->ap->host;
	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	int rc;

	/* First apply the usual rules */
	rc = ata_std_qc_defer(qc);
	if (rc != 0)
		return rc;

	/* Now apply serialization rules. Only allow a command if the
	   other channel state machine is idle */
	if (alt && alt->qc_active)
		return	ATA_DEFER_PORT;
	return 0;
}

static struct scsi_host_template artop_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations artop6210_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= ata_cable_40wire,
	.set_piomode		= artop6210_set_piomode,
	.set_dmamode		= artop6210_set_dmamode,
	.prereset		= artop62x0_pre_reset,
	.qc_defer		= artop6210_qc_defer,
};

static struct ata_port_operations artop6260_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= artop6260_cable_detect,
	.set_piomode		= artop6260_set_piomode,
	.set_dmamode		= artop6260_set_dmamode,
	.prereset		= artop62x0_pre_reset,
};

static void atp8xx_fixup(struct pci_dev *pdev)
{
	if (pdev->device == 0x0005)
		/* BIOS may have left us in UDMA, clear it before libata probe */
		pci_write_config_byte(pdev, 0x54, 0);
	else if (pdev->device == 0x0008 || pdev->device == 0x0009) {
		u8 reg;

		/* Mac systems come up with some registers not set as we
		   will need them */

		/* Clear reset & test bits */
		pci_read_config_byte(pdev, 0x49, &reg);
		pci_write_config_byte(pdev, 0x49, reg & ~0x30);

		/* PCI latency must be > 0x80 for burst mode, tweak it
		 * if required.
		 */
		pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
		if (reg <= 0x80)
			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);

		/* Enable IRQ output and burst mode */
		pci_read_config_byte(pdev, 0x4a, &reg);
		pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
	}
}

/**
 *	artop_init_one - Register ARTOP ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in artop_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_6210 = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA2,
		.port_ops	= &artop6210_ops,
	};
	static const struct ata_port_info info_626x = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA4,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_628x = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA5,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_628x_fast = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask 	= ATA_UDMA6,
		.port_ops	= &artop6260_ops,
	};
	const struct ata_port_info *ppi[] = { NULL, NULL };
	int rc;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (id->driver_data == 0)	/* 6210 variant */
		ppi[0] = &info_6210;
	else if (id->driver_data == 1)	/* 6260 */
		ppi[0] = &info_626x;
	else if (id->driver_data == 2)	{ /* 6280 or 6280 + fast */
		unsigned long io = pci_resource_start(pdev, 4);

		ppi[0] = &info_628x;
		if (inb(io) & 0x10)
			ppi[0] = &info_628x_fast;
	}

	BUG_ON(ppi[0] == NULL);

	atp8xx_fixup(pdev);

	return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
}

static const struct pci_device_id artop_pci_tbl[] = {
	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },

	{ }	/* terminate list */
};

#ifdef CONFIG_PM_SLEEP
static int atp8xx_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = pci_get_drvdata(pdev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	atp8xx_fixup(pdev);

	ata_host_resume(host);
	return 0;
}
#endif

static struct pci_driver artop_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= artop_pci_tbl,
	.probe			= artop_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend		= ata_pci_device_suspend,
	.resume			= atp8xx_reinit_one,
#endif
};

module_pci_driver(artop_pci_driver);

MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");
MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_artop.c - ARTOP ATA controller driver
	3	*
ab771630	4	* (C) 2006 Red Hat
067f8c7b	5	* (C) 2007,2011 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based in part on drivers/ide/pci/aec62xx.c
	8	* Copyright (C) 1999-2002 Andre Hedrick <[email protected]>
	9	* 865/865R fixes for Macintosh card version from a patch to the old
	10	* driver by Thibaut VARENE <[email protected]>
	11	* When setting the PCI latency we must set 0x80 or higher for burst
	12	* performance Alessandro Zummo <[email protected]>
	13	*
	14	* TODO
669a5db4 JG	15	* Investigate no_dsc on 850R
	16	* Clock detect
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
669a5db4 JG	22	#include <linux/blkdev.h>
	23	#include <linux/delay.h>
	24	#include <linux/device.h>
	25	#include <scsi/scsi_host.h>
	26	#include <linux/libata.h>
	27	#include <linux/ata.h>
	28
	29	#define DRV_NAME "pata_artop"
067f8c7b	30	#define DRV_VERSION "0.4.6"
669a5db4 JG	31
	32	/*
	33	* The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
	34	* get PCI bus speed functionality we leave this as 0. Its a variable
	35	* for when we get the functionality and also for folks wanting to
	36	* test stuff.
	37	*/
	38
	39	static int clock = 0;
	40
669a5db4	41	/**
f6b56696	42	* artop62x0_pre_reset - probe begin
cc0680a5	43	* @link: link
d4b2bab4	44	* @deadline: deadline jiffies for the operation
669a5db4	45	*
669a5db4 JG	46	* Nothing complicated needed here.
	47	*/
	48
f6b56696	49	static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 JG	50	{
	51	static const struct pci_bits artop_enable_bits[] = {
	52	{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
	53	{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
	54	};
	55
cc0680a5	56	struct ata_port *ap = link->ap;
669a5db4	57	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4	58
f6b56696	59	/* Odd numbered device ids are the units with enable bits. */
673424c0 JD	60	if ((pdev->device & 1) &&
673424c0 JD	61	!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
c961922b	62	return -ENOENT;
27c78b37	63
9363c382	64	return ata_sff_prereset(link, deadline);
a73984a0	65	}
c961922b	66
a73984a0 JG	67	/**
	68	* artop6260_cable_detect - identify cable type
	69	* @ap: Port
	70	*
c343a839	71	* Identify the cable type for the ARTOP interface in question
a73984a0	72	*/
a617c09f	73
a73984a0 JG	74	static int artop6260_cable_detect(struct ata_port *ap)
	75	{
	76	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	77	u8 tmp;
669a5db4	78	pci_read_config_byte(pdev, 0x49, &tmp);
3f9dd27a	79	if (tmp & (1 << ap->port_no))
a73984a0 JG	80	return ATA_CBL_PATA40;
a73984a0 JG	81	return ATA_CBL_PATA80;
669a5db4 JG	82	}
669a5db4 JG	83
669a5db4 JG	84	/**
	85	* artop6210_load_piomode - Load a set of PATA PIO timings
	86	* @ap: Port whose timings we are configuring
	87	* @adev: Device
	88	* @pio: PIO mode
	89	*
	90	* Set PIO mode for device, in host controller PCI config space. This
	91	* is used both to set PIO timings in PIO mode and also to set the
	92	* matching PIO clocking for UDMA, as well as the MWDMA timings.
	93	*
	94	* LOCKING:
	95	* None (inherited from caller).
	96	*/
	97
	98	static void artop6210_load_piomode(struct ata_port ap, struct ata_device adev, unsigned int pio)
	99	{
	100	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	101	int dn = adev->devno + 2 * ap->port_no;
	102	const u16 timing[2][5] = {
	103	{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
	104	{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
	105
	106	};
	107	/* Load the PIO timing active/recovery bits */
	108	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
	109	}
	110
	111	/**
	112	* artop6210_set_piomode - Initialize host controller PATA PIO timings
	113	* @ap: Port whose timings we are configuring
	114	* @adev: Device we are configuring
	115	*
	116	* Set PIO mode for device, in host controller PCI config space. For
	117	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
	118	* the event UDMA is used the later call to set_dmamode will set the
	119	* bits as required.
	120	*
	121	* LOCKING:
	122	* None (inherited from caller).
	123	*/
	124
	125	static void artop6210_set_piomode(struct ata_port ap, struct ata_device adev)
	126	{
	127	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	128	int dn = adev->devno + 2 * ap->port_no;
	129	u8 ultra;
	130
	131	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
	132
	133	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	134	pci_read_config_byte(pdev, 0x54, &ultra);
	135	ultra &= ~(3 << (2 * dn));
	136	pci_write_config_byte(pdev, 0x54, ultra);
	137	}
	138
	139	/**
	140	* artop6260_load_piomode - Initialize host controller PATA PIO timings
	141	* @ap: Port whose timings we are configuring
	142	* @adev: Device we are configuring
	143	* @pio: PIO mode
	144	*
	145	* Set PIO mode for device, in host controller PCI config space. The
	146	* ARTOP6260 and relatives store the timing data differently.
	147	*
148	* LOCKING:
149	* None (inherited from caller).
150	*/
151
152	static void artop6260_load_piomode (struct ata_port ap, struct ata_device adev, unsigned int pio)
153	{
154	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
155	int dn = adev->devno + 2 * ap->port_no;
156	const u8 timing[2][5] = {
157	{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
158	{ 0x70, 0x7A, 0x78, 0x43, 0x41 }
159
160	};
161	/* Load the PIO timing active/recovery bits */
162	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
163	}
164
165	/**
166	* artop6260_set_piomode - Initialize host controller PATA PIO timings
167	* @ap: Port whose timings we are configuring
168	* @adev: Device we are configuring
169	*
170	* Set PIO mode for device, in host controller PCI config space. For
171	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
172	* the event UDMA is used the later call to set_dmamode will set the
173	* bits as required.
174	*
175	* LOCKING:
176	* None (inherited from caller).
177	*/
178
179	static void artop6260_set_piomode(struct ata_port ap, struct ata_device adev)
180	{
181	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
182	u8 ultra;
183
184	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
185
186	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
187	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
188	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
189	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
190	}
191
192	/**
193	* artop6210_set_dmamode - Initialize host controller PATA PIO timings
194	* @ap: Port whose timings we are configuring
a73984a0	195	* @adev: Device whose timings we are configuring
669a5db4 JG	196	*
	197	* Set DMA mode for device, in host controller PCI config space.
	198	*
	199	* LOCKING:
	200	* None (inherited from caller).
	201	*/
	202
	203	static void artop6210_set_dmamode (struct ata_port ap, struct ata_device adev)
	204	{
	205	unsigned int pio;
	206	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	207	int dn = adev->devno + 2 * ap->port_no;
	208	u8 ultra;
	209
	210	if (adev->dma_mode == XFER_MW_DMA_0)
	211	pio = 1;
	212	else
	213	pio = 4;
	214
	215	/* Load the PIO timing active/recovery bits */
	216	artop6210_load_piomode(ap, adev, pio);
	217
	218	pci_read_config_byte(pdev, 0x54, &ultra);
	219	ultra &= ~(3 << (2 * dn));
	220
	221	/* Add ultra DMA bits if in UDMA mode */
	222	if (adev->dma_mode >= XFER_UDMA_0) {
	223	u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
	224	if (mode == 0)
	225	mode = 1;
	226	ultra \|= (mode << (2 * dn));
	227	}
	228	pci_write_config_byte(pdev, 0x54, ultra);
	229	}
	230
	231	/**
	232	* artop6260_set_dmamode - Initialize host controller PATA PIO timings
	233	* @ap: Port whose timings we are configuring
	234	* @adev: Device we are configuring
	235	*
	236	* Set DMA mode for device, in host controller PCI config space. The
	237	* ARTOP6260 and relatives store the timing data differently.
	238	*
	239	* LOCKING:
	240	* None (inherited from caller).
	241	*/
	242
	243	static void artop6260_set_dmamode (struct ata_port ap, struct ata_device adev)
	244	{
	245	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	246	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	247	u8 ultra;
	248
	249	if (adev->dma_mode == XFER_MW_DMA_0)
	250	pio = 1;
	251	else
	252	pio = 4;
	253
	254	/* Load the PIO timing active/recovery bits */
	255	artop6260_load_piomode(ap, adev, pio);
	256
	257	/* Add ultra DMA bits if in UDMA mode */
	258	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	259	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
260	if (adev->dma_mode >= XFER_UDMA_0) {
261	u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
262	if (mode == 0)
263	mode = 1;
264	ultra \|= (mode << (4 * adev->devno));
265	}
266	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
267	}
268
140d6fed AC	269	/**
	270	* artop_6210_qc_defer - implement serialization
	271	* @qc: command
	272	*
	273	* Issue commands per host on this chip.
	274	*/
	275
	276	static int artop6210_qc_defer(struct ata_queued_cmd *qc)
	277	{
	278	struct ata_host *host = qc->ap->host;
	279	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	280	int rc;
	281
	282	/* First apply the usual rules */
	283	rc = ata_std_qc_defer(qc);
	284	if (rc != 0)
	285	return rc;
	286
	287	/* Now apply serialization rules. Only allow a command if the
	288	other channel state machine is idle */
	289	if (alt && alt->qc_active)
	290	return ATA_DEFER_PORT;
	291	return 0;
	292	}
	293
669a5db4	294	static struct scsi_host_template artop_sht = {
68d1d07b	295	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	296	};
669a5db4 JG	297
029cfd6b TH	298	static struct ata_port_operations artop6210_ops = {
	299	.inherits = &ata_bmdma_port_ops,
	300	.cable_detect = ata_cable_40wire,
669a5db4 JG	301	.set_piomode = artop6210_set_piomode,
669a5db4 JG	302	.set_dmamode = artop6210_set_dmamode,
f6b56696	303	.prereset = artop62x0_pre_reset,
140d6fed	304	.qc_defer = artop6210_qc_defer,
669a5db4 JG	305	};
669a5db4 JG	306
029cfd6b TH	307	static struct ata_port_operations artop6260_ops = {
	308	.inherits = &ata_bmdma_port_ops,
	309	.cable_detect = artop6260_cable_detect,
669a5db4 JG	310	.set_piomode = artop6260_set_piomode,
669a5db4 JG	311	.set_dmamode = artop6260_set_dmamode,
f6b56696	312	.prereset = artop62x0_pre_reset,
669a5db4 JG	313	};
669a5db4 JG	314
067f8c7b BZ	315	static void atp8xx_fixup(struct pci_dev *pdev)
	316	{
	317	if (pdev->device == 0x0005)
	318	/* BIOS may have left us in UDMA, clear it before libata probe */
	319	pci_write_config_byte(pdev, 0x54, 0);
	320	else if (pdev->device == 0x0008 \|\| pdev->device == 0x0009) {
	321	u8 reg;
	322
	323	/* Mac systems come up with some registers not set as we
	324	will need them */
	325
	326	/* Clear reset & test bits */
	327	pci_read_config_byte(pdev, 0x49, &reg);
	328	pci_write_config_byte(pdev, 0x49, reg & ~0x30);
	329
	330	/* PCI latency must be > 0x80 for burst mode, tweak it
	331	* if required.
	332	*/
	333	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
	334	if (reg <= 0x80)
	335	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
	336
	337	/* Enable IRQ output and burst mode */
	338	pci_read_config_byte(pdev, 0x4a, &reg);
	339	pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) \| 0x80);
	340	}
	341	}
669a5db4 JG	342
	343	/**
	344	* artop_init_one - Register ARTOP ATA PCI device with kernel services
	345	* @pdev: PCI device to register
	346	* @ent: Entry in artop_pci_tbl matching with @pdev
	347	*
	348	* Called from kernel PCI layer.
	349	*
	350	* LOCKING:
	351	* Inherited from PCI layer (may sleep).
	352	*
	353	* RETURNS:
	354	* Zero on success, or -ERRNO value.
	355	*/
	356
	357	static int artop_init_one (struct pci_dev pdev, const struct pci_device_id id)
	358	{
1626aeb8	359	static const struct ata_port_info info_6210 = {
1d2808fd	360	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	361	.pio_mask = ATA_PIO4,
14bdef98 EIB	362	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	363	.udma_mask = ATA_UDMA2,
	364	.port_ops = &artop6210_ops,
	365	};
1626aeb8	366	static const struct ata_port_info info_626x = {
1d2808fd	367	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	368	.pio_mask = ATA_PIO4,
14bdef98 EIB	369	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	370	.udma_mask = ATA_UDMA4,
	371	.port_ops = &artop6260_ops,
	372	};
be456b77	373	static const struct ata_port_info info_628x = {
1d2808fd	374	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	375	.pio_mask = ATA_PIO4,
14bdef98 EIB	376	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	377	.udma_mask = ATA_UDMA5,
	378	.port_ops = &artop6260_ops,
	379	};
be456b77	380	static const struct ata_port_info info_628x_fast = {
be456b77	381	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	382	.pio_mask = ATA_PIO4,
14bdef98 EIB	383	.mwdma_mask = ATA_MWDMA2,
be456b77 BZ	384	.udma_mask = ATA_UDMA6,
	385	.port_ops = &artop6260_ops,
	386	};
1626aeb8	387	const struct ata_port_info *ppi[] = { NULL, NULL };
f08048e9	388	int rc;
669a5db4	389
06296a1e	390	ata_print_version_once(&pdev->dev, DRV_VERSION);
669a5db4	391
f08048e9 TH	392	rc = pcim_enable_device(pdev);
	393	if (rc)
	394	return rc;
	395
067f8c7b	396	if (id->driver_data == 0) /* 6210 variant */
1626aeb8	397	ppi[0] = &info_6210;
669a5db4	398	else if (id->driver_data == 1) /* 6260 */
1626aeb8	399	ppi[0] = &info_626x;
be456b77	400	else if (id->driver_data == 2) { /* 6280 or 6280 + fast */
669a5db4	401	unsigned long io = pci_resource_start(pdev, 4);
669a5db4	402
be456b77	403	ppi[0] = &info_628x;
669a5db4	404	if (inb(io) & 0x10)
be456b77	405	ppi[0] = &info_628x_fast;
669a5db4	406	}
15a7c3bb	407
1626aeb8	408	BUG_ON(ppi[0] == NULL);
15a7c3bb	409
067f8c7b BZ	410	atp8xx_fixup(pdev);
067f8c7b BZ	411
1c5afdf7	412	return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
669a5db4 JG	413	}
	414
	415	static const struct pci_device_id artop_pci_tbl[] = {
2d2744fc JG	416	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	417	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	418	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	419	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	420	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },
	421
669a5db4 JG	422	{ } /* terminate list */
	423	};
	424
58eb8cd5	425	#ifdef CONFIG_PM_SLEEP
067f8c7b BZ	426	static int atp8xx_reinit_one(struct pci_dev *pdev)
067f8c7b BZ	427	{
0a86e1c8	428	struct ata_host *host = pci_get_drvdata(pdev);
067f8c7b BZ	429	int rc;
	430
	431	rc = ata_pci_device_do_resume(pdev);
	432	if (rc)
	433	return rc;
	434
	435	atp8xx_fixup(pdev);
	436
	437	ata_host_resume(host);
	438	return 0;
	439	}
	440	#endif
	441
669a5db4 JG	442	static struct pci_driver artop_pci_driver = {
	443	.name = DRV_NAME,
	444	.id_table = artop_pci_tbl,
	445	.probe = artop_init_one,
	446	.remove = ata_pci_remove_one,
58eb8cd5	447	#ifdef CONFIG_PM_SLEEP
067f8c7b BZ	448	.suspend = ata_pci_device_suspend,
	449	.resume = atp8xx_reinit_one,
	450	#endif
669a5db4 JG	451	};
669a5db4 JG	452
2fc75da0	453	module_pci_driver(artop_pci_driver);
669a5db4	454
067f8c7b	455	MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");
669a5db4 JG	456	MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
	457	MODULE_LICENSE("GPL");
	458	MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
	459	MODULE_VERSION(DRV_VERSION);