[linux.git] / drivers / ata / pata_artop.c

/*
 *    pata_artop.c - ARTOP ATA controller driver
 *
 *	(C) 2006 Red Hat <[email protected]>
 *
 *    Based in part on drivers/ide/pci/aec62xx.c
 *	Copyright (C) 1999-2002	Andre Hedrick <[email protected]>
 *	865/865R fixes for Macintosh card version from a patch to the old
 *		driver by Thibaut VARENE <[email protected]>
 *	When setting the PCI latency we must set 0x80 or higher for burst
 *		performance Alessandro Zummo <[email protected]>
 *
 *	TODO
 *	850 serialization once the core supports it
 *	Investigate no_dsc on 850R
 *	Clock detect
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_artop"
#define DRV_VERSION	"0.4.3"

/*
 *	The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
 *	get PCI bus speed functionality we leave this as 0. Its a variable
 *	for when we get the functionality and also for folks wanting to
 *	test stuff.
 */

static int clock = 0;

static int artop6210_pre_reset(struct ata_port *ap, unsigned long deadline)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	const struct pci_bits artop_enable_bits[] = {
		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
	};

	if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_std_prereset(ap, deadline);
}

/**
 *	artop6210_error_handler - Probe specified port on PATA host controller
 *	@ap: Port to probe
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, artop6210_pre_reset,
				    ata_std_softreset, NULL,
				    ata_std_postreset);
}

/**
 *	artop6260_pre_reset	-	check for 40/80 pin
 *	@ap: Port
 *	@deadline: deadline jiffies for the operation
 *
 *	The ARTOP hardware reports the cable detect bits in register 0x49.
 *	Nothing complicated needed here.
 */

static int artop6260_pre_reset(struct ata_port *ap, unsigned long deadline)
{
	static const struct pci_bits artop_enable_bits[] = {
		{ 0x4AU, 1U, 0x02UL, 0x02UL },	/* port 0 */
		{ 0x4AU, 1U, 0x04UL, 0x04UL },	/* port 1 */
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	/* Odd numbered device ids are the units with enable bits (the -R cards) */
	if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_std_prereset(ap, deadline);
}

/**
 *	artop6260_cable_detect	-	identify cable type
 *	@ap: Port
 *
 *	Identify the cable type for the ARTOp interface in question
 */

static int artop6260_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 tmp;
	pci_read_config_byte(pdev, 0x49, &tmp);
	if (tmp & (1 << ap->port_no))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

/**
 *	artop6260_error_handler - Probe specified port on PATA host controller
 *	@ap: Port to probe
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, artop6260_pre_reset,
				    ata_std_softreset, NULL,
				    ata_std_postreset);
}

/**
 *	artop6210_load_piomode - Load a set of PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. This
 *	is used both to set PIO timings in PIO mode and also to set the
 *	matching PIO clocking for UDMA, as well as the MWDMA timings.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u16 timing[2][5] = {
		{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
		{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
}

/**
 *	artop6210_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_load_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *	@pio: PIO mode
 *
 *	Set PIO mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	const u8 timing[2][5] = {
		{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
		{ 0x70, 0x7A, 0x78, 0x43, 0x41 }

	};
	/* Load the PIO timing active/recovery bits */
	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
}

/**
 *	artop6260_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space. For
 *	ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
 *	the event UDMA is used the later call to set_dmamode will set the
 *	bits as required.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);

	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

/**
 *	artop6210_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device whose timings we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int dn = adev->devno + 2 * ap->port_no;
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6210_load_piomode(ap, adev, pio);

	pci_read_config_byte(pdev, 0x54, &ultra);
	ultra &= ~(3 << (2 * dn));

	/* Add ultra DMA bits if in UDMA mode */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (2 * dn));
	}
	pci_write_config_byte(pdev, 0x54, ultra);
}

/**
 *	artop6260_set_dmamode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device we are configuring
 *
 *	Set DMA mode for device, in host controller PCI config space. The
 *	ARTOP6260 and relatives store the timing data differently.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	u8 ultra;

	if (adev->dma_mode == XFER_MW_DMA_0)
		pio = 1;
	else
		pio = 4;

	/* Load the PIO timing active/recovery bits */
	artop6260_load_piomode(ap, adev, pio);

	/* Add ultra DMA bits if in UDMA mode */
	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	ultra &= ~(7 << (4  * adev->devno));	/* One nibble per drive */
	if (adev->dma_mode >= XFER_UDMA_0) {
		u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
		if (mode == 0)
			mode = 1;
		ultra |= (mode << (4 * adev->devno));
	}
	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
}

static struct scsi_host_template artop_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations artop6210_ops = {
	.port_disable		= ata_port_disable,
	.set_piomode		= artop6210_set_piomode,
	.set_dmamode		= artop6210_set_dmamode,
	.mode_filter		= ata_pci_default_filter,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= artop6210_error_handler,
	.post_internal_cmd 	= ata_bmdma_post_internal_cmd,
	.cable_detect		= ata_cable_40wire,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,

	.data_xfer		= ata_data_xfer,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};

static const struct ata_port_operations artop6260_ops = {
	.port_disable		= ata_port_disable,
	.set_piomode		= artop6260_set_piomode,
	.set_dmamode		= artop6260_set_dmamode,

	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,

	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= artop6260_error_handler,
	.post_internal_cmd 	= ata_bmdma_post_internal_cmd,
	.cable_detect		= artop6260_cable_detect,

	.bmdma_setup		= ata_bmdma_setup,
	.bmdma_start		= ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_data_xfer,

	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,

	.port_start		= ata_port_start,
};


/**
 *	artop_init_one - Register ARTOP ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in artop_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
{
	static int printed_version;
	static const struct ata_port_info info_6210 = {
		.sht		= &artop_sht,
		.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask 	= ATA_UDMA2,
		.port_ops	= &artop6210_ops,
	};
	static const struct ata_port_info info_626x = {
		.sht		= &artop_sht,
		.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask 	= ATA_UDMA4,
		.port_ops	= &artop6260_ops,
	};
	static const struct ata_port_info info_626x_fast = {
		.sht		= &artop_sht,
		.flags		= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
		.pio_mask	= 0x1f,	/* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask 	= ATA_UDMA5,
		.port_ops	= &artop6260_ops,
	};
	const struct ata_port_info *ppi[] = { NULL, NULL };

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");

	if (id->driver_data == 0) {	/* 6210 variant */
		ppi[0] = &info_6210;
		ppi[1] = &ata_dummy_port_info;
		/* BIOS may have left us in UDMA, clear it before libata probe */
		pci_write_config_byte(pdev, 0x54, 0);
		/* For the moment (also lacks dsc) */
		printk(KERN_WARNING "ARTOP 6210 requires serialize functionality not yet supported by libata.\n");
		printk(KERN_WARNING "Secondary ATA ports will not be activated.\n");
	}
	else if (id->driver_data == 1)	/* 6260 */
		ppi[0] = &info_626x;
	else if (id->driver_data == 2)	{ /* 6260 or 6260 + fast */
		unsigned long io = pci_resource_start(pdev, 4);
		u8 reg;

		ppi[0] = &info_626x;
		if (inb(io) & 0x10)
			ppi[0] = &info_626x_fast;
		/* Mac systems come up with some registers not set as we
		   will need them */

		/* Clear reset & test bits */
		pci_read_config_byte(pdev, 0x49, &reg);
		pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);

		/* PCI latency must be > 0x80 for burst mode, tweak it
		 * if required.
		 */
		pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
		if (reg <= 0x80)
			pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);

		/* Enable IRQ output and burst mode */
		pci_read_config_byte(pdev, 0x4a, &reg);
		pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);

	}

	BUG_ON(ppi[0] == NULL);

	return ata_pci_init_one(pdev, ppi);
}

static const struct pci_device_id artop_pci_tbl[] = {
	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },

	{ }	/* terminate list */
};

static struct pci_driver artop_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= artop_pci_tbl,
	.probe			= artop_init_one,
	.remove			= ata_pci_remove_one,
};

static int __init artop_init(void)
{
	return pci_register_driver(&artop_pci_driver);
}

static void __exit artop_exit(void)
{
	pci_unregister_driver(&artop_pci_driver);
}

module_init(artop_init);
module_exit(artop_exit);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_artop.c - ARTOP ATA controller driver
	3	*
	4	* (C) 2006 Red Hat <[email protected]>
	5	*
	6	* Based in part on drivers/ide/pci/aec62xx.c
	7	* Copyright (C) 1999-2002 Andre Hedrick <[email protected]>
	8	* 865/865R fixes for Macintosh card version from a patch to the old
	9	* driver by Thibaut VARENE <[email protected]>
	10	* When setting the PCI latency we must set 0x80 or higher for burst
	11	* performance Alessandro Zummo <[email protected]>
	12	*
	13	* TODO
	14	* 850 serialization once the core supports it
	15	* Investigate no_dsc on 850R
	16	* Clock detect
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
	22	#include <linux/init.h>
	23	#include <linux/blkdev.h>
	24	#include <linux/delay.h>
	25	#include <linux/device.h>
	26	#include <scsi/scsi_host.h>
	27	#include <linux/libata.h>
	28	#include <linux/ata.h>
	29
	30	#define DRV_NAME "pata_artop"
8bc3fc47	31	#define DRV_VERSION "0.4.3"
669a5db4 JG	32
	33	/*
	34	* The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
	35	* get PCI bus speed functionality we leave this as 0. Its a variable
	36	* for when we get the functionality and also for folks wanting to
	37	* test stuff.
	38	*/
	39
	40	static int clock = 0;
	41
d4b2bab4	42	static int artop6210_pre_reset(struct ata_port *ap, unsigned long deadline)
669a5db4 JG	43	{
	44	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	45	const struct pci_bits artop_enable_bits[] = {
	46	{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
	47	{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
	48	};
	49
c961922b AC	50	if (!pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
c961922b AC	51	return -ENOENT;
d4b2bab4 TH	52
d4b2bab4 TH	53	return ata_std_prereset(ap, deadline);
669a5db4 JG	54	}
	55
	56	/**
	57	* artop6210_error_handler - Probe specified port on PATA host controller
	58	* @ap: Port to probe
	59	*
	60	* LOCKING:
	61	* None (inherited from caller).
	62	*/
	63
	64	static void artop6210_error_handler(struct ata_port *ap)
	65	{
	66	ata_bmdma_drive_eh(ap, artop6210_pre_reset,
	67	ata_std_softreset, NULL,
	68	ata_std_postreset);
	69	}
	70
	71	/**
	72	* artop6260_pre_reset - check for 40/80 pin
	73	* @ap: Port
d4b2bab4	74	* @deadline: deadline jiffies for the operation
669a5db4 JG	75	*
	76	* The ARTOP hardware reports the cable detect bits in register 0x49.
	77	* Nothing complicated needed here.
	78	*/
	79
d4b2bab4	80	static int artop6260_pre_reset(struct ata_port *ap, unsigned long deadline)
669a5db4 JG	81	{
	82	static const struct pci_bits artop_enable_bits[] = {
	83	{ 0x4AU, 1U, 0x02UL, 0x02UL }, /* port 0 */
	84	{ 0x4AU, 1U, 0x04UL, 0x04UL }, /* port 1 */
	85	};
	86
	87	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4 JG	88
669a5db4 JG	89	/* Odd numbered device ids are the units with enable bits (the -R cards) */
c961922b AC	90	if (pdev->device % 1 && !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
c961922b AC	91	return -ENOENT;
27c78b37 JG	92
27c78b37 JG	93	return ata_std_prereset(ap, deadline);
a73984a0	94	}
c961922b	95
a73984a0 JG	96	/**
	97	* artop6260_cable_detect - identify cable type
	98	* @ap: Port
	99	*
	100	* Identify the cable type for the ARTOp interface in question
	101	*/
a617c09f	102
a73984a0 JG	103	static int artop6260_cable_detect(struct ata_port *ap)
	104	{
	105	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	106	u8 tmp;
669a5db4	107	pci_read_config_byte(pdev, 0x49, &tmp);
3f9dd27a	108	if (tmp & (1 << ap->port_no))
a73984a0 JG	109	return ATA_CBL_PATA40;
a73984a0 JG	110	return ATA_CBL_PATA80;
669a5db4 JG	111	}
	112
	113	/**
	114	* artop6260_error_handler - Probe specified port on PATA host controller
	115	* @ap: Port to probe
	116	*
	117	* LOCKING:
	118	* None (inherited from caller).
	119	*/
	120
	121	static void artop6260_error_handler(struct ata_port *ap)
	122	{
	123	ata_bmdma_drive_eh(ap, artop6260_pre_reset,
	124	ata_std_softreset, NULL,
	125	ata_std_postreset);
	126	}
	127
	128	/**
	129	* artop6210_load_piomode - Load a set of PATA PIO timings
	130	* @ap: Port whose timings we are configuring
	131	* @adev: Device
	132	* @pio: PIO mode
	133	*
	134	* Set PIO mode for device, in host controller PCI config space. This
	135	* is used both to set PIO timings in PIO mode and also to set the
	136	* matching PIO clocking for UDMA, as well as the MWDMA timings.
	137	*
	138	* LOCKING:
	139	* None (inherited from caller).
	140	*/
	141
	142	static void artop6210_load_piomode(struct ata_port ap, struct ata_device adev, unsigned int pio)
	143	{
	144	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	145	int dn = adev->devno + 2 * ap->port_no;
	146	const u16 timing[2][5] = {
	147	{ 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
	148	{ 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
	149
	150	};
	151	/* Load the PIO timing active/recovery bits */
	152	pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
	153	}
	154
	155	/**
	156	* artop6210_set_piomode - Initialize host controller PATA PIO timings
	157	* @ap: Port whose timings we are configuring
	158	* @adev: Device we are configuring
	159	*
	160	* Set PIO mode for device, in host controller PCI config space. For
	161	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
	162	* the event UDMA is used the later call to set_dmamode will set the
	163	* bits as required.
	164	*
	165	* LOCKING:
	166	* None (inherited from caller).
	167	*/
	168
	169	static void artop6210_set_piomode(struct ata_port ap, struct ata_device adev)
	170	{
	171	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	172	int dn = adev->devno + 2 * ap->port_no;
	173	u8 ultra;
	174
175	artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
176
177	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
178	pci_read_config_byte(pdev, 0x54, &ultra);
179	ultra &= ~(3 << (2 * dn));
180	pci_write_config_byte(pdev, 0x54, ultra);
181	}
182
183	/**
184	* artop6260_load_piomode - Initialize host controller PATA PIO timings
185	* @ap: Port whose timings we are configuring
186	* @adev: Device we are configuring
187	* @pio: PIO mode
188	*
189	* Set PIO mode for device, in host controller PCI config space. The
190	* ARTOP6260 and relatives store the timing data differently.
191	*
192	* LOCKING:
193	* None (inherited from caller).
194	*/
195
196	static void artop6260_load_piomode (struct ata_port ap, struct ata_device adev, unsigned int pio)
197	{
198	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
199	int dn = adev->devno + 2 * ap->port_no;
200	const u8 timing[2][5] = {
201	{ 0x00, 0x0A, 0x08, 0x33, 0x31 },
202	{ 0x70, 0x7A, 0x78, 0x43, 0x41 }
203
204	};
205	/* Load the PIO timing active/recovery bits */
206	pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
207	}
208
209	/**
210	* artop6260_set_piomode - Initialize host controller PATA PIO timings
211	* @ap: Port whose timings we are configuring
212	* @adev: Device we are configuring
213	*
214	* Set PIO mode for device, in host controller PCI config space. For
215	* ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
216	* the event UDMA is used the later call to set_dmamode will set the
217	* bits as required.
218	*
219	* LOCKING:
220	* None (inherited from caller).
221	*/
222
223	static void artop6260_set_piomode(struct ata_port ap, struct ata_device adev)
224	{
225	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
226	u8 ultra;
227
228	artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
229
230	/* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
231	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
232	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
233	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
234	}
235
236	/**
237	* artop6210_set_dmamode - Initialize host controller PATA PIO timings
238	* @ap: Port whose timings we are configuring
a73984a0	239	* @adev: Device whose timings we are configuring
669a5db4 JG	240	*
	241	* Set DMA mode for device, in host controller PCI config space.
	242	*
	243	* LOCKING:
	244	* None (inherited from caller).
	245	*/
	246
	247	static void artop6210_set_dmamode (struct ata_port ap, struct ata_device adev)
	248	{
	249	unsigned int pio;
	250	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	251	int dn = adev->devno + 2 * ap->port_no;
	252	u8 ultra;
	253
	254	if (adev->dma_mode == XFER_MW_DMA_0)
	255	pio = 1;
	256	else
	257	pio = 4;
	258
	259	/* Load the PIO timing active/recovery bits */
	260	artop6210_load_piomode(ap, adev, pio);
	261
	262	pci_read_config_byte(pdev, 0x54, &ultra);
	263	ultra &= ~(3 << (2 * dn));
	264
	265	/* Add ultra DMA bits if in UDMA mode */
	266	if (adev->dma_mode >= XFER_UDMA_0) {
	267	u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
	268	if (mode == 0)
	269	mode = 1;
	270	ultra \|= (mode << (2 * dn));
	271	}
	272	pci_write_config_byte(pdev, 0x54, ultra);
	273	}
	274
	275	/**
	276	* artop6260_set_dmamode - Initialize host controller PATA PIO timings
	277	* @ap: Port whose timings we are configuring
	278	* @adev: Device we are configuring
	279	*
	280	* Set DMA mode for device, in host controller PCI config space. The
	281	* ARTOP6260 and relatives store the timing data differently.
	282	*
	283	* LOCKING:
	284	* None (inherited from caller).
	285	*/
	286
	287	static void artop6260_set_dmamode (struct ata_port ap, struct ata_device adev)
	288	{
	289	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	290	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	291	u8 ultra;
	292
	293	if (adev->dma_mode == XFER_MW_DMA_0)
	294	pio = 1;
	295	else
	296	pio = 4;
	297
	298	/* Load the PIO timing active/recovery bits */
	299	artop6260_load_piomode(ap, adev, pio);
	300
	301	/* Add ultra DMA bits if in UDMA mode */
	302	pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
	303	ultra &= ~(7 << (4 * adev->devno)); /* One nibble per drive */
304	if (adev->dma_mode >= XFER_UDMA_0) {
305	u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
306	if (mode == 0)
307	mode = 1;
308	ultra \|= (mode << (4 * adev->devno));
309	}
310	pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
311	}
312
313	static struct scsi_host_template artop_sht = {
314	.module = THIS_MODULE,
315	.name = DRV_NAME,
316	.ioctl = ata_scsi_ioctl,
317	.queuecommand = ata_scsi_queuecmd,
318	.can_queue = ATA_DEF_QUEUE,
319	.this_id = ATA_SHT_THIS_ID,
320	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	321	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	322	.emulated = ATA_SHT_EMULATED,
	323	.use_clustering = ATA_SHT_USE_CLUSTERING,
	324	.proc_name = DRV_NAME,
	325	.dma_boundary = ATA_DMA_BOUNDARY,
	326	.slave_configure = ata_scsi_slave_config,
afdfe899	327	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	328	.bios_param = ata_std_bios_param,
	329	};
	330
	331	static const struct ata_port_operations artop6210_ops = {
	332	.port_disable = ata_port_disable,
	333	.set_piomode = artop6210_set_piomode,
	334	.set_dmamode = artop6210_set_dmamode,
	335	.mode_filter = ata_pci_default_filter,
	336
	337	.tf_load = ata_tf_load,
	338	.tf_read = ata_tf_read,
	339	.check_status = ata_check_status,
	340	.exec_command = ata_exec_command,
	341	.dev_select = ata_std_dev_select,
	342
	343	.freeze = ata_bmdma_freeze,
	344	.thaw = ata_bmdma_thaw,
	345	.error_handler = artop6210_error_handler,
	346	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	347	.cable_detect = ata_cable_40wire,
669a5db4 JG	348
	349	.bmdma_setup = ata_bmdma_setup,
	350	.bmdma_start = ata_bmdma_start,
	351	.bmdma_stop = ata_bmdma_stop,
	352	.bmdma_status = ata_bmdma_status,
	353	.qc_prep = ata_qc_prep,
	354	.qc_issue = ata_qc_issue_prot,
bda30288	355
0d5ff566	356	.data_xfer = ata_data_xfer,
669a5db4 JG	357
	358	.irq_handler = ata_interrupt,
	359	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	360	.irq_on = ata_irq_on,
246ce3b6 AI	361	.irq_ack = ata_irq_ack,
669a5db4 JG	362
669a5db4 JG	363	.port_start = ata_port_start,
669a5db4 JG	364	};
	365
	366	static const struct ata_port_operations artop6260_ops = {
	367	.port_disable = ata_port_disable,
	368	.set_piomode = artop6260_set_piomode,
	369	.set_dmamode = artop6260_set_dmamode,
	370
	371	.tf_load = ata_tf_load,
	372	.tf_read = ata_tf_read,
	373	.check_status = ata_check_status,
	374	.exec_command = ata_exec_command,
	375	.dev_select = ata_std_dev_select,
	376
	377	.freeze = ata_bmdma_freeze,
	378	.thaw = ata_bmdma_thaw,
	379	.error_handler = artop6260_error_handler,
	380	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	381	.cable_detect = artop6260_cable_detect,
669a5db4 JG	382
	383	.bmdma_setup = ata_bmdma_setup,
	384	.bmdma_start = ata_bmdma_start,
	385	.bmdma_stop = ata_bmdma_stop,
	386	.bmdma_status = ata_bmdma_status,
	387	.qc_prep = ata_qc_prep,
	388	.qc_issue = ata_qc_issue_prot,
0d5ff566	389	.data_xfer = ata_data_xfer,
669a5db4	390
669a5db4 JG	391	.irq_handler = ata_interrupt,
669a5db4 JG	392	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	393	.irq_on = ata_irq_on,
246ce3b6 AI	394	.irq_ack = ata_irq_ack,
669a5db4 JG	395
669a5db4 JG	396	.port_start = ata_port_start,
669a5db4 JG	397	};
	398
	399
	400	/**
	401	* artop_init_one - Register ARTOP ATA PCI device with kernel services
	402	* @pdev: PCI device to register
	403	* @ent: Entry in artop_pci_tbl matching with @pdev
	404	*
	405	* Called from kernel PCI layer.
	406	*
	407	* LOCKING:
	408	* Inherited from PCI layer (may sleep).
	409	*
	410	* RETURNS:
	411	* Zero on success, or -ERRNO value.
	412	*/
	413
	414	static int artop_init_one (struct pci_dev pdev, const struct pci_device_id id)
	415	{
	416	static int printed_version;
1626aeb8	417	static const struct ata_port_info info_6210 = {
669a5db4 JG	418	.sht = &artop_sht,
	419	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	420	.pio_mask = 0x1f, /* pio0-4 */
	421	.mwdma_mask = 0x07, /* mwdma0-2 */
	422	.udma_mask = ATA_UDMA2,
	423	.port_ops = &artop6210_ops,
	424	};
1626aeb8	425	static const struct ata_port_info info_626x = {
669a5db4 JG	426	.sht = &artop_sht,
	427	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	428	.pio_mask = 0x1f, /* pio0-4 */
	429	.mwdma_mask = 0x07, /* mwdma0-2 */
	430	.udma_mask = ATA_UDMA4,
	431	.port_ops = &artop6260_ops,
	432	};
1626aeb8	433	static const struct ata_port_info info_626x_fast = {
669a5db4 JG	434	.sht = &artop_sht,
	435	.flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST,
	436	.pio_mask = 0x1f, /* pio0-4 */
	437	.mwdma_mask = 0x07, /* mwdma0-2 */
	438	.udma_mask = ATA_UDMA5,
	439	.port_ops = &artop6260_ops,
	440	};
1626aeb8	441	const struct ata_port_info *ppi[] = { NULL, NULL };
669a5db4 JG	442
	443	if (!printed_version++)
	444	dev_printk(KERN_DEBUG, &pdev->dev,
	445	"version " DRV_VERSION "\n");
	446
	447	if (id->driver_data == 0) { /* 6210 variant */
1626aeb8 TH	448	ppi[0] = &info_6210;
1626aeb8 TH	449	ppi[1] = &ata_dummy_port_info;
669a5db4 JG	450	/* BIOS may have left us in UDMA, clear it before libata probe */
	451	pci_write_config_byte(pdev, 0x54, 0);
	452	/* For the moment (also lacks dsc) */
	453	printk(KERN_WARNING "ARTOP 6210 requires serialize functionality not yet supported by libata.\n");
	454	printk(KERN_WARNING "Secondary ATA ports will not be activated.\n");
669a5db4 JG	455	}
669a5db4 JG	456	else if (id->driver_data == 1) /* 6260 */
1626aeb8	457	ppi[0] = &info_626x;
669a5db4 JG	458	else if (id->driver_data == 2) { /* 6260 or 6260 + fast */
	459	unsigned long io = pci_resource_start(pdev, 4);
	460	u8 reg;
	461
1626aeb8	462	ppi[0] = &info_626x;
669a5db4	463	if (inb(io) & 0x10)
1626aeb8	464	ppi[0] = &info_626x_fast;
669a5db4 JG	465	/* Mac systems come up with some registers not set as we
	466	will need them */
	467
	468	/* Clear reset & test bits */
	469	pci_read_config_byte(pdev, 0x49, &reg);
	470	pci_write_config_byte(pdev, 0x49, reg & ~ 0x30);
	471
	472	/* PCI latency must be > 0x80 for burst mode, tweak it
	473	* if required.
	474	*/
	475	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
	476	if (reg <= 0x80)
	477	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
	478
	479	/* Enable IRQ output and burst mode */
	480	pci_read_config_byte(pdev, 0x4a, &reg);
	481	pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) \| 0x80);
	482
	483	}
15a7c3bb	484
1626aeb8	485	BUG_ON(ppi[0] == NULL);
15a7c3bb	486
1626aeb8	487	return ata_pci_init_one(pdev, ppi);
669a5db4 JG	488	}
	489
	490	static const struct pci_device_id artop_pci_tbl[] = {
2d2744fc JG	491	{ PCI_VDEVICE(ARTOP, 0x0005), 0 },
	492	{ PCI_VDEVICE(ARTOP, 0x0006), 1 },
	493	{ PCI_VDEVICE(ARTOP, 0x0007), 1 },
	494	{ PCI_VDEVICE(ARTOP, 0x0008), 2 },
	495	{ PCI_VDEVICE(ARTOP, 0x0009), 2 },
	496
669a5db4 JG	497	{ } /* terminate list */
	498	};
	499
	500	static struct pci_driver artop_pci_driver = {
	501	.name = DRV_NAME,
	502	.id_table = artop_pci_tbl,
	503	.probe = artop_init_one,
	504	.remove = ata_pci_remove_one,
	505	};
	506
	507	static int __init artop_init(void)
	508	{
	509	return pci_register_driver(&artop_pci_driver);
	510	}
	511
	512	static void __exit artop_exit(void)
	513	{
	514	pci_unregister_driver(&artop_pci_driver);
	515	}
	516
669a5db4 JG	517	module_init(artop_init);
	518	module_exit(artop_exit);
	519
	520	MODULE_AUTHOR("Alan Cox");
	521	MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
	522	MODULE_LICENSE("GPL");
	523	MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
	524	MODULE_VERSION(DRV_VERSION);
	525