[linux.git] / drivers / pwm / pwm-cros-ec.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Expose a PWM controlled by the ChromeOS EC to the host processor.
 *
 * Copyright (C) 2016 Google, Inc.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_ec_proto.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

#include <dt-bindings/mfd/cros_ec.h>

/**
 * struct cros_ec_pwm_device - Driver data for EC PWM
 *
 * @dev: Device node
 * @ec: Pointer to EC device
 * @chip: PWM controller chip
 * @use_pwm_type: Use PWM types instead of generic channels
 * @channel: array with per-channel data
 */
struct cros_ec_pwm_device {
	struct device *dev;
	struct cros_ec_device *ec;
	struct pwm_chip chip;
	bool use_pwm_type;
	struct cros_ec_pwm *channel;
};

/**
 * struct cros_ec_pwm - per-PWM driver data
 * @duty_cycle: cached duty cycle
 */
struct cros_ec_pwm {
	u16 duty_cycle;
};

static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct cros_ec_pwm_device, chip);
}

static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type)
{
	switch (dt_index) {
	case CROS_EC_PWM_DT_KB_LIGHT:
		*pwm_type = EC_PWM_TYPE_KB_LIGHT;
		return 0;
	case CROS_EC_PWM_DT_DISPLAY_LIGHT:
		*pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
		return 0;
	default:
		return -EINVAL;
	}
}

static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index,
				u16 duty)
{
	struct cros_ec_device *ec = ec_pwm->ec;
	struct {
		struct cros_ec_command msg;
		struct ec_params_pwm_set_duty params;
	} __packed buf;
	struct ec_params_pwm_set_duty *params = &buf.params;
	struct cros_ec_command *msg = &buf.msg;
	int ret;

	memset(&buf, 0, sizeof(buf));

	msg->version = 0;
	msg->command = EC_CMD_PWM_SET_DUTY;
	msg->insize = 0;
	msg->outsize = sizeof(*params);

	params->duty = duty;

	if (ec_pwm->use_pwm_type) {
		ret = cros_ec_dt_type_to_pwm_type(index, &params->pwm_type);
		if (ret) {
			dev_err(ec->dev, "Invalid PWM type index: %d\n", index);
			return ret;
		}
		params->index = 0;
	} else {
		params->pwm_type = EC_PWM_TYPE_GENERIC;
		params->index = index;
	}

	return cros_ec_cmd_xfer_status(ec, msg);
}

static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 index)
{
	struct cros_ec_device *ec = ec_pwm->ec;
	struct {
		struct cros_ec_command msg;
		union {
			struct ec_params_pwm_get_duty params;
			struct ec_response_pwm_get_duty resp;
		};
	} __packed buf;
	struct ec_params_pwm_get_duty *params = &buf.params;
	struct ec_response_pwm_get_duty *resp = &buf.resp;
	struct cros_ec_command *msg = &buf.msg;
	int ret;

	memset(&buf, 0, sizeof(buf));

	msg->version = 0;
	msg->command = EC_CMD_PWM_GET_DUTY;
	msg->insize = sizeof(*resp);
	msg->outsize = sizeof(*params);

	if (ec_pwm->use_pwm_type) {
		ret = cros_ec_dt_type_to_pwm_type(index, &params->pwm_type);
		if (ret) {
			dev_err(ec->dev, "Invalid PWM type index: %d\n", index);
			return ret;
		}
		params->index = 0;
	} else {
		params->pwm_type = EC_PWM_TYPE_GENERIC;
		params->index = index;
	}

	ret = cros_ec_cmd_xfer_status(ec, msg);
	if (ret < 0)
		return ret;

	return resp->duty;
}

static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			     const struct pwm_state *state)
{
	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
	struct cros_ec_pwm *channel = &ec_pwm->channel[pwm->hwpwm];
	u16 duty_cycle;
	int ret;

	/* The EC won't let us change the period */
	if (state->period != EC_PWM_MAX_DUTY)
		return -EINVAL;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	/*
	 * EC doesn't separate the concept of duty cycle and enabled, but
	 * kernel does. Translate.
	 */
	duty_cycle = state->enabled ? state->duty_cycle : 0;

	ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle);
	if (ret < 0)
		return ret;

	channel->duty_cycle = state->duty_cycle;

	return 0;
}

static int cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				 struct pwm_state *state)
{
	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
	struct cros_ec_pwm *channel = &ec_pwm->channel[pwm->hwpwm];
	int ret;

	ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm);
	if (ret < 0) {
		dev_err(chip->dev, "error getting initial duty: %d\n", ret);
		return ret;
	}

	state->enabled = (ret > 0);
	state->period = EC_PWM_MAX_DUTY;
	state->polarity = PWM_POLARITY_NORMAL;

	/*
	 * Note that "disabled" and "duty cycle == 0" are treated the same. If
	 * the cached duty cycle is not zero, used the cached duty cycle. This
	 * ensures that the configured duty cycle is kept across a disable and
	 * enable operation and avoids potentially confusing consumers.
	 *
	 * For the case of the initial hardware readout, channel->duty_cycle
	 * will be 0 and the actual duty cycle read from the EC is used.
	 */
	if (ret == 0 && channel->duty_cycle > 0)
		state->duty_cycle = channel->duty_cycle;
	else
		state->duty_cycle = ret;

	return 0;
}

static struct pwm_device *
cros_ec_pwm_xlate(struct pwm_chip *chip, const struct of_phandle_args *args)
{
	struct pwm_device *pwm;

	if (args->args[0] >= chip->npwm)
		return ERR_PTR(-EINVAL);

	pwm = pwm_request_from_chip(chip, args->args[0], NULL);
	if (IS_ERR(pwm))
		return pwm;

	/* The EC won't let us change the period */
	pwm->args.period = EC_PWM_MAX_DUTY;

	return pwm;
}

static const struct pwm_ops cros_ec_pwm_ops = {
	.get_state	= cros_ec_pwm_get_state,
	.apply		= cros_ec_pwm_apply,
};

/*
 * Determine the number of supported PWMs. The EC does not return the number
 * of PWMs it supports directly, so we have to read the pwm duty cycle for
 * subsequent channels until we get an error.
 */
static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm)
{
	int i, ret;

	/* The index field is only 8 bits */
	for (i = 0; i <= U8_MAX; i++) {
		ret = cros_ec_pwm_get_duty(ec_pwm, i);
		/*
		 * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
		 * responses; everything else is treated as an error.
		 * The EC error codes map to -EOPNOTSUPP and -EINVAL,
		 * so check for those.
		 */
		switch (ret) {
		case -EOPNOTSUPP:	/* invalid command */
			return -ENODEV;
		case -EINVAL:		/* invalid parameter */
			return i;
		default:
			if (ret < 0)
				return ret;
			break;
		}
	}

	return U8_MAX;
}

static int cros_ec_pwm_probe(struct platform_device *pdev)
{
	struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct cros_ec_pwm_device *ec_pwm;
	struct pwm_chip *chip;
	int ret;

	if (!ec)
		return dev_err_probe(dev, -EINVAL, "no parent EC device\n");

	ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
	if (!ec_pwm)
		return -ENOMEM;
	chip = &ec_pwm->chip;
	ec_pwm->ec = ec;

	if (of_device_is_compatible(np, "google,cros-ec-pwm-type"))
		ec_pwm->use_pwm_type = true;

	/* PWM chip */
	chip->dev = dev;
	chip->ops = &cros_ec_pwm_ops;
	chip->of_xlate = cros_ec_pwm_xlate;
	chip->of_pwm_n_cells = 1;

	if (ec_pwm->use_pwm_type) {
		chip->npwm = CROS_EC_PWM_DT_COUNT;
	} else {
		ret = cros_ec_num_pwms(ec_pwm);
		if (ret < 0)
			return dev_err_probe(dev, ret, "Couldn't find PWMs\n");
		chip->npwm = ret;
	}

	ec_pwm->channel = devm_kcalloc(dev, chip->npwm, sizeof(*ec_pwm->channel),
					GFP_KERNEL);
	if (!ec_pwm->channel)
		return -ENOMEM;

	dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);

	ret = devm_pwmchip_add(dev, chip);
	if (ret < 0)
		return dev_err_probe(dev, ret, "cannot register PWM\n");

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id cros_ec_pwm_of_match[] = {
	{ .compatible = "google,cros-ec-pwm" },
	{ .compatible = "google,cros-ec-pwm-type" },
	{},
};
MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
#endif

static struct platform_driver cros_ec_pwm_driver = {
	.probe = cros_ec_pwm_probe,
	.driver = {
		.name = "cros-ec-pwm",
		.of_match_table = of_match_ptr(cros_ec_pwm_of_match),
	},
};
module_platform_driver(cros_ec_pwm_driver);

MODULE_ALIAS("platform:cros-ec-pwm");
MODULE_DESCRIPTION("ChromeOS EC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4964cb52	1	// SPDX-License-Identifier: GPL-2.0
1f0d3bb0	2	/*
1f0d3bb0	3	* Expose a PWM controlled by the ChromeOS EC to the host processor.
4964cb52 EBS	4	*
4964cb52 EBS	5	* Copyright (C) 2016 Google, Inc.
1f0d3bb0 BN	6	*/
	7
	8	#include <linux/module.h>
0a41b0c5	9	#include <linux/of.h>
840d9f13 EBS	10	#include <linux/platform_data/cros_ec_commands.h>
840d9f13 EBS	11	#include <linux/platform_data/cros_ec_proto.h>
1f0d3bb0 BN	12	#include <linux/platform_device.h>
	13	#include <linux/pwm.h>
	14	#include <linux/slab.h>
	15
3d593b6e FB	16	#include <dt-bindings/mfd/cros_ec.h>
3d593b6e FB	17
1f0d3bb0 BN	18	/**
	19	* struct cros_ec_pwm_device - Driver data for EC PWM
	20	*
	21	* @dev: Device node
	22	* @ec: Pointer to EC device
	23	* @chip: PWM controller chip
3d593b6e	24	* @use_pwm_type: Use PWM types instead of generic channels
82adc1b2	25	* @channel: array with per-channel data
1f0d3bb0 BN	26	*/
	27	struct cros_ec_pwm_device {
	28	struct device *dev;
	29	struct cros_ec_device *ec;
	30	struct pwm_chip chip;
3d593b6e	31	bool use_pwm_type;
82adc1b2	32	struct cros_ec_pwm *channel;
1f0d3bb0 BN	33	};
1f0d3bb0 BN	34
1db37f95 TR	35	/**
	36	* struct cros_ec_pwm - per-PWM driver data
	37	* @duty_cycle: cached duty cycle
	38	*/
	39	struct cros_ec_pwm {
	40	u16 duty_cycle;
	41	};
	42
5996cdf1	43	static inline struct cros_ec_pwm_device pwm_to_cros_ec_pwm(struct pwm_chip chip)
1f0d3bb0	44	{
5996cdf1	45	return container_of(chip, struct cros_ec_pwm_device, chip);
1f0d3bb0 BN	46	}
1f0d3bb0 BN	47
3d593b6e	48	static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type)
1f0d3bb0	49	{
3d593b6e FB	50	switch (dt_index) {
	51	case CROS_EC_PWM_DT_KB_LIGHT:
	52	*pwm_type = EC_PWM_TYPE_KB_LIGHT;
	53	return 0;
	54	case CROS_EC_PWM_DT_DISPLAY_LIGHT:
	55	*pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
	56	return 0;
	57	default:
	58	return -EINVAL;
	59	}
	60	}
	61
	62	static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index,
	63	u16 duty)
	64	{
	65	struct cros_ec_device *ec = ec_pwm->ec;
1f0d3bb0 BN	66	struct {
	67	struct cros_ec_command msg;
	68	struct ec_params_pwm_set_duty params;
065cfbbb	69	} __packed buf;
1f0d3bb0 BN	70	struct ec_params_pwm_set_duty *params = &buf.params;
1f0d3bb0 BN	71	struct cros_ec_command *msg = &buf.msg;
3d593b6e	72	int ret;
1f0d3bb0 BN	73
	74	memset(&buf, 0, sizeof(buf));
	75
	76	msg->version = 0;
	77	msg->command = EC_CMD_PWM_SET_DUTY;
	78	msg->insize = 0;
	79	msg->outsize = sizeof(*params);
	80
	81	params->duty = duty;
3d593b6e FB	82
	83	if (ec_pwm->use_pwm_type) {
	84	ret = cros_ec_dt_type_to_pwm_type(index, &params->pwm_type);
	85	if (ret) {
	86	dev_err(ec->dev, "Invalid PWM type index: %d\n", index);
	87	return ret;
	88	}
	89	params->index = 0;
	90	} else {
	91	params->pwm_type = EC_PWM_TYPE_GENERIC;
	92	params->index = index;
	93	}
1f0d3bb0 BN	94
	95	return cros_ec_cmd_xfer_status(ec, msg);
	96	}
	97
3d593b6e	98	static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 index)
1f0d3bb0	99	{
3d593b6e	100	struct cros_ec_device *ec = ec_pwm->ec;
1f0d3bb0 BN	101	struct {
	102	struct cros_ec_command msg;
	103	union {
	104	struct ec_params_pwm_get_duty params;
	105	struct ec_response_pwm_get_duty resp;
	106	};
065cfbbb	107	} __packed buf;
1f0d3bb0 BN	108	struct ec_params_pwm_get_duty *params = &buf.params;
	109	struct ec_response_pwm_get_duty *resp = &buf.resp;
	110	struct cros_ec_command *msg = &buf.msg;
	111	int ret;
	112
	113	memset(&buf, 0, sizeof(buf));
	114
	115	msg->version = 0;
	116	msg->command = EC_CMD_PWM_GET_DUTY;
e47866a1 NV	117	msg->insize = sizeof(*resp);
e47866a1 NV	118	msg->outsize = sizeof(*params);
1f0d3bb0	119
3d593b6e FB	120	if (ec_pwm->use_pwm_type) {
	121	ret = cros_ec_dt_type_to_pwm_type(index, &params->pwm_type);
	122	if (ret) {
	123	dev_err(ec->dev, "Invalid PWM type index: %d\n", index);
	124	return ret;
	125	}
	126	params->index = 0;
	127	} else {
	128	params->pwm_type = EC_PWM_TYPE_GENERIC;
	129	params->index = index;
	130	}
1f0d3bb0 BN	131
1f0d3bb0 BN	132	ret = cros_ec_cmd_xfer_status(ec, msg);
1f0d3bb0 BN	133	if (ret < 0)
	134	return ret;
	135
	136	return resp->duty;
	137	}
	138
1f0d3bb0	139	static int cros_ec_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	140	const struct pwm_state *state)
1f0d3bb0 BN	141	{
1f0d3bb0 BN	142	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
82adc1b2	143	struct cros_ec_pwm *channel = &ec_pwm->channel[pwm->hwpwm];
1db37f95 TR	144	u16 duty_cycle;
1db37f95 TR	145	int ret;
1f0d3bb0 BN	146
	147	/* The EC won't let us change the period */
	148	if (state->period != EC_PWM_MAX_DUTY)
	149	return -EINVAL;
	150
9f0f6107 UKK	151	if (state->polarity != PWM_POLARITY_NORMAL)
	152	return -EINVAL;
	153
1f0d3bb0 BN	154	/*
	155	* EC doesn't separate the concept of duty cycle and enabled, but
	156	* kernel does. Translate.
	157	*/
	158	duty_cycle = state->enabled ? state->duty_cycle : 0;
	159
3d593b6e	160	ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle);
1db37f95 TR	161	if (ret < 0)
	162	return ret;
	163
	164	channel->duty_cycle = state->duty_cycle;
	165
	166	return 0;
1f0d3bb0 BN	167	}
1f0d3bb0 BN	168
6c452cff UKK	169	static int cros_ec_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
6c452cff UKK	170	struct pwm_state *state)
1f0d3bb0 BN	171	{
1f0d3bb0 BN	172	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
82adc1b2	173	struct cros_ec_pwm *channel = &ec_pwm->channel[pwm->hwpwm];
1f0d3bb0 BN	174	int ret;
1f0d3bb0 BN	175
3d593b6e	176	ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm);
1f0d3bb0 BN	177	if (ret < 0) {
1f0d3bb0 BN	178	dev_err(chip->dev, "error getting initial duty: %d\n", ret);
ee02c1cb	179	return ret;
1f0d3bb0 BN	180	}
	181
	182	state->enabled = (ret > 0);
	183	state->period = EC_PWM_MAX_DUTY;
30006b77	184	state->polarity = PWM_POLARITY_NORMAL;
1f0d3bb0	185
1db37f95 TR	186	/*
	187	* Note that "disabled" and "duty cycle == 0" are treated the same. If
	188	* the cached duty cycle is not zero, used the cached duty cycle. This
	189	* ensures that the configured duty cycle is kept across a disable and
	190	* enable operation and avoids potentially confusing consumers.
	191	*
	192	* For the case of the initial hardware readout, channel->duty_cycle
	193	* will be 0 and the actual duty cycle read from the EC is used.
	194	*/
	195	if (ret == 0 && channel->duty_cycle > 0)
	196	state->duty_cycle = channel->duty_cycle;
	197	else
	198	state->duty_cycle = ret;
6c452cff UKK	199
6c452cff UKK	200	return 0;
1f0d3bb0 BN	201	}
	202
	203	static struct pwm_device *
5996cdf1	204	cros_ec_pwm_xlate(struct pwm_chip chip, const struct of_phandle_args args)
1f0d3bb0 BN	205	{
	206	struct pwm_device *pwm;
	207
5996cdf1	208	if (args->args[0] >= chip->npwm)
1f0d3bb0 BN	209	return ERR_PTR(-EINVAL);
1f0d3bb0 BN	210
5996cdf1	211	pwm = pwm_request_from_chip(chip, args->args[0], NULL);
1f0d3bb0 BN	212	if (IS_ERR(pwm))
	213	return pwm;
	214
	215	/* The EC won't let us change the period */
	216	pwm->args.period = EC_PWM_MAX_DUTY;
	217
	218	return pwm;
	219	}
	220
	221	static const struct pwm_ops cros_ec_pwm_ops = {
	222	.get_state = cros_ec_pwm_get_state,
	223	.apply = cros_ec_pwm_apply,
1f0d3bb0 BN	224	};
1f0d3bb0 BN	225
d509f8a7 GR	226	/*
	227	* Determine the number of supported PWMs. The EC does not return the number
	228	* of PWMs it supports directly, so we have to read the pwm duty cycle for
	229	* subsequent channels until we get an error.
	230	*/
3d593b6e	231	static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm)
1f0d3bb0 BN	232	{
	233	int i, ret;
	234
	235	/* The index field is only 8 bits */
	236	for (i = 0; i <= U8_MAX; i++) {
3d593b6e	237	ret = cros_ec_pwm_get_duty(ec_pwm, i);
1f0d3bb0 BN	238	/*
	239	* We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
	240	* responses; everything else is treated as an error.
be020f0d GR	241	* The EC error codes map to -EOPNOTSUPP and -EINVAL,
be020f0d GR	242	* so check for those.
1f0d3bb0	243	*/
d509f8a7 GR	244	switch (ret) {
d509f8a7 GR	245	case -EOPNOTSUPP: /* invalid command */
1f0d3bb0	246	return -ENODEV;
d509f8a7	247	case -EINVAL: /* invalid parameter */
1f0d3bb0	248	return i;
d509f8a7 GR	249	default:
	250	if (ret < 0)
	251	return ret;
	252	break;
	253	}
1f0d3bb0 BN	254	}
	255
	256	return U8_MAX;
	257	}
	258
	259	static int cros_ec_pwm_probe(struct platform_device *pdev)
	260	{
	261	struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
	262	struct device *dev = &pdev->dev;
3d593b6e	263	struct device_node *np = pdev->dev.of_node;
1f0d3bb0 BN	264	struct cros_ec_pwm_device *ec_pwm;
	265	struct pwm_chip *chip;
	266	int ret;
	267
896c4509 UKK	268	if (!ec)
896c4509 UKK	269	return dev_err_probe(dev, -EINVAL, "no parent EC device\n");
1f0d3bb0 BN	270
	271	ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
	272	if (!ec_pwm)
	273	return -ENOMEM;
	274	chip = &ec_pwm->chip;
	275	ec_pwm->ec = ec;
	276
3d593b6e FB	277	if (of_device_is_compatible(np, "google,cros-ec-pwm-type"))
	278	ec_pwm->use_pwm_type = true;
	279
1f0d3bb0 BN	280	/* PWM chip */
	281	chip->dev = dev;
	282	chip->ops = &cros_ec_pwm_ops;
	283	chip->of_xlate = cros_ec_pwm_xlate;
	284	chip->of_pwm_n_cells = 1;
3d593b6e FB	285
	286	if (ec_pwm->use_pwm_type) {
	287	chip->npwm = CROS_EC_PWM_DT_COUNT;
	288	} else {
	289	ret = cros_ec_num_pwms(ec_pwm);
896c4509 UKK	290	if (ret < 0)
896c4509 UKK	291	return dev_err_probe(dev, ret, "Couldn't find PWMs\n");
3d593b6e	292	chip->npwm = ret;
1f0d3bb0	293	}
3d593b6e	294
82adc1b2 UKK	295	ec_pwm->channel = devm_kcalloc(dev, chip->npwm, sizeof(*ec_pwm->channel),
	296	GFP_KERNEL);
	297	if (!ec_pwm->channel)
	298	return -ENOMEM;
	299
1f0d3bb0 BN	300	dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);
1f0d3bb0 BN	301
896c4509 UKK	302	ret = devm_pwmchip_add(dev, chip);
	303	if (ret < 0)
	304	return dev_err_probe(dev, ret, "cannot register PWM\n");
1f0d3bb0	305
896c4509	306	return 0;
1f0d3bb0 BN	307	}
	308
	309	#ifdef CONFIG_OF
	310	static const struct of_device_id cros_ec_pwm_of_match[] = {
	311	{ .compatible = "google,cros-ec-pwm" },
3d593b6e	312	{ .compatible = "google,cros-ec-pwm-type" },
1f0d3bb0 BN	313	{},
	314	};
	315	MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
	316	#endif
	317
	318	static struct platform_driver cros_ec_pwm_driver = {
	319	.probe = cros_ec_pwm_probe,
1f0d3bb0 BN	320	.driver = {
	321	.name = "cros-ec-pwm",
	322	.of_match_table = of_match_ptr(cros_ec_pwm_of_match),
	323	},
	324	};
	325	module_platform_driver(cros_ec_pwm_driver);
	326
	327	MODULE_ALIAS("platform:cros-ec-pwm");
	328	MODULE_DESCRIPTION("ChromeOS EC PWM driver");
	329	MODULE_LICENSE("GPL v2");