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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <[email protected]>
5 * Please ALWAYS copy [email protected]
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4 54enum {
318893e1
AR		 55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_STANDARD = 5,
441577ef
TH		 57};
58
59enum board_ids {
60 /* board IDs by feature in alphabetical order */
61 board_ahci,
62 board_ahci_ign_iferr,
63 board_ahci_nosntf,
5f173107 64 board_ahci_yes_fbs,
1da177e4 65
441577ef
TH		 66 /* board IDs for specific chipsets in alphabetical order */
67 board_ahci_mcp65,
83f2b963
TH		 68 board_ahci_mcp77,
69 board_ahci_mcp89,
441577ef
TH		 70 board_ahci_mv,
71 board_ahci_sb600,
72 board_ahci_sb700, /* for SB700 and SB800 */
73 board_ahci_vt8251,
74
75 /* aliases */
76 board_ahci_mcp_linux = board_ahci_mcp65,
77 board_ahci_mcp67 = board_ahci_mcp65,
78 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 79 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 80};
81
2dcb407e 82static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
438ac6d5 87#ifdef CONFIG_PM
c1332875
TH		 88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 90#endif
ad616ffb 91
fad16e7a
TH		 92static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94};
95
029cfd6b
TH		 96static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
a1efdaba 98 .hardreset = ahci_vt8251_hardreset,
029cfd6b 99};
edc93052 100
029cfd6b
TH		 101static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
a1efdaba 103 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 104};
105
98ac62de 106static const struct ata_port_info ahci_port_info[] = {
441577ef 107 /* by features */
facb8fa6 108 [board_ahci] = {
1188c0d8 109 .flags = AHCI_FLAG_COMMON,
14bdef98 110 .pio_mask = ATA_PIO4,
469248ab 111 .udma_mask = ATA_UDMA6,
1da177e4
LT		 112 .port_ops = &ahci_ops,
113 },
facb8fa6 114 [board_ahci_ign_iferr] = {
441577ef 115 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 116 .flags = AHCI_FLAG_COMMON,
14bdef98 117 .pio_mask = ATA_PIO4,
469248ab 118 .udma_mask = ATA_UDMA6,
441577ef 119 .port_ops = &ahci_ops,
bf2af2a2 120 },
facb8fa6 121 [board_ahci_nosntf] = {
441577ef 122 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 123 .flags = AHCI_FLAG_COMMON,
14bdef98 124 .pio_mask = ATA_PIO4,
469248ab 125 .udma_mask = ATA_UDMA6,
41669553
TH		 126 .port_ops = &ahci_ops,
127 },
facb8fa6 128 [board_ahci_yes_fbs] = {
5f173107
TH		 129 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
130 .flags = AHCI_FLAG_COMMON,
131 .pio_mask = ATA_PIO4,
132 .udma_mask = ATA_UDMA6,
133 .port_ops = &ahci_ops,
134 },
441577ef 135 /* by chipsets */
facb8fa6 136 [board_ahci_mcp65] = {
83f2b963
TH		 137 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
138 AHCI_HFLAG_YES_NCQ),
ae01b249 139 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
83f2b963
TH		 140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
facb8fa6 144 [board_ahci_mcp77] = {
83f2b963
TH		 145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
facb8fa6 151 [board_ahci_mcp89] = {
83f2b963 152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 153 .flags = AHCI_FLAG_COMMON,
14bdef98 154 .pio_mask = ATA_PIO4,
469248ab 155 .udma_mask = ATA_UDMA6,
441577ef 156 .port_ops = &ahci_ops,
55a61604 157 },
facb8fa6 158 [board_ahci_mv] = {
417a1a6d 159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 160 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
9cbe056f 161 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
14bdef98 162 .pio_mask = ATA_PIO4,
cd70c266
JG		 163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
facb8fa6 166 [board_ahci_sb600] = {
441577ef
TH		 167 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
168 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
169 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 170 .flags = AHCI_FLAG_COMMON,
14bdef98 171 .pio_mask = ATA_PIO4,
e39fc8c9 172 .udma_mask = ATA_UDMA6,
345347c5 173 .port_ops = &ahci_pmp_retry_srst_ops,
e39fc8c9 174 },
facb8fa6 175 [board_ahci_sb700] = { /* for SB700 and SB800 */
441577ef 176 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 177 .flags = AHCI_FLAG_COMMON,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
345347c5 180 .port_ops = &ahci_pmp_retry_srst_ops,
aa431dd3 181 },
facb8fa6 182 [board_ahci_vt8251] = {
441577ef 183 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 184 .flags = AHCI_FLAG_COMMON,
185 .pio_mask = ATA_PIO4,
186 .udma_mask = ATA_UDMA6,
441577ef 187 .port_ops = &ahci_vt8251_ops,
1b677afd 188 },
1da177e4
LT		 189};
190
3b7d697d 191static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 192 /* Intel */
54bb3a94
JG		 193 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
194 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
195 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
196 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
197 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 198 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 199 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
200 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 203 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 204 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 205 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
207 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
209 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
214 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 220 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
221 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 222 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 223 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 224 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 225 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
226 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 227 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 228 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 229 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 230 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 231 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 232 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 233 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
234 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
236 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
992b3fb9
SH		 239 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
240 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
241 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
64a3903d 242 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
a4a461a6 243 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
181e3cea
SH		 244 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
245 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
247 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
2cab7a4c 250 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
ea4ace66
SH		 251 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
252 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
254 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
77b12bc9
JR		 259 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
260 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
262 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
fe7fa31a 267
e34bb370
TH		 268 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
269 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
270 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
1fefb8fd
BH		 271 /* JMicron 362B and 362C have an AHCI function with IDE class code */
272 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
273 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
fe7fa31a
JG		 274
275 /* ATI */
c65ec1c2 276 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 277 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
279 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
280 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 283
e2dd90b1 284 /* AMD */
5deab536 285 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 286 /* AMD is using RAID class only for ahci controllers */
287 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
288 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
289
fe7fa31a 290 /* VIA */
54bb3a94 291 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 292 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 293
294 /* NVIDIA */
e297d99e
TH		 295 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 303 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 379
95916edd 380 /* SiS */
20e2de4a
TH		 381 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
382 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
383 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 384
318893e1
AR		 385 /* ST Microelectronics */
386 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
387
cd70c266
JG		 388 /* Marvell */
389 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 390 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107 391 { PCI_DEVICE(0x1b4b, 0x9123),
10aca06c
AH		 392 .class = PCI_CLASS_STORAGE_SATA_AHCI,
393 .class_mask = 0xffffff,
5f173107 394 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
467b41c6
PJ		 395 { PCI_DEVICE(0x1b4b, 0x9125),
396 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
642d8925
MJ		 397 { PCI_DEVICE(0x1b4b, 0x917a),
398 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
17c60c6b
AC		 399 { PCI_DEVICE(0x1b4b, 0x9192),
400 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
50be5e36
TH		 401 { PCI_DEVICE(0x1b4b, 0x91a3),
402 .driver_data = board_ahci_yes_fbs },
cd70c266 403
c77a036b
MN		 404 /* Promise */
405 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
406
c9703765 407 /* Asmedia */
7b4f6eca
AC		 408 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
409 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
410 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
411 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
c9703765 412
415ae2b5
JG		 413 /* Generic, PCI class code for AHCI */
414 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 415 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 416
1da177e4
LT		 417 { } /* terminate list */
418};
419
420
421static struct pci_driver ahci_pci_driver = {
422 .name = DRV_NAME,
423 .id_table = ahci_pci_tbl,
424 .probe = ahci_init_one,
24dc5f33 425 .remove = ata_pci_remove_one,
438ac6d5 426#ifdef CONFIG_PM
c1332875 427 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 428 .resume = ahci_pci_device_resume,
429#endif
430};
1da177e4 431
365cfa1e
AV		 432#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
433static int marvell_enable;
434#else
435static int marvell_enable = 1;
436#endif
437module_param(marvell_enable, int, 0644);
438MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 439
1da177e4 440
365cfa1e
AV		 441static void ahci_pci_save_initial_config(struct pci_dev *pdev,
442 struct ahci_host_priv *hpriv)
443{
444 unsigned int force_port_map = 0;
445 unsigned int mask_port_map = 0;
67846b30 446
365cfa1e
AV		 447 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
448 dev_info(&pdev->dev, "JMB361 has only one port\n");
449 force_port_map = 1;
1da177e4
LT		 450 }
451
365cfa1e
AV		 452 /*
453 * Temporary Marvell 6145 hack: PATA port presence
454 * is asserted through the standard AHCI port
455 * presence register, as bit 4 (counting from 0)
d28f87aa 456 */
365cfa1e
AV		 457 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
458 if (pdev->device == 0x6121)
459 mask_port_map = 0x3;
460 else
461 mask_port_map = 0xf;
462 dev_info(&pdev->dev,
463 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
464 }
1da177e4 465
365cfa1e
AV		 466 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
467 mask_port_map);
1da177e4
LT		 468}
469
365cfa1e 470static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 471{
365cfa1e 472 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 473
365cfa1e 474 ahci_reset_controller(host);
1da177e4 475
365cfa1e
AV		 476 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
477 struct ahci_host_priv *hpriv = host->private_data;
478 u16 tmp16;
d6ef3153 479
365cfa1e
AV		 480 /* configure PCS */
481 pci_read_config_word(pdev, 0x92, &tmp16);
482 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
483 tmp16 |= hpriv->port_map;
484 pci_write_config_word(pdev, 0x92, tmp16);
485 }
d6ef3153
SH		 486 }
487
1da177e4
LT		 488 return 0;
489}
490
365cfa1e 491static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 492{
365cfa1e
AV		 493 struct ahci_host_priv *hpriv = host->private_data;
494 struct pci_dev *pdev = to_pci_dev(host->dev);
495 void __iomem *port_mmio;
78cd52d0 496 u32 tmp;
365cfa1e 497 int mv;
78cd52d0 498
365cfa1e
AV		 499 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
500 if (pdev->device == 0x6121)
501 mv = 2;
502 else
503 mv = 4;
504 port_mmio = __ahci_port_base(host, mv);
78cd52d0 505
365cfa1e 506 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 507
365cfa1e
AV		 508 /* clear port IRQ */
509 tmp = readl(port_mmio + PORT_IRQ_STAT);
510 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
511 if (tmp)
512 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 513 }
514
365cfa1e 515 ahci_init_controller(host);
edc93052
TH		 516}
517
365cfa1e
AV		 518static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
519 unsigned long deadline)
d6ef3153 520{
365cfa1e
AV		 521 struct ata_port *ap = link->ap;
522 bool online;
d6ef3153
SH		 523 int rc;
524
365cfa1e 525 DPRINTK("ENTER\n");
d6ef3153 526
365cfa1e 527 ahci_stop_engine(ap);
d6ef3153 528
365cfa1e
AV		 529 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
530 deadline, &online, NULL);
d6ef3153
SH		 531
532 ahci_start_engine(ap);
d6ef3153 533
365cfa1e 534 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 535
365cfa1e
AV		 536 /* vt8251 doesn't clear BSY on signature FIS reception,
537 * request follow-up softreset.
538 */
539 return online ? -EAGAIN : rc;
7d50b60b
TH		 540}
541
365cfa1e
AV		 542static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
543 unsigned long deadline)
7d50b60b 544{
365cfa1e 545 struct ata_port *ap = link->ap;
1c954a4d 546 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 547 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
548 struct ata_taskfile tf;
549 bool online;
550 int rc;
7d50b60b 551
365cfa1e 552 ahci_stop_engine(ap);
028a2596 553
365cfa1e
AV		 554 /* clear D2H reception area to properly wait for D2H FIS */
555 ata_tf_init(link->device, &tf);
556 tf.command = 0x80;
557 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 558
365cfa1e
AV		 559 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
560 deadline, &online, NULL);
028a2596 561
365cfa1e 562 ahci_start_engine(ap);
c1332875 563
365cfa1e
AV		 564 /* The pseudo configuration device on SIMG4726 attached to
565 * ASUS P5W-DH Deluxe doesn't send signature FIS after
566 * hardreset if no device is attached to the first downstream
567 * port && the pseudo device locks up on SRST w/ PMP==0. To
568 * work around this, wait for !BSY only briefly. If BSY isn't
569 * cleared, perform CLO and proceed to IDENTIFY (achieved by
570 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
571 *
572 * Wait for two seconds. Devices attached to downstream port
573 * which can't process the following IDENTIFY after this will
574 * have to be reset again. For most cases, this should
575 * suffice while making probing snappish enough.
576 */
577 if (online) {
578 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
579 ahci_check_ready);
580 if (rc)
581 ahci_kick_engine(ap);
c1332875 582 }
c1332875
TH		 583 return rc;
584}
585
365cfa1e 586#ifdef CONFIG_PM
c1332875
TH		 587static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
588{
cca3974e 589 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 590 struct ahci_host_priv *hpriv = host->private_data;
d8993349 591 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 592 u32 ctl;
593
9b10ae86
TH		 594 if (mesg.event & PM_EVENT_SUSPEND &&
595 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
a44fec1f
JP		 596 dev_err(&pdev->dev,
597 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 598 return -EIO;
599 }
600
3a2d5b70 601 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 602 /* AHCI spec rev1.1 section 8.3.3:
603 * Software must disable interrupts prior to requesting a
604 * transition of the HBA to D3 state.
605 */
606 ctl = readl(mmio + HOST_CTL);
607 ctl &= ~HOST_IRQ_EN;
608 writel(ctl, mmio + HOST_CTL);
609 readl(mmio + HOST_CTL); /* flush */
610 }
611
612 return ata_pci_device_suspend(pdev, mesg);
613}
614
615static int ahci_pci_device_resume(struct pci_dev *pdev)
616{
cca3974e 617 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 618 int rc;
619
553c4aa6
TH		 620 rc = ata_pci_device_do_resume(pdev);
621 if (rc)
622 return rc;
c1332875
TH		 623
624 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 625 rc = ahci_pci_reset_controller(host);
c1332875
TH		 626 if (rc)
627 return rc;
628
781d6550 629 ahci_pci_init_controller(host);
c1332875
TH		 630 }
631
cca3974e 632 ata_host_resume(host);
c1332875
TH		 633
634 return 0;
635}
438ac6d5 636#endif
c1332875 637
4447d351 638static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 639{
1da177e4 640 int rc;
1da177e4 641
318893e1
AR		 642 /*
643 * If the device fixup already set the dma_mask to some non-standard
644 * value, don't extend it here. This happens on STA2X11, for example.
645 */
646 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
647 return 0;
648
1da177e4 649 if (using_dac &&
6a35528a
YH		 650 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
651 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 652 if (rc) {
284901a9 653 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 654 if (rc) {
a44fec1f
JP		 655 dev_err(&pdev->dev,
656 "64-bit DMA enable failed\n");
1da177e4
LT		 657 return rc;
658 }
659 }
1da177e4 660 } else {
284901a9 661 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 662 if (rc) {
a44fec1f 663 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1da177e4
LT		 664 return rc;
665 }
284901a9 666 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 667 if (rc) {
a44fec1f
JP		 668 dev_err(&pdev->dev,
669 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 670 return rc;
671 }
672 }
1da177e4
LT		 673 return 0;
674}
675
439fcaec
AV		 676static void ahci_pci_print_info(struct ata_host *host)
677{
678 struct pci_dev *pdev = to_pci_dev(host->dev);
679 u16 cc;
680 const char *scc_s;
681
682 pci_read_config_word(pdev, 0x0a, &cc);
683 if (cc == PCI_CLASS_STORAGE_IDE)
684 scc_s = "IDE";
685 else if (cc == PCI_CLASS_STORAGE_SATA)
686 scc_s = "SATA";
687 else if (cc == PCI_CLASS_STORAGE_RAID)
688 scc_s = "RAID";
689 else
690 scc_s = "unknown";
691
692 ahci_print_info(host, scc_s);
693}
694
edc93052
TH		 695/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
696 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
697 * support PMP and the 4726 either directly exports the device
698 * attached to the first downstream port or acts as a hardware storage
699 * controller and emulate a single ATA device (can be RAID 0/1 or some
700 * other configuration).
701 *
702 * When there's no device attached to the first downstream port of the
703 * 4726, "Config Disk" appears, which is a pseudo ATA device to
704 * configure the 4726. However, ATA emulation of the device is very
705 * lame. It doesn't send signature D2H Reg FIS after the initial
706 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
707 *
708 * The following function works around the problem by always using
709 * hardreset on the port and not depending on receiving signature FIS
710 * afterward. If signature FIS isn't received soon, ATA class is
711 * assumed without follow-up softreset.
712 */
713static void ahci_p5wdh_workaround(struct ata_host *host)
714{
715 static struct dmi_system_id sysids[] = {
716 {
717 .ident = "P5W DH Deluxe",
718 .matches = {
719 DMI_MATCH(DMI_SYS_VENDOR,
720 "ASUSTEK COMPUTER INC"),
721 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
722 },
723 },
724 { }
725 };
726 struct pci_dev *pdev = to_pci_dev(host->dev);
727
728 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
729 dmi_check_system(sysids)) {
730 struct ata_port *ap = host->ports[1];
731
a44fec1f
JP		 732 dev_info(&pdev->dev,
733 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
edc93052
TH		 734
735 ap->ops = &ahci_p5wdh_ops;
736 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
737 }
738}
739
2fcad9d2
TH		 740/* only some SB600 ahci controllers can do 64bit DMA */
741static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 742{
743 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 744 /*
745 * The oldest version known to be broken is 0901 and
746 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 747 * Enable 64bit DMA on 1501 and anything newer.
748 *
03d783bf
TH		 749 * Please read bko#9412 for more info.
750 */
58a09b38
SH		 751 {
752 .ident = "ASUS M2A-VM",
753 .matches = {
754 DMI_MATCH(DMI_BOARD_VENDOR,
755 "ASUSTeK Computer INC."),
756 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
757 },
03d783bf 758 .driver_data = "20071026", /* yyyymmdd */
58a09b38 759 },
e65cc194
MN		 760 /*
761 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
762 * support 64bit DMA.
763 *
764 * BIOS versions earlier than 1.5 had the Manufacturer DMI
765 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
766 * This spelling mistake was fixed in BIOS version 1.5, so
767 * 1.5 and later have the Manufacturer as
768 * "MICRO-STAR INTERNATIONAL CO.,LTD".
769 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
770 *
771 * BIOS versions earlier than 1.9 had a Board Product Name
772 * DMI field of "MS-7376". This was changed to be
773 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
774 * match on DMI_BOARD_NAME of "MS-7376".
775 */
776 {
777 .ident = "MSI K9A2 Platinum",
778 .matches = {
779 DMI_MATCH(DMI_BOARD_VENDOR,
780 "MICRO-STAR INTER"),
781 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
782 },
783 },
ff0173c1
MN		 784 /*
785 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
786 * 64bit DMA.
787 *
788 * This board also had the typo mentioned above in the
789 * Manufacturer DMI field (fixed in BIOS version 1.5), so
790 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
791 */
792 {
793 .ident = "MSI K9AGM2",
794 .matches = {
795 DMI_MATCH(DMI_BOARD_VENDOR,
796 "MICRO-STAR INTER"),
797 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
798 },
799 },
3c4aa91f
MN		 800 /*
801 * All BIOS versions for the Asus M3A support 64bit DMA.
802 * (all release versions from 0301 to 1206 were tested)
803 */
804 {
805 .ident = "ASUS M3A",
806 .matches = {
807 DMI_MATCH(DMI_BOARD_VENDOR,
808 "ASUSTeK Computer INC."),
809 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
810 },
811 },
58a09b38
SH		 812 { }
813 };
03d783bf 814 const struct dmi_system_id *match;
2fcad9d2
TH		 815 int year, month, date;
816 char buf[9];
58a09b38 817
03d783bf 818 match = dmi_first_match(sysids);
58a09b38 819 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 820 !match)
58a09b38
SH		 821 return false;
822
e65cc194
MN		 823 if (!match->driver_data)
824 goto enable_64bit;
825
2fcad9d2
TH		 826 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
827 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 828
e65cc194
MN		 829 if (strcmp(buf, match->driver_data) >= 0)
830 goto enable_64bit;
831 else {
a44fec1f
JP		 832 dev_warn(&pdev->dev,
833 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
834 match->ident);
2fcad9d2
TH		 835 return false;
836 }
e65cc194
MN		 837
838enable_64bit:
a44fec1f 839 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
e65cc194 840 return true;
58a09b38
SH		 841}
842
1fd68434
RW		 843static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
844{
845 static const struct dmi_system_id broken_systems[] = {
846 {
847 .ident = "HP Compaq nx6310",
848 .matches = {
849 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
850 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
851 },
852 /* PCI slot number of the controller */
853 .driver_data = (void *)0x1FUL,
854 },
d2f9c061
MR		 855 {
856 .ident = "HP Compaq 6720s",
857 .matches = {
858 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
859 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
860 },
861 /* PCI slot number of the controller */
862 .driver_data = (void *)0x1FUL,
863 },
1fd68434
RW		 864
865 { } /* terminate list */
866 };
867 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
868
869 if (dmi) {
870 unsigned long slot = (unsigned long)dmi->driver_data;
871 /* apply the quirk only to on-board controllers */
872 return slot == PCI_SLOT(pdev->devfn);
873 }
874
875 return false;
876}
877
9b10ae86
TH		 878static bool ahci_broken_suspend(struct pci_dev *pdev)
879{
880 static const struct dmi_system_id sysids[] = {
881 /*
882 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
883 * to the harddisk doesn't become online after
884 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 885 *
886 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
887 *
888 * Use dates instead of versions to match as HP is
889 * apparently recycling both product and version
890 * strings.
891 *
892 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 893 */
894 {
895 .ident = "dv4",
896 .matches = {
897 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
898 DMI_MATCH(DMI_PRODUCT_NAME,
899 "HP Pavilion dv4 Notebook PC"),
900 },
9deb3431 901 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 902 },
903 {
904 .ident = "dv5",
905 .matches = {
906 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
907 DMI_MATCH(DMI_PRODUCT_NAME,
908 "HP Pavilion dv5 Notebook PC"),
909 },
9deb3431 910 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 911 },
912 {
913 .ident = "dv6",
914 .matches = {
915 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
916 DMI_MATCH(DMI_PRODUCT_NAME,
917 "HP Pavilion dv6 Notebook PC"),
918 },
9deb3431 919 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 920 },
921 {
922 .ident = "HDX18",
923 .matches = {
924 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
925 DMI_MATCH(DMI_PRODUCT_NAME,
926 "HP HDX18 Notebook PC"),
927 },
9deb3431 928 .driver_data = "20090430", /* F.23 */
9b10ae86 929 },
cedc9bf9
TH		 930 /*
931 * Acer eMachines G725 has the same problem. BIOS
932 * V1.03 is known to be broken. V3.04 is known to
25985edc 933 * work. Between, there are V1.06, V2.06 and V3.03
cedc9bf9
TH		 934 * that we don't have much idea about. For now,
935 * blacklist anything older than V3.04.
9deb3431
TH		 936 *
937 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 938 */
939 {
940 .ident = "G725",
941 .matches = {
942 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
943 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
944 },
9deb3431 945 .driver_data = "20091216", /* V3.04 */
cedc9bf9 946 },
9b10ae86
TH		 947 { } /* terminate list */
948 };
949 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 950 int year, month, date;
951 char buf[9];
9b10ae86
TH		 952
953 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
954 return false;
955
9deb3431
TH		 956 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
957 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 958
9deb3431 959 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 960}
961
5594639a
TH		 962static bool ahci_broken_online(struct pci_dev *pdev)
963{
964#define ENCODE_BUSDEVFN(bus, slot, func) \
965 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
966 static const struct dmi_system_id sysids[] = {
967 /*
968 * There are several gigabyte boards which use
969 * SIMG5723s configured as hardware RAID. Certain
970 * 5723 firmware revisions shipped there keep the link
971 * online but fail to answer properly to SRST or
972 * IDENTIFY when no device is attached downstream
973 * causing libata to retry quite a few times leading
974 * to excessive detection delay.
975 *
976 * As these firmwares respond to the second reset try
977 * with invalid device signature, considering unknown
978 * sig as offline works around the problem acceptably.
979 */
980 {
981 .ident = "EP45-DQ6",
982 .matches = {
983 DMI_MATCH(DMI_BOARD_VENDOR,
984 "Gigabyte Technology Co., Ltd."),
985 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
986 },
987 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
988 },
989 {
990 .ident = "EP45-DS5",
991 .matches = {
992 DMI_MATCH(DMI_BOARD_VENDOR,
993 "Gigabyte Technology Co., Ltd."),
994 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
995 },
996 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
997 },
998 { } /* terminate list */
999 };
1000#undef ENCODE_BUSDEVFN
1001 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1002 unsigned int val;
1003
1004 if (!dmi)
1005 return false;
1006
1007 val = (unsigned long)dmi->driver_data;
1008
1009 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1010}
1011
8e513217 1012#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 1013static void ahci_gtf_filter_workaround(struct ata_host *host)
1014{
1015 static const struct dmi_system_id sysids[] = {
1016 /*
1017 * Aspire 3810T issues a bunch of SATA enable commands
1018 * via _GTF including an invalid one and one which is
1019 * rejected by the device. Among the successful ones
1020 * is FPDMA non-zero offset enable which when enabled
1021 * only on the drive side leads to NCQ command
1022 * failures. Filter it out.
1023 */
1024 {
1025 .ident = "Aspire 3810T",
1026 .matches = {
1027 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1028 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1029 },
1030 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1031 },
1032 { }
1033 };
1034 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1035 unsigned int filter;
1036 int i;
1037
1038 if (!dmi)
1039 return;
1040
1041 filter = (unsigned long)dmi->driver_data;
a44fec1f
JP		 1042 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1043 filter, dmi->ident);
f80ae7e4
TH		 1044
1045 for (i = 0; i < host->n_ports; i++) {
1046 struct ata_port *ap = host->ports[i];
1047 struct ata_link *link;
1048 struct ata_device *dev;
1049
1050 ata_for_each_link(link, ap, EDGE)
1051 ata_for_each_dev(dev, link, ALL)
1052 dev->gtf_filter |= filter;
1053 }
1054}
8e513217
MT		 1055#else
1056static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1057{}
1058#endif
f80ae7e4 1059
24dc5f33 1060static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1061{
e297d99e
TH		 1062 unsigned int board_id = ent->driver_data;
1063 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1064 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1065 struct device *dev = &pdev->dev;
1da177e4 1066 struct ahci_host_priv *hpriv;
4447d351 1067 struct ata_host *host;
837f5f8f 1068 int n_ports, i, rc;
318893e1 1069 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1da177e4
LT		 1070
1071 VPRINTK("ENTER\n");
1072
b429dd59 1073 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1074
06296a1e 1075 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1076
5b66c829
AC		 1077 /* The AHCI driver can only drive the SATA ports, the PATA driver
1078 can drive them all so if both drivers are selected make sure
1079 AHCI stays out of the way */
1080 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1081 return -ENODEV;
1082
c6353b45
TH		 1083 /*
1084 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1085 * ahci, use ata_generic instead.
1086 */
1087 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1088 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1089 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1090 pdev->subsystem_device == 0xcb89)
1091 return -ENODEV;
1092
7a02267e
MN		 1093 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1094 * At the moment, we can only use the AHCI mode. Let the users know
1095 * that for SAS drives they're out of luck.
1096 */
1097 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
a44fec1f
JP		 1098 dev_info(&pdev->dev,
1099 "PDC42819 can only drive SATA devices with this driver\n");
7a02267e 1100
318893e1
AR		 1101 /* The Connext uses non-standard BAR */
1102 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1103 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1104
4447d351 1105 /* acquire resources */
24dc5f33 1106 rc = pcim_enable_device(pdev);
1da177e4
LT		 1107 if (rc)
1108 return rc;
1109
dea55137
TH		 1110 /* AHCI controllers often implement SFF compatible interface.
1111 * Grab all PCI BARs just in case.
1112 */
318893e1 1113 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
0d5ff566 1114 if (rc == -EBUSY)
24dc5f33 1115 pcim_pin_device(pdev);
0d5ff566 1116 if (rc)
24dc5f33 1117 return rc;
1da177e4 1118
c4f7792c
TH		 1119 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1120 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1121 u8 map;
1122
1123 /* ICH6s share the same PCI ID for both piix and ahci
1124 * modes. Enabling ahci mode while MAP indicates
1125 * combined mode is a bad idea. Yield to ata_piix.
1126 */
1127 pci_read_config_byte(pdev, ICH_MAP, &map);
1128 if (map & 0x3) {
a44fec1f
JP		 1129 dev_info(&pdev->dev,
1130 "controller is in combined mode, can't enable AHCI mode\n");
c4f7792c
TH		 1131 return -ENODEV;
1132 }
1133 }
1134
24dc5f33
TH		 1135 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1136 if (!hpriv)
1137 return -ENOMEM;
417a1a6d
TH		 1138 hpriv->flags |= (unsigned long)pi.private_data;
1139
e297d99e
TH		 1140 /* MCP65 revision A1 and A2 can't do MSI */
1141 if (board_id == board_ahci_mcp65 &&
1142 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1143 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1144
e427fe04
SH		 1145 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1146 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1147 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1148
2fcad9d2
TH		 1149 /* only some SB600s can do 64bit DMA */
1150 if (ahci_sb600_enable_64bit(pdev))
1151 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1152
31b239ad
TH		 1153 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1154 pci_intx(pdev, 1);
1da177e4 1155
318893e1 1156 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
d8993349 1157
4447d351 1158 /* save initial config */
394d6e53 1159 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1160
4447d351 1161 /* prepare host */
453d3131
RH		 1162 if (hpriv->cap & HOST_CAP_NCQ) {
1163 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1164 /*
1165 * Auto-activate optimization is supposed to be
1166 * supported on all AHCI controllers indicating NCQ
1167 * capability, but it seems to be broken on some
1168 * chipsets including NVIDIAs.
1169 */
1170 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1171 pi.flags |= ATA_FLAG_FPDMA_AA;
1172 }
1da177e4 1173
7d50b60b
TH		 1174 if (hpriv->cap & HOST_CAP_PMP)
1175 pi.flags |= ATA_FLAG_PMP;
1176
0cbb0e77 1177 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1178
1fd68434
RW		 1179 if (ahci_broken_system_poweroff(pdev)) {
1180 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1181 dev_info(&pdev->dev,
1182 "quirky BIOS, skipping spindown on poweroff\n");
1183 }
1184
9b10ae86
TH		 1185 if (ahci_broken_suspend(pdev)) {
1186 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
a44fec1f
JP		 1187 dev_warn(&pdev->dev,
1188 "BIOS update required for suspend/resume\n");
9b10ae86
TH		 1189 }
1190
5594639a
TH		 1191 if (ahci_broken_online(pdev)) {
1192 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1193 dev_info(&pdev->dev,
1194 "online status unreliable, applying workaround\n");
1195 }
1196
837f5f8f
TH		 1197 /* CAP.NP sometimes indicate the index of the last enabled
1198 * port, at other times, that of the last possible port, so
1199 * determining the maximum port number requires looking at
1200 * both CAP.NP and port_map.
1201 */
1202 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1203
1204 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1205 if (!host)
1206 return -ENOMEM;
4447d351
TH		 1207 host->private_data = hpriv;
1208
f3d7f23f 1209 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1210 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1211 else
1212 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1213
18f7ba4c
KCA		 1214 if (pi.flags & ATA_FLAG_EM)
1215 ahci_reset_em(host);
1216
4447d351 1217 for (i = 0; i < host->n_ports; i++) {
dab632e8 1218 struct ata_port *ap = host->ports[i];
4447d351 1219
318893e1
AR		 1220 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1221 ata_port_pbar_desc(ap, ahci_pci_bar,
cbcdd875
TH		 1222 0x100 + ap->port_no * 0x80, "port");
1223
18f7ba4c
KCA		 1224 /* set enclosure management message type */
1225 if (ap->flags & ATA_FLAG_EM)
008dbd61 1226 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1227
1228
dab632e8 1229 /* disabled/not-implemented port */
350756f6 1230 if (!(hpriv->port_map & (1 << i)))
dab632e8 1231 ap->ops = &ata_dummy_port_ops;
4447d351 1232 }
d447df14 1233
edc93052
TH		 1234 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1235 ahci_p5wdh_workaround(host);
1236
f80ae7e4
TH		 1237 /* apply gtf filter quirk */
1238 ahci_gtf_filter_workaround(host);
1239
4447d351
TH		 1240 /* initialize adapter */
1241 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1242 if (rc)
24dc5f33 1243 return rc;
1da177e4 1244
3303040d 1245 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1246 if (rc)
1247 return rc;
1da177e4 1248
781d6550 1249 ahci_pci_init_controller(host);
439fcaec 1250 ahci_pci_print_info(host);
1da177e4 1251
4447d351
TH		 1252 pci_set_master(pdev);
1253 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1254 &ahci_sht);
907f4678 1255}
1da177e4 1256
2fc75da0 1257module_pci_driver(ahci_pci_driver);
1da177e4
LT		 1258
1259MODULE_AUTHOR("Jeff Garzik");
1260MODULE_DESCRIPTION("AHCI SATA low-level driver");
1261MODULE_LICENSE("GPL");
1262MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1263MODULE_VERSION(DRV_VERSION);
Empty description
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