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Merge branch 'upstream-fixes' of git://lost.foo-projects.org/~ahkok/git/netdev-2...
[linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
3d41e30a 4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <[email protected]>
3d41e30a 25 e1000-devel Mailing List <[email protected]>
1da177e4
LT		 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28*******************************************************************************/
29
30#include "e1000.h"
31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
dc335d97 39#define DRV_VERSION "7.1.9-k6"DRIVERNAPI
1da177e4 40char e1000_driver_version[] = DRV_VERSION;
3d41e30a 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
1da177e4
LT		 51 INTEL_E1000_ETHERNET_DEVICE(0x1001),
52 INTEL_E1000_ETHERNET_DEVICE(0x1004),
53 INTEL_E1000_ETHERNET_DEVICE(0x1008),
54 INTEL_E1000_ETHERNET_DEVICE(0x1009),
55 INTEL_E1000_ETHERNET_DEVICE(0x100C),
56 INTEL_E1000_ETHERNET_DEVICE(0x100D),
57 INTEL_E1000_ETHERNET_DEVICE(0x100E),
58 INTEL_E1000_ETHERNET_DEVICE(0x100F),
59 INTEL_E1000_ETHERNET_DEVICE(0x1010),
60 INTEL_E1000_ETHERNET_DEVICE(0x1011),
61 INTEL_E1000_ETHERNET_DEVICE(0x1012),
62 INTEL_E1000_ETHERNET_DEVICE(0x1013),
63 INTEL_E1000_ETHERNET_DEVICE(0x1014),
64 INTEL_E1000_ETHERNET_DEVICE(0x1015),
65 INTEL_E1000_ETHERNET_DEVICE(0x1016),
66 INTEL_E1000_ETHERNET_DEVICE(0x1017),
67 INTEL_E1000_ETHERNET_DEVICE(0x1018),
68 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 69 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 70 INTEL_E1000_ETHERNET_DEVICE(0x101D),
71 INTEL_E1000_ETHERNET_DEVICE(0x101E),
72 INTEL_E1000_ETHERNET_DEVICE(0x1026),
73 INTEL_E1000_ETHERNET_DEVICE(0x1027),
74 INTEL_E1000_ETHERNET_DEVICE(0x1028),
ae2c3860
AK		 75 INTEL_E1000_ETHERNET_DEVICE(0x1049),
76 INTEL_E1000_ETHERNET_DEVICE(0x104A),
77 INTEL_E1000_ETHERNET_DEVICE(0x104B),
78 INTEL_E1000_ETHERNET_DEVICE(0x104C),
79 INTEL_E1000_ETHERNET_DEVICE(0x104D),
07b8fede
MC		 80 INTEL_E1000_ETHERNET_DEVICE(0x105E),
81 INTEL_E1000_ETHERNET_DEVICE(0x105F),
82 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 83 INTEL_E1000_ETHERNET_DEVICE(0x1075),
84 INTEL_E1000_ETHERNET_DEVICE(0x1076),
85 INTEL_E1000_ETHERNET_DEVICE(0x1077),
86 INTEL_E1000_ETHERNET_DEVICE(0x1078),
87 INTEL_E1000_ETHERNET_DEVICE(0x1079),
88 INTEL_E1000_ETHERNET_DEVICE(0x107A),
89 INTEL_E1000_ETHERNET_DEVICE(0x107B),
90 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 91 INTEL_E1000_ETHERNET_DEVICE(0x107D),
92 INTEL_E1000_ETHERNET_DEVICE(0x107E),
93 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 94 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 95 INTEL_E1000_ETHERNET_DEVICE(0x108B),
96 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 97 INTEL_E1000_ETHERNET_DEVICE(0x1096),
98 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 99 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 101 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 102 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
ae2c3860
AK		 103 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
104 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
1da177e4
LT		 105 /* required last entry */
106 {0,}
107};
108
109MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
110
3ad2cc67 111static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 112 struct e1000_tx_ring *txdr);
3ad2cc67 113static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 114 struct e1000_rx_ring *rxdr);
3ad2cc67 115static void e1000_free_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 116 struct e1000_tx_ring *tx_ring);
3ad2cc67 117static void e1000_free_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 118 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 119
120/* Local Function Prototypes */
121
122static int e1000_init_module(void);
123static void e1000_exit_module(void);
124static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
125static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 126static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 127static int e1000_sw_init(struct e1000_adapter *adapter);
128static int e1000_open(struct net_device *netdev);
129static int e1000_close(struct net_device *netdev);
130static void e1000_configure_tx(struct e1000_adapter *adapter);
131static void e1000_configure_rx(struct e1000_adapter *adapter);
132static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 133static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
134static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
135static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
136 struct e1000_tx_ring *tx_ring);
137static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
138 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 139static void e1000_set_multi(struct net_device *netdev);
140static void e1000_update_phy_info(unsigned long data);
141static void e1000_watchdog(unsigned long data);
1da177e4
LT		 142static void e1000_82547_tx_fifo_stall(unsigned long data);
143static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
144static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
145static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
146static int e1000_set_mac(struct net_device *netdev, void *p);
147static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 148static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
149 struct e1000_tx_ring *tx_ring);
1da177e4 150#ifdef CONFIG_E1000_NAPI
581d708e 151static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 152static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 153 struct e1000_rx_ring *rx_ring,
1da177e4 154 int *work_done, int work_to_do);
2d7edb92 155static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 156 struct e1000_rx_ring *rx_ring,
2d7edb92 157 int *work_done, int work_to_do);
1da177e4 158#else
581d708e
MC		 159static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
160 struct e1000_rx_ring *rx_ring);
161static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
162 struct e1000_rx_ring *rx_ring);
1da177e4 163#endif
581d708e 164static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 165 struct e1000_rx_ring *rx_ring,
166 int cleaned_count);
581d708e 167static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 168 struct e1000_rx_ring *rx_ring,
169 int cleaned_count);
1da177e4
LT		 170static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
171static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
172 int cmd);
1da177e4
LT		 173static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
174static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
175static void e1000_tx_timeout(struct net_device *dev);
87041639 176static void e1000_reset_task(struct net_device *dev);
1da177e4 177static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 178static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
179 struct sk_buff *skb);
1da177e4
LT		 180
181static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
182static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
183static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
184static void e1000_restore_vlan(struct e1000_adapter *adapter);
185
977e74b5 186static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 187#ifdef CONFIG_PM
1da177e4
LT		 188static int e1000_resume(struct pci_dev *pdev);
189#endif
c653e635 190static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 191
192#ifdef CONFIG_NET_POLL_CONTROLLER
193/* for netdump / net console */
194static void e1000_netpoll (struct net_device *netdev);
195#endif
196
9026729b
AK		 197static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
198 pci_channel_state_t state);
199static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
200static void e1000_io_resume(struct pci_dev *pdev);
201
202static struct pci_error_handlers e1000_err_handler = {
203 .error_detected = e1000_io_error_detected,
204 .slot_reset = e1000_io_slot_reset,
205 .resume = e1000_io_resume,
206};
24025e4e 207
1da177e4
LT		 208static struct pci_driver e1000_driver = {
209 .name = e1000_driver_name,
210 .id_table = e1000_pci_tbl,
211 .probe = e1000_probe,
212 .remove = __devexit_p(e1000_remove),
213 /* Power Managment Hooks */
1da177e4 214 .suspend = e1000_suspend,
6fdfef16 215#ifdef CONFIG_PM
c653e635 216 .resume = e1000_resume,
1da177e4 217#endif
9026729b
AK		 218 .shutdown = e1000_shutdown,
219 .err_handler = &e1000_err_handler
1da177e4
LT		 220};
221
222MODULE_AUTHOR("Intel Corporation, <[email protected]>");
223MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(DRV_VERSION);
226
227static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
228module_param(debug, int, 0);
229MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
230
231/**
232 * e1000_init_module - Driver Registration Routine
233 *
234 * e1000_init_module is the first routine called when the driver is
235 * loaded. All it does is register with the PCI subsystem.
236 **/
237
238static int __init
239e1000_init_module(void)
240{
241 int ret;
242 printk(KERN_INFO "%s - version %s\n",
243 e1000_driver_string, e1000_driver_version);
244
245 printk(KERN_INFO "%s\n", e1000_copyright);
246
29917620 247 ret = pci_register_driver(&e1000_driver);
8b378def 248
1da177e4
LT		 249 return ret;
250}
251
252module_init(e1000_init_module);
253
254/**
255 * e1000_exit_module - Driver Exit Cleanup Routine
256 *
257 * e1000_exit_module is called just before the driver is removed
258 * from memory.
259 **/
260
261static void __exit
262e1000_exit_module(void)
263{
1da177e4
LT		 264 pci_unregister_driver(&e1000_driver);
265}
266
267module_exit(e1000_exit_module);
268
2db10a08
AK		 269static int e1000_request_irq(struct e1000_adapter *adapter)
270{
271 struct net_device *netdev = adapter->netdev;
272 int flags, err = 0;
273
c0bc8721 274 flags = IRQF_SHARED;
2db10a08
AK		 275#ifdef CONFIG_PCI_MSI
276 if (adapter->hw.mac_type > e1000_82547_rev_2) {
277 adapter->have_msi = TRUE;
278 if ((err = pci_enable_msi(adapter->pdev))) {
279 DPRINTK(PROBE, ERR,
280 "Unable to allocate MSI interrupt Error: %d\n", err);
281 adapter->have_msi = FALSE;
282 }
283 }
284 if (adapter->have_msi)
61ef5c00 285 flags &= ~IRQF_SHARED;
2db10a08
AK		 286#endif
287 if ((err = request_irq(adapter->pdev->irq, &e1000_intr, flags,
288 netdev->name, netdev)))
289 DPRINTK(PROBE, ERR,
290 "Unable to allocate interrupt Error: %d\n", err);
291
292 return err;
293}
294
295static void e1000_free_irq(struct e1000_adapter *adapter)
296{
297 struct net_device *netdev = adapter->netdev;
298
299 free_irq(adapter->pdev->irq, netdev);
300
301#ifdef CONFIG_PCI_MSI
302 if (adapter->have_msi)
303 pci_disable_msi(adapter->pdev);
304#endif
305}
306
1da177e4
LT		 307/**
308 * e1000_irq_disable - Mask off interrupt generation on the NIC
309 * @adapter: board private structure
310 **/
311
e619d523 312static void
1da177e4
LT		 313e1000_irq_disable(struct e1000_adapter *adapter)
314{
315 atomic_inc(&adapter->irq_sem);
316 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
317 E1000_WRITE_FLUSH(&adapter->hw);
318 synchronize_irq(adapter->pdev->irq);
319}
320
321/**
322 * e1000_irq_enable - Enable default interrupt generation settings
323 * @adapter: board private structure
324 **/
325
e619d523 326static void
1da177e4
LT		 327e1000_irq_enable(struct e1000_adapter *adapter)
328{
96838a40 329 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 330 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
331 E1000_WRITE_FLUSH(&adapter->hw);
332 }
333}
3ad2cc67
AB		 334
335static void
2d7edb92
MC		 336e1000_update_mng_vlan(struct e1000_adapter *adapter)
337{
338 struct net_device *netdev = adapter->netdev;
339 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
340 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 341 if (adapter->vlgrp) {
342 if (!adapter->vlgrp->vlan_devices[vid]) {
343 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 344 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
345 e1000_vlan_rx_add_vid(netdev, vid);
346 adapter->mng_vlan_id = vid;
347 } else
348 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 349
350 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
351 (vid != old_vid) &&
2d7edb92
MC		 352 !adapter->vlgrp->vlan_devices[old_vid])
353 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 354 } else
355 adapter->mng_vlan_id = vid;
2d7edb92
MC		 356 }
357}
b55ccb35
JK		 358
359/**
360 * e1000_release_hw_control - release control of the h/w to f/w
361 * @adapter: address of board private structure
362 *
363 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
364 * For ASF and Pass Through versions of f/w this means that the
365 * driver is no longer loaded. For AMT version (only with 82573) i
366 * of the f/w this means that the netowrk i/f is closed.
76c224bc 367 *
b55ccb35
JK		 368 **/
369
e619d523 370static void
b55ccb35
JK		 371e1000_release_hw_control(struct e1000_adapter *adapter)
372{
373 uint32_t ctrl_ext;
374 uint32_t swsm;
cd94dd0b 375 uint32_t extcnf;
b55ccb35
JK		 376
377 /* Let firmware taken over control of h/w */
378 switch (adapter->hw.mac_type) {
379 case e1000_82571:
380 case e1000_82572:
4cc15f54 381 case e1000_80003es2lan:
b55ccb35
JK		 382 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
383 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
384 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
385 break;
386 case e1000_82573:
387 swsm = E1000_READ_REG(&adapter->hw, SWSM);
388 E1000_WRITE_REG(&adapter->hw, SWSM,
389 swsm & ~E1000_SWSM_DRV_LOAD);
cd94dd0b
AK		 390 case e1000_ich8lan:
391 extcnf = E1000_READ_REG(&adapter->hw, CTRL_EXT);
392 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
393 extcnf & ~E1000_CTRL_EXT_DRV_LOAD);
394 break;
b55ccb35
JK		 395 default:
396 break;
397 }
398}
399
400/**
401 * e1000_get_hw_control - get control of the h/w from f/w
402 * @adapter: address of board private structure
403 *
404 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 405 * For ASF and Pass Through versions of f/w this means that
406 * the driver is loaded. For AMT version (only with 82573)
b55ccb35 407 * of the f/w this means that the netowrk i/f is open.
76c224bc 408 *
b55ccb35
JK		 409 **/
410
e619d523 411static void
b55ccb35
JK		 412e1000_get_hw_control(struct e1000_adapter *adapter)
413{
414 uint32_t ctrl_ext;
415 uint32_t swsm;
cd94dd0b 416 uint32_t extcnf;
b55ccb35
JK		 417 /* Let firmware know the driver has taken over */
418 switch (adapter->hw.mac_type) {
419 case e1000_82571:
420 case e1000_82572:
4cc15f54 421 case e1000_80003es2lan:
b55ccb35
JK		 422 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
423 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
424 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
425 break;
426 case e1000_82573:
427 swsm = E1000_READ_REG(&adapter->hw, SWSM);
428 E1000_WRITE_REG(&adapter->hw, SWSM,
429 swsm | E1000_SWSM_DRV_LOAD);
430 break;
cd94dd0b
AK		 431 case e1000_ich8lan:
432 extcnf = E1000_READ_REG(&adapter->hw, EXTCNF_CTRL);
433 E1000_WRITE_REG(&adapter->hw, EXTCNF_CTRL,
434 extcnf | E1000_EXTCNF_CTRL_SWFLAG);
435 break;
b55ccb35
JK		 436 default:
437 break;
438 }
439}
440
1da177e4
LT		 441int
442e1000_up(struct e1000_adapter *adapter)
443{
444 struct net_device *netdev = adapter->netdev;
2db10a08 445 int i;
1da177e4
LT		 446
447 /* hardware has been reset, we need to reload some things */
448
1da177e4
LT		 449 e1000_set_multi(netdev);
450
451 e1000_restore_vlan(adapter);
452
453 e1000_configure_tx(adapter);
454 e1000_setup_rctl(adapter);
455 e1000_configure_rx(adapter);
72d64a43
JK		 456 /* call E1000_DESC_UNUSED which always leaves
457 * at least 1 descriptor unused to make sure
458 * next_to_use != next_to_clean */
f56799ea 459 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 460 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 461 adapter->alloc_rx_buf(adapter, ring,
462 E1000_DESC_UNUSED(ring));
f56799ea 463 }
1da177e4 464
7bfa4816
JK		 465 adapter->tx_queue_len = netdev->tx_queue_len;
466
1da177e4 467 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 468
469#ifdef CONFIG_E1000_NAPI
470 netif_poll_enable(netdev);
471#endif
5de55624
MC		 472 e1000_irq_enable(adapter);
473
1da177e4
LT		 474 return 0;
475}
476
79f05bf0
AK		 477/**
478 * e1000_power_up_phy - restore link in case the phy was powered down
479 * @adapter: address of board private structure
480 *
481 * The phy may be powered down to save power and turn off link when the
482 * driver is unloaded and wake on lan is not enabled (among others)
483 * *** this routine MUST be followed by a call to e1000_reset ***
484 *
485 **/
486
d658266e 487void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0
AK		 488{
489 uint16_t mii_reg = 0;
490
491 /* Just clear the power down bit to wake the phy back up */
492 if (adapter->hw.media_type == e1000_media_type_copper) {
493 /* according to the manual, the phy will retain its
494 * settings across a power-down/up cycle */
495 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
496 mii_reg &= ~MII_CR_POWER_DOWN;
497 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
498 }
499}
500
501static void e1000_power_down_phy(struct e1000_adapter *adapter)
502{
503 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
504 e1000_check_mng_mode(&adapter->hw);
505 /* Power down the PHY so no link is implied when interface is down
506 * The PHY cannot be powered down if any of the following is TRUE
507 * (a) WoL is enabled
508 * (b) AMT is active
509 * (c) SoL/IDER session is active */
510 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 511 adapter->hw.mac_type != e1000_ich8lan &&
79f05bf0
AK		 512 adapter->hw.media_type == e1000_media_type_copper &&
513 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
514 !mng_mode_enabled &&
515 !e1000_check_phy_reset_block(&adapter->hw)) {
516 uint16_t mii_reg = 0;
517 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
518 mii_reg |= MII_CR_POWER_DOWN;
519 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
520 mdelay(1);
521 }
522}
523
1da177e4
LT		 524void
525e1000_down(struct e1000_adapter *adapter)
526{
527 struct net_device *netdev = adapter->netdev;
528
529 e1000_irq_disable(adapter);
c1605eb3 530
1da177e4
LT		 531 del_timer_sync(&adapter->tx_fifo_stall_timer);
532 del_timer_sync(&adapter->watchdog_timer);
533 del_timer_sync(&adapter->phy_info_timer);
534
535#ifdef CONFIG_E1000_NAPI
536 netif_poll_disable(netdev);
537#endif
7bfa4816 538 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 539 adapter->link_speed = 0;
540 adapter->link_duplex = 0;
541 netif_carrier_off(netdev);
542 netif_stop_queue(netdev);
543
544 e1000_reset(adapter);
581d708e
MC		 545 e1000_clean_all_tx_rings(adapter);
546 e1000_clean_all_rx_rings(adapter);
1da177e4 547}
1da177e4 548
2db10a08
AK		 549void
550e1000_reinit_locked(struct e1000_adapter *adapter)
551{
552 WARN_ON(in_interrupt());
553 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
554 msleep(1);
555 e1000_down(adapter);
556 e1000_up(adapter);
557 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 558}
559
560void
561e1000_reset(struct e1000_adapter *adapter)
562{
2d7edb92 563 uint32_t pba, manc;
1125ecbc 564 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 565
566 /* Repartition Pba for greater than 9k mtu
567 * To take effect CTRL.RST is required.
568 */
569
2d7edb92
MC		 570 switch (adapter->hw.mac_type) {
571 case e1000_82547:
0e6ef3e0 572 case e1000_82547_rev_2:
2d7edb92
MC		 573 pba = E1000_PBA_30K;
574 break;
868d5309
MC		 575 case e1000_82571:
576 case e1000_82572:
6418ecc6 577 case e1000_80003es2lan:
868d5309
MC		 578 pba = E1000_PBA_38K;
579 break;
2d7edb92
MC		 580 case e1000_82573:
581 pba = E1000_PBA_12K;
582 break;
cd94dd0b
AK		 583 case e1000_ich8lan:
584 pba = E1000_PBA_8K;
585 break;
2d7edb92
MC		 586 default:
587 pba = E1000_PBA_48K;
588 break;
589 }
590
96838a40 591 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 592 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 593 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 594
595
96838a40 596 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 597 adapter->tx_fifo_head = 0;
598 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
599 adapter->tx_fifo_size =
600 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
601 atomic_set(&adapter->tx_fifo_stall, 0);
602 }
2d7edb92 603
1da177e4
LT		 604 E1000_WRITE_REG(&adapter->hw, PBA, pba);
605
606 /* flow control settings */
f11b7f85
JK		 607 /* Set the FC high water mark to 90% of the FIFO size.
608 * Required to clear last 3 LSB */
609 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 610 /* We can't use 90% on small FIFOs because the remainder
611 * would be less than 1 full frame. In this case, we size
612 * it to allow at least a full frame above the high water
613 * mark. */
614 if (pba < E1000_PBA_16K)
615 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 616
617 adapter->hw.fc_high_water = fc_high_water_mark;
618 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 619 if (adapter->hw.mac_type == e1000_80003es2lan)
620 adapter->hw.fc_pause_time = 0xFFFF;
621 else
622 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 623 adapter->hw.fc_send_xon = 1;
624 adapter->hw.fc = adapter->hw.original_fc;
625
2d7edb92 626 /* Allow time for pending master requests to run */
1da177e4 627 e1000_reset_hw(&adapter->hw);
96838a40 628 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 629 E1000_WRITE_REG(&adapter->hw, WUC, 0);
96838a40 630 if (e1000_init_hw(&adapter->hw))
1da177e4 631 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 632 e1000_update_mng_vlan(adapter);
1da177e4
LT		 633 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
634 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
635
636 e1000_reset_adaptive(&adapter->hw);
637 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 638
639 if (!adapter->smart_power_down &&
640 (adapter->hw.mac_type == e1000_82571 ||
641 adapter->hw.mac_type == e1000_82572)) {
642 uint16_t phy_data = 0;
643 /* speed up time to link by disabling smart power down, ignore
644 * the return value of this function because there is nothing
645 * different we would do if it failed */
646 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
647 &phy_data);
648 phy_data &= ~IGP02E1000_PM_SPD;
649 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
650 phy_data);
651 }
652
cd94dd0b
AK		 653 if (adapter->hw.mac_type < e1000_ich8lan)
654 /* FIXME: this code is duplicate and wrong for PCI Express */
2d7edb92
MC		 655 if (adapter->en_mng_pt) {
656 manc = E1000_READ_REG(&adapter->hw, MANC);
657 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
658 E1000_WRITE_REG(&adapter->hw, MANC, manc);
659 }
1da177e4
LT		 660}
661
662/**
663 * e1000_probe - Device Initialization Routine
664 * @pdev: PCI device information struct
665 * @ent: entry in e1000_pci_tbl
666 *
667 * Returns 0 on success, negative on failure
668 *
669 * e1000_probe initializes an adapter identified by a pci_dev structure.
670 * The OS initialization, configuring of the adapter private structure,
671 * and a hardware reset occur.
672 **/
673
674static int __devinit
675e1000_probe(struct pci_dev *pdev,
676 const struct pci_device_id *ent)
677{
678 struct net_device *netdev;
679 struct e1000_adapter *adapter;
2d7edb92 680 unsigned long mmio_start, mmio_len;
cd94dd0b 681 unsigned long flash_start, flash_len;
2d7edb92 682
1da177e4 683 static int cards_found = 0;
84916829 684 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
2d7edb92 685 int i, err, pci_using_dac;
1da177e4
LT		 686 uint16_t eeprom_data;
687 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 688 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 689 return err;
690
cd94dd0b
AK		 691 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
692 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 693 pci_using_dac = 1;
694 } else {
cd94dd0b
AK		 695 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
696 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 697 E1000_ERR("No usable DMA configuration, aborting\n");
698 return err;
699 }
700 pci_using_dac = 0;
701 }
702
96838a40 703 if ((err = pci_request_regions(pdev, e1000_driver_name)))
1da177e4
LT		 704 return err;
705
706 pci_set_master(pdev);
707
708 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
96838a40 709 if (!netdev) {
1da177e4
LT		 710 err = -ENOMEM;
711 goto err_alloc_etherdev;
712 }
713
714 SET_MODULE_OWNER(netdev);
715 SET_NETDEV_DEV(netdev, &pdev->dev);
716
717 pci_set_drvdata(pdev, netdev);
60490fe0 718 adapter = netdev_priv(netdev);
1da177e4
LT		 719 adapter->netdev = netdev;
720 adapter->pdev = pdev;
721 adapter->hw.back = adapter;
722 adapter->msg_enable = (1 << debug) - 1;
723
724 mmio_start = pci_resource_start(pdev, BAR_0);
725 mmio_len = pci_resource_len(pdev, BAR_0);
726
727 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
96838a40 728 if (!adapter->hw.hw_addr) {
1da177e4
LT		 729 err = -EIO;
730 goto err_ioremap;
731 }
732
96838a40
JB		 733 for (i = BAR_1; i <= BAR_5; i++) {
734 if (pci_resource_len(pdev, i) == 0)
1da177e4 735 continue;
96838a40 736 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 737 adapter->hw.io_base = pci_resource_start(pdev, i);
738 break;
739 }
740 }
741
742 netdev->open = &e1000_open;
743 netdev->stop = &e1000_close;
744 netdev->hard_start_xmit = &e1000_xmit_frame;
745 netdev->get_stats = &e1000_get_stats;
746 netdev->set_multicast_list = &e1000_set_multi;
747 netdev->set_mac_address = &e1000_set_mac;
748 netdev->change_mtu = &e1000_change_mtu;
749 netdev->do_ioctl = &e1000_ioctl;
750 e1000_set_ethtool_ops(netdev);
751 netdev->tx_timeout = &e1000_tx_timeout;
752 netdev->watchdog_timeo = 5 * HZ;
753#ifdef CONFIG_E1000_NAPI
754 netdev->poll = &e1000_clean;
755 netdev->weight = 64;
756#endif
757 netdev->vlan_rx_register = e1000_vlan_rx_register;
758 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
759 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
760#ifdef CONFIG_NET_POLL_CONTROLLER
761 netdev->poll_controller = e1000_netpoll;
762#endif
763 strcpy(netdev->name, pci_name(pdev));
764
765 netdev->mem_start = mmio_start;
766 netdev->mem_end = mmio_start + mmio_len;
767 netdev->base_addr = adapter->hw.io_base;
768
769 adapter->bd_number = cards_found;
770
771 /* setup the private structure */
772
96838a40 773 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 774 goto err_sw_init;
775
cd94dd0b
AK		 776 /* Flash BAR mapping must happen after e1000_sw_init
777 * because it depends on mac_type */
778 if ((adapter->hw.mac_type == e1000_ich8lan) &&
779 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
780 flash_start = pci_resource_start(pdev, 1);
781 flash_len = pci_resource_len(pdev, 1);
782 adapter->hw.flash_address = ioremap(flash_start, flash_len);
783 if (!adapter->hw.flash_address) {
784 err = -EIO;
785 goto err_flashmap;
786 }
787 }
788
96838a40 789 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
2d7edb92
MC		 790 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
791
84916829 792 /* if ksp3, indicate if it's port a being setup */
76c224bc
AK		 793 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
794 e1000_ksp3_port_a == 0)
84916829
JK		 795 adapter->ksp3_port_a = 1;
796 e1000_ksp3_port_a++;
797 /* Reset for multiple KP3 adapters */
798 if (e1000_ksp3_port_a == 4)
799 e1000_ksp3_port_a = 0;
800
96838a40 801 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 802 netdev->features = NETIF_F_SG |
803 NETIF_F_HW_CSUM |
804 NETIF_F_HW_VLAN_TX |
805 NETIF_F_HW_VLAN_RX |
806 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 807 if (adapter->hw.mac_type == e1000_ich8lan)
808 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 809 }
810
811#ifdef NETIF_F_TSO
96838a40 812 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 813 (adapter->hw.mac_type != e1000_82547))
814 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 815
816#ifdef NETIF_F_TSO_IPV6
96838a40 817 if (adapter->hw.mac_type > e1000_82547_rev_2)
2d7edb92
MC		 818 netdev->features |= NETIF_F_TSO_IPV6;
819#endif
1da177e4 820#endif
96838a40 821 if (pci_using_dac)
1da177e4
LT		 822 netdev->features |= NETIF_F_HIGHDMA;
823
76c224bc
AK		 824 netdev->features |= NETIF_F_LLTX;
825
2d7edb92
MC		 826 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
827
cd94dd0b
AK		 828 /* initialize eeprom parameters */
829
830 if (e1000_init_eeprom_params(&adapter->hw)) {
831 E1000_ERR("EEPROM initialization failed\n");
832 return -EIO;
833 }
834
96838a40 835 /* before reading the EEPROM, reset the controller to
1da177e4 836 * put the device in a known good starting state */
96838a40 837
1da177e4
LT		 838 e1000_reset_hw(&adapter->hw);
839
840 /* make sure the EEPROM is good */
841
96838a40 842 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4
LT		 843 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
844 err = -EIO;
845 goto err_eeprom;
846 }
847
848 /* copy the MAC address out of the EEPROM */
849
96838a40 850 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 851 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
852 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 853 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 854
96838a40 855 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 856 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
857 err = -EIO;
858 goto err_eeprom;
859 }
860
861 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
862
863 e1000_get_bus_info(&adapter->hw);
864
865 init_timer(&adapter->tx_fifo_stall_timer);
866 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
867 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
868
869 init_timer(&adapter->watchdog_timer);
870 adapter->watchdog_timer.function = &e1000_watchdog;
871 adapter->watchdog_timer.data = (unsigned long) adapter;
872
1da177e4
LT		 873 init_timer(&adapter->phy_info_timer);
874 adapter->phy_info_timer.function = &e1000_update_phy_info;
875 adapter->phy_info_timer.data = (unsigned long) adapter;
876
87041639
JK		 877 INIT_WORK(&adapter->reset_task,
878 (void (*)(void *))e1000_reset_task, netdev);
1da177e4
LT		 879
880 /* we're going to reset, so assume we have no link for now */
881
882 netif_carrier_off(netdev);
883 netif_stop_queue(netdev);
884
885 e1000_check_options(adapter);
886
887 /* Initial Wake on LAN setting
888 * If APM wake is enabled in the EEPROM,
889 * enable the ACPI Magic Packet filter
890 */
891
96838a40 892 switch (adapter->hw.mac_type) {
1da177e4
LT		 893 case e1000_82542_rev2_0:
894 case e1000_82542_rev2_1:
895 case e1000_82543:
896 break;
897 case e1000_82544:
898 e1000_read_eeprom(&adapter->hw,
899 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
900 eeprom_apme_mask = E1000_EEPROM_82544_APM;
901 break;
cd94dd0b
AK		 902 case e1000_ich8lan:
903 e1000_read_eeprom(&adapter->hw,
904 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
905 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
906 break;
1da177e4
LT		 907 case e1000_82546:
908 case e1000_82546_rev_3:
fd803241 909 case e1000_82571:
6418ecc6 910 case e1000_80003es2lan:
96838a40 911 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 912 e1000_read_eeprom(&adapter->hw,
913 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
914 break;
915 }
916 /* Fall Through */
917 default:
918 e1000_read_eeprom(&adapter->hw,
919 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
920 break;
921 }
96838a40 922 if (eeprom_data & eeprom_apme_mask)
1da177e4
LT		 923 adapter->wol |= E1000_WUFC_MAG;
924
fb3d47d4
JK		 925 /* print bus type/speed/width info */
926 {
927 struct e1000_hw *hw = &adapter->hw;
928 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
929 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
930 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
931 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
932 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
933 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
934 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
935 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
936 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
937 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
938 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
939 "32-bit"));
940 }
941
942 for (i = 0; i < 6; i++)
943 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
944
1da177e4
LT		 945 /* reset the hardware with the new settings */
946 e1000_reset(adapter);
947
b55ccb35
JK		 948 /* If the controller is 82573 and f/w is AMT, do not set
949 * DRV_LOAD until the interface is up. For all other cases,
950 * let the f/w know that the h/w is now under the control
951 * of the driver. */
952 if (adapter->hw.mac_type != e1000_82573 ||
953 !e1000_check_mng_mode(&adapter->hw))
954 e1000_get_hw_control(adapter);
2d7edb92 955
1da177e4 956 strcpy(netdev->name, "eth%d");
96838a40 957 if ((err = register_netdev(netdev)))
1da177e4
LT		 958 goto err_register;
959
960 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
961
962 cards_found++;
963 return 0;
964
965err_register:
cd94dd0b
AK		 966 if (adapter->hw.flash_address)
967 iounmap(adapter->hw.flash_address);
968err_flashmap:
1da177e4
LT		 969err_sw_init:
970err_eeprom:
971 iounmap(adapter->hw.hw_addr);
972err_ioremap:
973 free_netdev(netdev);
974err_alloc_etherdev:
975 pci_release_regions(pdev);
976 return err;
977}
978
979/**
980 * e1000_remove - Device Removal Routine
981 * @pdev: PCI device information struct
982 *
983 * e1000_remove is called by the PCI subsystem to alert the driver
984 * that it should release a PCI device. The could be caused by a
985 * Hot-Plug event, or because the driver is going to be removed from
986 * memory.
987 **/
988
989static void __devexit
990e1000_remove(struct pci_dev *pdev)
991{
992 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 993 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 994 uint32_t manc;
581d708e
MC		 995#ifdef CONFIG_E1000_NAPI
996 int i;
997#endif
1da177e4 998
be2b28ed
JG		 999 flush_scheduled_work();
1000
96838a40 1001 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 1002 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 1003 adapter->hw.media_type == e1000_media_type_copper) {
1004 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 1005 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 1006 manc |= E1000_MANC_ARP_EN;
1007 E1000_WRITE_REG(&adapter->hw, MANC, manc);
1008 }
1009 }
1010
b55ccb35
JK		 1011 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1012 * would have already happened in close and is redundant. */
1013 e1000_release_hw_control(adapter);
2d7edb92 1014
1da177e4 1015 unregister_netdev(netdev);
581d708e 1016#ifdef CONFIG_E1000_NAPI
f56799ea 1017 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1018 dev_put(&adapter->polling_netdev[i]);
581d708e 1019#endif
1da177e4 1020
96838a40 1021 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1022 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1023
24025e4e
MC		 1024 kfree(adapter->tx_ring);
1025 kfree(adapter->rx_ring);
1026#ifdef CONFIG_E1000_NAPI
1027 kfree(adapter->polling_netdev);
1028#endif
1029
1da177e4 1030 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1031 if (adapter->hw.flash_address)
1032 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1033 pci_release_regions(pdev);
1034
1035 free_netdev(netdev);
1036
1037 pci_disable_device(pdev);
1038}
1039
1040/**
1041 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1042 * @adapter: board private structure to initialize
1043 *
1044 * e1000_sw_init initializes the Adapter private data structure.
1045 * Fields are initialized based on PCI device information and
1046 * OS network device settings (MTU size).
1047 **/
1048
1049static int __devinit
1050e1000_sw_init(struct e1000_adapter *adapter)
1051{
1052 struct e1000_hw *hw = &adapter->hw;
1053 struct net_device *netdev = adapter->netdev;
1054 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1055#ifdef CONFIG_E1000_NAPI
1056 int i;
1057#endif
1da177e4
LT		 1058
1059 /* PCI config space info */
1060
1061 hw->vendor_id = pdev->vendor;
1062 hw->device_id = pdev->device;
1063 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1064 hw->subsystem_id = pdev->subsystem_device;
1065
1066 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
1067
1068 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1069
eb0f8054 1070 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1071 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1072 hw->max_frame_size = netdev->mtu +
1073 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1074 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1075
1076 /* identify the MAC */
1077
96838a40 1078 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1079 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1080 return -EIO;
1081 }
1082
96838a40 1083 switch (hw->mac_type) {
1da177e4
LT		 1084 default:
1085 break;
1086 case e1000_82541:
1087 case e1000_82547:
1088 case e1000_82541_rev_2:
1089 case e1000_82547_rev_2:
1090 hw->phy_init_script = 1;
1091 break;
1092 }
1093
1094 e1000_set_media_type(hw);
1095
1096 hw->wait_autoneg_complete = FALSE;
1097 hw->tbi_compatibility_en = TRUE;
1098 hw->adaptive_ifs = TRUE;
1099
1100 /* Copper options */
1101
96838a40 1102 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1103 hw->mdix = AUTO_ALL_MODES;
1104 hw->disable_polarity_correction = FALSE;
1105 hw->master_slave = E1000_MASTER_SLAVE;
1106 }
1107
f56799ea
JK		 1108 adapter->num_tx_queues = 1;
1109 adapter->num_rx_queues = 1;
581d708e
MC		 1110
1111 if (e1000_alloc_queues(adapter)) {
1112 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1113 return -ENOMEM;
1114 }
1115
1116#ifdef CONFIG_E1000_NAPI
f56799ea 1117 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1118 adapter->polling_netdev[i].priv = adapter;
1119 adapter->polling_netdev[i].poll = &e1000_clean;
1120 adapter->polling_netdev[i].weight = 64;
1121 dev_hold(&adapter->polling_netdev[i]);
1122 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1123 }
7bfa4816 1124 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1125#endif
1126
1da177e4
LT		 1127 atomic_set(&adapter->irq_sem, 1);
1128 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1129
1130 return 0;
1131}
1132
581d708e
MC		 1133/**
1134 * e1000_alloc_queues - Allocate memory for all rings
1135 * @adapter: board private structure to initialize
1136 *
1137 * We allocate one ring per queue at run-time since we don't know the
1138 * number of queues at compile-time. The polling_netdev array is
1139 * intended for Multiqueue, but should work fine with a single queue.
1140 **/
1141
1142static int __devinit
1143e1000_alloc_queues(struct e1000_adapter *adapter)
1144{
1145 int size;
1146
f56799ea 1147 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1148 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1149 if (!adapter->tx_ring)
1150 return -ENOMEM;
1151 memset(adapter->tx_ring, 0, size);
1152
f56799ea 1153 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1154 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1155 if (!adapter->rx_ring) {
1156 kfree(adapter->tx_ring);
1157 return -ENOMEM;
1158 }
1159 memset(adapter->rx_ring, 0, size);
1160
1161#ifdef CONFIG_E1000_NAPI
f56799ea 1162 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1163 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1164 if (!adapter->polling_netdev) {
1165 kfree(adapter->tx_ring);
1166 kfree(adapter->rx_ring);
1167 return -ENOMEM;
1168 }
1169 memset(adapter->polling_netdev, 0, size);
1170#endif
1171
1172 return E1000_SUCCESS;
1173}
1174
1da177e4
LT		 1175/**
1176 * e1000_open - Called when a network interface is made active
1177 * @netdev: network interface device structure
1178 *
1179 * Returns 0 on success, negative value on failure
1180 *
1181 * The open entry point is called when a network interface is made
1182 * active by the system (IFF_UP). At this point all resources needed
1183 * for transmit and receive operations are allocated, the interrupt
1184 * handler is registered with the OS, the watchdog timer is started,
1185 * and the stack is notified that the interface is ready.
1186 **/
1187
1188static int
1189e1000_open(struct net_device *netdev)
1190{
60490fe0 1191 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1192 int err;
1193
2db10a08
AK		 1194 /* disallow open during test */
1195 if (test_bit(__E1000_DRIVER_TESTING, &adapter->flags))
1196 return -EBUSY;
1197
1da177e4
LT		 1198 /* allocate transmit descriptors */
1199
581d708e 1200 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1201 goto err_setup_tx;
1202
1203 /* allocate receive descriptors */
1204
581d708e 1205 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1206 goto err_setup_rx;
1207
2db10a08
AK		 1208 err = e1000_request_irq(adapter);
1209 if (err)
1210 goto err_up;
1211
79f05bf0
AK		 1212 e1000_power_up_phy(adapter);
1213
96838a40 1214 if ((err = e1000_up(adapter)))
1da177e4 1215 goto err_up;
2d7edb92 1216 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1217 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1218 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1219 e1000_update_mng_vlan(adapter);
1220 }
1da177e4 1221
b55ccb35
JK		 1222 /* If AMT is enabled, let the firmware know that the network
1223 * interface is now open */
1224 if (adapter->hw.mac_type == e1000_82573 &&
1225 e1000_check_mng_mode(&adapter->hw))
1226 e1000_get_hw_control(adapter);
1227
1da177e4
LT		 1228 return E1000_SUCCESS;
1229
1230err_up:
581d708e 1231 e1000_free_all_rx_resources(adapter);
1da177e4 1232err_setup_rx:
581d708e 1233 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1234err_setup_tx:
1235 e1000_reset(adapter);
1236
1237 return err;
1238}
1239
1240/**
1241 * e1000_close - Disables a network interface
1242 * @netdev: network interface device structure
1243 *
1244 * Returns 0, this is not allowed to fail
1245 *
1246 * The close entry point is called when an interface is de-activated
1247 * by the OS. The hardware is still under the drivers control, but
1248 * needs to be disabled. A global MAC reset is issued to stop the
1249 * hardware, and all transmit and receive resources are freed.
1250 **/
1251
1252static int
1253e1000_close(struct net_device *netdev)
1254{
60490fe0 1255 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1256
2db10a08 1257 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1258 e1000_down(adapter);
79f05bf0 1259 e1000_power_down_phy(adapter);
2db10a08 1260 e1000_free_irq(adapter);
1da177e4 1261
581d708e
MC		 1262 e1000_free_all_tx_resources(adapter);
1263 e1000_free_all_rx_resources(adapter);
1da177e4 1264
96838a40 1265 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1266 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1267 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1268 }
b55ccb35
JK		 1269
1270 /* If AMT is enabled, let the firmware know that the network
1271 * interface is now closed */
1272 if (adapter->hw.mac_type == e1000_82573 &&
1273 e1000_check_mng_mode(&adapter->hw))
1274 e1000_release_hw_control(adapter);
1275
1da177e4
LT		 1276 return 0;
1277}
1278
1279/**
1280 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1281 * @adapter: address of board private structure
2d7edb92
MC		 1282 * @start: address of beginning of memory
1283 * @len: length of memory
1da177e4 1284 **/
e619d523 1285static boolean_t
1da177e4
LT		 1286e1000_check_64k_bound(struct e1000_adapter *adapter,
1287 void *start, unsigned long len)
1288{
1289 unsigned long begin = (unsigned long) start;
1290 unsigned long end = begin + len;
1291
2648345f
MC		 1292 /* First rev 82545 and 82546 need to not allow any memory
1293 * write location to cross 64k boundary due to errata 23 */
1da177e4 1294 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1295 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1296 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1297 }
1298
1299 return TRUE;
1300}
1301
1302/**
1303 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1304 * @adapter: board private structure
581d708e 1305 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1306 *
1307 * Return 0 on success, negative on failure
1308 **/
1309
3ad2cc67 1310static int
581d708e
MC		 1311e1000_setup_tx_resources(struct e1000_adapter *adapter,
1312 struct e1000_tx_ring *txdr)
1da177e4 1313{
1da177e4
LT		 1314 struct pci_dev *pdev = adapter->pdev;
1315 int size;
1316
1317 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1318 txdr->buffer_info = vmalloc(size);
96838a40 1319 if (!txdr->buffer_info) {
2648345f
MC		 1320 DPRINTK(PROBE, ERR,
1321 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1322 return -ENOMEM;
1323 }
1324 memset(txdr->buffer_info, 0, size);
1325
1326 /* round up to nearest 4K */
1327
1328 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1329 E1000_ROUNDUP(txdr->size, 4096);
1330
1331 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1332 if (!txdr->desc) {
1da177e4 1333setup_tx_desc_die:
1da177e4 1334 vfree(txdr->buffer_info);
2648345f
MC		 1335 DPRINTK(PROBE, ERR,
1336 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1337 return -ENOMEM;
1338 }
1339
2648345f 1340 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1341 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1342 void *olddesc = txdr->desc;
1343 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1344 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1345 "at %p\n", txdr->size, txdr->desc);
1346 /* Try again, without freeing the previous */
1da177e4 1347 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1348 /* Failed allocation, critical failure */
96838a40 1349 if (!txdr->desc) {
1da177e4
LT		 1350 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1351 goto setup_tx_desc_die;
1352 }
1353
1354 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1355 /* give up */
2648345f
MC		 1356 pci_free_consistent(pdev, txdr->size, txdr->desc,
1357 txdr->dma);
1da177e4
LT		 1358 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1359 DPRINTK(PROBE, ERR,
2648345f
MC		 1360 "Unable to allocate aligned memory "
1361 "for the transmit descriptor ring\n");
1da177e4
LT		 1362 vfree(txdr->buffer_info);
1363 return -ENOMEM;
1364 } else {
2648345f 1365 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1366 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1367 }
1368 }
1369 memset(txdr->desc, 0, txdr->size);
1370
1371 txdr->next_to_use = 0;
1372 txdr->next_to_clean = 0;
2ae76d98 1373 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1374
1375 return 0;
1376}
1377
581d708e
MC		 1378/**
1379 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1380 * (Descriptors) for all queues
1381 * @adapter: board private structure
1382 *
1383 * If this function returns with an error, then it's possible one or
1384 * more of the rings is populated (while the rest are not). It is the
1385 * callers duty to clean those orphaned rings.
1386 *
1387 * Return 0 on success, negative on failure
1388 **/
1389
1390int
1391e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1392{
1393 int i, err = 0;
1394
f56799ea 1395 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1396 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1397 if (err) {
1398 DPRINTK(PROBE, ERR,
1399 "Allocation for Tx Queue %u failed\n", i);
1400 break;
1401 }
1402 }
1403
1404 return err;
1405}
1406
1da177e4
LT		 1407/**
1408 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1409 * @adapter: board private structure
1410 *
1411 * Configure the Tx unit of the MAC after a reset.
1412 **/
1413
1414static void
1415e1000_configure_tx(struct e1000_adapter *adapter)
1416{
581d708e
MC		 1417 uint64_t tdba;
1418 struct e1000_hw *hw = &adapter->hw;
1419 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1420 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1421
1422 /* Setup the HW Tx Head and Tail descriptor pointers */
1423
f56799ea 1424 switch (adapter->num_tx_queues) {
24025e4e
MC		 1425 case 1:
1426 default:
581d708e
MC		 1427 tdba = adapter->tx_ring[0].dma;
1428 tdlen = adapter->tx_ring[0].count *
1429 sizeof(struct e1000_tx_desc);
581d708e 1430 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1431 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1432 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1433 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1434 E1000_WRITE_REG(hw, TDH, 0);
581d708e
MC		 1435 adapter->tx_ring[0].tdh = E1000_TDH;
1436 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1437 break;
1438 }
1da177e4
LT		 1439
1440 /* Set the default values for the Tx Inter Packet Gap timer */
1441
0fadb059
JK		 1442 if (hw->media_type == e1000_media_type_fiber ||
1443 hw->media_type == e1000_media_type_internal_serdes)
1444 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1445 else
1446 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1447
581d708e 1448 switch (hw->mac_type) {
1da177e4
LT		 1449 case e1000_82542_rev2_0:
1450 case e1000_82542_rev2_1:
1451 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1452 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1453 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1454 break;
87041639
JK		 1455 case e1000_80003es2lan:
1456 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1457 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1458 break;
1da177e4 1459 default:
0fadb059
JK		 1460 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1461 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1462 break;
1da177e4 1463 }
0fadb059
JK		 1464 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1465 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1466 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1467
1468 /* Set the Tx Interrupt Delay register */
1469
581d708e
MC		 1470 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1471 if (hw->mac_type >= e1000_82540)
1472 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1473
1474 /* Program the Transmit Control Register */
1475
581d708e 1476 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1477
1478 tctl &= ~E1000_TCTL_CT;
7e6c9861 1479 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1480 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1481
7e6c9861
JK		 1482#ifdef DISABLE_MULR
1483 /* disable Multiple Reads for debugging */
1484 tctl &= ~E1000_TCTL_MULR;
1485#endif
1da177e4 1486
2ae76d98
MC		 1487 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1488 tarc = E1000_READ_REG(hw, TARC0);
1489 tarc |= ((1 << 25) | (1 << 21));
1490 E1000_WRITE_REG(hw, TARC0, tarc);
1491 tarc = E1000_READ_REG(hw, TARC1);
1492 tarc |= (1 << 25);
1493 if (tctl & E1000_TCTL_MULR)
1494 tarc &= ~(1 << 28);
1495 else
1496 tarc |= (1 << 28);
1497 E1000_WRITE_REG(hw, TARC1, tarc);
87041639
JK		 1498 } else if (hw->mac_type == e1000_80003es2lan) {
1499 tarc = E1000_READ_REG(hw, TARC0);
1500 tarc |= 1;
87041639
JK		 1501 E1000_WRITE_REG(hw, TARC0, tarc);
1502 tarc = E1000_READ_REG(hw, TARC1);
1503 tarc |= 1;
1504 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1505 }
1506
581d708e 1507 e1000_config_collision_dist(hw);
1da177e4
LT		 1508
1509 /* Setup Transmit Descriptor Settings for eop descriptor */
1510 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1511 E1000_TXD_CMD_IFCS;
1512
581d708e 1513 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1514 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1515 else
1516 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1517
1518 /* Cache if we're 82544 running in PCI-X because we'll
1519 * need this to apply a workaround later in the send path. */
581d708e
MC		 1520 if (hw->mac_type == e1000_82544 &&
1521 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1522 adapter->pcix_82544 = 1;
7e6c9861
JK		 1523
1524 E1000_WRITE_REG(hw, TCTL, tctl);
1525
1da177e4
LT		 1526}
1527
1528/**
1529 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1530 * @adapter: board private structure
581d708e 1531 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1532 *
1533 * Returns 0 on success, negative on failure
1534 **/
1535
3ad2cc67 1536static int
581d708e
MC		 1537e1000_setup_rx_resources(struct e1000_adapter *adapter,
1538 struct e1000_rx_ring *rxdr)
1da177e4 1539{
1da177e4 1540 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1541 int size, desc_len;
1da177e4
LT		 1542
1543 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1544 rxdr->buffer_info = vmalloc(size);
581d708e 1545 if (!rxdr->buffer_info) {
2648345f
MC		 1546 DPRINTK(PROBE, ERR,
1547 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1548 return -ENOMEM;
1549 }
1550 memset(rxdr->buffer_info, 0, size);
1551
2d7edb92
MC		 1552 size = sizeof(struct e1000_ps_page) * rxdr->count;
1553 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1554 if (!rxdr->ps_page) {
2d7edb92
MC		 1555 vfree(rxdr->buffer_info);
1556 DPRINTK(PROBE, ERR,
1557 "Unable to allocate memory for the receive descriptor ring\n");
1558 return -ENOMEM;
1559 }
1560 memset(rxdr->ps_page, 0, size);
1561
1562 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1563 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1564 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1565 vfree(rxdr->buffer_info);
1566 kfree(rxdr->ps_page);
1567 DPRINTK(PROBE, ERR,
1568 "Unable to allocate memory for the receive descriptor ring\n");
1569 return -ENOMEM;
1570 }
1571 memset(rxdr->ps_page_dma, 0, size);
1572
96838a40 1573 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1574 desc_len = sizeof(struct e1000_rx_desc);
1575 else
1576 desc_len = sizeof(union e1000_rx_desc_packet_split);
1577
1da177e4
LT		 1578 /* Round up to nearest 4K */
1579
2d7edb92 1580 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1581 E1000_ROUNDUP(rxdr->size, 4096);
1582
1583 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1584
581d708e
MC		 1585 if (!rxdr->desc) {
1586 DPRINTK(PROBE, ERR,
1587 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1588setup_rx_desc_die:
1da177e4 1589 vfree(rxdr->buffer_info);
2d7edb92
MC		 1590 kfree(rxdr->ps_page);
1591 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1592 return -ENOMEM;
1593 }
1594
2648345f 1595 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1596 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1597 void *olddesc = rxdr->desc;
1598 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1599 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1600 "at %p\n", rxdr->size, rxdr->desc);
1601 /* Try again, without freeing the previous */
1da177e4 1602 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1603 /* Failed allocation, critical failure */
581d708e 1604 if (!rxdr->desc) {
1da177e4 1605 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1606 DPRINTK(PROBE, ERR,
1607 "Unable to allocate memory "
1608 "for the receive descriptor ring\n");
1da177e4
LT		 1609 goto setup_rx_desc_die;
1610 }
1611
1612 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1613 /* give up */
2648345f
MC		 1614 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1615 rxdr->dma);
1da177e4 1616 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1617 DPRINTK(PROBE, ERR,
1618 "Unable to allocate aligned memory "
1619 "for the receive descriptor ring\n");
581d708e 1620 goto setup_rx_desc_die;
1da177e4 1621 } else {
2648345f 1622 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1623 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1624 }
1625 }
1626 memset(rxdr->desc, 0, rxdr->size);
1627
1628 rxdr->next_to_clean = 0;
1629 rxdr->next_to_use = 0;
1630
1631 return 0;
1632}
1633
581d708e
MC		 1634/**
1635 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1636 * (Descriptors) for all queues
1637 * @adapter: board private structure
1638 *
1639 * If this function returns with an error, then it's possible one or
1640 * more of the rings is populated (while the rest are not). It is the
1641 * callers duty to clean those orphaned rings.
1642 *
1643 * Return 0 on success, negative on failure
1644 **/
1645
1646int
1647e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1648{
1649 int i, err = 0;
1650
f56799ea 1651 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1652 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1653 if (err) {
1654 DPRINTK(PROBE, ERR,
1655 "Allocation for Rx Queue %u failed\n", i);
1656 break;
1657 }
1658 }
1659
1660 return err;
1661}
1662
1da177e4 1663/**
2648345f 1664 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1665 * @adapter: Board private structure
1666 **/
e4c811c9
MC		 1667#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1668 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1669static void
1670e1000_setup_rctl(struct e1000_adapter *adapter)
1671{
2d7edb92
MC		 1672 uint32_t rctl, rfctl;
1673 uint32_t psrctl = 0;
35ec56bb 1674#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1675 uint32_t pages = 0;
1676#endif
1da177e4
LT		 1677
1678 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1679
1680 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1681
1682 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1683 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1684 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1685
0fadb059 1686 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1687 rctl |= E1000_RCTL_SBP;
1688 else
1689 rctl &= ~E1000_RCTL_SBP;
1690
2d7edb92
MC		 1691 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1692 rctl &= ~E1000_RCTL_LPE;
1693 else
1694 rctl |= E1000_RCTL_LPE;
1695
1da177e4 1696 /* Setup buffer sizes */
9e2feace
AK		 1697 rctl &= ~E1000_RCTL_SZ_4096;
1698 rctl |= E1000_RCTL_BSEX;
1699 switch (adapter->rx_buffer_len) {
1700 case E1000_RXBUFFER_256:
1701 rctl |= E1000_RCTL_SZ_256;
1702 rctl &= ~E1000_RCTL_BSEX;
1703 break;
1704 case E1000_RXBUFFER_512:
1705 rctl |= E1000_RCTL_SZ_512;
1706 rctl &= ~E1000_RCTL_BSEX;
1707 break;
1708 case E1000_RXBUFFER_1024:
1709 rctl |= E1000_RCTL_SZ_1024;
1710 rctl &= ~E1000_RCTL_BSEX;
1711 break;
a1415ee6
JK		 1712 case E1000_RXBUFFER_2048:
1713 default:
1714 rctl |= E1000_RCTL_SZ_2048;
1715 rctl &= ~E1000_RCTL_BSEX;
1716 break;
1717 case E1000_RXBUFFER_4096:
1718 rctl |= E1000_RCTL_SZ_4096;
1719 break;
1720 case E1000_RXBUFFER_8192:
1721 rctl |= E1000_RCTL_SZ_8192;
1722 break;
1723 case E1000_RXBUFFER_16384:
1724 rctl |= E1000_RCTL_SZ_16384;
1725 break;
2d7edb92
MC		 1726 }
1727
35ec56bb 1728#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1729 /* 82571 and greater support packet-split where the protocol
1730 * header is placed in skb->data and the packet data is
1731 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1732 * In the case of a non-split, skb->data is linearly filled,
1733 * followed by the page buffers. Therefore, skb->data is
1734 * sized to hold the largest protocol header.
1735 */
e4c811c9
MC		 1736 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1737 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1738 PAGE_SIZE <= 16384)
1739 adapter->rx_ps_pages = pages;
1740 else
1741 adapter->rx_ps_pages = 0;
2d7edb92 1742#endif
e4c811c9 1743 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1744 /* Configure extra packet-split registers */
1745 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1746 rfctl |= E1000_RFCTL_EXTEN;
1747 /* disable IPv6 packet split support */
1748 rfctl |= E1000_RFCTL_IPV6_DIS;
1749 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1750
7dfee0cb 1751 rctl |= E1000_RCTL_DTYP_PS;
96838a40 1752
2d7edb92
MC		 1753 psrctl |= adapter->rx_ps_bsize0 >>
1754 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1755
1756 switch (adapter->rx_ps_pages) {
1757 case 3:
1758 psrctl |= PAGE_SIZE <<
1759 E1000_PSRCTL_BSIZE3_SHIFT;
1760 case 2:
1761 psrctl |= PAGE_SIZE <<
1762 E1000_PSRCTL_BSIZE2_SHIFT;
1763 case 1:
1764 psrctl |= PAGE_SIZE >>
1765 E1000_PSRCTL_BSIZE1_SHIFT;
1766 break;
1767 }
2d7edb92
MC		 1768
1769 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1770 }
1771
1772 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1773}
1774
1775/**
1776 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1777 * @adapter: board private structure
1778 *
1779 * Configure the Rx unit of the MAC after a reset.
1780 **/
1781
1782static void
1783e1000_configure_rx(struct e1000_adapter *adapter)
1784{
581d708e
MC		 1785 uint64_t rdba;
1786 struct e1000_hw *hw = &adapter->hw;
1787 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 1788
e4c811c9 1789 if (adapter->rx_ps_pages) {
0f15a8fa 1790 /* this is a 32 byte descriptor */
581d708e 1791 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1792 sizeof(union e1000_rx_desc_packet_split);
1793 adapter->clean_rx = e1000_clean_rx_irq_ps;
1794 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1795 } else {
581d708e
MC		 1796 rdlen = adapter->rx_ring[0].count *
1797 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1798 adapter->clean_rx = e1000_clean_rx_irq;
1799 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1800 }
1da177e4
LT		 1801
1802 /* disable receives while setting up the descriptors */
581d708e
MC		 1803 rctl = E1000_READ_REG(hw, RCTL);
1804 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1805
1806 /* set the Receive Delay Timer Register */
581d708e 1807 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1808
581d708e
MC		 1809 if (hw->mac_type >= e1000_82540) {
1810 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1811 if (adapter->itr > 1)
581d708e 1812 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1813 1000000000 / (adapter->itr * 256));
1814 }
1815
2ae76d98 1816 if (hw->mac_type >= e1000_82571) {
2ae76d98 1817 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1818 /* Reset delay timers after every interrupt */
6fc7a7ec 1819 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9
JK		 1820#ifdef CONFIG_E1000_NAPI
1821 /* Auto-Mask interrupts upon ICR read. */
1822 ctrl_ext |= E1000_CTRL_EXT_IAME;
1823#endif
2ae76d98 1824 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1825 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1826 E1000_WRITE_FLUSH(hw);
1827 }
1828
581d708e
MC		 1829 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1830 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1831 switch (adapter->num_rx_queues) {
24025e4e
MC		 1832 case 1:
1833 default:
581d708e 1834 rdba = adapter->rx_ring[0].dma;
581d708e 1835 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 1836 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1837 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 1838 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 1839 E1000_WRITE_REG(hw, RDH, 0);
581d708e
MC		 1840 adapter->rx_ring[0].rdh = E1000_RDH;
1841 adapter->rx_ring[0].rdt = E1000_RDT;
1842 break;
24025e4e
MC		 1843 }
1844
1da177e4 1845 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1846 if (hw->mac_type >= e1000_82543) {
1847 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1848 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1849 rxcsum |= E1000_RXCSUM_TUOFL;
1850
868d5309 1851 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1852 * Must be used in conjunction with packet-split. */
96838a40
JB		 1853 if ((hw->mac_type >= e1000_82571) &&
1854 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1855 rxcsum |= E1000_RXCSUM_IPPCSE;
1856 }
1857 } else {
1858 rxcsum &= ~E1000_RXCSUM_TUOFL;
1859 /* don't need to clear IPPCSE as it defaults to 0 */
1860 }
581d708e 1861 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 1862 }
1863
1864 /* Enable Receives */
581d708e 1865 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1866}
1867
1868/**
581d708e 1869 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1870 * @adapter: board private structure
581d708e 1871 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1872 *
1873 * Free all transmit software resources
1874 **/
1875
3ad2cc67 1876static void
581d708e
MC		 1877e1000_free_tx_resources(struct e1000_adapter *adapter,
1878 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1879{
1880 struct pci_dev *pdev = adapter->pdev;
1881
581d708e 1882 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1883
581d708e
MC		 1884 vfree(tx_ring->buffer_info);
1885 tx_ring->buffer_info = NULL;
1da177e4 1886
581d708e 1887 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1888
581d708e
MC		 1889 tx_ring->desc = NULL;
1890}
1891
1892/**
1893 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1894 * @adapter: board private structure
1895 *
1896 * Free all transmit software resources
1897 **/
1898
1899void
1900e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1901{
1902 int i;
1903
f56799ea 1904 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1905 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1906}
1907
e619d523 1908static void
1da177e4
LT		 1909e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1910 struct e1000_buffer *buffer_info)
1911{
96838a40 1912 if (buffer_info->dma) {
2648345f
MC		 1913 pci_unmap_page(adapter->pdev,
1914 buffer_info->dma,
1915 buffer_info->length,
1916 PCI_DMA_TODEVICE);
1da177e4 1917 }
8241e35e 1918 if (buffer_info->skb)
1da177e4 1919 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1920 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1921}
1922
1923/**
1924 * e1000_clean_tx_ring - Free Tx Buffers
1925 * @adapter: board private structure
581d708e 1926 * @tx_ring: ring to be cleaned
1da177e4
LT		 1927 **/
1928
1929static void
581d708e
MC		 1930e1000_clean_tx_ring(struct e1000_adapter *adapter,
1931 struct e1000_tx_ring *tx_ring)
1da177e4 1932{
1da177e4
LT		 1933 struct e1000_buffer *buffer_info;
1934 unsigned long size;
1935 unsigned int i;
1936
1937 /* Free all the Tx ring sk_buffs */
1938
96838a40 1939 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 1940 buffer_info = &tx_ring->buffer_info[i];
1941 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1942 }
1943
1944 size = sizeof(struct e1000_buffer) * tx_ring->count;
1945 memset(tx_ring->buffer_info, 0, size);
1946
1947 /* Zero out the descriptor ring */
1948
1949 memset(tx_ring->desc, 0, tx_ring->size);
1950
1951 tx_ring->next_to_use = 0;
1952 tx_ring->next_to_clean = 0;
fd803241 1953 tx_ring->last_tx_tso = 0;
1da177e4 1954
581d708e
MC		 1955 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1956 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1957}
1958
1959/**
1960 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1961 * @adapter: board private structure
1962 **/
1963
1964static void
1965e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1966{
1967 int i;
1968
f56799ea 1969 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1970 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1971}
1972
1973/**
1974 * e1000_free_rx_resources - Free Rx Resources
1975 * @adapter: board private structure
581d708e 1976 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1977 *
1978 * Free all receive software resources
1979 **/
1980
3ad2cc67 1981static void
581d708e
MC		 1982e1000_free_rx_resources(struct e1000_adapter *adapter,
1983 struct e1000_rx_ring *rx_ring)
1da177e4 1984{
1da177e4
LT		 1985 struct pci_dev *pdev = adapter->pdev;
1986
581d708e 1987 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1988
1989 vfree(rx_ring->buffer_info);
1990 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1991 kfree(rx_ring->ps_page);
1992 rx_ring->ps_page = NULL;
1993 kfree(rx_ring->ps_page_dma);
1994 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1995
1996 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1997
1998 rx_ring->desc = NULL;
1999}
2000
2001/**
581d708e 2002 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2003 * @adapter: board private structure
581d708e
MC		 2004 *
2005 * Free all receive software resources
2006 **/
2007
2008void
2009e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2010{
2011 int i;
2012
f56799ea 2013 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2014 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2015}
2016
2017/**
2018 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2019 * @adapter: board private structure
2020 * @rx_ring: ring to free buffers from
1da177e4
LT		 2021 **/
2022
2023static void
581d708e
MC		 2024e1000_clean_rx_ring(struct e1000_adapter *adapter,
2025 struct e1000_rx_ring *rx_ring)
1da177e4 2026{
1da177e4 2027 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2028 struct e1000_ps_page *ps_page;
2029 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2030 struct pci_dev *pdev = adapter->pdev;
2031 unsigned long size;
2d7edb92 2032 unsigned int i, j;
1da177e4
LT		 2033
2034 /* Free all the Rx ring sk_buffs */
96838a40 2035 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2036 buffer_info = &rx_ring->buffer_info[i];
96838a40 2037 if (buffer_info->skb) {
1da177e4
LT		 2038 pci_unmap_single(pdev,
2039 buffer_info->dma,
2040 buffer_info->length,
2041 PCI_DMA_FROMDEVICE);
2042
2043 dev_kfree_skb(buffer_info->skb);
2044 buffer_info->skb = NULL;
997f5cbd
JK		 2045 }
2046 ps_page = &rx_ring->ps_page[i];
2047 ps_page_dma = &rx_ring->ps_page_dma[i];
2048 for (j = 0; j < adapter->rx_ps_pages; j++) {
2049 if (!ps_page->ps_page[j]) break;
2050 pci_unmap_page(pdev,
2051 ps_page_dma->ps_page_dma[j],
2052 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2053 ps_page_dma->ps_page_dma[j] = 0;
2054 put_page(ps_page->ps_page[j]);
2055 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2056 }
2057 }
2058
2059 size = sizeof(struct e1000_buffer) * rx_ring->count;
2060 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2061 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2062 memset(rx_ring->ps_page, 0, size);
2063 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2064 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2065
2066 /* Zero out the descriptor ring */
2067
2068 memset(rx_ring->desc, 0, rx_ring->size);
2069
2070 rx_ring->next_to_clean = 0;
2071 rx_ring->next_to_use = 0;
2072
581d708e
MC		 2073 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2074 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2075}
2076
2077/**
2078 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2079 * @adapter: board private structure
2080 **/
2081
2082static void
2083e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2084{
2085 int i;
2086
f56799ea 2087 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2088 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2089}
2090
2091/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2092 * and memory write and invalidate disabled for certain operations
2093 */
2094static void
2095e1000_enter_82542_rst(struct e1000_adapter *adapter)
2096{
2097 struct net_device *netdev = adapter->netdev;
2098 uint32_t rctl;
2099
2100 e1000_pci_clear_mwi(&adapter->hw);
2101
2102 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2103 rctl |= E1000_RCTL_RST;
2104 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2105 E1000_WRITE_FLUSH(&adapter->hw);
2106 mdelay(5);
2107
96838a40 2108 if (netif_running(netdev))
581d708e 2109 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2110}
2111
2112static void
2113e1000_leave_82542_rst(struct e1000_adapter *adapter)
2114{
2115 struct net_device *netdev = adapter->netdev;
2116 uint32_t rctl;
2117
2118 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2119 rctl &= ~E1000_RCTL_RST;
2120 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2121 E1000_WRITE_FLUSH(&adapter->hw);
2122 mdelay(5);
2123
96838a40 2124 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2125 e1000_pci_set_mwi(&adapter->hw);
2126
96838a40 2127 if (netif_running(netdev)) {
72d64a43
JK		 2128 /* No need to loop, because 82542 supports only 1 queue */
2129 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2130 e1000_configure_rx(adapter);
72d64a43 2131 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2132 }
2133}
2134
2135/**
2136 * e1000_set_mac - Change the Ethernet Address of the NIC
2137 * @netdev: network interface device structure
2138 * @p: pointer to an address structure
2139 *
2140 * Returns 0 on success, negative on failure
2141 **/
2142
2143static int
2144e1000_set_mac(struct net_device *netdev, void *p)
2145{
60490fe0 2146 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2147 struct sockaddr *addr = p;
2148
96838a40 2149 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2150 return -EADDRNOTAVAIL;
2151
2152 /* 82542 2.0 needs to be in reset to write receive address registers */
2153
96838a40 2154 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2155 e1000_enter_82542_rst(adapter);
2156
2157 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2158 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2159
2160 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2161
868d5309
MC		 2162 /* With 82571 controllers, LAA may be overwritten (with the default)
2163 * due to controller reset from the other port. */
2164 if (adapter->hw.mac_type == e1000_82571) {
2165 /* activate the work around */
2166 adapter->hw.laa_is_present = 1;
2167
96838a40
JB		 2168 /* Hold a copy of the LAA in RAR[14] This is done so that
2169 * between the time RAR[0] gets clobbered and the time it
2170 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2171 * of the RARs and no incoming packets directed to this port
96838a40 2172 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2173 * RAR[14] */
96838a40 2174 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2175 E1000_RAR_ENTRIES - 1);
2176 }
2177
96838a40 2178 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2179 e1000_leave_82542_rst(adapter);
2180
2181 return 0;
2182}
2183
2184/**
2185 * e1000_set_multi - Multicast and Promiscuous mode set
2186 * @netdev: network interface device structure
2187 *
2188 * The set_multi entry point is called whenever the multicast address
2189 * list or the network interface flags are updated. This routine is
2190 * responsible for configuring the hardware for proper multicast,
2191 * promiscuous mode, and all-multi behavior.
2192 **/
2193
2194static void
2195e1000_set_multi(struct net_device *netdev)
2196{
60490fe0 2197 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2198 struct e1000_hw *hw = &adapter->hw;
2199 struct dev_mc_list *mc_ptr;
2200 uint32_t rctl;
2201 uint32_t hash_value;
868d5309 2202 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2203 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2204 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2205 E1000_NUM_MTA_REGISTERS;
2206
2207 if (adapter->hw.mac_type == e1000_ich8lan)
2208 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2209
868d5309
MC		 2210 /* reserve RAR[14] for LAA over-write work-around */
2211 if (adapter->hw.mac_type == e1000_82571)
2212 rar_entries--;
1da177e4 2213
2648345f
MC		 2214 /* Check for Promiscuous and All Multicast modes */
2215
1da177e4
LT		 2216 rctl = E1000_READ_REG(hw, RCTL);
2217
96838a40 2218 if (netdev->flags & IFF_PROMISC) {
1da177e4 2219 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2220 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2221 rctl |= E1000_RCTL_MPE;
2222 rctl &= ~E1000_RCTL_UPE;
2223 } else {
2224 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2225 }
2226
2227 E1000_WRITE_REG(hw, RCTL, rctl);
2228
2229 /* 82542 2.0 needs to be in reset to write receive address registers */
2230
96838a40 2231 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2232 e1000_enter_82542_rst(adapter);
2233
2234 /* load the first 14 multicast address into the exact filters 1-14
2235 * RAR 0 is used for the station MAC adddress
2236 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2237 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2238 */
2239 mc_ptr = netdev->mc_list;
2240
96838a40 2241 for (i = 1; i < rar_entries; i++) {
868d5309 2242 if (mc_ptr) {
1da177e4
LT		 2243 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2244 mc_ptr = mc_ptr->next;
2245 } else {
2246 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2247 E1000_WRITE_FLUSH(hw);
1da177e4 2248 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2249 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2250 }
2251 }
2252
2253 /* clear the old settings from the multicast hash table */
2254
cd94dd0b 2255 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2256 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2257 E1000_WRITE_FLUSH(hw);
2258 }
1da177e4
LT		 2259
2260 /* load any remaining addresses into the hash table */
2261
96838a40 2262 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2263 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2264 e1000_mta_set(hw, hash_value);
2265 }
2266
96838a40 2267 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2268 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2269}
2270
2271/* Need to wait a few seconds after link up to get diagnostic information from
2272 * the phy */
2273
2274static void
2275e1000_update_phy_info(unsigned long data)
2276{
2277 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2278 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2279}
2280
2281/**
2282 * e1000_82547_tx_fifo_stall - Timer Call-back
2283 * @data: pointer to adapter cast into an unsigned long
2284 **/
2285
2286static void
2287e1000_82547_tx_fifo_stall(unsigned long data)
2288{
2289 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2290 struct net_device *netdev = adapter->netdev;
2291 uint32_t tctl;
2292
96838a40
JB		 2293 if (atomic_read(&adapter->tx_fifo_stall)) {
2294 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2295 E1000_READ_REG(&adapter->hw, TDH)) &&
2296 (E1000_READ_REG(&adapter->hw, TDFT) ==
2297 E1000_READ_REG(&adapter->hw, TDFH)) &&
2298 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2299 E1000_READ_REG(&adapter->hw, TDFHS))) {
2300 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2301 E1000_WRITE_REG(&adapter->hw, TCTL,
2302 tctl & ~E1000_TCTL_EN);
2303 E1000_WRITE_REG(&adapter->hw, TDFT,
2304 adapter->tx_head_addr);
2305 E1000_WRITE_REG(&adapter->hw, TDFH,
2306 adapter->tx_head_addr);
2307 E1000_WRITE_REG(&adapter->hw, TDFTS,
2308 adapter->tx_head_addr);
2309 E1000_WRITE_REG(&adapter->hw, TDFHS,
2310 adapter->tx_head_addr);
2311 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2312 E1000_WRITE_FLUSH(&adapter->hw);
2313
2314 adapter->tx_fifo_head = 0;
2315 atomic_set(&adapter->tx_fifo_stall, 0);
2316 netif_wake_queue(netdev);
2317 } else {
2318 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2319 }
2320 }
2321}
2322
2323/**
2324 * e1000_watchdog - Timer Call-back
2325 * @data: pointer to adapter cast into an unsigned long
2326 **/
2327static void
2328e1000_watchdog(unsigned long data)
2329{
2330 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2331 struct net_device *netdev = adapter->netdev;
545c67c0 2332 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2333 uint32_t link, tctl;
cd94dd0b
AK		 2334 int32_t ret_val;
2335
2336 ret_val = e1000_check_for_link(&adapter->hw);
2337 if ((ret_val == E1000_ERR_PHY) &&
2338 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2339 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2340 /* See e1000_kumeran_lock_loss_workaround() */
2341 DPRINTK(LINK, INFO,
2342 "Gigabit has been disabled, downgrading speed\n");
2343 }
2d7edb92
MC		 2344 if (adapter->hw.mac_type == e1000_82573) {
2345 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2346 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2347 e1000_update_mng_vlan(adapter);
96838a40 2348 }
1da177e4 2349
96838a40 2350 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2351 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2352 link = !adapter->hw.serdes_link_down;
2353 else
2354 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2355
96838a40
JB		 2356 if (link) {
2357 if (!netif_carrier_ok(netdev)) {
fe7fe28e 2358 boolean_t txb2b = 1;
1da177e4
LT		 2359 e1000_get_speed_and_duplex(&adapter->hw,
2360 &adapter->link_speed,
2361 &adapter->link_duplex);
2362
2363 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2364 adapter->link_speed,
2365 adapter->link_duplex == FULL_DUPLEX ?
2366 "Full Duplex" : "Half Duplex");
2367
7e6c9861
JK		 2368 /* tweak tx_queue_len according to speed/duplex
2369 * and adjust the timeout factor */
66a2b0a3
JK		 2370 netdev->tx_queue_len = adapter->tx_queue_len;
2371 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2372 switch (adapter->link_speed) {
2373 case SPEED_10:
fe7fe28e 2374 txb2b = 0;
7e6c9861
JK		 2375 netdev->tx_queue_len = 10;
2376 adapter->tx_timeout_factor = 8;
2377 break;
2378 case SPEED_100:
fe7fe28e 2379 txb2b = 0;
7e6c9861
JK		 2380 netdev->tx_queue_len = 100;
2381 /* maybe add some timeout factor ? */
2382 break;
2383 }
2384
fe7fe28e 2385 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2386 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2387 txb2b == 0) {
7e6c9861
JK		 2388#define SPEED_MODE_BIT (1 << 21)
2389 uint32_t tarc0;
2390 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2391 tarc0 &= ~SPEED_MODE_BIT;
2392 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2393 }
2394
2395#ifdef NETIF_F_TSO
2396 /* disable TSO for pcie and 10/100 speeds, to avoid
2397 * some hardware issues */
2398 if (!adapter->tso_force &&
2399 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2400 switch (adapter->link_speed) {
2401 case SPEED_10:
66a2b0a3 2402 case SPEED_100:
7e6c9861
JK		 2403 DPRINTK(PROBE,INFO,
2404 "10/100 speed: disabling TSO\n");
2405 netdev->features &= ~NETIF_F_TSO;
2406 break;
2407 case SPEED_1000:
2408 netdev->features |= NETIF_F_TSO;
2409 break;
2410 default:
2411 /* oops */
66a2b0a3
JK		 2412 break;
2413 }
2414 }
7e6c9861
JK		 2415#endif
2416
2417 /* enable transmits in the hardware, need to do this
2418 * after setting TARC0 */
2419 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2420 tctl |= E1000_TCTL_EN;
2421 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2422
1da177e4
LT		 2423 netif_carrier_on(netdev);
2424 netif_wake_queue(netdev);
2425 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2426 adapter->smartspeed = 0;
2427 }
2428 } else {
96838a40 2429 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2430 adapter->link_speed = 0;
2431 adapter->link_duplex = 0;
2432 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2433 netif_carrier_off(netdev);
2434 netif_stop_queue(netdev);
2435 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
87041639
JK		 2436
2437 /* 80003ES2LAN workaround--
2438 * For packet buffer work-around on link down event;
2439 * disable receives in the ISR and
2440 * reset device here in the watchdog
2441 */
2442 if (adapter->hw.mac_type == e1000_80003es2lan) {
2443 /* reset device */
2444 schedule_work(&adapter->reset_task);
2445 }
1da177e4
LT		 2446 }
2447
2448 e1000_smartspeed(adapter);
2449 }
2450
2451 e1000_update_stats(adapter);
2452
2453 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2454 adapter->tpt_old = adapter->stats.tpt;
2455 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2456 adapter->colc_old = adapter->stats.colc;
2457
2458 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2459 adapter->gorcl_old = adapter->stats.gorcl;
2460 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2461 adapter->gotcl_old = adapter->stats.gotcl;
2462
2463 e1000_update_adaptive(&adapter->hw);
2464
f56799ea 2465 if (!netif_carrier_ok(netdev)) {
581d708e 2466 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2467 /* We've lost link, so the controller stops DMA,
2468 * but we've got queued Tx work that's never going
2469 * to get done, so reset controller to flush Tx.
2470 * (Do the reset outside of interrupt context). */
87041639
JK		 2471 adapter->tx_timeout_count++;
2472 schedule_work(&adapter->reset_task);
1da177e4
LT		 2473 }
2474 }
2475
2476 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2477 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2478 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2479 * asymmetrical Tx or Rx gets ITR=8000; everyone
2480 * else is between 2000-8000. */
2481 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2482 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2483 adapter->gotcl - adapter->gorcl :
2484 adapter->gorcl - adapter->gotcl) / 10000;
2485 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2486 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2487 }
2488
2489 /* Cause software interrupt to ensure rx ring is cleaned */
2490 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2491
2648345f 2492 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2493 adapter->detect_tx_hung = TRUE;
2494
96838a40 2495 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2496 * reset from the other port. Set the appropriate LAA in RAR[0] */
2497 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2498 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2499
1da177e4
LT		 2500 /* Reset the timer */
2501 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2502}
2503
2504#define E1000_TX_FLAGS_CSUM 0x00000001
2505#define E1000_TX_FLAGS_VLAN 0x00000002
2506#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2507#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2508#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2509#define E1000_TX_FLAGS_VLAN_SHIFT 16
2510
e619d523 2511static int
581d708e
MC		 2512e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2513 struct sk_buff *skb)
1da177e4
LT		 2514{
2515#ifdef NETIF_F_TSO
2516 struct e1000_context_desc *context_desc;
545c67c0 2517 struct e1000_buffer *buffer_info;
1da177e4
LT		 2518 unsigned int i;
2519 uint32_t cmd_length = 0;
2d7edb92 2520 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2521 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2522 int err;
2523
89114afd 2524 if (skb_is_gso(skb)) {
1da177e4
LT		 2525 if (skb_header_cloned(skb)) {
2526 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2527 if (err)
2528 return err;
2529 }
2530
2531 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
7967168c 2532 mss = skb_shinfo(skb)->gso_size;
60828236 2533 if (skb->protocol == htons(ETH_P_IP)) {
2d7edb92
MC		 2534 skb->nh.iph->tot_len = 0;
2535 skb->nh.iph->check = 0;
2536 skb->h.th->check =
2537 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2538 skb->nh.iph->daddr,
2539 0,
2540 IPPROTO_TCP,
2541 0);
2542 cmd_length = E1000_TXD_CMD_IP;
2543 ipcse = skb->h.raw - skb->data - 1;
2544#ifdef NETIF_F_TSO_IPV6
e15fdd03 2545 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2d7edb92
MC		 2546 skb->nh.ipv6h->payload_len = 0;
2547 skb->h.th->check =
2548 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2549 &skb->nh.ipv6h->daddr,
2550 0,
2551 IPPROTO_TCP,
2552 0);
2553 ipcse = 0;
2554#endif
2555 }
1da177e4
LT		 2556 ipcss = skb->nh.raw - skb->data;
2557 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2558 tucss = skb->h.raw - skb->data;
2559 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2560 tucse = 0;
2561
2562 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2563 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2564
581d708e
MC		 2565 i = tx_ring->next_to_use;
2566 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2567 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2568
2569 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2570 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2571 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2572 context_desc->upper_setup.tcp_fields.tucss = tucss;
2573 context_desc->upper_setup.tcp_fields.tucso = tucso;
2574 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2575 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2576 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2577 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2578
545c67c0
JK		 2579 buffer_info->time_stamp = jiffies;
2580
581d708e
MC		 2581 if (++i == tx_ring->count) i = 0;
2582 tx_ring->next_to_use = i;
1da177e4 2583
8241e35e 2584 return TRUE;
1da177e4
LT		 2585 }
2586#endif
2587
8241e35e 2588 return FALSE;
1da177e4
LT		 2589}
2590
e619d523 2591static boolean_t
581d708e
MC		 2592e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2593 struct sk_buff *skb)
1da177e4
LT		 2594{
2595 struct e1000_context_desc *context_desc;
545c67c0 2596 struct e1000_buffer *buffer_info;
1da177e4
LT		 2597 unsigned int i;
2598 uint8_t css;
2599
96838a40 2600 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1da177e4
LT		 2601 css = skb->h.raw - skb->data;
2602
581d708e 2603 i = tx_ring->next_to_use;
545c67c0 2604 buffer_info = &tx_ring->buffer_info[i];
581d708e 2605 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2606
2607 context_desc->upper_setup.tcp_fields.tucss = css;
2608 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2609 context_desc->upper_setup.tcp_fields.tucse = 0;
2610 context_desc->tcp_seg_setup.data = 0;
2611 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2612
545c67c0
JK		 2613 buffer_info->time_stamp = jiffies;
2614
581d708e
MC		 2615 if (unlikely(++i == tx_ring->count)) i = 0;
2616 tx_ring->next_to_use = i;
1da177e4
LT		 2617
2618 return TRUE;
2619 }
2620
2621 return FALSE;
2622}
2623
2624#define E1000_MAX_TXD_PWR 12
2625#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2626
e619d523 2627static int
581d708e
MC		 2628e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2629 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2630 unsigned int nr_frags, unsigned int mss)
1da177e4 2631{
1da177e4
LT		 2632 struct e1000_buffer *buffer_info;
2633 unsigned int len = skb->len;
2634 unsigned int offset = 0, size, count = 0, i;
2635 unsigned int f;
2636 len -= skb->data_len;
2637
2638 i = tx_ring->next_to_use;
2639
96838a40 2640 while (len) {
1da177e4
LT		 2641 buffer_info = &tx_ring->buffer_info[i];
2642 size = min(len, max_per_txd);
2643#ifdef NETIF_F_TSO
fd803241
JK		 2644 /* Workaround for Controller erratum --
2645 * descriptor for non-tso packet in a linear SKB that follows a
2646 * tso gets written back prematurely before the data is fully
0f15a8fa 2647 * DMA'd to the controller */
fd803241 2648 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 2649 !skb_is_gso(skb)) {
fd803241
JK		 2650 tx_ring->last_tx_tso = 0;
2651 size -= 4;
2652 }
2653
1da177e4
LT		 2654 /* Workaround for premature desc write-backs
2655 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2656 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2657 size -= 4;
2658#endif
97338bde
MC		 2659 /* work-around for errata 10 and it applies
2660 * to all controllers in PCI-X mode
2661 * The fix is to make sure that the first descriptor of a
2662 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2663 */
96838a40 2664 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2665 (size > 2015) && count == 0))
2666 size = 2015;
96838a40 2667
1da177e4
LT		 2668 /* Workaround for potential 82544 hang in PCI-X. Avoid
2669 * terminating buffers within evenly-aligned dwords. */
96838a40 2670 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2671 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2672 size > 4))
2673 size -= 4;
2674
2675 buffer_info->length = size;
2676 buffer_info->dma =
2677 pci_map_single(adapter->pdev,
2678 skb->data + offset,
2679 size,
2680 PCI_DMA_TODEVICE);
2681 buffer_info->time_stamp = jiffies;
2682
2683 len -= size;
2684 offset += size;
2685 count++;
96838a40 2686 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2687 }
2688
96838a40 2689 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2690 struct skb_frag_struct *frag;
2691
2692 frag = &skb_shinfo(skb)->frags[f];
2693 len = frag->size;
2694 offset = frag->page_offset;
2695
96838a40 2696 while (len) {
1da177e4
LT		 2697 buffer_info = &tx_ring->buffer_info[i];
2698 size = min(len, max_per_txd);
2699#ifdef NETIF_F_TSO
2700 /* Workaround for premature desc write-backs
2701 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2702 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2703 size -= 4;
2704#endif
2705 /* Workaround for potential 82544 hang in PCI-X.
2706 * Avoid terminating buffers within evenly-aligned
2707 * dwords. */
96838a40 2708 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2709 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2710 size > 4))
2711 size -= 4;
2712
2713 buffer_info->length = size;
2714 buffer_info->dma =
2715 pci_map_page(adapter->pdev,
2716 frag->page,
2717 offset,
2718 size,
2719 PCI_DMA_TODEVICE);
2720 buffer_info->time_stamp = jiffies;
2721
2722 len -= size;
2723 offset += size;
2724 count++;
96838a40 2725 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2726 }
2727 }
2728
2729 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2730 tx_ring->buffer_info[i].skb = skb;
2731 tx_ring->buffer_info[first].next_to_watch = i;
2732
2733 return count;
2734}
2735
e619d523 2736static void
581d708e
MC		 2737e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2738 int tx_flags, int count)
1da177e4 2739{
1da177e4
LT		 2740 struct e1000_tx_desc *tx_desc = NULL;
2741 struct e1000_buffer *buffer_info;
2742 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2743 unsigned int i;
2744
96838a40 2745 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2746 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2747 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2748 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2749
96838a40 2750 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2751 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2752 }
2753
96838a40 2754 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2755 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2756 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2757 }
2758
96838a40 2759 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2760 txd_lower |= E1000_TXD_CMD_VLE;
2761 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2762 }
2763
2764 i = tx_ring->next_to_use;
2765
96838a40 2766 while (count--) {
1da177e4
LT		 2767 buffer_info = &tx_ring->buffer_info[i];
2768 tx_desc = E1000_TX_DESC(*tx_ring, i);
2769 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2770 tx_desc->lower.data =
2771 cpu_to_le32(txd_lower | buffer_info->length);
2772 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2773 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2774 }
2775
2776 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2777
2778 /* Force memory writes to complete before letting h/w
2779 * know there are new descriptors to fetch. (Only
2780 * applicable for weak-ordered memory model archs,
2781 * such as IA-64). */
2782 wmb();
2783
2784 tx_ring->next_to_use = i;
581d708e 2785 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2786}
2787
2788/**
2789 * 82547 workaround to avoid controller hang in half-duplex environment.
2790 * The workaround is to avoid queuing a large packet that would span
2791 * the internal Tx FIFO ring boundary by notifying the stack to resend
2792 * the packet at a later time. This gives the Tx FIFO an opportunity to
2793 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2794 * to the beginning of the Tx FIFO.
2795 **/
2796
2797#define E1000_FIFO_HDR 0x10
2798#define E1000_82547_PAD_LEN 0x3E0
2799
e619d523 2800static int
1da177e4
LT		 2801e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2802{
2803 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2804 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2805
2806 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2807
96838a40 2808 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2809 goto no_fifo_stall_required;
2810
96838a40 2811 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2812 return 1;
2813
96838a40 2814 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2815 atomic_set(&adapter->tx_fifo_stall, 1);
2816 return 1;
2817 }
2818
2819no_fifo_stall_required:
2820 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2821 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2822 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2823 return 0;
2824}
2825
2d7edb92 2826#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 2827static int
2d7edb92
MC		 2828e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2829{
2830 struct e1000_hw *hw = &adapter->hw;
2831 uint16_t length, offset;
96838a40
JB		 2832 if (vlan_tx_tag_present(skb)) {
2833 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2834 ( adapter->hw.mng_cookie.status &
2835 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2836 return 0;
2837 }
20a44028 2838 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 2839 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2840 if ((htons(ETH_P_IP) == eth->h_proto)) {
2841 const struct iphdr *ip =
2d7edb92 2842 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2843 if (IPPROTO_UDP == ip->protocol) {
2844 struct udphdr *udp =
2845 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2846 (ip->ihl << 2));
96838a40 2847 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2848 offset = (uint8_t *)udp + 8 - skb->data;
2849 length = skb->len - offset;
2850
2851 return e1000_mng_write_dhcp_info(hw,
96838a40 2852 (uint8_t *)udp + 8,
2d7edb92
MC		 2853 length);
2854 }
2855 }
2856 }
2857 }
2858 return 0;
2859}
2860
1da177e4
LT		 2861#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2862static int
2863e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2864{
60490fe0 2865 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2866 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2867 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2868 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2869 unsigned int tx_flags = 0;
2870 unsigned int len = skb->len;
2871 unsigned long flags;
2872 unsigned int nr_frags = 0;
2873 unsigned int mss = 0;
2874 int count = 0;
76c224bc 2875 int tso;
1da177e4
LT		 2876 unsigned int f;
2877 len -= skb->data_len;
2878
581d708e 2879 tx_ring = adapter->tx_ring;
24025e4e 2880
581d708e 2881 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2882 dev_kfree_skb_any(skb);
2883 return NETDEV_TX_OK;
2884 }
2885
2886#ifdef NETIF_F_TSO
7967168c 2887 mss = skb_shinfo(skb)->gso_size;
76c224bc 2888 /* The controller does a simple calculation to
1da177e4
LT		 2889 * make sure there is enough room in the FIFO before
2890 * initiating the DMA for each buffer. The calc is:
2891 * 4 = ceil(buffer len/mss). To make sure we don't
2892 * overrun the FIFO, adjust the max buffer len if mss
2893 * drops. */
96838a40 2894 if (mss) {
9a3056da 2895 uint8_t hdr_len;
1da177e4
LT		 2896 max_per_txd = min(mss << 2, max_per_txd);
2897 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 2898
9f687888 2899 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
9a3056da
JK		 2900 * points to just header, pull a few bytes of payload from
2901 * frags into skb->data */
2902 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
9f687888
JK		 2903 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
2904 switch (adapter->hw.mac_type) {
2905 unsigned int pull_size;
2906 case e1000_82571:
2907 case e1000_82572:
2908 case e1000_82573:
cd94dd0b 2909 case e1000_ich8lan:
9f687888
JK		 2910 pull_size = min((unsigned int)4, skb->data_len);
2911 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 2912 DPRINTK(DRV, ERR,
9f687888
JK		 2913 "__pskb_pull_tail failed.\n");
2914 dev_kfree_skb_any(skb);
749dfc70 2915 return NETDEV_TX_OK;
9f687888
JK		 2916 }
2917 len = skb->len - skb->data_len;
2918 break;
2919 default:
2920 /* do nothing */
2921 break;
d74bbd3b 2922 }
9a3056da 2923 }
1da177e4
LT		 2924 }
2925
9a3056da 2926 /* reserve a descriptor for the offload context */
96838a40 2927 if ((mss) || (skb->ip_summed == CHECKSUM_HW))
1da177e4 2928 count++;
2648345f 2929 count++;
1da177e4 2930#else
96838a40 2931 if (skb->ip_summed == CHECKSUM_HW)
1da177e4
LT		 2932 count++;
2933#endif
fd803241
JK		 2934
2935#ifdef NETIF_F_TSO
2936 /* Controller Erratum workaround */
89114afd 2937 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241
JK		 2938 count++;
2939#endif
2940
1da177e4
LT		 2941 count += TXD_USE_COUNT(len, max_txd_pwr);
2942
96838a40 2943 if (adapter->pcix_82544)
1da177e4
LT		 2944 count++;
2945
96838a40 2946 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 2947 * in PCI-X mode, so add one more descriptor to the count
2948 */
96838a40 2949 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2950 (len > 2015)))
2951 count++;
2952
1da177e4 2953 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 2954 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 2955 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2956 max_txd_pwr);
96838a40 2957 if (adapter->pcix_82544)
1da177e4
LT		 2958 count += nr_frags;
2959
0f15a8fa
JK		 2960
2961 if (adapter->hw.tx_pkt_filtering &&
2962 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 2963 e1000_transfer_dhcp_info(adapter, skb);
2964
581d708e
MC		 2965 local_irq_save(flags);
2966 if (!spin_trylock(&tx_ring->tx_lock)) {
2967 /* Collision - tell upper layer to requeue */
2968 local_irq_restore(flags);
2969 return NETDEV_TX_LOCKED;
2970 }
1da177e4
LT		 2971
2972 /* need: count + 2 desc gap to keep tail from touching
2973 * head, otherwise try next time */
581d708e 2974 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2975 netif_stop_queue(netdev);
581d708e 2976 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2977 return NETDEV_TX_BUSY;
2978 }
2979
96838a40
JB		 2980 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
2981 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4
LT		 2982 netif_stop_queue(netdev);
2983 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2984 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2985 return NETDEV_TX_BUSY;
2986 }
2987 }
2988
96838a40 2989 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 2990 tx_flags |= E1000_TX_FLAGS_VLAN;
2991 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2992 }
2993
581d708e 2994 first = tx_ring->next_to_use;
96838a40 2995
581d708e 2996 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2997 if (tso < 0) {
2998 dev_kfree_skb_any(skb);
581d708e 2999 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3000 return NETDEV_TX_OK;
3001 }
3002
fd803241
JK		 3003 if (likely(tso)) {
3004 tx_ring->last_tx_tso = 1;
1da177e4 3005 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3006 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3007 tx_flags |= E1000_TX_FLAGS_CSUM;
3008
2d7edb92 3009 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3010 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3011 * no longer assume, we must. */
60828236 3012 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3013 tx_flags |= E1000_TX_FLAGS_IPV4;
3014
581d708e
MC		 3015 e1000_tx_queue(adapter, tx_ring, tx_flags,
3016 e1000_tx_map(adapter, tx_ring, skb, first,
3017 max_per_txd, nr_frags, mss));
1da177e4
LT		 3018
3019 netdev->trans_start = jiffies;
3020
3021 /* Make sure there is space in the ring for the next send. */
581d708e 3022 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 3023 netif_stop_queue(netdev);
3024
581d708e 3025 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3026 return NETDEV_TX_OK;
3027}
3028
3029/**
3030 * e1000_tx_timeout - Respond to a Tx Hang
3031 * @netdev: network interface device structure
3032 **/
3033
3034static void
3035e1000_tx_timeout(struct net_device *netdev)
3036{
60490fe0 3037 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3038
3039 /* Do the reset outside of interrupt context */
87041639
JK		 3040 adapter->tx_timeout_count++;
3041 schedule_work(&adapter->reset_task);
1da177e4
LT		 3042}
3043
3044static void
87041639 3045e1000_reset_task(struct net_device *netdev)
1da177e4 3046{
60490fe0 3047 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3048
2db10a08 3049 e1000_reinit_locked(adapter);
1da177e4
LT		 3050}
3051
3052/**
3053 * e1000_get_stats - Get System Network Statistics
3054 * @netdev: network interface device structure
3055 *
3056 * Returns the address of the device statistics structure.
3057 * The statistics are actually updated from the timer callback.
3058 **/
3059
3060static struct net_device_stats *
3061e1000_get_stats(struct net_device *netdev)
3062{
60490fe0 3063 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3064
6b7660cd 3065 /* only return the current stats */
1da177e4
LT		 3066 return &adapter->net_stats;
3067}
3068
3069/**
3070 * e1000_change_mtu - Change the Maximum Transfer Unit
3071 * @netdev: network interface device structure
3072 * @new_mtu: new value for maximum frame size
3073 *
3074 * Returns 0 on success, negative on failure
3075 **/
3076
3077static int
3078e1000_change_mtu(struct net_device *netdev, int new_mtu)
3079{
60490fe0 3080 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3081 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 3082 uint16_t eeprom_data = 0;
1da177e4 3083
96838a40
JB		 3084 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3085 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3086 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3087 return -EINVAL;
2d7edb92 3088 }
1da177e4 3089
997f5cbd
JK		 3090 /* Adapter-specific max frame size limits. */
3091 switch (adapter->hw.mac_type) {
9e2feace 3092 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3093 case e1000_ich8lan:
997f5cbd
JK		 3094 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3095 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3096 return -EINVAL;
2d7edb92 3097 }
997f5cbd 3098 break;
85b22eb6
JK		 3099 case e1000_82573:
3100 /* only enable jumbo frames if ASPM is disabled completely
3101 * this means both bits must be zero in 0x1A bits 3:2 */
3102 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3103 &eeprom_data);
3104 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
3105 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3106 DPRINTK(PROBE, ERR,
3107 "Jumbo Frames not supported.\n");
3108 return -EINVAL;
3109 }
3110 break;
3111 }
3112 /* fall through to get support */
997f5cbd
JK		 3113 case e1000_82571:
3114 case e1000_82572:
87041639 3115 case e1000_80003es2lan:
997f5cbd
JK		 3116#define MAX_STD_JUMBO_FRAME_SIZE 9234
3117 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3118 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3119 return -EINVAL;
3120 }
3121 break;
3122 default:
3123 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3124 break;
1da177e4
LT		 3125 }
3126
87f5032e 3127 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3128 * means we reserve 2 more, this pushes us to allocate from the next
3129 * larger slab size
3130 * i.e. RXBUFFER_2048 --> size-4096 slab */
3131
3132 if (max_frame <= E1000_RXBUFFER_256)
3133 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3134 else if (max_frame <= E1000_RXBUFFER_512)
3135 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3136 else if (max_frame <= E1000_RXBUFFER_1024)
3137 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3138 else if (max_frame <= E1000_RXBUFFER_2048)
3139 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3140 else if (max_frame <= E1000_RXBUFFER_4096)
3141 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3142 else if (max_frame <= E1000_RXBUFFER_8192)
3143 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3144 else if (max_frame <= E1000_RXBUFFER_16384)
3145 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3146
3147 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3148 if (!adapter->hw.tbi_compatibility_on &&
3149 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3150 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3151 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3152
2d7edb92
MC		 3153 netdev->mtu = new_mtu;
3154
2db10a08
AK		 3155 if (netif_running(netdev))
3156 e1000_reinit_locked(adapter);
1da177e4 3157
1da177e4
LT		 3158 adapter->hw.max_frame_size = max_frame;
3159
3160 return 0;
3161}
3162
3163/**
3164 * e1000_update_stats - Update the board statistics counters
3165 * @adapter: board private structure
3166 **/
3167
3168void
3169e1000_update_stats(struct e1000_adapter *adapter)
3170{
3171 struct e1000_hw *hw = &adapter->hw;
282f33c9 3172 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3173 unsigned long flags;
3174 uint16_t phy_tmp;
3175
3176#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3177
282f33c9
LV		 3178 /*
3179 * Prevent stats update while adapter is being reset, or if the pci
3180 * connection is down.
3181 */
9026729b 3182 if (adapter->link_speed == 0)
282f33c9
LV		 3183 return;
3184 if (pdev->error_state && pdev->error_state != pci_channel_io_normal)
9026729b
AK		 3185 return;
3186
1da177e4
LT		 3187 spin_lock_irqsave(&adapter->stats_lock, flags);
3188
3189 /* these counters are modified from e1000_adjust_tbi_stats,
3190 * called from the interrupt context, so they must only
3191 * be written while holding adapter->stats_lock
3192 */
3193
3194 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3195 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3196 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3197 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3198 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3199 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3200 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3201
3202 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 3203 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3204 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3205 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3206 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3207 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3208 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3209 }
1da177e4
LT		 3210
3211 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3212 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3213 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3214 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3215 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3216 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3217 adapter->stats.dc += E1000_READ_REG(hw, DC);
3218 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3219 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3220 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3221 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3222 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3223 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3224 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3225 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3226 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3227 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3228 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3229 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3230 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3231 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3232 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3233 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3234 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3235 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3236 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3237
3238 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 3239 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3240 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3241 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3242 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3243 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3244 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3245 }
3246
1da177e4
LT		 3247 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3248 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3249
3250 /* used for adaptive IFS */
3251
3252 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3253 adapter->stats.tpt += hw->tx_packet_delta;
3254 hw->collision_delta = E1000_READ_REG(hw, COLC);
3255 adapter->stats.colc += hw->collision_delta;
3256
96838a40 3257 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3258 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3259 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3260 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3261 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3262 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3263 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3264 }
96838a40 3265 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3266 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3267 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3268
3269 if (adapter->hw.mac_type != e1000_ich8lan) {
2d7edb92
MC		 3270 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3271 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3272 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3273 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3274 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3275 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3276 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3277 }
2d7edb92 3278 }
1da177e4
LT		 3279
3280 /* Fill out the OS statistics structure */
3281
3282 adapter->net_stats.rx_packets = adapter->stats.gprc;
3283 adapter->net_stats.tx_packets = adapter->stats.gptc;
3284 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3285 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3286 adapter->net_stats.multicast = adapter->stats.mprc;
3287 adapter->net_stats.collisions = adapter->stats.colc;
3288
3289 /* Rx Errors */
3290
87041639
JK		 3291 /* RLEC on some newer hardware can be incorrect so build
3292 * our own version based on RUC and ROC */
1da177e4
LT		 3293 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3294 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3295 adapter->stats.ruc + adapter->stats.roc +
3296 adapter->stats.cexterr;
87041639
JK		 3297 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3298 adapter->stats.roc;
1da177e4
LT		 3299 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3300 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3301 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3302
3303 /* Tx Errors */
3304
3305 adapter->net_stats.tx_errors = adapter->stats.ecol +
3306 adapter->stats.latecol;
3307 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3308 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3309 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3310
3311 /* Tx Dropped needs to be maintained elsewhere */
3312
3313 /* Phy Stats */
3314
96838a40
JB		 3315 if (hw->media_type == e1000_media_type_copper) {
3316 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3317 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3318 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3319 adapter->phy_stats.idle_errors += phy_tmp;
3320 }
3321
96838a40 3322 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3323 (hw->phy_type == e1000_phy_m88) &&
3324 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3325 adapter->phy_stats.receive_errors += phy_tmp;
3326 }
3327
3328 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3329}
3330
3331/**
3332 * e1000_intr - Interrupt Handler
3333 * @irq: interrupt number
3334 * @data: pointer to a network interface device structure
3335 * @pt_regs: CPU registers structure
3336 **/
3337
3338static irqreturn_t
3339e1000_intr(int irq, void *data, struct pt_regs *regs)
3340{
3341 struct net_device *netdev = data;
60490fe0 3342 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3343 struct e1000_hw *hw = &adapter->hw;
87041639 3344 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3345#ifndef CONFIG_E1000_NAPI
581d708e 3346 int i;
1e613fd9
JK		 3347#else
3348 /* Interrupt Auto-Mask...upon reading ICR,
3349 * interrupts are masked. No need for the
3350 * IMC write, but it does mean we should
3351 * account for it ASAP. */
3352 if (likely(hw->mac_type >= e1000_82571))
3353 atomic_inc(&adapter->irq_sem);
be2b28ed 3354#endif
1da177e4 3355
1e613fd9
JK		 3356 if (unlikely(!icr)) {
3357#ifdef CONFIG_E1000_NAPI
3358 if (hw->mac_type >= e1000_82571)
3359 e1000_irq_enable(adapter);
3360#endif
1da177e4 3361 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3362 }
1da177e4 3363
96838a40 3364 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3365 hw->get_link_status = 1;
87041639
JK		 3366 /* 80003ES2LAN workaround--
3367 * For packet buffer work-around on link down event;
3368 * disable receives here in the ISR and
3369 * reset adapter in watchdog
3370 */
3371 if (netif_carrier_ok(netdev) &&
3372 (adapter->hw.mac_type == e1000_80003es2lan)) {
3373 /* disable receives */
3374 rctl = E1000_READ_REG(hw, RCTL);
3375 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3376 }
1da177e4
LT		 3377 mod_timer(&adapter->watchdog_timer, jiffies);
3378 }
3379
3380#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3381 if (unlikely(hw->mac_type < e1000_82571)) {
3382 atomic_inc(&adapter->irq_sem);
3383 E1000_WRITE_REG(hw, IMC, ~0);
3384 E1000_WRITE_FLUSH(hw);
3385 }
d3d9e484
AK		 3386 if (likely(netif_rx_schedule_prep(netdev)))
3387 __netif_rx_schedule(netdev);
581d708e
MC		 3388 else
3389 e1000_irq_enable(adapter);
c1605eb3 3390#else
1da177e4 3391 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3392 * Due to Hub Link bus being occupied, an interrupt
3393 * de-assertion message is not able to be sent.
3394 * When an interrupt assertion message is generated later,
3395 * two messages are re-ordered and sent out.
3396 * That causes APIC to think 82547 is in de-assertion
3397 * state, while 82547 is in assertion state, resulting
3398 * in dead lock. Writing IMC forces 82547 into
3399 * de-assertion state.
3400 */
3401 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3402 atomic_inc(&adapter->irq_sem);
2648345f 3403 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3404 }
3405
96838a40
JB		 3406 for (i = 0; i < E1000_MAX_INTR; i++)
3407 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3408 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3409 break;
3410
96838a40 3411 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3412 e1000_irq_enable(adapter);
581d708e 3413
c1605eb3 3414#endif
1da177e4
LT		 3415
3416 return IRQ_HANDLED;
3417}
3418
3419#ifdef CONFIG_E1000_NAPI
3420/**
3421 * e1000_clean - NAPI Rx polling callback
3422 * @adapter: board private structure
3423 **/
3424
3425static int
581d708e 3426e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3427{
581d708e
MC		 3428 struct e1000_adapter *adapter;
3429 int work_to_do = min(*budget, poll_dev->quota);
d3d9e484 3430 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3431
3432 /* Must NOT use netdev_priv macro here. */
3433 adapter = poll_dev->priv;
3434
3435 /* Keep link state information with original netdev */
d3d9e484 3436 if (!netif_carrier_ok(poll_dev))
581d708e 3437 goto quit_polling;
2648345f 3438
d3d9e484
AK		 3439 /* e1000_clean is called per-cpu. This lock protects
3440 * tx_ring[0] from being cleaned by multiple cpus
3441 * simultaneously. A failure obtaining the lock means
3442 * tx_ring[0] is currently being cleaned anyway. */
3443 if (spin_trylock(&adapter->tx_queue_lock)) {
3444 tx_cleaned = e1000_clean_tx_irq(adapter,
3445 &adapter->tx_ring[0]);
3446 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3447 }
3448
d3d9e484 3449 adapter->clean_rx(adapter, &adapter->rx_ring[0],
581d708e 3450 &work_done, work_to_do);
1da177e4
LT		 3451
3452 *budget -= work_done;
581d708e 3453 poll_dev->quota -= work_done;
96838a40 3454
2b02893e 3455 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3456 if ((!tx_cleaned && (work_done == 0)) ||
d3d9e484 3457 !netif_running(poll_dev)) {
581d708e
MC		 3458quit_polling:
3459 netif_rx_complete(poll_dev);
1da177e4
LT		 3460 e1000_irq_enable(adapter);
3461 return 0;
3462 }
3463
3464 return 1;
3465}
3466
3467#endif
3468/**
3469 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3470 * @adapter: board private structure
3471 **/
3472
3473static boolean_t
581d708e
MC		 3474e1000_clean_tx_irq(struct e1000_adapter *adapter,
3475 struct e1000_tx_ring *tx_ring)
1da177e4 3476{
1da177e4
LT		 3477 struct net_device *netdev = adapter->netdev;
3478 struct e1000_tx_desc *tx_desc, *eop_desc;
3479 struct e1000_buffer *buffer_info;
3480 unsigned int i, eop;
2a1af5d7
JK		 3481#ifdef CONFIG_E1000_NAPI
3482 unsigned int count = 0;
3483#endif
1da177e4
LT		 3484 boolean_t cleaned = FALSE;
3485
3486 i = tx_ring->next_to_clean;
3487 eop = tx_ring->buffer_info[i].next_to_watch;
3488 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3489
581d708e 3490 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3491 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3492 tx_desc = E1000_TX_DESC(*tx_ring, i);
3493 buffer_info = &tx_ring->buffer_info[i];
3494 cleaned = (i == eop);
3495
fd803241 3496 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3497 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3498
96838a40 3499 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3500 }
581d708e 3501
7bfa4816 3502
1da177e4
LT		 3503 eop = tx_ring->buffer_info[i].next_to_watch;
3504 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3505#ifdef CONFIG_E1000_NAPI
3506#define E1000_TX_WEIGHT 64
3507 /* weight of a sort for tx, to avoid endless transmit cleanup */
3508 if (count++ == E1000_TX_WEIGHT) break;
3509#endif
1da177e4
LT		 3510 }
3511
3512 tx_ring->next_to_clean = i;
3513
77b2aad5 3514#define TX_WAKE_THRESHOLD 32
96838a40 3515 if (unlikely(cleaned && netif_queue_stopped(netdev) &&
77b2aad5
AK		 3516 netif_carrier_ok(netdev))) {
3517 spin_lock(&tx_ring->tx_lock);
3518 if (netif_queue_stopped(netdev) &&
3519 (E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))
3520 netif_wake_queue(netdev);
3521 spin_unlock(&tx_ring->tx_lock);
3522 }
2648345f 3523
581d708e 3524 if (adapter->detect_tx_hung) {
2648345f 3525 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3526 * check with the clearing of time_stamp and movement of i */
3527 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3528 if (tx_ring->buffer_info[eop].dma &&
3529 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 3530 (adapter->tx_timeout_factor * HZ))
70b8f1e1 3531 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3532 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3533
3534 /* detected Tx unit hang */
c6963ef5 3535 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3536 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3537 " TDH <%x>\n"
3538 " TDT <%x>\n"
3539 " next_to_use <%x>\n"
3540 " next_to_clean <%x>\n"
3541 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3542 " time_stamp <%lx>\n"
3543 " next_to_watch <%x>\n"
3544 " jiffies <%lx>\n"
3545 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3546 (unsigned long)((tx_ring - adapter->tx_ring) /
3547 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3548 readl(adapter->hw.hw_addr + tx_ring->tdh),
3549 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3550 tx_ring->next_to_use,
392137fa
JK		 3551 tx_ring->next_to_clean,
3552 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3553 eop,
3554 jiffies,
3555 eop_desc->upper.fields.status);
1da177e4 3556 netif_stop_queue(netdev);
70b8f1e1 3557 }
1da177e4 3558 }
1da177e4
LT		 3559 return cleaned;
3560}
3561
3562/**
3563 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3564 * @adapter: board private structure
3565 * @status_err: receive descriptor status and error fields
3566 * @csum: receive descriptor csum field
3567 * @sk_buff: socket buffer with received data
1da177e4
LT		 3568 **/
3569
e619d523 3570static void
1da177e4 3571e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3572 uint32_t status_err, uint32_t csum,
3573 struct sk_buff *skb)
1da177e4 3574{
2d7edb92
MC		 3575 uint16_t status = (uint16_t)status_err;
3576 uint8_t errors = (uint8_t)(status_err >> 24);
3577 skb->ip_summed = CHECKSUM_NONE;
3578
1da177e4 3579 /* 82543 or newer only */
96838a40 3580 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3581 /* Ignore Checksum bit is set */
96838a40 3582 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3583 /* TCP/UDP checksum error bit is set */
96838a40 3584 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3585 /* let the stack verify checksum errors */
1da177e4 3586 adapter->hw_csum_err++;
2d7edb92
MC		 3587 return;
3588 }
3589 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3590 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3591 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3592 return;
1da177e4 3593 } else {
96838a40 3594 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3595 return;
3596 }
3597 /* It must be a TCP or UDP packet with a valid checksum */
3598 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3599 /* TCP checksum is good */
3600 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3601 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3602 /* IP fragment with UDP payload */
3603 /* Hardware complements the payload checksum, so we undo it
3604 * and then put the value in host order for further stack use.
3605 */
3606 csum = ntohl(csum ^ 0xFFFF);
3607 skb->csum = csum;
3608 skb->ip_summed = CHECKSUM_HW;
1da177e4 3609 }
2d7edb92 3610 adapter->hw_csum_good++;
1da177e4
LT		 3611}
3612
3613/**
2d7edb92 3614 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3615 * @adapter: board private structure
3616 **/
3617
3618static boolean_t
3619#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3620e1000_clean_rx_irq(struct e1000_adapter *adapter,
3621 struct e1000_rx_ring *rx_ring,
3622 int *work_done, int work_to_do)
1da177e4 3623#else
581d708e
MC		 3624e1000_clean_rx_irq(struct e1000_adapter *adapter,
3625 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3626#endif
3627{
1da177e4
LT		 3628 struct net_device *netdev = adapter->netdev;
3629 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 3630 struct e1000_rx_desc *rx_desc, *next_rxd;
3631 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 3632 unsigned long flags;
3633 uint32_t length;
3634 uint8_t last_byte;
3635 unsigned int i;
72d64a43 3636 int cleaned_count = 0;
a1415ee6 3637 boolean_t cleaned = FALSE;
1da177e4
LT		 3638
3639 i = rx_ring->next_to_clean;
3640 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3641 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3642
b92ff8ee 3643 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 3644 struct sk_buff *skb;
a292ca6e 3645 u8 status;
1da177e4 3646#ifdef CONFIG_E1000_NAPI
96838a40 3647 if (*work_done >= work_to_do)
1da177e4
LT		 3648 break;
3649 (*work_done)++;
3650#endif
a292ca6e 3651 status = rx_desc->status;
b92ff8ee 3652 skb = buffer_info->skb;
86c3d59f
JB		 3653 buffer_info->skb = NULL;
3654
30320be8
JK		 3655 prefetch(skb->data - NET_IP_ALIGN);
3656
86c3d59f
JB		 3657 if (++i == rx_ring->count) i = 0;
3658 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 3659 prefetch(next_rxd);
3660
86c3d59f 3661 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3662
72d64a43
JK		 3663 cleaned = TRUE;
3664 cleaned_count++;
a292ca6e
JK		 3665 pci_unmap_single(pdev,
3666 buffer_info->dma,
3667 buffer_info->length,
1da177e4
LT		 3668 PCI_DMA_FROMDEVICE);
3669
1da177e4
LT		 3670 length = le16_to_cpu(rx_desc->length);
3671
f235a2ab
AK		 3672 /* adjust length to remove Ethernet CRC */
3673 length -= 4;
3674
a1415ee6
JK		 3675 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3676 /* All receives must fit into a single buffer */
3677 E1000_DBG("%s: Receive packet consumed multiple"
3678 " buffers\n", netdev->name);
864c4e45
AK		 3679 /* recycle */
3680 buffer_info-> skb = skb;
1da177e4
LT		 3681 goto next_desc;
3682 }
3683
96838a40 3684 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3685 last_byte = *(skb->data + length - 1);
b92ff8ee 3686 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3687 rx_desc->errors, length, last_byte)) {
3688 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3689 e1000_tbi_adjust_stats(&adapter->hw,
3690 &adapter->stats,
1da177e4
LT		 3691 length, skb->data);
3692 spin_unlock_irqrestore(&adapter->stats_lock,
3693 flags);
3694 length--;
3695 } else {
9e2feace
AK		 3696 /* recycle */
3697 buffer_info->skb = skb;
1da177e4
LT		 3698 goto next_desc;
3699 }
1cb5821f 3700 }
1da177e4 3701
a292ca6e
JK		 3702 /* code added for copybreak, this should improve
3703 * performance for small packets with large amounts
3704 * of reassembly being done in the stack */
3705#define E1000_CB_LENGTH 256
a1415ee6 3706 if (length < E1000_CB_LENGTH) {
a292ca6e 3707 struct sk_buff *new_skb =
87f5032e 3708 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 3709 if (new_skb) {
3710 skb_reserve(new_skb, NET_IP_ALIGN);
3711 new_skb->dev = netdev;
3712 memcpy(new_skb->data - NET_IP_ALIGN,
3713 skb->data - NET_IP_ALIGN,
3714 length + NET_IP_ALIGN);
3715 /* save the skb in buffer_info as good */
3716 buffer_info->skb = skb;
3717 skb = new_skb;
3718 skb_put(skb, length);
3719 }
a1415ee6
JK		 3720 } else
3721 skb_put(skb, length);
a292ca6e
JK		 3722
3723 /* end copybreak code */
1da177e4
LT		 3724
3725 /* Receive Checksum Offload */
a292ca6e
JK		 3726 e1000_rx_checksum(adapter,
3727 (uint32_t)(status) |
2d7edb92 3728 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 3729 le16_to_cpu(rx_desc->csum), skb);
96838a40 3730
1da177e4
LT		 3731 skb->protocol = eth_type_trans(skb, netdev);
3732#ifdef CONFIG_E1000_NAPI
96838a40 3733 if (unlikely(adapter->vlgrp &&
a292ca6e 3734 (status & E1000_RXD_STAT_VP))) {
1da177e4 3735 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3736 le16_to_cpu(rx_desc->special) &
3737 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3738 } else {
3739 netif_receive_skb(skb);
3740 }
3741#else /* CONFIG_E1000_NAPI */
96838a40 3742 if (unlikely(adapter->vlgrp &&
b92ff8ee 3743 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3744 vlan_hwaccel_rx(skb, adapter->vlgrp,
3745 le16_to_cpu(rx_desc->special) &
3746 E1000_RXD_SPC_VLAN_MASK);
3747 } else {
3748 netif_rx(skb);
3749 }
3750#endif /* CONFIG_E1000_NAPI */
3751 netdev->last_rx = jiffies;
3752
3753next_desc:
3754 rx_desc->status = 0;
1da177e4 3755
72d64a43
JK		 3756 /* return some buffers to hardware, one at a time is too slow */
3757 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3758 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3759 cleaned_count = 0;
3760 }
3761
30320be8 3762 /* use prefetched values */
86c3d59f
JB		 3763 rx_desc = next_rxd;
3764 buffer_info = next_buffer;
1da177e4 3765 }
1da177e4 3766 rx_ring->next_to_clean = i;
72d64a43
JK		 3767
3768 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3769 if (cleaned_count)
3770 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3771
3772 return cleaned;
3773}
3774
3775/**
3776 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3777 * @adapter: board private structure
3778 **/
3779
3780static boolean_t
3781#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3782e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3783 struct e1000_rx_ring *rx_ring,
3784 int *work_done, int work_to_do)
2d7edb92 3785#else
581d708e
MC		 3786e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3787 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3788#endif
3789{
86c3d59f 3790 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 3791 struct net_device *netdev = adapter->netdev;
3792 struct pci_dev *pdev = adapter->pdev;
86c3d59f 3793 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 3794 struct e1000_ps_page *ps_page;
3795 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 3796 struct sk_buff *skb;
2d7edb92
MC		 3797 unsigned int i, j;
3798 uint32_t length, staterr;
72d64a43 3799 int cleaned_count = 0;
2d7edb92
MC		 3800 boolean_t cleaned = FALSE;
3801
3802 i = rx_ring->next_to_clean;
3803 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3804 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 3805 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 3806
96838a40 3807 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 3808 ps_page = &rx_ring->ps_page[i];
3809 ps_page_dma = &rx_ring->ps_page_dma[i];
3810#ifdef CONFIG_E1000_NAPI
96838a40 3811 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3812 break;
3813 (*work_done)++;
3814#endif
86c3d59f
JB		 3815 skb = buffer_info->skb;
3816
30320be8
JK		 3817 /* in the packet split case this is header only */
3818 prefetch(skb->data - NET_IP_ALIGN);
3819
86c3d59f
JB		 3820 if (++i == rx_ring->count) i = 0;
3821 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 3822 prefetch(next_rxd);
3823
86c3d59f 3824 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3825
2d7edb92 3826 cleaned = TRUE;
72d64a43 3827 cleaned_count++;
2d7edb92
MC		 3828 pci_unmap_single(pdev, buffer_info->dma,
3829 buffer_info->length,
3830 PCI_DMA_FROMDEVICE);
3831
96838a40 3832 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3833 E1000_DBG("%s: Packet Split buffers didn't pick up"
3834 " the full packet\n", netdev->name);
3835 dev_kfree_skb_irq(skb);
3836 goto next_desc;
3837 }
1da177e4 3838
96838a40 3839 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3840 dev_kfree_skb_irq(skb);
3841 goto next_desc;
3842 }
3843
3844 length = le16_to_cpu(rx_desc->wb.middle.length0);
3845
96838a40 3846 if (unlikely(!length)) {
2d7edb92
MC		 3847 E1000_DBG("%s: Last part of the packet spanning"
3848 " multiple descriptors\n", netdev->name);
3849 dev_kfree_skb_irq(skb);
3850 goto next_desc;
3851 }
3852
3853 /* Good Receive */
3854 skb_put(skb, length);
3855
dc7c6add
JK		 3856 {
3857 /* this looks ugly, but it seems compiler issues make it
3858 more efficient than reusing j */
3859 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
3860
3861 /* page alloc/put takes too long and effects small packet
3862 * throughput, so unsplit small packets and save the alloc/put*/
9e2feace 3863 if (l1 && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 3864 u8 *vaddr;
76c224bc 3865 /* there is no documentation about how to call
dc7c6add
JK		 3866 * kmap_atomic, so we can't hold the mapping
3867 * very long */
3868 pci_dma_sync_single_for_cpu(pdev,
3869 ps_page_dma->ps_page_dma[0],
3870 PAGE_SIZE,
3871 PCI_DMA_FROMDEVICE);
3872 vaddr = kmap_atomic(ps_page->ps_page[0],
3873 KM_SKB_DATA_SOFTIRQ);
3874 memcpy(skb->tail, vaddr, l1);
3875 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
3876 pci_dma_sync_single_for_device(pdev,
3877 ps_page_dma->ps_page_dma[0],
3878 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 3879 /* remove the CRC */
3880 l1 -= 4;
dc7c6add 3881 skb_put(skb, l1);
dc7c6add
JK		 3882 goto copydone;
3883 } /* if */
3884 }
3885
96838a40 3886 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 3887 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 3888 break;
2d7edb92
MC		 3889 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3890 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3891 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 3892 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
3893 length);
2d7edb92 3894 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 3895 skb->len += length;
3896 skb->data_len += length;
5d51b80f 3897 skb->truesize += length;
2d7edb92
MC		 3898 }
3899
f235a2ab
AK		 3900 /* strip the ethernet crc, problem is we're using pages now so
3901 * this whole operation can get a little cpu intensive */
3902 pskb_trim(skb, skb->len - 4);
3903
dc7c6add 3904copydone:
2d7edb92 3905 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 3906 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 3907 skb->protocol = eth_type_trans(skb, netdev);
3908
96838a40 3909 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 3910 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 3911 adapter->rx_hdr_split++;
2d7edb92 3912#ifdef CONFIG_E1000_NAPI
96838a40 3913 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3914 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3915 le16_to_cpu(rx_desc->wb.middle.vlan) &
3916 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3917 } else {
3918 netif_receive_skb(skb);
3919 }
3920#else /* CONFIG_E1000_NAPI */
96838a40 3921 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3922 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3923 le16_to_cpu(rx_desc->wb.middle.vlan) &
3924 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3925 } else {
3926 netif_rx(skb);
3927 }
3928#endif /* CONFIG_E1000_NAPI */
3929 netdev->last_rx = jiffies;
3930
3931next_desc:
c3d7a3a4 3932 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 3933 buffer_info->skb = NULL;
2d7edb92 3934
72d64a43
JK		 3935 /* return some buffers to hardware, one at a time is too slow */
3936 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3937 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3938 cleaned_count = 0;
3939 }
3940
30320be8 3941 /* use prefetched values */
86c3d59f
JB		 3942 rx_desc = next_rxd;
3943 buffer_info = next_buffer;
3944
683a38f3 3945 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3946 }
3947 rx_ring->next_to_clean = i;
72d64a43
JK		 3948
3949 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3950 if (cleaned_count)
3951 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3952
3953 return cleaned;
3954}
3955
3956/**
2d7edb92 3957 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3958 * @adapter: address of board private structure
3959 **/
3960
3961static void
581d708e 3962e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3963 struct e1000_rx_ring *rx_ring,
a292ca6e 3964 int cleaned_count)
1da177e4 3965{
1da177e4
LT		 3966 struct net_device *netdev = adapter->netdev;
3967 struct pci_dev *pdev = adapter->pdev;
3968 struct e1000_rx_desc *rx_desc;
3969 struct e1000_buffer *buffer_info;
3970 struct sk_buff *skb;
2648345f
MC		 3971 unsigned int i;
3972 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3973
3974 i = rx_ring->next_to_use;
3975 buffer_info = &rx_ring->buffer_info[i];
3976
a292ca6e
JK		 3977 while (cleaned_count--) {
3978 if (!(skb = buffer_info->skb))
87f5032e 3979 skb = netdev_alloc_skb(netdev, bufsz);
a292ca6e
JK		 3980 else {
3981 skb_trim(skb, 0);
3982 goto map_skb;
3983 }
3984
96838a40 3985 if (unlikely(!skb)) {
1da177e4 3986 /* Better luck next round */
72d64a43 3987 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 3988 break;
3989 }
3990
2648345f 3991 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3992 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3993 struct sk_buff *oldskb = skb;
2648345f
MC		 3994 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3995 "at %p\n", bufsz, skb->data);
3996 /* Try again, without freeing the previous */
87f5032e 3997 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 3998 /* Failed allocation, critical failure */
1da177e4
LT		 3999 if (!skb) {
4000 dev_kfree_skb(oldskb);
4001 break;
4002 }
2648345f 4003
1da177e4
LT		 4004 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4005 /* give up */
4006 dev_kfree_skb(skb);
4007 dev_kfree_skb(oldskb);
4008 break; /* while !buffer_info->skb */
4009 } else {
2648345f 4010 /* Use new allocation */
1da177e4
LT		 4011 dev_kfree_skb(oldskb);
4012 }
4013 }
1da177e4
LT		 4014 /* Make buffer alignment 2 beyond a 16 byte boundary
4015 * this will result in a 16 byte aligned IP header after
4016 * the 14 byte MAC header is removed
4017 */
4018 skb_reserve(skb, NET_IP_ALIGN);
4019
4020 skb->dev = netdev;
4021
4022 buffer_info->skb = skb;
4023 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4024map_skb:
1da177e4
LT		 4025 buffer_info->dma = pci_map_single(pdev,
4026 skb->data,
4027 adapter->rx_buffer_len,
4028 PCI_DMA_FROMDEVICE);
4029
2648345f
MC		 4030 /* Fix for errata 23, can't cross 64kB boundary */
4031 if (!e1000_check_64k_bound(adapter,
4032 (void *)(unsigned long)buffer_info->dma,
4033 adapter->rx_buffer_len)) {
4034 DPRINTK(RX_ERR, ERR,
4035 "dma align check failed: %u bytes at %p\n",
4036 adapter->rx_buffer_len,
4037 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4038 dev_kfree_skb(skb);
4039 buffer_info->skb = NULL;
4040
2648345f 4041 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4042 adapter->rx_buffer_len,
4043 PCI_DMA_FROMDEVICE);
4044
4045 break; /* while !buffer_info->skb */
4046 }
1da177e4
LT		 4047 rx_desc = E1000_RX_DESC(*rx_ring, i);
4048 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4049
96838a40
JB		 4050 if (unlikely(++i == rx_ring->count))
4051 i = 0;
1da177e4
LT		 4052 buffer_info = &rx_ring->buffer_info[i];
4053 }
4054
b92ff8ee
JB		 4055 if (likely(rx_ring->next_to_use != i)) {
4056 rx_ring->next_to_use = i;
4057 if (unlikely(i-- == 0))
4058 i = (rx_ring->count - 1);
4059
4060 /* Force memory writes to complete before letting h/w
4061 * know there are new descriptors to fetch. (Only
4062 * applicable for weak-ordered memory model archs,
4063 * such as IA-64). */
4064 wmb();
4065 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4066 }
1da177e4
LT		 4067}
4068
2d7edb92
MC		 4069/**
4070 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4071 * @adapter: address of board private structure
4072 **/
4073
4074static void
581d708e 4075e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4076 struct e1000_rx_ring *rx_ring,
4077 int cleaned_count)
2d7edb92 4078{
2d7edb92
MC		 4079 struct net_device *netdev = adapter->netdev;
4080 struct pci_dev *pdev = adapter->pdev;
4081 union e1000_rx_desc_packet_split *rx_desc;
4082 struct e1000_buffer *buffer_info;
4083 struct e1000_ps_page *ps_page;
4084 struct e1000_ps_page_dma *ps_page_dma;
4085 struct sk_buff *skb;
4086 unsigned int i, j;
4087
4088 i = rx_ring->next_to_use;
4089 buffer_info = &rx_ring->buffer_info[i];
4090 ps_page = &rx_ring->ps_page[i];
4091 ps_page_dma = &rx_ring->ps_page_dma[i];
4092
72d64a43 4093 while (cleaned_count--) {
2d7edb92
MC		 4094 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4095
96838a40 4096 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4097 if (j < adapter->rx_ps_pages) {
4098 if (likely(!ps_page->ps_page[j])) {
4099 ps_page->ps_page[j] =
4100 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4101 if (unlikely(!ps_page->ps_page[j])) {
4102 adapter->alloc_rx_buff_failed++;
e4c811c9 4103 goto no_buffers;
b92ff8ee 4104 }
e4c811c9
MC		 4105 ps_page_dma->ps_page_dma[j] =
4106 pci_map_page(pdev,
4107 ps_page->ps_page[j],
4108 0, PAGE_SIZE,
4109 PCI_DMA_FROMDEVICE);
4110 }
4111 /* Refresh the desc even if buffer_addrs didn't
96838a40 4112 * change because each write-back erases
e4c811c9
MC		 4113 * this info.
4114 */
4115 rx_desc->read.buffer_addr[j+1] =
4116 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4117 } else
4118 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4119 }
4120
87f5032e
DM		 4121 skb = netdev_alloc_skb(netdev,
4122 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4123
b92ff8ee
JB		 4124 if (unlikely(!skb)) {
4125 adapter->alloc_rx_buff_failed++;
2d7edb92 4126 break;
b92ff8ee 4127 }
2d7edb92
MC		 4128
4129 /* Make buffer alignment 2 beyond a 16 byte boundary
4130 * this will result in a 16 byte aligned IP header after
4131 * the 14 byte MAC header is removed
4132 */
4133 skb_reserve(skb, NET_IP_ALIGN);
4134
4135 skb->dev = netdev;
4136
4137 buffer_info->skb = skb;
4138 buffer_info->length = adapter->rx_ps_bsize0;
4139 buffer_info->dma = pci_map_single(pdev, skb->data,
4140 adapter->rx_ps_bsize0,
4141 PCI_DMA_FROMDEVICE);
4142
4143 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4144
96838a40 4145 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4146 buffer_info = &rx_ring->buffer_info[i];
4147 ps_page = &rx_ring->ps_page[i];
4148 ps_page_dma = &rx_ring->ps_page_dma[i];
4149 }
4150
4151no_buffers:
b92ff8ee
JB		 4152 if (likely(rx_ring->next_to_use != i)) {
4153 rx_ring->next_to_use = i;
4154 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4155
4156 /* Force memory writes to complete before letting h/w
4157 * know there are new descriptors to fetch. (Only
4158 * applicable for weak-ordered memory model archs,
4159 * such as IA-64). */
4160 wmb();
4161 /* Hardware increments by 16 bytes, but packet split
4162 * descriptors are 32 bytes...so we increment tail
4163 * twice as much.
4164 */
4165 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4166 }
2d7edb92
MC		 4167}
4168
1da177e4
LT		 4169/**
4170 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4171 * @adapter:
4172 **/
4173
4174static void
4175e1000_smartspeed(struct e1000_adapter *adapter)
4176{
4177 uint16_t phy_status;
4178 uint16_t phy_ctrl;
4179
96838a40 4180 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4181 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4182 return;
4183
96838a40 4184 if (adapter->smartspeed == 0) {
1da177e4
LT		 4185 /* If Master/Slave config fault is asserted twice,
4186 * we assume back-to-back */
4187 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4188 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4189 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4190 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4191 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4192 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4193 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4194 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4195 phy_ctrl);
4196 adapter->smartspeed++;
96838a40 4197 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4198 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4199 &phy_ctrl)) {
4200 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4201 MII_CR_RESTART_AUTO_NEG);
4202 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4203 phy_ctrl);
4204 }
4205 }
4206 return;
96838a40 4207 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4208 /* If still no link, perhaps using 2/3 pair cable */
4209 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4210 phy_ctrl |= CR_1000T_MS_ENABLE;
4211 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4212 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4213 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4214 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4215 MII_CR_RESTART_AUTO_NEG);
4216 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4217 }
4218 }
4219 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4220 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4221 adapter->smartspeed = 0;
4222}
4223
4224/**
4225 * e1000_ioctl -
4226 * @netdev:
4227 * @ifreq:
4228 * @cmd:
4229 **/
4230
4231static int
4232e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4233{
4234 switch (cmd) {
4235 case SIOCGMIIPHY:
4236 case SIOCGMIIREG:
4237 case SIOCSMIIREG:
4238 return e1000_mii_ioctl(netdev, ifr, cmd);
4239 default:
4240 return -EOPNOTSUPP;
4241 }
4242}
4243
4244/**
4245 * e1000_mii_ioctl -
4246 * @netdev:
4247 * @ifreq:
4248 * @cmd:
4249 **/
4250
4251static int
4252e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4253{
60490fe0 4254 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4255 struct mii_ioctl_data *data = if_mii(ifr);
4256 int retval;
4257 uint16_t mii_reg;
4258 uint16_t spddplx;
97876fc6 4259 unsigned long flags;
1da177e4 4260
96838a40 4261 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4262 return -EOPNOTSUPP;
4263
4264 switch (cmd) {
4265 case SIOCGMIIPHY:
4266 data->phy_id = adapter->hw.phy_addr;
4267 break;
4268 case SIOCGMIIREG:
96838a40 4269 if (!capable(CAP_NET_ADMIN))
1da177e4 4270 return -EPERM;
97876fc6 4271 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4272 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4273 &data->val_out)) {
4274 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4275 return -EIO;
97876fc6
MC		 4276 }
4277 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4278 break;
4279 case SIOCSMIIREG:
96838a40 4280 if (!capable(CAP_NET_ADMIN))
1da177e4 4281 return -EPERM;
96838a40 4282 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4283 return -EFAULT;
4284 mii_reg = data->val_in;
97876fc6 4285 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4286 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4287 mii_reg)) {
4288 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4289 return -EIO;
97876fc6 4290 }
dc86d32a 4291 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4292 switch (data->reg_num) {
4293 case PHY_CTRL:
96838a40 4294 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4295 break;
96838a40 4296 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4297 adapter->hw.autoneg = 1;
4298 adapter->hw.autoneg_advertised = 0x2F;
4299 } else {
4300 if (mii_reg & 0x40)
4301 spddplx = SPEED_1000;
4302 else if (mii_reg & 0x2000)
4303 spddplx = SPEED_100;
4304 else
4305 spddplx = SPEED_10;
4306 spddplx += (mii_reg & 0x100)
cb764326
JK		 4307 ? DUPLEX_FULL :
4308 DUPLEX_HALF;
1da177e4
LT		 4309 retval = e1000_set_spd_dplx(adapter,
4310 spddplx);
96838a40 4311 if (retval) {
97876fc6 4312 spin_unlock_irqrestore(
96838a40 4313 &adapter->stats_lock,
97876fc6 4314 flags);
1da177e4 4315 return retval;
97876fc6 4316 }
1da177e4 4317 }
2db10a08
AK		 4318 if (netif_running(adapter->netdev))
4319 e1000_reinit_locked(adapter);
4320 else
1da177e4
LT		 4321 e1000_reset(adapter);
4322 break;
4323 case M88E1000_PHY_SPEC_CTRL:
4324 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4325 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4326 spin_unlock_irqrestore(
4327 &adapter->stats_lock, flags);
1da177e4 4328 return -EIO;
97876fc6 4329 }
1da177e4
LT		 4330 break;
4331 }
4332 } else {
4333 switch (data->reg_num) {
4334 case PHY_CTRL:
96838a40 4335 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4336 break;
2db10a08
AK		 4337 if (netif_running(adapter->netdev))
4338 e1000_reinit_locked(adapter);
4339 else
1da177e4
LT		 4340 e1000_reset(adapter);
4341 break;
4342 }
4343 }
97876fc6 4344 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4345 break;
4346 default:
4347 return -EOPNOTSUPP;
4348 }
4349 return E1000_SUCCESS;
4350}
4351
4352void
4353e1000_pci_set_mwi(struct e1000_hw *hw)
4354{
4355 struct e1000_adapter *adapter = hw->back;
2648345f 4356 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4357
96838a40 4358 if (ret_val)
2648345f 4359 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4360}
4361
4362void
4363e1000_pci_clear_mwi(struct e1000_hw *hw)
4364{
4365 struct e1000_adapter *adapter = hw->back;
4366
4367 pci_clear_mwi(adapter->pdev);
4368}
4369
4370void
4371e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4372{
4373 struct e1000_adapter *adapter = hw->back;
4374
4375 pci_read_config_word(adapter->pdev, reg, value);
4376}
4377
4378void
4379e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4380{
4381 struct e1000_adapter *adapter = hw->back;
4382
4383 pci_write_config_word(adapter->pdev, reg, *value);
4384}
4385
e4c780b1 4386#if 0
1da177e4
LT		 4387uint32_t
4388e1000_io_read(struct e1000_hw *hw, unsigned long port)
4389{
4390 return inl(port);
4391}
e4c780b1 4392#endif /* 0 */
1da177e4
LT		 4393
4394void
4395e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4396{
4397 outl(value, port);
4398}
4399
4400static void
4401e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4402{
60490fe0 4403 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4404 uint32_t ctrl, rctl;
4405
4406 e1000_irq_disable(adapter);
4407 adapter->vlgrp = grp;
4408
96838a40 4409 if (grp) {
1da177e4
LT		 4410 /* enable VLAN tag insert/strip */
4411 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4412 ctrl |= E1000_CTRL_VME;
4413 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4414
cd94dd0b 4415 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 4416 /* enable VLAN receive filtering */
4417 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4418 rctl |= E1000_RCTL_VFE;
4419 rctl &= ~E1000_RCTL_CFIEN;
4420 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4421 e1000_update_mng_vlan(adapter);
cd94dd0b 4422 }
1da177e4
LT		 4423 } else {
4424 /* disable VLAN tag insert/strip */
4425 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4426 ctrl &= ~E1000_CTRL_VME;
4427 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4428
cd94dd0b 4429 if (adapter->hw.mac_type != e1000_ich8lan) {
1da177e4
LT		 4430 /* disable VLAN filtering */
4431 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4432 rctl &= ~E1000_RCTL_VFE;
4433 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
96838a40 4434 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
2d7edb92
MC		 4435 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4436 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4437 }
cd94dd0b 4438 }
1da177e4
LT		 4439 }
4440
4441 e1000_irq_enable(adapter);
4442}
4443
4444static void
4445e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4446{
60490fe0 4447 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4448 uint32_t vfta, index;
96838a40
JB		 4449
4450 if ((adapter->hw.mng_cookie.status &
4451 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4452 (vid == adapter->mng_vlan_id))
2d7edb92 4453 return;
1da177e4
LT		 4454 /* add VID to filter table */
4455 index = (vid >> 5) & 0x7F;
4456 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4457 vfta |= (1 << (vid & 0x1F));
4458 e1000_write_vfta(&adapter->hw, index, vfta);
4459}
4460
4461static void
4462e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4463{
60490fe0 4464 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4465 uint32_t vfta, index;
4466
4467 e1000_irq_disable(adapter);
4468
96838a40 4469 if (adapter->vlgrp)
1da177e4
LT		 4470 adapter->vlgrp->vlan_devices[vid] = NULL;
4471
4472 e1000_irq_enable(adapter);
4473
96838a40
JB		 4474 if ((adapter->hw.mng_cookie.status &
4475 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4476 (vid == adapter->mng_vlan_id)) {
4477 /* release control to f/w */
4478 e1000_release_hw_control(adapter);
2d7edb92 4479 return;
ff147013
JK		 4480 }
4481
1da177e4
LT		 4482 /* remove VID from filter table */
4483 index = (vid >> 5) & 0x7F;
4484 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4485 vfta &= ~(1 << (vid & 0x1F));
4486 e1000_write_vfta(&adapter->hw, index, vfta);
4487}
4488
4489static void
4490e1000_restore_vlan(struct e1000_adapter *adapter)
4491{
4492 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4493
96838a40 4494 if (adapter->vlgrp) {
1da177e4 4495 uint16_t vid;
96838a40
JB		 4496 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4497 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4498 continue;
4499 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4500 }
4501 }
4502}
4503
4504int
4505e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4506{
4507 adapter->hw.autoneg = 0;
4508
6921368f 4509 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4510 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4511 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4512 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4513 return -EINVAL;
4514 }
4515
96838a40 4516 switch (spddplx) {
1da177e4
LT		 4517 case SPEED_10 + DUPLEX_HALF:
4518 adapter->hw.forced_speed_duplex = e1000_10_half;
4519 break;
4520 case SPEED_10 + DUPLEX_FULL:
4521 adapter->hw.forced_speed_duplex = e1000_10_full;
4522 break;
4523 case SPEED_100 + DUPLEX_HALF:
4524 adapter->hw.forced_speed_duplex = e1000_100_half;
4525 break;
4526 case SPEED_100 + DUPLEX_FULL:
4527 adapter->hw.forced_speed_duplex = e1000_100_full;
4528 break;
4529 case SPEED_1000 + DUPLEX_FULL:
4530 adapter->hw.autoneg = 1;
4531 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4532 break;
4533 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4534 default:
2648345f 4535 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4536 return -EINVAL;
4537 }
4538 return 0;
4539}
4540
b6a1d5f8 4541#ifdef CONFIG_PM
0f15a8fa
JK		 4542/* Save/restore 16 or 64 dwords of PCI config space depending on which
4543 * bus we're on (PCI(X) vs. PCI-E)
2f82665f
JB		 4544 */
4545#define PCIE_CONFIG_SPACE_LEN 256
4546#define PCI_CONFIG_SPACE_LEN 64
4547static int
4548e1000_pci_save_state(struct e1000_adapter *adapter)
4549{
4550 struct pci_dev *dev = adapter->pdev;
4551 int size;
4552 int i;
0f15a8fa 4553
2f82665f
JB		 4554 if (adapter->hw.mac_type >= e1000_82571)
4555 size = PCIE_CONFIG_SPACE_LEN;
4556 else
4557 size = PCI_CONFIG_SPACE_LEN;
4558
4559 WARN_ON(adapter->config_space != NULL);
4560
4561 adapter->config_space = kmalloc(size, GFP_KERNEL);
4562 if (!adapter->config_space) {
4563 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4564 return -ENOMEM;
4565 }
4566 for (i = 0; i < (size / 4); i++)
4567 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4568 return 0;
4569}
4570
4571static void
4572e1000_pci_restore_state(struct e1000_adapter *adapter)
4573{
4574 struct pci_dev *dev = adapter->pdev;
4575 int size;
4576 int i;
0f15a8fa 4577
2f82665f
JB		 4578 if (adapter->config_space == NULL)
4579 return;
0f15a8fa 4580
2f82665f
JB		 4581 if (adapter->hw.mac_type >= e1000_82571)
4582 size = PCIE_CONFIG_SPACE_LEN;
4583 else
4584 size = PCI_CONFIG_SPACE_LEN;
4585 for (i = 0; i < (size / 4); i++)
4586 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4587 kfree(adapter->config_space);
4588 adapter->config_space = NULL;
4589 return;
4590}
4591#endif /* CONFIG_PM */
4592
1da177e4 4593static int
829ca9a3 4594e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4595{
4596 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4597 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4598 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4599 uint32_t wufc = adapter->wol;
6fdfef16 4600#ifdef CONFIG_PM
240b1710 4601 int retval = 0;
6fdfef16 4602#endif
1da177e4
LT		 4603
4604 netif_device_detach(netdev);
4605
2db10a08
AK		 4606 if (netif_running(netdev)) {
4607 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 4608 e1000_down(adapter);
2db10a08 4609 }
1da177e4 4610
2f82665f 4611#ifdef CONFIG_PM
0f15a8fa
JK		 4612 /* Implement our own version of pci_save_state(pdev) because pci-
4613 * express adapters have 256-byte config spaces. */
2f82665f
JB		 4614 retval = e1000_pci_save_state(adapter);
4615 if (retval)
4616 return retval;
4617#endif
4618
1da177e4 4619 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4620 if (status & E1000_STATUS_LU)
1da177e4
LT		 4621 wufc &= ~E1000_WUFC_LNKC;
4622
96838a40 4623 if (wufc) {
1da177e4
LT		 4624 e1000_setup_rctl(adapter);
4625 e1000_set_multi(netdev);
4626
4627 /* turn on all-multi mode if wake on multicast is enabled */
96838a40 4628 if (adapter->wol & E1000_WUFC_MC) {
1da177e4
LT		 4629 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4630 rctl |= E1000_RCTL_MPE;
4631 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4632 }
4633
96838a40 4634 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4635 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4636 /* advertise wake from D3Cold */
4637 #define E1000_CTRL_ADVD3WUC 0x00100000
4638 /* phy power management enable */
4639 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4640 ctrl |= E1000_CTRL_ADVD3WUC |
4641 E1000_CTRL_EN_PHY_PWR_MGMT;
4642 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4643 }
4644
96838a40 4645 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4646 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4647 /* keep the laser running in D3 */
4648 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4649 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4650 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4651 }
4652
2d7edb92
MC		 4653 /* Allow time for pending master requests to run */
4654 e1000_disable_pciex_master(&adapter->hw);
4655
1da177e4
LT		 4656 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4657 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 4658 pci_enable_wake(pdev, PCI_D3hot, 1);
4659 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4660 } else {
4661 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4662 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 4663 pci_enable_wake(pdev, PCI_D3hot, 0);
4664 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4665 }
4666
cd94dd0b 4667 /* FIXME: this code is incorrect for PCI Express */
96838a40 4668 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 4669 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 4670 adapter->hw.media_type == e1000_media_type_copper) {
4671 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4672 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4673 manc |= E1000_MANC_ARP_EN;
4674 E1000_WRITE_REG(&adapter->hw, MANC, manc);
d0e027db
AK		 4675 pci_enable_wake(pdev, PCI_D3hot, 1);
4676 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4677 }
4678 }
4679
cd94dd0b
AK		 4680 if (adapter->hw.phy_type == e1000_phy_igp_3)
4681 e1000_phy_powerdown_workaround(&adapter->hw);
4682
b55ccb35
JK		 4683 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4684 * would have already happened in close and is redundant. */
4685 e1000_release_hw_control(adapter);
2d7edb92 4686
1da177e4 4687 pci_disable_device(pdev);
240b1710 4688
d0e027db 4689 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4690
4691 return 0;
4692}
4693
2f82665f 4694#ifdef CONFIG_PM
1da177e4
LT		 4695static int
4696e1000_resume(struct pci_dev *pdev)
4697{
4698 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4699 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4700 uint32_t manc, ret_val;
1da177e4 4701
d0e027db 4702 pci_set_power_state(pdev, PCI_D0);
2f82665f 4703 e1000_pci_restore_state(adapter);
2b02893e 4704 ret_val = pci_enable_device(pdev);
a4cb847d 4705 pci_set_master(pdev);
1da177e4 4706
d0e027db
AK		 4707 pci_enable_wake(pdev, PCI_D3hot, 0);
4708 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4709
4710 e1000_reset(adapter);
4711 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4712
96838a40 4713 if (netif_running(netdev))
1da177e4
LT		 4714 e1000_up(adapter);
4715
4716 netif_device_attach(netdev);
4717
cd94dd0b 4718 /* FIXME: this code is incorrect for PCI Express */
96838a40 4719 if (adapter->hw.mac_type >= e1000_82540 &&
cd94dd0b 4720 adapter->hw.mac_type != e1000_ich8lan &&
1da177e4
LT		 4721 adapter->hw.media_type == e1000_media_type_copper) {
4722 manc = E1000_READ_REG(&adapter->hw, MANC);
4723 manc &= ~(E1000_MANC_ARP_EN);
4724 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4725 }
4726
b55ccb35
JK		 4727 /* If the controller is 82573 and f/w is AMT, do not set
4728 * DRV_LOAD until the interface is up. For all other cases,
4729 * let the f/w know that the h/w is now under the control
4730 * of the driver. */
4731 if (adapter->hw.mac_type != e1000_82573 ||
4732 !e1000_check_mng_mode(&adapter->hw))
4733 e1000_get_hw_control(adapter);
2d7edb92 4734
1da177e4
LT		 4735 return 0;
4736}
4737#endif
c653e635
AK		 4738
4739static void e1000_shutdown(struct pci_dev *pdev)
4740{
4741 e1000_suspend(pdev, PMSG_SUSPEND);
4742}
4743
1da177e4
LT		 4744#ifdef CONFIG_NET_POLL_CONTROLLER
4745/*
4746 * Polling 'interrupt' - used by things like netconsole to send skbs
4747 * without having to re-enable interrupts. It's not called while
4748 * the interrupt routine is executing.
4749 */
4750static void
2648345f 4751e1000_netpoll(struct net_device *netdev)
1da177e4 4752{
60490fe0 4753 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 4754
1da177e4
LT		 4755 disable_irq(adapter->pdev->irq);
4756 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4757 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4758#ifndef CONFIG_E1000_NAPI
4759 adapter->clean_rx(adapter, adapter->rx_ring);
4760#endif
1da177e4
LT		 4761 enable_irq(adapter->pdev->irq);
4762}
4763#endif
4764
9026729b
AK		 4765/**
4766 * e1000_io_error_detected - called when PCI error is detected
4767 * @pdev: Pointer to PCI device
4768 * @state: The current pci conneection state
4769 *
4770 * This function is called after a PCI bus error affecting
4771 * this device has been detected.
4772 */
4773static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4774{
4775 struct net_device *netdev = pci_get_drvdata(pdev);
4776 struct e1000_adapter *adapter = netdev->priv;
4777
4778 netif_device_detach(netdev);
4779
4780 if (netif_running(netdev))
4781 e1000_down(adapter);
4782
4783 /* Request a slot slot reset. */
4784 return PCI_ERS_RESULT_NEED_RESET;
4785}
4786
4787/**
4788 * e1000_io_slot_reset - called after the pci bus has been reset.
4789 * @pdev: Pointer to PCI device
4790 *
4791 * Restart the card from scratch, as if from a cold-boot. Implementation
4792 * resembles the first-half of the e1000_resume routine.
4793 */
4794static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
4795{
4796 struct net_device *netdev = pci_get_drvdata(pdev);
4797 struct e1000_adapter *adapter = netdev->priv;
4798
4799 if (pci_enable_device(pdev)) {
4800 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
4801 return PCI_ERS_RESULT_DISCONNECT;
4802 }
4803 pci_set_master(pdev);
4804
4805 pci_enable_wake(pdev, 3, 0);
4806 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
4807
4808 /* Perform card reset only on one instance of the card */
4809 if (PCI_FUNC (pdev->devfn) != 0)
4810 return PCI_ERS_RESULT_RECOVERED;
4811
4812 e1000_reset(adapter);
4813 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4814
4815 return PCI_ERS_RESULT_RECOVERED;
4816}
4817
4818/**
4819 * e1000_io_resume - called when traffic can start flowing again.
4820 * @pdev: Pointer to PCI device
4821 *
4822 * This callback is called when the error recovery driver tells us that
4823 * its OK to resume normal operation. Implementation resembles the
4824 * second-half of the e1000_resume routine.
4825 */
4826static void e1000_io_resume(struct pci_dev *pdev)
4827{
4828 struct net_device *netdev = pci_get_drvdata(pdev);
4829 struct e1000_adapter *adapter = netdev->priv;
4830 uint32_t manc, swsm;
4831
4832 if (netif_running(netdev)) {
4833 if (e1000_up(adapter)) {
4834 printk("e1000: can't bring device back up after reset\n");
4835 return;
4836 }
4837 }
4838
4839 netif_device_attach(netdev);
4840
4841 if (adapter->hw.mac_type >= e1000_82540 &&
4842 adapter->hw.media_type == e1000_media_type_copper) {
4843 manc = E1000_READ_REG(&adapter->hw, MANC);
4844 manc &= ~(E1000_MANC_ARP_EN);
4845 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4846 }
4847
4848 switch (adapter->hw.mac_type) {
4849 case e1000_82573:
4850 swsm = E1000_READ_REG(&adapter->hw, SWSM);
4851 E1000_WRITE_REG(&adapter->hw, SWSM,
4852 swsm | E1000_SWSM_DRV_LOAD);
4853 break;
4854 default:
4855 break;
4856 }
4857
4858 if (netif_running(netdev))
4859 mod_timer(&adapter->watchdog_timer, jiffies);
4860}
4861
1da177e4 4862/* e1000_main.c */
Empty description
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