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e1000: fix loopback ethtool test
[linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
3d41e30a 4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <[email protected]>
3d41e30a 25 e1000-devel Mailing List <[email protected]>
1da177e4
LT		 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28*******************************************************************************/
29
30#include "e1000.h"
31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
440c052d 39#define DRV_VERSION "7.0.38-k4"DRIVERNAPI
1da177e4 40char e1000_driver_version[] = DRV_VERSION;
3d41e30a 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
51 INTEL_E1000_ETHERNET_DEVICE(0x1000),
52 INTEL_E1000_ETHERNET_DEVICE(0x1001),
53 INTEL_E1000_ETHERNET_DEVICE(0x1004),
54 INTEL_E1000_ETHERNET_DEVICE(0x1008),
55 INTEL_E1000_ETHERNET_DEVICE(0x1009),
56 INTEL_E1000_ETHERNET_DEVICE(0x100C),
57 INTEL_E1000_ETHERNET_DEVICE(0x100D),
58 INTEL_E1000_ETHERNET_DEVICE(0x100E),
59 INTEL_E1000_ETHERNET_DEVICE(0x100F),
60 INTEL_E1000_ETHERNET_DEVICE(0x1010),
61 INTEL_E1000_ETHERNET_DEVICE(0x1011),
62 INTEL_E1000_ETHERNET_DEVICE(0x1012),
63 INTEL_E1000_ETHERNET_DEVICE(0x1013),
64 INTEL_E1000_ETHERNET_DEVICE(0x1014),
65 INTEL_E1000_ETHERNET_DEVICE(0x1015),
66 INTEL_E1000_ETHERNET_DEVICE(0x1016),
67 INTEL_E1000_ETHERNET_DEVICE(0x1017),
68 INTEL_E1000_ETHERNET_DEVICE(0x1018),
69 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 70 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 71 INTEL_E1000_ETHERNET_DEVICE(0x101D),
72 INTEL_E1000_ETHERNET_DEVICE(0x101E),
73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 76 INTEL_E1000_ETHERNET_DEVICE(0x105E),
77 INTEL_E1000_ETHERNET_DEVICE(0x105F),
78 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 79 INTEL_E1000_ETHERNET_DEVICE(0x1075),
80 INTEL_E1000_ETHERNET_DEVICE(0x1076),
81 INTEL_E1000_ETHERNET_DEVICE(0x1077),
82 INTEL_E1000_ETHERNET_DEVICE(0x1078),
83 INTEL_E1000_ETHERNET_DEVICE(0x1079),
84 INTEL_E1000_ETHERNET_DEVICE(0x107A),
85 INTEL_E1000_ETHERNET_DEVICE(0x107B),
86 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 87 INTEL_E1000_ETHERNET_DEVICE(0x107D),
88 INTEL_E1000_ETHERNET_DEVICE(0x107E),
89 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 90 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 91 INTEL_E1000_ETHERNET_DEVICE(0x108B),
92 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 93 INTEL_E1000_ETHERNET_DEVICE(0x1096),
94 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 95 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 96 INTEL_E1000_ETHERNET_DEVICE(0x109A),
b7ee49db 97 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 98 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
1da177e4
LT		 99 /* required last entry */
100 {0,}
101};
102
103MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
104
3ad2cc67 105static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 106 struct e1000_tx_ring *txdr);
3ad2cc67 107static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 108 struct e1000_rx_ring *rxdr);
3ad2cc67 109static void e1000_free_tx_resources(struct e1000_adapter *adapter,
0f15a8fa 110 struct e1000_tx_ring *tx_ring);
3ad2cc67 111static void e1000_free_rx_resources(struct e1000_adapter *adapter,
0f15a8fa 112 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 113
114/* Local Function Prototypes */
115
116static int e1000_init_module(void);
117static void e1000_exit_module(void);
118static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
119static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 120static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 121static int e1000_sw_init(struct e1000_adapter *adapter);
122static int e1000_open(struct net_device *netdev);
123static int e1000_close(struct net_device *netdev);
124static void e1000_configure_tx(struct e1000_adapter *adapter);
125static void e1000_configure_rx(struct e1000_adapter *adapter);
126static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 127static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
128static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
129static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
130 struct e1000_tx_ring *tx_ring);
131static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
132 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 133static void e1000_set_multi(struct net_device *netdev);
134static void e1000_update_phy_info(unsigned long data);
135static void e1000_watchdog(unsigned long data);
136static void e1000_watchdog_task(struct e1000_adapter *adapter);
137static void e1000_82547_tx_fifo_stall(unsigned long data);
138static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
139static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
140static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
141static int e1000_set_mac(struct net_device *netdev, void *p);
142static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 143static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
144 struct e1000_tx_ring *tx_ring);
1da177e4 145#ifdef CONFIG_E1000_NAPI
581d708e 146static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 147static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 148 struct e1000_rx_ring *rx_ring,
1da177e4 149 int *work_done, int work_to_do);
2d7edb92 150static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 151 struct e1000_rx_ring *rx_ring,
2d7edb92 152 int *work_done, int work_to_do);
1da177e4 153#else
581d708e
MC		 154static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
155 struct e1000_rx_ring *rx_ring);
156static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
157 struct e1000_rx_ring *rx_ring);
1da177e4 158#endif
581d708e 159static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 160 struct e1000_rx_ring *rx_ring,
161 int cleaned_count);
581d708e 162static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 163 struct e1000_rx_ring *rx_ring,
164 int cleaned_count);
1da177e4
LT		 165static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
166static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
167 int cmd);
1da177e4
LT		 168static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
169static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
170static void e1000_tx_timeout(struct net_device *dev);
87041639 171static void e1000_reset_task(struct net_device *dev);
1da177e4 172static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 173static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
174 struct sk_buff *skb);
1da177e4
LT		 175
176static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
177static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
178static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
179static void e1000_restore_vlan(struct e1000_adapter *adapter);
180
1da177e4 181#ifdef CONFIG_PM
977e74b5 182static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 183static int e1000_resume(struct pci_dev *pdev);
184#endif
c653e635 185static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 186
187#ifdef CONFIG_NET_POLL_CONTROLLER
188/* for netdump / net console */
189static void e1000_netpoll (struct net_device *netdev);
190#endif
191
9026729b
AK		 192static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
193 pci_channel_state_t state);
194static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
195static void e1000_io_resume(struct pci_dev *pdev);
196
197static struct pci_error_handlers e1000_err_handler = {
198 .error_detected = e1000_io_error_detected,
199 .slot_reset = e1000_io_slot_reset,
200 .resume = e1000_io_resume,
201};
24025e4e 202
1da177e4
LT		 203static struct pci_driver e1000_driver = {
204 .name = e1000_driver_name,
205 .id_table = e1000_pci_tbl,
206 .probe = e1000_probe,
207 .remove = __devexit_p(e1000_remove),
208 /* Power Managment Hooks */
209#ifdef CONFIG_PM
210 .suspend = e1000_suspend,
c653e635 211 .resume = e1000_resume,
1da177e4 212#endif
9026729b
AK		 213 .shutdown = e1000_shutdown,
214 .err_handler = &e1000_err_handler
1da177e4
LT		 215};
216
217MODULE_AUTHOR("Intel Corporation, <[email protected]>");
218MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
219MODULE_LICENSE("GPL");
220MODULE_VERSION(DRV_VERSION);
221
222static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
223module_param(debug, int, 0);
224MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
225
226/**
227 * e1000_init_module - Driver Registration Routine
228 *
229 * e1000_init_module is the first routine called when the driver is
230 * loaded. All it does is register with the PCI subsystem.
231 **/
232
233static int __init
234e1000_init_module(void)
235{
236 int ret;
237 printk(KERN_INFO "%s - version %s\n",
238 e1000_driver_string, e1000_driver_version);
239
240 printk(KERN_INFO "%s\n", e1000_copyright);
241
242 ret = pci_module_init(&e1000_driver);
8b378def 243
1da177e4
LT		 244 return ret;
245}
246
247module_init(e1000_init_module);
248
249/**
250 * e1000_exit_module - Driver Exit Cleanup Routine
251 *
252 * e1000_exit_module is called just before the driver is removed
253 * from memory.
254 **/
255
256static void __exit
257e1000_exit_module(void)
258{
1da177e4
LT		 259 pci_unregister_driver(&e1000_driver);
260}
261
262module_exit(e1000_exit_module);
263
264/**
265 * e1000_irq_disable - Mask off interrupt generation on the NIC
266 * @adapter: board private structure
267 **/
268
e619d523 269static void
1da177e4
LT		 270e1000_irq_disable(struct e1000_adapter *adapter)
271{
272 atomic_inc(&adapter->irq_sem);
273 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
274 E1000_WRITE_FLUSH(&adapter->hw);
275 synchronize_irq(adapter->pdev->irq);
276}
277
278/**
279 * e1000_irq_enable - Enable default interrupt generation settings
280 * @adapter: board private structure
281 **/
282
e619d523 283static void
1da177e4
LT		 284e1000_irq_enable(struct e1000_adapter *adapter)
285{
96838a40 286 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 287 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
288 E1000_WRITE_FLUSH(&adapter->hw);
289 }
290}
3ad2cc67
AB		 291
292static void
2d7edb92
MC		 293e1000_update_mng_vlan(struct e1000_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
297 uint16_t old_vid = adapter->mng_vlan_id;
96838a40
JB		 298 if (adapter->vlgrp) {
299 if (!adapter->vlgrp->vlan_devices[vid]) {
300 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 301 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
302 e1000_vlan_rx_add_vid(netdev, vid);
303 adapter->mng_vlan_id = vid;
304 } else
305 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 306
307 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
308 (vid != old_vid) &&
2d7edb92
MC		 309 !adapter->vlgrp->vlan_devices[old_vid])
310 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 311 } else
312 adapter->mng_vlan_id = vid;
2d7edb92
MC		 313 }
314}
b55ccb35
JK		 315
316/**
317 * e1000_release_hw_control - release control of the h/w to f/w
318 * @adapter: address of board private structure
319 *
320 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
321 * For ASF and Pass Through versions of f/w this means that the
322 * driver is no longer loaded. For AMT version (only with 82573) i
323 * of the f/w this means that the netowrk i/f is closed.
76c224bc 324 *
b55ccb35
JK		 325 **/
326
e619d523 327static void
b55ccb35
JK		 328e1000_release_hw_control(struct e1000_adapter *adapter)
329{
330 uint32_t ctrl_ext;
331 uint32_t swsm;
332
333 /* Let firmware taken over control of h/w */
334 switch (adapter->hw.mac_type) {
335 case e1000_82571:
336 case e1000_82572:
4cc15f54 337 case e1000_80003es2lan:
b55ccb35
JK		 338 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
339 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
340 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
341 break;
342 case e1000_82573:
343 swsm = E1000_READ_REG(&adapter->hw, SWSM);
344 E1000_WRITE_REG(&adapter->hw, SWSM,
345 swsm & ~E1000_SWSM_DRV_LOAD);
346 default:
347 break;
348 }
349}
350
351/**
352 * e1000_get_hw_control - get control of the h/w from f/w
353 * @adapter: address of board private structure
354 *
355 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 356 * For ASF and Pass Through versions of f/w this means that
357 * the driver is loaded. For AMT version (only with 82573)
b55ccb35 358 * of the f/w this means that the netowrk i/f is open.
76c224bc 359 *
b55ccb35
JK		 360 **/
361
e619d523 362static void
b55ccb35
JK		 363e1000_get_hw_control(struct e1000_adapter *adapter)
364{
365 uint32_t ctrl_ext;
366 uint32_t swsm;
367 /* Let firmware know the driver has taken over */
368 switch (adapter->hw.mac_type) {
369 case e1000_82571:
370 case e1000_82572:
4cc15f54 371 case e1000_80003es2lan:
b55ccb35
JK		 372 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
373 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
374 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
375 break;
376 case e1000_82573:
377 swsm = E1000_READ_REG(&adapter->hw, SWSM);
378 E1000_WRITE_REG(&adapter->hw, SWSM,
379 swsm | E1000_SWSM_DRV_LOAD);
380 break;
381 default:
382 break;
383 }
384}
385
1da177e4
LT		 386int
387e1000_up(struct e1000_adapter *adapter)
388{
389 struct net_device *netdev = adapter->netdev;
581d708e 390 int i, err;
1da177e4
LT		 391
392 /* hardware has been reset, we need to reload some things */
393
394 /* Reset the PHY if it was previously powered down */
96838a40 395 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 396 uint16_t mii_reg;
397 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
96838a40 398 if (mii_reg & MII_CR_POWER_DOWN)
4cc15f54 399 e1000_phy_hw_reset(&adapter->hw);
1da177e4
LT		 400 }
401
402 e1000_set_multi(netdev);
403
404 e1000_restore_vlan(adapter);
405
406 e1000_configure_tx(adapter);
407 e1000_setup_rctl(adapter);
408 e1000_configure_rx(adapter);
72d64a43
JK		 409 /* call E1000_DESC_UNUSED which always leaves
410 * at least 1 descriptor unused to make sure
411 * next_to_use != next_to_clean */
f56799ea 412 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 413 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 414 adapter->alloc_rx_buf(adapter, ring,
415 E1000_DESC_UNUSED(ring));
f56799ea 416 }
1da177e4 417
fa4f7ef3 418#ifdef CONFIG_PCI_MSI
96838a40 419 if (adapter->hw.mac_type > e1000_82547_rev_2) {
fa4f7ef3 420 adapter->have_msi = TRUE;
96838a40 421 if ((err = pci_enable_msi(adapter->pdev))) {
fa4f7ef3
MC		 422 DPRINTK(PROBE, ERR,
423 "Unable to allocate MSI interrupt Error: %d\n", err);
424 adapter->have_msi = FALSE;
425 }
426 }
427#endif
96838a40 428 if ((err = request_irq(adapter->pdev->irq, &e1000_intr,
1da177e4 429 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 430 netdev->name, netdev))) {
431 DPRINTK(PROBE, ERR,
432 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 433 return err;
2648345f 434 }
1da177e4 435
7bfa4816
JK		 436 adapter->tx_queue_len = netdev->tx_queue_len;
437
1da177e4 438 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 439
440#ifdef CONFIG_E1000_NAPI
441 netif_poll_enable(netdev);
442#endif
5de55624
MC		 443 e1000_irq_enable(adapter);
444
1da177e4
LT		 445 return 0;
446}
447
448void
449e1000_down(struct e1000_adapter *adapter)
450{
451 struct net_device *netdev = adapter->netdev;
57128197
JK		 452 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
453 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 454
455 e1000_irq_disable(adapter);
c1605eb3 456
1da177e4 457 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3 458#ifdef CONFIG_PCI_MSI
96838a40 459 if (adapter->hw.mac_type > e1000_82547_rev_2 &&
fa4f7ef3
MC		 460 adapter->have_msi == TRUE)
461 pci_disable_msi(adapter->pdev);
462#endif
1da177e4
LT		 463 del_timer_sync(&adapter->tx_fifo_stall_timer);
464 del_timer_sync(&adapter->watchdog_timer);
465 del_timer_sync(&adapter->phy_info_timer);
466
467#ifdef CONFIG_E1000_NAPI
468 netif_poll_disable(netdev);
469#endif
7bfa4816 470 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 471 adapter->link_speed = 0;
472 adapter->link_duplex = 0;
473 netif_carrier_off(netdev);
474 netif_stop_queue(netdev);
475
476 e1000_reset(adapter);
581d708e
MC		 477 e1000_clean_all_tx_rings(adapter);
478 e1000_clean_all_rx_rings(adapter);
1da177e4 479
57128197
JK		 480 /* Power down the PHY so no link is implied when interface is down *
481 * The PHY cannot be powered down if any of the following is TRUE *
482 * (a) WoL is enabled
483 * (b) AMT is active
484 * (c) SoL/IDER session is active */
485 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 486 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 487 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
488 !mng_mode_enabled &&
489 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 490 uint16_t mii_reg;
491 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
492 mii_reg |= MII_CR_POWER_DOWN;
493 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 494 mdelay(1);
1da177e4
LT		 495 }
496}
497
498void
499e1000_reset(struct e1000_adapter *adapter)
500{
2d7edb92 501 uint32_t pba, manc;
1125ecbc 502 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
1da177e4
LT		 503
504 /* Repartition Pba for greater than 9k mtu
505 * To take effect CTRL.RST is required.
506 */
507
2d7edb92
MC		 508 switch (adapter->hw.mac_type) {
509 case e1000_82547:
0e6ef3e0 510 case e1000_82547_rev_2:
2d7edb92
MC		 511 pba = E1000_PBA_30K;
512 break;
868d5309
MC		 513 case e1000_82571:
514 case e1000_82572:
6418ecc6 515 case e1000_80003es2lan:
868d5309
MC		 516 pba = E1000_PBA_38K;
517 break;
2d7edb92
MC		 518 case e1000_82573:
519 pba = E1000_PBA_12K;
520 break;
521 default:
522 pba = E1000_PBA_48K;
523 break;
524 }
525
96838a40 526 if ((adapter->hw.mac_type != e1000_82573) &&
f11b7f85 527 (adapter->netdev->mtu > E1000_RXBUFFER_8192))
1125ecbc 528 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92
MC		 529
530
96838a40 531 if (adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 532 adapter->tx_fifo_head = 0;
533 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
534 adapter->tx_fifo_size =
535 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
536 atomic_set(&adapter->tx_fifo_stall, 0);
537 }
2d7edb92 538
1da177e4
LT		 539 E1000_WRITE_REG(&adapter->hw, PBA, pba);
540
541 /* flow control settings */
f11b7f85
JK		 542 /* Set the FC high water mark to 90% of the FIFO size.
543 * Required to clear last 3 LSB */
544 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
545
546 adapter->hw.fc_high_water = fc_high_water_mark;
547 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 548 if (adapter->hw.mac_type == e1000_80003es2lan)
549 adapter->hw.fc_pause_time = 0xFFFF;
550 else
551 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 552 adapter->hw.fc_send_xon = 1;
553 adapter->hw.fc = adapter->hw.original_fc;
554
2d7edb92 555 /* Allow time for pending master requests to run */
1da177e4 556 e1000_reset_hw(&adapter->hw);
96838a40 557 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 558 E1000_WRITE_REG(&adapter->hw, WUC, 0);
96838a40 559 if (e1000_init_hw(&adapter->hw))
1da177e4 560 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 561 e1000_update_mng_vlan(adapter);
1da177e4
LT		 562 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
563 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
564
565 e1000_reset_adaptive(&adapter->hw);
566 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 567 if (adapter->en_mng_pt) {
568 manc = E1000_READ_REG(&adapter->hw, MANC);
569 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
570 E1000_WRITE_REG(&adapter->hw, MANC, manc);
571 }
1da177e4
LT		 572}
573
574/**
575 * e1000_probe - Device Initialization Routine
576 * @pdev: PCI device information struct
577 * @ent: entry in e1000_pci_tbl
578 *
579 * Returns 0 on success, negative on failure
580 *
581 * e1000_probe initializes an adapter identified by a pci_dev structure.
582 * The OS initialization, configuring of the adapter private structure,
583 * and a hardware reset occur.
584 **/
585
586static int __devinit
587e1000_probe(struct pci_dev *pdev,
588 const struct pci_device_id *ent)
589{
590 struct net_device *netdev;
591 struct e1000_adapter *adapter;
2d7edb92 592 unsigned long mmio_start, mmio_len;
2d7edb92 593
1da177e4 594 static int cards_found = 0;
84916829 595 static int e1000_ksp3_port_a = 0; /* global ksp3 port a indication */
2d7edb92 596 int i, err, pci_using_dac;
1da177e4
LT		 597 uint16_t eeprom_data;
598 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 599 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 600 return err;
601
96838a40 602 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 603 pci_using_dac = 1;
604 } else {
96838a40 605 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 606 E1000_ERR("No usable DMA configuration, aborting\n");
607 return err;
608 }
609 pci_using_dac = 0;
610 }
611
96838a40 612 if ((err = pci_request_regions(pdev, e1000_driver_name)))
1da177e4
LT		 613 return err;
614
615 pci_set_master(pdev);
616
617 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
96838a40 618 if (!netdev) {
1da177e4
LT		 619 err = -ENOMEM;
620 goto err_alloc_etherdev;
621 }
622
623 SET_MODULE_OWNER(netdev);
624 SET_NETDEV_DEV(netdev, &pdev->dev);
625
626 pci_set_drvdata(pdev, netdev);
60490fe0 627 adapter = netdev_priv(netdev);
1da177e4
LT		 628 adapter->netdev = netdev;
629 adapter->pdev = pdev;
630 adapter->hw.back = adapter;
631 adapter->msg_enable = (1 << debug) - 1;
632
633 mmio_start = pci_resource_start(pdev, BAR_0);
634 mmio_len = pci_resource_len(pdev, BAR_0);
635
636 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
96838a40 637 if (!adapter->hw.hw_addr) {
1da177e4
LT		 638 err = -EIO;
639 goto err_ioremap;
640 }
641
96838a40
JB		 642 for (i = BAR_1; i <= BAR_5; i++) {
643 if (pci_resource_len(pdev, i) == 0)
1da177e4 644 continue;
96838a40 645 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 646 adapter->hw.io_base = pci_resource_start(pdev, i);
647 break;
648 }
649 }
650
651 netdev->open = &e1000_open;
652 netdev->stop = &e1000_close;
653 netdev->hard_start_xmit = &e1000_xmit_frame;
654 netdev->get_stats = &e1000_get_stats;
655 netdev->set_multicast_list = &e1000_set_multi;
656 netdev->set_mac_address = &e1000_set_mac;
657 netdev->change_mtu = &e1000_change_mtu;
658 netdev->do_ioctl = &e1000_ioctl;
659 e1000_set_ethtool_ops(netdev);
660 netdev->tx_timeout = &e1000_tx_timeout;
661 netdev->watchdog_timeo = 5 * HZ;
662#ifdef CONFIG_E1000_NAPI
663 netdev->poll = &e1000_clean;
664 netdev->weight = 64;
665#endif
666 netdev->vlan_rx_register = e1000_vlan_rx_register;
667 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
668 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
669#ifdef CONFIG_NET_POLL_CONTROLLER
670 netdev->poll_controller = e1000_netpoll;
671#endif
672 strcpy(netdev->name, pci_name(pdev));
673
674 netdev->mem_start = mmio_start;
675 netdev->mem_end = mmio_start + mmio_len;
676 netdev->base_addr = adapter->hw.io_base;
677
678 adapter->bd_number = cards_found;
679
680 /* setup the private structure */
681
96838a40 682 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 683 goto err_sw_init;
684
96838a40 685 if ((err = e1000_check_phy_reset_block(&adapter->hw)))
2d7edb92
MC		 686 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
687
84916829 688 /* if ksp3, indicate if it's port a being setup */
76c224bc
AK		 689 if (pdev->device == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 &&
690 e1000_ksp3_port_a == 0)
84916829
JK		 691 adapter->ksp3_port_a = 1;
692 e1000_ksp3_port_a++;
693 /* Reset for multiple KP3 adapters */
694 if (e1000_ksp3_port_a == 4)
695 e1000_ksp3_port_a = 0;
696
96838a40 697 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 698 netdev->features = NETIF_F_SG |
699 NETIF_F_HW_CSUM |
700 NETIF_F_HW_VLAN_TX |
701 NETIF_F_HW_VLAN_RX |
702 NETIF_F_HW_VLAN_FILTER;
703 }
704
705#ifdef NETIF_F_TSO
96838a40 706 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 707 (adapter->hw.mac_type != e1000_82547))
708 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 709
710#ifdef NETIF_F_TSO_IPV6
96838a40 711 if (adapter->hw.mac_type > e1000_82547_rev_2)
2d7edb92
MC		 712 netdev->features |= NETIF_F_TSO_IPV6;
713#endif
1da177e4 714#endif
96838a40 715 if (pci_using_dac)
1da177e4
LT		 716 netdev->features |= NETIF_F_HIGHDMA;
717
76c224bc
AK		 718 /* hard_start_xmit is safe against parallel locking */
719 netdev->features |= NETIF_F_LLTX;
720
2d7edb92
MC		 721 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
722
96838a40 723 /* before reading the EEPROM, reset the controller to
1da177e4 724 * put the device in a known good starting state */
96838a40 725
1da177e4
LT		 726 e1000_reset_hw(&adapter->hw);
727
728 /* make sure the EEPROM is good */
729
96838a40 730 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4
LT		 731 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
732 err = -EIO;
733 goto err_eeprom;
734 }
735
736 /* copy the MAC address out of the EEPROM */
737
96838a40 738 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 739 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
740 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 741 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 742
96838a40 743 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 744 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
745 err = -EIO;
746 goto err_eeprom;
747 }
748
749 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
750
751 e1000_get_bus_info(&adapter->hw);
752
753 init_timer(&adapter->tx_fifo_stall_timer);
754 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
755 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
756
757 init_timer(&adapter->watchdog_timer);
758 adapter->watchdog_timer.function = &e1000_watchdog;
759 adapter->watchdog_timer.data = (unsigned long) adapter;
760
761 INIT_WORK(&adapter->watchdog_task,
762 (void (*)(void *))e1000_watchdog_task, adapter);
763
764 init_timer(&adapter->phy_info_timer);
765 adapter->phy_info_timer.function = &e1000_update_phy_info;
766 adapter->phy_info_timer.data = (unsigned long) adapter;
767
87041639
JK		 768 INIT_WORK(&adapter->reset_task,
769 (void (*)(void *))e1000_reset_task, netdev);
1da177e4
LT		 770
771 /* we're going to reset, so assume we have no link for now */
772
773 netif_carrier_off(netdev);
774 netif_stop_queue(netdev);
775
776 e1000_check_options(adapter);
777
778 /* Initial Wake on LAN setting
779 * If APM wake is enabled in the EEPROM,
780 * enable the ACPI Magic Packet filter
781 */
782
96838a40 783 switch (adapter->hw.mac_type) {
1da177e4
LT		 784 case e1000_82542_rev2_0:
785 case e1000_82542_rev2_1:
786 case e1000_82543:
787 break;
788 case e1000_82544:
789 e1000_read_eeprom(&adapter->hw,
790 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
791 eeprom_apme_mask = E1000_EEPROM_82544_APM;
792 break;
793 case e1000_82546:
794 case e1000_82546_rev_3:
fd803241 795 case e1000_82571:
6418ecc6 796 case e1000_80003es2lan:
96838a40 797 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 798 e1000_read_eeprom(&adapter->hw,
799 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
800 break;
801 }
802 /* Fall Through */
803 default:
804 e1000_read_eeprom(&adapter->hw,
805 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
806 break;
807 }
96838a40 808 if (eeprom_data & eeprom_apme_mask)
1da177e4
LT		 809 adapter->wol |= E1000_WUFC_MAG;
810
fb3d47d4
JK		 811 /* print bus type/speed/width info */
812 {
813 struct e1000_hw *hw = &adapter->hw;
814 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
815 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
816 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
817 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
818 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
819 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
820 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
821 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
822 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
823 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
824 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
825 "32-bit"));
826 }
827
828 for (i = 0; i < 6; i++)
829 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
830
1da177e4
LT		 831 /* reset the hardware with the new settings */
832 e1000_reset(adapter);
833
b55ccb35
JK		 834 /* If the controller is 82573 and f/w is AMT, do not set
835 * DRV_LOAD until the interface is up. For all other cases,
836 * let the f/w know that the h/w is now under the control
837 * of the driver. */
838 if (adapter->hw.mac_type != e1000_82573 ||
839 !e1000_check_mng_mode(&adapter->hw))
840 e1000_get_hw_control(adapter);
2d7edb92 841
1da177e4 842 strcpy(netdev->name, "eth%d");
96838a40 843 if ((err = register_netdev(netdev)))
1da177e4
LT		 844 goto err_register;
845
846 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
847
848 cards_found++;
849 return 0;
850
851err_register:
852err_sw_init:
853err_eeprom:
854 iounmap(adapter->hw.hw_addr);
855err_ioremap:
856 free_netdev(netdev);
857err_alloc_etherdev:
858 pci_release_regions(pdev);
859 return err;
860}
861
862/**
863 * e1000_remove - Device Removal Routine
864 * @pdev: PCI device information struct
865 *
866 * e1000_remove is called by the PCI subsystem to alert the driver
867 * that it should release a PCI device. The could be caused by a
868 * Hot-Plug event, or because the driver is going to be removed from
869 * memory.
870 **/
871
872static void __devexit
873e1000_remove(struct pci_dev *pdev)
874{
875 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 876 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 877 uint32_t manc;
581d708e
MC		 878#ifdef CONFIG_E1000_NAPI
879 int i;
880#endif
1da177e4 881
be2b28ed
JG		 882 flush_scheduled_work();
883
96838a40 884 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 885 adapter->hw.media_type == e1000_media_type_copper) {
886 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 887 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 888 manc |= E1000_MANC_ARP_EN;
889 E1000_WRITE_REG(&adapter->hw, MANC, manc);
890 }
891 }
892
b55ccb35
JK		 893 /* Release control of h/w to f/w. If f/w is AMT enabled, this
894 * would have already happened in close and is redundant. */
895 e1000_release_hw_control(adapter);
2d7edb92 896
1da177e4 897 unregister_netdev(netdev);
581d708e 898#ifdef CONFIG_E1000_NAPI
f56799ea 899 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 900 dev_put(&adapter->polling_netdev[i]);
581d708e 901#endif
1da177e4 902
96838a40 903 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 904 e1000_phy_hw_reset(&adapter->hw);
1da177e4 905
24025e4e
MC		 906 kfree(adapter->tx_ring);
907 kfree(adapter->rx_ring);
908#ifdef CONFIG_E1000_NAPI
909 kfree(adapter->polling_netdev);
910#endif
911
1da177e4
LT		 912 iounmap(adapter->hw.hw_addr);
913 pci_release_regions(pdev);
914
915 free_netdev(netdev);
916
917 pci_disable_device(pdev);
918}
919
920/**
921 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
922 * @adapter: board private structure to initialize
923 *
924 * e1000_sw_init initializes the Adapter private data structure.
925 * Fields are initialized based on PCI device information and
926 * OS network device settings (MTU size).
927 **/
928
929static int __devinit
930e1000_sw_init(struct e1000_adapter *adapter)
931{
932 struct e1000_hw *hw = &adapter->hw;
933 struct net_device *netdev = adapter->netdev;
934 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 935#ifdef CONFIG_E1000_NAPI
936 int i;
937#endif
1da177e4
LT		 938
939 /* PCI config space info */
940
941 hw->vendor_id = pdev->vendor;
942 hw->device_id = pdev->device;
943 hw->subsystem_vendor_id = pdev->subsystem_vendor;
944 hw->subsystem_id = pdev->subsystem_device;
945
946 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
947
948 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
949
9e2feace
AK		 950 adapter->rx_buffer_len = MAXIMUM_ETHERNET_FRAME_SIZE;
951 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 952 hw->max_frame_size = netdev->mtu +
953 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
954 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
955
956 /* identify the MAC */
957
96838a40 958 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 959 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
960 return -EIO;
961 }
962
963 /* initialize eeprom parameters */
964
96838a40 965 if (e1000_init_eeprom_params(hw)) {
2d7edb92
MC		 966 E1000_ERR("EEPROM initialization failed\n");
967 return -EIO;
968 }
1da177e4 969
96838a40 970 switch (hw->mac_type) {
1da177e4
LT		 971 default:
972 break;
973 case e1000_82541:
974 case e1000_82547:
975 case e1000_82541_rev_2:
976 case e1000_82547_rev_2:
977 hw->phy_init_script = 1;
978 break;
979 }
980
981 e1000_set_media_type(hw);
982
983 hw->wait_autoneg_complete = FALSE;
984 hw->tbi_compatibility_en = TRUE;
985 hw->adaptive_ifs = TRUE;
986
987 /* Copper options */
988
96838a40 989 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 990 hw->mdix = AUTO_ALL_MODES;
991 hw->disable_polarity_correction = FALSE;
992 hw->master_slave = E1000_MASTER_SLAVE;
993 }
994
f56799ea
JK		 995 adapter->num_tx_queues = 1;
996 adapter->num_rx_queues = 1;
581d708e
MC		 997
998 if (e1000_alloc_queues(adapter)) {
999 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1000 return -ENOMEM;
1001 }
1002
1003#ifdef CONFIG_E1000_NAPI
f56799ea 1004 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1005 adapter->polling_netdev[i].priv = adapter;
1006 adapter->polling_netdev[i].poll = &e1000_clean;
1007 adapter->polling_netdev[i].weight = 64;
1008 dev_hold(&adapter->polling_netdev[i]);
1009 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1010 }
7bfa4816 1011 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1012#endif
1013
1da177e4
LT		 1014 atomic_set(&adapter->irq_sem, 1);
1015 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 1016
1017 return 0;
1018}
1019
581d708e
MC		 1020/**
1021 * e1000_alloc_queues - Allocate memory for all rings
1022 * @adapter: board private structure to initialize
1023 *
1024 * We allocate one ring per queue at run-time since we don't know the
1025 * number of queues at compile-time. The polling_netdev array is
1026 * intended for Multiqueue, but should work fine with a single queue.
1027 **/
1028
1029static int __devinit
1030e1000_alloc_queues(struct e1000_adapter *adapter)
1031{
1032 int size;
1033
f56799ea 1034 size = sizeof(struct e1000_tx_ring) * adapter->num_tx_queues;
581d708e
MC		 1035 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
1036 if (!adapter->tx_ring)
1037 return -ENOMEM;
1038 memset(adapter->tx_ring, 0, size);
1039
f56799ea 1040 size = sizeof(struct e1000_rx_ring) * adapter->num_rx_queues;
581d708e
MC		 1041 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
1042 if (!adapter->rx_ring) {
1043 kfree(adapter->tx_ring);
1044 return -ENOMEM;
1045 }
1046 memset(adapter->rx_ring, 0, size);
1047
1048#ifdef CONFIG_E1000_NAPI
f56799ea 1049 size = sizeof(struct net_device) * adapter->num_rx_queues;
581d708e
MC		 1050 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
1051 if (!adapter->polling_netdev) {
1052 kfree(adapter->tx_ring);
1053 kfree(adapter->rx_ring);
1054 return -ENOMEM;
1055 }
1056 memset(adapter->polling_netdev, 0, size);
1057#endif
1058
1059 return E1000_SUCCESS;
1060}
1061
1da177e4
LT		 1062/**
1063 * e1000_open - Called when a network interface is made active
1064 * @netdev: network interface device structure
1065 *
1066 * Returns 0 on success, negative value on failure
1067 *
1068 * The open entry point is called when a network interface is made
1069 * active by the system (IFF_UP). At this point all resources needed
1070 * for transmit and receive operations are allocated, the interrupt
1071 * handler is registered with the OS, the watchdog timer is started,
1072 * and the stack is notified that the interface is ready.
1073 **/
1074
1075static int
1076e1000_open(struct net_device *netdev)
1077{
60490fe0 1078 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1079 int err;
1080
1081 /* allocate transmit descriptors */
1082
581d708e 1083 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1084 goto err_setup_tx;
1085
1086 /* allocate receive descriptors */
1087
581d708e 1088 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1089 goto err_setup_rx;
1090
96838a40 1091 if ((err = e1000_up(adapter)))
1da177e4 1092 goto err_up;
2d7edb92 1093 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1094 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1095 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1096 e1000_update_mng_vlan(adapter);
1097 }
1da177e4 1098
b55ccb35
JK		 1099 /* If AMT is enabled, let the firmware know that the network
1100 * interface is now open */
1101 if (adapter->hw.mac_type == e1000_82573 &&
1102 e1000_check_mng_mode(&adapter->hw))
1103 e1000_get_hw_control(adapter);
1104
1da177e4
LT		 1105 return E1000_SUCCESS;
1106
1107err_up:
581d708e 1108 e1000_free_all_rx_resources(adapter);
1da177e4 1109err_setup_rx:
581d708e 1110 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1111err_setup_tx:
1112 e1000_reset(adapter);
1113
1114 return err;
1115}
1116
1117/**
1118 * e1000_close - Disables a network interface
1119 * @netdev: network interface device structure
1120 *
1121 * Returns 0, this is not allowed to fail
1122 *
1123 * The close entry point is called when an interface is de-activated
1124 * by the OS. The hardware is still under the drivers control, but
1125 * needs to be disabled. A global MAC reset is issued to stop the
1126 * hardware, and all transmit and receive resources are freed.
1127 **/
1128
1129static int
1130e1000_close(struct net_device *netdev)
1131{
60490fe0 1132 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1133
1134 e1000_down(adapter);
1135
581d708e
MC		 1136 e1000_free_all_tx_resources(adapter);
1137 e1000_free_all_rx_resources(adapter);
1da177e4 1138
96838a40 1139 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1140 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1141 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1142 }
b55ccb35
JK		 1143
1144 /* If AMT is enabled, let the firmware know that the network
1145 * interface is now closed */
1146 if (adapter->hw.mac_type == e1000_82573 &&
1147 e1000_check_mng_mode(&adapter->hw))
1148 e1000_release_hw_control(adapter);
1149
1da177e4
LT		 1150 return 0;
1151}
1152
1153/**
1154 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1155 * @adapter: address of board private structure
2d7edb92
MC		 1156 * @start: address of beginning of memory
1157 * @len: length of memory
1da177e4 1158 **/
e619d523 1159static boolean_t
1da177e4
LT		 1160e1000_check_64k_bound(struct e1000_adapter *adapter,
1161 void *start, unsigned long len)
1162{
1163 unsigned long begin = (unsigned long) start;
1164 unsigned long end = begin + len;
1165
2648345f
MC		 1166 /* First rev 82545 and 82546 need to not allow any memory
1167 * write location to cross 64k boundary due to errata 23 */
1da177e4 1168 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1169 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1170 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1171 }
1172
1173 return TRUE;
1174}
1175
1176/**
1177 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1178 * @adapter: board private structure
581d708e 1179 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1180 *
1181 * Return 0 on success, negative on failure
1182 **/
1183
3ad2cc67 1184static int
581d708e
MC		 1185e1000_setup_tx_resources(struct e1000_adapter *adapter,
1186 struct e1000_tx_ring *txdr)
1da177e4 1187{
1da177e4
LT		 1188 struct pci_dev *pdev = adapter->pdev;
1189 int size;
1190
1191 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1192
1193 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
96838a40 1194 if (!txdr->buffer_info) {
2648345f
MC		 1195 DPRINTK(PROBE, ERR,
1196 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1197 return -ENOMEM;
1198 }
1199 memset(txdr->buffer_info, 0, size);
1200
1201 /* round up to nearest 4K */
1202
1203 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1204 E1000_ROUNDUP(txdr->size, 4096);
1205
1206 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1207 if (!txdr->desc) {
1da177e4 1208setup_tx_desc_die:
1da177e4 1209 vfree(txdr->buffer_info);
2648345f
MC		 1210 DPRINTK(PROBE, ERR,
1211 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1212 return -ENOMEM;
1213 }
1214
2648345f 1215 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1216 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1217 void *olddesc = txdr->desc;
1218 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1219 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1220 "at %p\n", txdr->size, txdr->desc);
1221 /* Try again, without freeing the previous */
1da177e4 1222 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1223 /* Failed allocation, critical failure */
96838a40 1224 if (!txdr->desc) {
1da177e4
LT		 1225 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1226 goto setup_tx_desc_die;
1227 }
1228
1229 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1230 /* give up */
2648345f
MC		 1231 pci_free_consistent(pdev, txdr->size, txdr->desc,
1232 txdr->dma);
1da177e4
LT		 1233 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1234 DPRINTK(PROBE, ERR,
2648345f
MC		 1235 "Unable to allocate aligned memory "
1236 "for the transmit descriptor ring\n");
1da177e4
LT		 1237 vfree(txdr->buffer_info);
1238 return -ENOMEM;
1239 } else {
2648345f 1240 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1241 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1242 }
1243 }
1244 memset(txdr->desc, 0, txdr->size);
1245
1246 txdr->next_to_use = 0;
1247 txdr->next_to_clean = 0;
2ae76d98 1248 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1249
1250 return 0;
1251}
1252
581d708e
MC		 1253/**
1254 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1255 * (Descriptors) for all queues
1256 * @adapter: board private structure
1257 *
1258 * If this function returns with an error, then it's possible one or
1259 * more of the rings is populated (while the rest are not). It is the
1260 * callers duty to clean those orphaned rings.
1261 *
1262 * Return 0 on success, negative on failure
1263 **/
1264
1265int
1266e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1267{
1268 int i, err = 0;
1269
f56799ea 1270 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1271 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1272 if (err) {
1273 DPRINTK(PROBE, ERR,
1274 "Allocation for Tx Queue %u failed\n", i);
1275 break;
1276 }
1277 }
1278
1279 return err;
1280}
1281
1da177e4
LT		 1282/**
1283 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1284 * @adapter: board private structure
1285 *
1286 * Configure the Tx unit of the MAC after a reset.
1287 **/
1288
1289static void
1290e1000_configure_tx(struct e1000_adapter *adapter)
1291{
581d708e
MC		 1292 uint64_t tdba;
1293 struct e1000_hw *hw = &adapter->hw;
1294 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1295 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1296
1297 /* Setup the HW Tx Head and Tail descriptor pointers */
1298
f56799ea 1299 switch (adapter->num_tx_queues) {
24025e4e
MC		 1300 case 1:
1301 default:
581d708e
MC		 1302 tdba = adapter->tx_ring[0].dma;
1303 tdlen = adapter->tx_ring[0].count *
1304 sizeof(struct e1000_tx_desc);
1305 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1306 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1307 E1000_WRITE_REG(hw, TDLEN, tdlen);
1308 E1000_WRITE_REG(hw, TDH, 0);
1309 E1000_WRITE_REG(hw, TDT, 0);
1310 adapter->tx_ring[0].tdh = E1000_TDH;
1311 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1312 break;
1313 }
1da177e4
LT		 1314
1315 /* Set the default values for the Tx Inter Packet Gap timer */
1316
0fadb059
JK		 1317 if (hw->media_type == e1000_media_type_fiber ||
1318 hw->media_type == e1000_media_type_internal_serdes)
1319 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1320 else
1321 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1322
581d708e 1323 switch (hw->mac_type) {
1da177e4
LT		 1324 case e1000_82542_rev2_0:
1325 case e1000_82542_rev2_1:
1326 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1327 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1328 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1329 break;
87041639
JK		 1330 case e1000_80003es2lan:
1331 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1332 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1333 break;
1da177e4 1334 default:
0fadb059
JK		 1335 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1336 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1337 break;
1da177e4 1338 }
0fadb059
JK		 1339 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1340 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1341 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1342
1343 /* Set the Tx Interrupt Delay register */
1344
581d708e
MC		 1345 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1346 if (hw->mac_type >= e1000_82540)
1347 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1348
1349 /* Program the Transmit Control Register */
1350
581d708e 1351 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1352
1353 tctl &= ~E1000_TCTL_CT;
7e6c9861 1354 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1355 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1356
7e6c9861
JK		 1357#ifdef DISABLE_MULR
1358 /* disable Multiple Reads for debugging */
1359 tctl &= ~E1000_TCTL_MULR;
1360#endif
1da177e4 1361
2ae76d98
MC		 1362 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1363 tarc = E1000_READ_REG(hw, TARC0);
1364 tarc |= ((1 << 25) | (1 << 21));
1365 E1000_WRITE_REG(hw, TARC0, tarc);
1366 tarc = E1000_READ_REG(hw, TARC1);
1367 tarc |= (1 << 25);
1368 if (tctl & E1000_TCTL_MULR)
1369 tarc &= ~(1 << 28);
1370 else
1371 tarc |= (1 << 28);
1372 E1000_WRITE_REG(hw, TARC1, tarc);
87041639
JK		 1373 } else if (hw->mac_type == e1000_80003es2lan) {
1374 tarc = E1000_READ_REG(hw, TARC0);
1375 tarc |= 1;
1376 if (hw->media_type == e1000_media_type_internal_serdes)
1377 tarc |= (1 << 20);
1378 E1000_WRITE_REG(hw, TARC0, tarc);
1379 tarc = E1000_READ_REG(hw, TARC1);
1380 tarc |= 1;
1381 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1382 }
1383
581d708e 1384 e1000_config_collision_dist(hw);
1da177e4
LT		 1385
1386 /* Setup Transmit Descriptor Settings for eop descriptor */
1387 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1388 E1000_TXD_CMD_IFCS;
1389
581d708e 1390 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1391 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1392 else
1393 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1394
1395 /* Cache if we're 82544 running in PCI-X because we'll
1396 * need this to apply a workaround later in the send path. */
581d708e
MC		 1397 if (hw->mac_type == e1000_82544 &&
1398 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1399 adapter->pcix_82544 = 1;
7e6c9861
JK		 1400
1401 E1000_WRITE_REG(hw, TCTL, tctl);
1402
1da177e4
LT		 1403}
1404
1405/**
1406 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1407 * @adapter: board private structure
581d708e 1408 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1409 *
1410 * Returns 0 on success, negative on failure
1411 **/
1412
3ad2cc67 1413static int
581d708e
MC		 1414e1000_setup_rx_resources(struct e1000_adapter *adapter,
1415 struct e1000_rx_ring *rxdr)
1da177e4 1416{
1da177e4 1417 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1418 int size, desc_len;
1da177e4
LT		 1419
1420 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1421 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1422 if (!rxdr->buffer_info) {
2648345f
MC		 1423 DPRINTK(PROBE, ERR,
1424 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1425 return -ENOMEM;
1426 }
1427 memset(rxdr->buffer_info, 0, size);
1428
2d7edb92
MC		 1429 size = sizeof(struct e1000_ps_page) * rxdr->count;
1430 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
96838a40 1431 if (!rxdr->ps_page) {
2d7edb92
MC		 1432 vfree(rxdr->buffer_info);
1433 DPRINTK(PROBE, ERR,
1434 "Unable to allocate memory for the receive descriptor ring\n");
1435 return -ENOMEM;
1436 }
1437 memset(rxdr->ps_page, 0, size);
1438
1439 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1440 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
96838a40 1441 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1442 vfree(rxdr->buffer_info);
1443 kfree(rxdr->ps_page);
1444 DPRINTK(PROBE, ERR,
1445 "Unable to allocate memory for the receive descriptor ring\n");
1446 return -ENOMEM;
1447 }
1448 memset(rxdr->ps_page_dma, 0, size);
1449
96838a40 1450 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1451 desc_len = sizeof(struct e1000_rx_desc);
1452 else
1453 desc_len = sizeof(union e1000_rx_desc_packet_split);
1454
1da177e4
LT		 1455 /* Round up to nearest 4K */
1456
2d7edb92 1457 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1458 E1000_ROUNDUP(rxdr->size, 4096);
1459
1460 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1461
581d708e
MC		 1462 if (!rxdr->desc) {
1463 DPRINTK(PROBE, ERR,
1464 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1465setup_rx_desc_die:
1da177e4 1466 vfree(rxdr->buffer_info);
2d7edb92
MC		 1467 kfree(rxdr->ps_page);
1468 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1469 return -ENOMEM;
1470 }
1471
2648345f 1472 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1473 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1474 void *olddesc = rxdr->desc;
1475 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1476 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1477 "at %p\n", rxdr->size, rxdr->desc);
1478 /* Try again, without freeing the previous */
1da177e4 1479 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1480 /* Failed allocation, critical failure */
581d708e 1481 if (!rxdr->desc) {
1da177e4 1482 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1483 DPRINTK(PROBE, ERR,
1484 "Unable to allocate memory "
1485 "for the receive descriptor ring\n");
1da177e4
LT		 1486 goto setup_rx_desc_die;
1487 }
1488
1489 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1490 /* give up */
2648345f
MC		 1491 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1492 rxdr->dma);
1da177e4 1493 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1494 DPRINTK(PROBE, ERR,
1495 "Unable to allocate aligned memory "
1496 "for the receive descriptor ring\n");
581d708e 1497 goto setup_rx_desc_die;
1da177e4 1498 } else {
2648345f 1499 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1500 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1501 }
1502 }
1503 memset(rxdr->desc, 0, rxdr->size);
1504
1505 rxdr->next_to_clean = 0;
1506 rxdr->next_to_use = 0;
1507
1508 return 0;
1509}
1510
581d708e
MC		 1511/**
1512 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1513 * (Descriptors) for all queues
1514 * @adapter: board private structure
1515 *
1516 * If this function returns with an error, then it's possible one or
1517 * more of the rings is populated (while the rest are not). It is the
1518 * callers duty to clean those orphaned rings.
1519 *
1520 * Return 0 on success, negative on failure
1521 **/
1522
1523int
1524e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1525{
1526 int i, err = 0;
1527
f56799ea 1528 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1529 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1530 if (err) {
1531 DPRINTK(PROBE, ERR,
1532 "Allocation for Rx Queue %u failed\n", i);
1533 break;
1534 }
1535 }
1536
1537 return err;
1538}
1539
1da177e4 1540/**
2648345f 1541 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1542 * @adapter: Board private structure
1543 **/
e4c811c9
MC		 1544#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1545 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1546static void
1547e1000_setup_rctl(struct e1000_adapter *adapter)
1548{
2d7edb92
MC		 1549 uint32_t rctl, rfctl;
1550 uint32_t psrctl = 0;
35ec56bb 1551#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1552 uint32_t pages = 0;
1553#endif
1da177e4
LT		 1554
1555 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1556
1557 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1558
1559 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1560 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1561 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1562
0fadb059
JK		 1563 if (adapter->hw.mac_type > e1000_82543)
1564 rctl |= E1000_RCTL_SECRC;
1565
1566 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1567 rctl |= E1000_RCTL_SBP;
1568 else
1569 rctl &= ~E1000_RCTL_SBP;
1570
2d7edb92
MC		 1571 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1572 rctl &= ~E1000_RCTL_LPE;
1573 else
1574 rctl |= E1000_RCTL_LPE;
1575
1da177e4 1576 /* Setup buffer sizes */
9e2feace
AK		 1577 rctl &= ~E1000_RCTL_SZ_4096;
1578 rctl |= E1000_RCTL_BSEX;
1579 switch (adapter->rx_buffer_len) {
1580 case E1000_RXBUFFER_256:
1581 rctl |= E1000_RCTL_SZ_256;
1582 rctl &= ~E1000_RCTL_BSEX;
1583 break;
1584 case E1000_RXBUFFER_512:
1585 rctl |= E1000_RCTL_SZ_512;
1586 rctl &= ~E1000_RCTL_BSEX;
1587 break;
1588 case E1000_RXBUFFER_1024:
1589 rctl |= E1000_RCTL_SZ_1024;
1590 rctl &= ~E1000_RCTL_BSEX;
1591 break;
a1415ee6
JK		 1592 case E1000_RXBUFFER_2048:
1593 default:
1594 rctl |= E1000_RCTL_SZ_2048;
1595 rctl &= ~E1000_RCTL_BSEX;
1596 break;
1597 case E1000_RXBUFFER_4096:
1598 rctl |= E1000_RCTL_SZ_4096;
1599 break;
1600 case E1000_RXBUFFER_8192:
1601 rctl |= E1000_RCTL_SZ_8192;
1602 break;
1603 case E1000_RXBUFFER_16384:
1604 rctl |= E1000_RCTL_SZ_16384;
1605 break;
2d7edb92
MC		 1606 }
1607
35ec56bb 1608#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1609 /* 82571 and greater support packet-split where the protocol
1610 * header is placed in skb->data and the packet data is
1611 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1612 * In the case of a non-split, skb->data is linearly filled,
1613 * followed by the page buffers. Therefore, skb->data is
1614 * sized to hold the largest protocol header.
1615 */
e4c811c9
MC		 1616 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1617 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1618 PAGE_SIZE <= 16384)
1619 adapter->rx_ps_pages = pages;
1620 else
1621 adapter->rx_ps_pages = 0;
2d7edb92 1622#endif
e4c811c9 1623 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1624 /* Configure extra packet-split registers */
1625 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1626 rfctl |= E1000_RFCTL_EXTEN;
1627 /* disable IPv6 packet split support */
1628 rfctl |= E1000_RFCTL_IPV6_DIS;
1629 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1630
1631 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
96838a40 1632
2d7edb92
MC		 1633 psrctl |= adapter->rx_ps_bsize0 >>
1634 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1635
1636 switch (adapter->rx_ps_pages) {
1637 case 3:
1638 psrctl |= PAGE_SIZE <<
1639 E1000_PSRCTL_BSIZE3_SHIFT;
1640 case 2:
1641 psrctl |= PAGE_SIZE <<
1642 E1000_PSRCTL_BSIZE2_SHIFT;
1643 case 1:
1644 psrctl |= PAGE_SIZE >>
1645 E1000_PSRCTL_BSIZE1_SHIFT;
1646 break;
1647 }
2d7edb92
MC		 1648
1649 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1650 }
1651
1652 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1653}
1654
1655/**
1656 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1657 * @adapter: board private structure
1658 *
1659 * Configure the Rx unit of the MAC after a reset.
1660 **/
1661
1662static void
1663e1000_configure_rx(struct e1000_adapter *adapter)
1664{
581d708e
MC		 1665 uint64_t rdba;
1666 struct e1000_hw *hw = &adapter->hw;
1667 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 1668
e4c811c9 1669 if (adapter->rx_ps_pages) {
0f15a8fa 1670 /* this is a 32 byte descriptor */
581d708e 1671 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1672 sizeof(union e1000_rx_desc_packet_split);
1673 adapter->clean_rx = e1000_clean_rx_irq_ps;
1674 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1675 } else {
581d708e
MC		 1676 rdlen = adapter->rx_ring[0].count *
1677 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1678 adapter->clean_rx = e1000_clean_rx_irq;
1679 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1680 }
1da177e4
LT		 1681
1682 /* disable receives while setting up the descriptors */
581d708e
MC		 1683 rctl = E1000_READ_REG(hw, RCTL);
1684 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1685
1686 /* set the Receive Delay Timer Register */
581d708e 1687 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1688
581d708e
MC		 1689 if (hw->mac_type >= e1000_82540) {
1690 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
96838a40 1691 if (adapter->itr > 1)
581d708e 1692 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1693 1000000000 / (adapter->itr * 256));
1694 }
1695
2ae76d98 1696 if (hw->mac_type >= e1000_82571) {
2ae76d98 1697 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 1698 /* Reset delay timers after every interrupt */
6fc7a7ec 1699 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9
JK		 1700#ifdef CONFIG_E1000_NAPI
1701 /* Auto-Mask interrupts upon ICR read. */
1702 ctrl_ext |= E1000_CTRL_EXT_IAME;
1703#endif
2ae76d98 1704 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1e613fd9 1705 E1000_WRITE_REG(hw, IAM, ~0);
2ae76d98
MC		 1706 E1000_WRITE_FLUSH(hw);
1707 }
1708
581d708e
MC		 1709 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1710 * the Base and Length of the Rx Descriptor Ring */
f56799ea 1711 switch (adapter->num_rx_queues) {
24025e4e
MC		 1712 case 1:
1713 default:
581d708e
MC		 1714 rdba = adapter->rx_ring[0].dma;
1715 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1716 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1717 E1000_WRITE_REG(hw, RDLEN, rdlen);
1718 E1000_WRITE_REG(hw, RDH, 0);
1719 E1000_WRITE_REG(hw, RDT, 0);
1720 adapter->rx_ring[0].rdh = E1000_RDH;
1721 adapter->rx_ring[0].rdt = E1000_RDT;
1722 break;
24025e4e
MC		 1723 }
1724
1da177e4 1725 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1726 if (hw->mac_type >= e1000_82543) {
1727 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 1728 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 1729 rxcsum |= E1000_RXCSUM_TUOFL;
1730
868d5309 1731 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1732 * Must be used in conjunction with packet-split. */
96838a40
JB		 1733 if ((hw->mac_type >= e1000_82571) &&
1734 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1735 rxcsum |= E1000_RXCSUM_IPPCSE;
1736 }
1737 } else {
1738 rxcsum &= ~E1000_RXCSUM_TUOFL;
1739 /* don't need to clear IPPCSE as it defaults to 0 */
1740 }
581d708e 1741 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 1742 }
1743
581d708e
MC		 1744 if (hw->mac_type == e1000_82573)
1745 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1746
1da177e4 1747 /* Enable Receives */
581d708e 1748 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1749}
1750
1751/**
581d708e 1752 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1753 * @adapter: board private structure
581d708e 1754 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1755 *
1756 * Free all transmit software resources
1757 **/
1758
3ad2cc67 1759static void
581d708e
MC		 1760e1000_free_tx_resources(struct e1000_adapter *adapter,
1761 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1762{
1763 struct pci_dev *pdev = adapter->pdev;
1764
581d708e 1765 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1766
581d708e
MC		 1767 vfree(tx_ring->buffer_info);
1768 tx_ring->buffer_info = NULL;
1da177e4 1769
581d708e 1770 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1771
581d708e
MC		 1772 tx_ring->desc = NULL;
1773}
1774
1775/**
1776 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1777 * @adapter: board private structure
1778 *
1779 * Free all transmit software resources
1780 **/
1781
1782void
1783e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1784{
1785 int i;
1786
f56799ea 1787 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1788 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1789}
1790
e619d523 1791static void
1da177e4
LT		 1792e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1793 struct e1000_buffer *buffer_info)
1794{
96838a40 1795 if (buffer_info->dma) {
2648345f
MC		 1796 pci_unmap_page(adapter->pdev,
1797 buffer_info->dma,
1798 buffer_info->length,
1799 PCI_DMA_TODEVICE);
1da177e4 1800 }
8241e35e 1801 if (buffer_info->skb)
1da177e4 1802 dev_kfree_skb_any(buffer_info->skb);
8241e35e 1803 memset(buffer_info, 0, sizeof(struct e1000_buffer));
1da177e4
LT		 1804}
1805
1806/**
1807 * e1000_clean_tx_ring - Free Tx Buffers
1808 * @adapter: board private structure
581d708e 1809 * @tx_ring: ring to be cleaned
1da177e4
LT		 1810 **/
1811
1812static void
581d708e
MC		 1813e1000_clean_tx_ring(struct e1000_adapter *adapter,
1814 struct e1000_tx_ring *tx_ring)
1da177e4 1815{
1da177e4
LT		 1816 struct e1000_buffer *buffer_info;
1817 unsigned long size;
1818 unsigned int i;
1819
1820 /* Free all the Tx ring sk_buffs */
1821
96838a40 1822 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 1823 buffer_info = &tx_ring->buffer_info[i];
1824 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1825 }
1826
1827 size = sizeof(struct e1000_buffer) * tx_ring->count;
1828 memset(tx_ring->buffer_info, 0, size);
1829
1830 /* Zero out the descriptor ring */
1831
1832 memset(tx_ring->desc, 0, tx_ring->size);
1833
1834 tx_ring->next_to_use = 0;
1835 tx_ring->next_to_clean = 0;
fd803241 1836 tx_ring->last_tx_tso = 0;
1da177e4 1837
581d708e
MC		 1838 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1839 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1840}
1841
1842/**
1843 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1844 * @adapter: board private structure
1845 **/
1846
1847static void
1848e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1849{
1850 int i;
1851
f56799ea 1852 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 1853 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1854}
1855
1856/**
1857 * e1000_free_rx_resources - Free Rx Resources
1858 * @adapter: board private structure
581d708e 1859 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1860 *
1861 * Free all receive software resources
1862 **/
1863
3ad2cc67 1864static void
581d708e
MC		 1865e1000_free_rx_resources(struct e1000_adapter *adapter,
1866 struct e1000_rx_ring *rx_ring)
1da177e4 1867{
1da177e4
LT		 1868 struct pci_dev *pdev = adapter->pdev;
1869
581d708e 1870 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1871
1872 vfree(rx_ring->buffer_info);
1873 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1874 kfree(rx_ring->ps_page);
1875 rx_ring->ps_page = NULL;
1876 kfree(rx_ring->ps_page_dma);
1877 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1878
1879 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1880
1881 rx_ring->desc = NULL;
1882}
1883
1884/**
581d708e 1885 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 1886 * @adapter: board private structure
581d708e
MC		 1887 *
1888 * Free all receive software resources
1889 **/
1890
1891void
1892e1000_free_all_rx_resources(struct e1000_adapter *adapter)
1893{
1894 int i;
1895
f56799ea 1896 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 1897 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
1898}
1899
1900/**
1901 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1902 * @adapter: board private structure
1903 * @rx_ring: ring to free buffers from
1da177e4
LT		 1904 **/
1905
1906static void
581d708e
MC		 1907e1000_clean_rx_ring(struct e1000_adapter *adapter,
1908 struct e1000_rx_ring *rx_ring)
1da177e4 1909{
1da177e4 1910 struct e1000_buffer *buffer_info;
2d7edb92
MC		 1911 struct e1000_ps_page *ps_page;
1912 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 1913 struct pci_dev *pdev = adapter->pdev;
1914 unsigned long size;
2d7edb92 1915 unsigned int i, j;
1da177e4
LT		 1916
1917 /* Free all the Rx ring sk_buffs */
96838a40 1918 for (i = 0; i < rx_ring->count; i++) {
1da177e4 1919 buffer_info = &rx_ring->buffer_info[i];
96838a40 1920 if (buffer_info->skb) {
1da177e4
LT		 1921 pci_unmap_single(pdev,
1922 buffer_info->dma,
1923 buffer_info->length,
1924 PCI_DMA_FROMDEVICE);
1925
1926 dev_kfree_skb(buffer_info->skb);
1927 buffer_info->skb = NULL;
997f5cbd
JK		 1928 }
1929 ps_page = &rx_ring->ps_page[i];
1930 ps_page_dma = &rx_ring->ps_page_dma[i];
1931 for (j = 0; j < adapter->rx_ps_pages; j++) {
1932 if (!ps_page->ps_page[j]) break;
1933 pci_unmap_page(pdev,
1934 ps_page_dma->ps_page_dma[j],
1935 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1936 ps_page_dma->ps_page_dma[j] = 0;
1937 put_page(ps_page->ps_page[j]);
1938 ps_page->ps_page[j] = NULL;
1da177e4
LT		 1939 }
1940 }
1941
1942 size = sizeof(struct e1000_buffer) * rx_ring->count;
1943 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 1944 size = sizeof(struct e1000_ps_page) * rx_ring->count;
1945 memset(rx_ring->ps_page, 0, size);
1946 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
1947 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 1948
1949 /* Zero out the descriptor ring */
1950
1951 memset(rx_ring->desc, 0, rx_ring->size);
1952
1953 rx_ring->next_to_clean = 0;
1954 rx_ring->next_to_use = 0;
1955
581d708e
MC		 1956 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
1957 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
1958}
1959
1960/**
1961 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
1962 * @adapter: board private structure
1963 **/
1964
1965static void
1966e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
1967{
1968 int i;
1969
f56799ea 1970 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 1971 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 1972}
1973
1974/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
1975 * and memory write and invalidate disabled for certain operations
1976 */
1977static void
1978e1000_enter_82542_rst(struct e1000_adapter *adapter)
1979{
1980 struct net_device *netdev = adapter->netdev;
1981 uint32_t rctl;
1982
1983 e1000_pci_clear_mwi(&adapter->hw);
1984
1985 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1986 rctl |= E1000_RCTL_RST;
1987 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1988 E1000_WRITE_FLUSH(&adapter->hw);
1989 mdelay(5);
1990
96838a40 1991 if (netif_running(netdev))
581d708e 1992 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 1993}
1994
1995static void
1996e1000_leave_82542_rst(struct e1000_adapter *adapter)
1997{
1998 struct net_device *netdev = adapter->netdev;
1999 uint32_t rctl;
2000
2001 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2002 rctl &= ~E1000_RCTL_RST;
2003 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2004 E1000_WRITE_FLUSH(&adapter->hw);
2005 mdelay(5);
2006
96838a40 2007 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2008 e1000_pci_set_mwi(&adapter->hw);
2009
96838a40 2010 if (netif_running(netdev)) {
72d64a43
JK		 2011 /* No need to loop, because 82542 supports only 1 queue */
2012 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2013 e1000_configure_rx(adapter);
72d64a43 2014 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2015 }
2016}
2017
2018/**
2019 * e1000_set_mac - Change the Ethernet Address of the NIC
2020 * @netdev: network interface device structure
2021 * @p: pointer to an address structure
2022 *
2023 * Returns 0 on success, negative on failure
2024 **/
2025
2026static int
2027e1000_set_mac(struct net_device *netdev, void *p)
2028{
60490fe0 2029 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2030 struct sockaddr *addr = p;
2031
96838a40 2032 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2033 return -EADDRNOTAVAIL;
2034
2035 /* 82542 2.0 needs to be in reset to write receive address registers */
2036
96838a40 2037 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2038 e1000_enter_82542_rst(adapter);
2039
2040 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2041 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2042
2043 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2044
868d5309
MC		 2045 /* With 82571 controllers, LAA may be overwritten (with the default)
2046 * due to controller reset from the other port. */
2047 if (adapter->hw.mac_type == e1000_82571) {
2048 /* activate the work around */
2049 adapter->hw.laa_is_present = 1;
2050
96838a40
JB		 2051 /* Hold a copy of the LAA in RAR[14] This is done so that
2052 * between the time RAR[0] gets clobbered and the time it
2053 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2054 * of the RARs and no incoming packets directed to this port
96838a40 2055 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2056 * RAR[14] */
96838a40 2057 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2058 E1000_RAR_ENTRIES - 1);
2059 }
2060
96838a40 2061 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2062 e1000_leave_82542_rst(adapter);
2063
2064 return 0;
2065}
2066
2067/**
2068 * e1000_set_multi - Multicast and Promiscuous mode set
2069 * @netdev: network interface device structure
2070 *
2071 * The set_multi entry point is called whenever the multicast address
2072 * list or the network interface flags are updated. This routine is
2073 * responsible for configuring the hardware for proper multicast,
2074 * promiscuous mode, and all-multi behavior.
2075 **/
2076
2077static void
2078e1000_set_multi(struct net_device *netdev)
2079{
60490fe0 2080 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2081 struct e1000_hw *hw = &adapter->hw;
2082 struct dev_mc_list *mc_ptr;
2083 uint32_t rctl;
2084 uint32_t hash_value;
868d5309 2085 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2086
868d5309
MC		 2087 /* reserve RAR[14] for LAA over-write work-around */
2088 if (adapter->hw.mac_type == e1000_82571)
2089 rar_entries--;
1da177e4 2090
2648345f
MC		 2091 /* Check for Promiscuous and All Multicast modes */
2092
1da177e4
LT		 2093 rctl = E1000_READ_REG(hw, RCTL);
2094
96838a40 2095 if (netdev->flags & IFF_PROMISC) {
1da177e4 2096 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2097 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2098 rctl |= E1000_RCTL_MPE;
2099 rctl &= ~E1000_RCTL_UPE;
2100 } else {
2101 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2102 }
2103
2104 E1000_WRITE_REG(hw, RCTL, rctl);
2105
2106 /* 82542 2.0 needs to be in reset to write receive address registers */
2107
96838a40 2108 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2109 e1000_enter_82542_rst(adapter);
2110
2111 /* load the first 14 multicast address into the exact filters 1-14
2112 * RAR 0 is used for the station MAC adddress
2113 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2114 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2115 */
2116 mc_ptr = netdev->mc_list;
2117
96838a40 2118 for (i = 1; i < rar_entries; i++) {
868d5309 2119 if (mc_ptr) {
1da177e4
LT		 2120 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2121 mc_ptr = mc_ptr->next;
2122 } else {
2123 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2124 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2125 }
2126 }
2127
2128 /* clear the old settings from the multicast hash table */
2129
96838a40 2130 for (i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
1da177e4
LT		 2131 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2132
2133 /* load any remaining addresses into the hash table */
2134
96838a40 2135 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2136 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2137 e1000_mta_set(hw, hash_value);
2138 }
2139
96838a40 2140 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2141 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2142}
2143
2144/* Need to wait a few seconds after link up to get diagnostic information from
2145 * the phy */
2146
2147static void
2148e1000_update_phy_info(unsigned long data)
2149{
2150 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2151 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2152}
2153
2154/**
2155 * e1000_82547_tx_fifo_stall - Timer Call-back
2156 * @data: pointer to adapter cast into an unsigned long
2157 **/
2158
2159static void
2160e1000_82547_tx_fifo_stall(unsigned long data)
2161{
2162 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2163 struct net_device *netdev = adapter->netdev;
2164 uint32_t tctl;
2165
96838a40
JB		 2166 if (atomic_read(&adapter->tx_fifo_stall)) {
2167 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2168 E1000_READ_REG(&adapter->hw, TDH)) &&
2169 (E1000_READ_REG(&adapter->hw, TDFT) ==
2170 E1000_READ_REG(&adapter->hw, TDFH)) &&
2171 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2172 E1000_READ_REG(&adapter->hw, TDFHS))) {
2173 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2174 E1000_WRITE_REG(&adapter->hw, TCTL,
2175 tctl & ~E1000_TCTL_EN);
2176 E1000_WRITE_REG(&adapter->hw, TDFT,
2177 adapter->tx_head_addr);
2178 E1000_WRITE_REG(&adapter->hw, TDFH,
2179 adapter->tx_head_addr);
2180 E1000_WRITE_REG(&adapter->hw, TDFTS,
2181 adapter->tx_head_addr);
2182 E1000_WRITE_REG(&adapter->hw, TDFHS,
2183 adapter->tx_head_addr);
2184 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2185 E1000_WRITE_FLUSH(&adapter->hw);
2186
2187 adapter->tx_fifo_head = 0;
2188 atomic_set(&adapter->tx_fifo_stall, 0);
2189 netif_wake_queue(netdev);
2190 } else {
2191 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2192 }
2193 }
2194}
2195
2196/**
2197 * e1000_watchdog - Timer Call-back
2198 * @data: pointer to adapter cast into an unsigned long
2199 **/
2200static void
2201e1000_watchdog(unsigned long data)
2202{
2203 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2204
2205 /* Do the rest outside of interrupt context */
2206 schedule_work(&adapter->watchdog_task);
2207}
2208
2209static void
2210e1000_watchdog_task(struct e1000_adapter *adapter)
2211{
2212 struct net_device *netdev = adapter->netdev;
545c67c0 2213 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2214 uint32_t link, tctl;
1da177e4
LT		 2215
2216 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2217 if (adapter->hw.mac_type == e1000_82573) {
2218 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2219 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2220 e1000_update_mng_vlan(adapter);
96838a40 2221 }
1da177e4 2222
96838a40 2223 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2224 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2225 link = !adapter->hw.serdes_link_down;
2226 else
2227 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2228
96838a40
JB		 2229 if (link) {
2230 if (!netif_carrier_ok(netdev)) {
fe7fe28e 2231 boolean_t txb2b = 1;
1da177e4
LT		 2232 e1000_get_speed_and_duplex(&adapter->hw,
2233 &adapter->link_speed,
2234 &adapter->link_duplex);
2235
2236 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2237 adapter->link_speed,
2238 adapter->link_duplex == FULL_DUPLEX ?
2239 "Full Duplex" : "Half Duplex");
2240
7e6c9861
JK		 2241 /* tweak tx_queue_len according to speed/duplex
2242 * and adjust the timeout factor */
66a2b0a3
JK		 2243 netdev->tx_queue_len = adapter->tx_queue_len;
2244 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2245 switch (adapter->link_speed) {
2246 case SPEED_10:
fe7fe28e 2247 txb2b = 0;
7e6c9861
JK		 2248 netdev->tx_queue_len = 10;
2249 adapter->tx_timeout_factor = 8;
2250 break;
2251 case SPEED_100:
fe7fe28e 2252 txb2b = 0;
7e6c9861
JK		 2253 netdev->tx_queue_len = 100;
2254 /* maybe add some timeout factor ? */
2255 break;
2256 }
2257
fe7fe28e 2258 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2259 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2260 txb2b == 0) {
7e6c9861
JK		 2261#define SPEED_MODE_BIT (1 << 21)
2262 uint32_t tarc0;
2263 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
2264 tarc0 &= ~SPEED_MODE_BIT;
2265 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2266 }
2267
2268#ifdef NETIF_F_TSO
2269 /* disable TSO for pcie and 10/100 speeds, to avoid
2270 * some hardware issues */
2271 if (!adapter->tso_force &&
2272 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2273 switch (adapter->link_speed) {
2274 case SPEED_10:
66a2b0a3 2275 case SPEED_100:
7e6c9861
JK		 2276 DPRINTK(PROBE,INFO,
2277 "10/100 speed: disabling TSO\n");
2278 netdev->features &= ~NETIF_F_TSO;
2279 break;
2280 case SPEED_1000:
2281 netdev->features |= NETIF_F_TSO;
2282 break;
2283 default:
2284 /* oops */
66a2b0a3
JK		 2285 break;
2286 }
2287 }
7e6c9861
JK		 2288#endif
2289
2290 /* enable transmits in the hardware, need to do this
2291 * after setting TARC0 */
2292 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2293 tctl |= E1000_TCTL_EN;
2294 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2295
1da177e4
LT		 2296 netif_carrier_on(netdev);
2297 netif_wake_queue(netdev);
2298 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2299 adapter->smartspeed = 0;
2300 }
2301 } else {
96838a40 2302 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2303 adapter->link_speed = 0;
2304 adapter->link_duplex = 0;
2305 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2306 netif_carrier_off(netdev);
2307 netif_stop_queue(netdev);
2308 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
87041639
JK		 2309
2310 /* 80003ES2LAN workaround--
2311 * For packet buffer work-around on link down event;
2312 * disable receives in the ISR and
2313 * reset device here in the watchdog
2314 */
2315 if (adapter->hw.mac_type == e1000_80003es2lan) {
2316 /* reset device */
2317 schedule_work(&adapter->reset_task);
2318 }
1da177e4
LT		 2319 }
2320
2321 e1000_smartspeed(adapter);
2322 }
2323
2324 e1000_update_stats(adapter);
2325
2326 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2327 adapter->tpt_old = adapter->stats.tpt;
2328 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2329 adapter->colc_old = adapter->stats.colc;
2330
2331 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2332 adapter->gorcl_old = adapter->stats.gorcl;
2333 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2334 adapter->gotcl_old = adapter->stats.gotcl;
2335
2336 e1000_update_adaptive(&adapter->hw);
2337
f56799ea 2338 if (!netif_carrier_ok(netdev)) {
581d708e 2339 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2340 /* We've lost link, so the controller stops DMA,
2341 * but we've got queued Tx work that's never going
2342 * to get done, so reset controller to flush Tx.
2343 * (Do the reset outside of interrupt context). */
87041639
JK		 2344 adapter->tx_timeout_count++;
2345 schedule_work(&adapter->reset_task);
1da177e4
LT		 2346 }
2347 }
2348
2349 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
96838a40 2350 if (adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
1da177e4
LT		 2351 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2352 * asymmetrical Tx or Rx gets ITR=8000; everyone
2353 * else is between 2000-8000. */
2354 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
96838a40 2355 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
1da177e4
LT		 2356 adapter->gotcl - adapter->gorcl :
2357 adapter->gorcl - adapter->gotcl) / 10000;
2358 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2359 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2360 }
2361
2362 /* Cause software interrupt to ensure rx ring is cleaned */
2363 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2364
2648345f 2365 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2366 adapter->detect_tx_hung = TRUE;
2367
96838a40 2368 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2369 * reset from the other port. Set the appropriate LAA in RAR[0] */
2370 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2371 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2372
1da177e4
LT		 2373 /* Reset the timer */
2374 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2375}
2376
2377#define E1000_TX_FLAGS_CSUM 0x00000001
2378#define E1000_TX_FLAGS_VLAN 0x00000002
2379#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2380#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2381#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2382#define E1000_TX_FLAGS_VLAN_SHIFT 16
2383
e619d523 2384static int
581d708e
MC		 2385e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2386 struct sk_buff *skb)
1da177e4
LT		 2387{
2388#ifdef NETIF_F_TSO
2389 struct e1000_context_desc *context_desc;
545c67c0 2390 struct e1000_buffer *buffer_info;
1da177e4
LT		 2391 unsigned int i;
2392 uint32_t cmd_length = 0;
2d7edb92 2393 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2394 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2395 int err;
2396
96838a40 2397 if (skb_shinfo(skb)->tso_size) {
1da177e4
LT		 2398 if (skb_header_cloned(skb)) {
2399 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2400 if (err)
2401 return err;
2402 }
2403
2404 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2405 mss = skb_shinfo(skb)->tso_size;
60828236 2406 if (skb->protocol == htons(ETH_P_IP)) {
2d7edb92
MC		 2407 skb->nh.iph->tot_len = 0;
2408 skb->nh.iph->check = 0;
2409 skb->h.th->check =
2410 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2411 skb->nh.iph->daddr,
2412 0,
2413 IPPROTO_TCP,
2414 0);
2415 cmd_length = E1000_TXD_CMD_IP;
2416 ipcse = skb->h.raw - skb->data - 1;
2417#ifdef NETIF_F_TSO_IPV6
96838a40 2418 } else if (skb->protocol == ntohs(ETH_P_IPV6)) {
2d7edb92
MC		 2419 skb->nh.ipv6h->payload_len = 0;
2420 skb->h.th->check =
2421 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2422 &skb->nh.ipv6h->daddr,
2423 0,
2424 IPPROTO_TCP,
2425 0);
2426 ipcse = 0;
2427#endif
2428 }
1da177e4
LT		 2429 ipcss = skb->nh.raw - skb->data;
2430 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2431 tucss = skb->h.raw - skb->data;
2432 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2433 tucse = 0;
2434
2435 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2436 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2437
581d708e
MC		 2438 i = tx_ring->next_to_use;
2439 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2440 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2441
2442 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2443 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2444 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2445 context_desc->upper_setup.tcp_fields.tucss = tucss;
2446 context_desc->upper_setup.tcp_fields.tucso = tucso;
2447 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2448 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2449 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2450 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2451
545c67c0
JK		 2452 buffer_info->time_stamp = jiffies;
2453
581d708e
MC		 2454 if (++i == tx_ring->count) i = 0;
2455 tx_ring->next_to_use = i;
1da177e4 2456
8241e35e 2457 return TRUE;
1da177e4
LT		 2458 }
2459#endif
2460
8241e35e 2461 return FALSE;
1da177e4
LT		 2462}
2463
e619d523 2464static boolean_t
581d708e
MC		 2465e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2466 struct sk_buff *skb)
1da177e4
LT		 2467{
2468 struct e1000_context_desc *context_desc;
545c67c0 2469 struct e1000_buffer *buffer_info;
1da177e4
LT		 2470 unsigned int i;
2471 uint8_t css;
2472
96838a40 2473 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1da177e4
LT		 2474 css = skb->h.raw - skb->data;
2475
581d708e 2476 i = tx_ring->next_to_use;
545c67c0 2477 buffer_info = &tx_ring->buffer_info[i];
581d708e 2478 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2479
2480 context_desc->upper_setup.tcp_fields.tucss = css;
2481 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2482 context_desc->upper_setup.tcp_fields.tucse = 0;
2483 context_desc->tcp_seg_setup.data = 0;
2484 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2485
545c67c0
JK		 2486 buffer_info->time_stamp = jiffies;
2487
581d708e
MC		 2488 if (unlikely(++i == tx_ring->count)) i = 0;
2489 tx_ring->next_to_use = i;
1da177e4
LT		 2490
2491 return TRUE;
2492 }
2493
2494 return FALSE;
2495}
2496
2497#define E1000_MAX_TXD_PWR 12
2498#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2499
e619d523 2500static int
581d708e
MC		 2501e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2502 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2503 unsigned int nr_frags, unsigned int mss)
1da177e4 2504{
1da177e4
LT		 2505 struct e1000_buffer *buffer_info;
2506 unsigned int len = skb->len;
2507 unsigned int offset = 0, size, count = 0, i;
2508 unsigned int f;
2509 len -= skb->data_len;
2510
2511 i = tx_ring->next_to_use;
2512
96838a40 2513 while (len) {
1da177e4
LT		 2514 buffer_info = &tx_ring->buffer_info[i];
2515 size = min(len, max_per_txd);
2516#ifdef NETIF_F_TSO
fd803241
JK		 2517 /* Workaround for Controller erratum --
2518 * descriptor for non-tso packet in a linear SKB that follows a
2519 * tso gets written back prematurely before the data is fully
0f15a8fa 2520 * DMA'd to the controller */
fd803241 2521 if (!skb->data_len && tx_ring->last_tx_tso &&
0f15a8fa 2522 !skb_shinfo(skb)->tso_size) {
fd803241
JK		 2523 tx_ring->last_tx_tso = 0;
2524 size -= 4;
2525 }
2526
1da177e4
LT		 2527 /* Workaround for premature desc write-backs
2528 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2529 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4
LT		 2530 size -= 4;
2531#endif
97338bde
MC		 2532 /* work-around for errata 10 and it applies
2533 * to all controllers in PCI-X mode
2534 * The fix is to make sure that the first descriptor of a
2535 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2536 */
96838a40 2537 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2538 (size > 2015) && count == 0))
2539 size = 2015;
96838a40 2540
1da177e4
LT		 2541 /* Workaround for potential 82544 hang in PCI-X. Avoid
2542 * terminating buffers within evenly-aligned dwords. */
96838a40 2543 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2544 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2545 size > 4))
2546 size -= 4;
2547
2548 buffer_info->length = size;
2549 buffer_info->dma =
2550 pci_map_single(adapter->pdev,
2551 skb->data + offset,
2552 size,
2553 PCI_DMA_TODEVICE);
2554 buffer_info->time_stamp = jiffies;
2555
2556 len -= size;
2557 offset += size;
2558 count++;
96838a40 2559 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2560 }
2561
96838a40 2562 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 2563 struct skb_frag_struct *frag;
2564
2565 frag = &skb_shinfo(skb)->frags[f];
2566 len = frag->size;
2567 offset = frag->page_offset;
2568
96838a40 2569 while (len) {
1da177e4
LT		 2570 buffer_info = &tx_ring->buffer_info[i];
2571 size = min(len, max_per_txd);
2572#ifdef NETIF_F_TSO
2573 /* Workaround for premature desc write-backs
2574 * in TSO mode. Append 4-byte sentinel desc */
96838a40 2575 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4
LT		 2576 size -= 4;
2577#endif
2578 /* Workaround for potential 82544 hang in PCI-X.
2579 * Avoid terminating buffers within evenly-aligned
2580 * dwords. */
96838a40 2581 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 2582 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2583 size > 4))
2584 size -= 4;
2585
2586 buffer_info->length = size;
2587 buffer_info->dma =
2588 pci_map_page(adapter->pdev,
2589 frag->page,
2590 offset,
2591 size,
2592 PCI_DMA_TODEVICE);
2593 buffer_info->time_stamp = jiffies;
2594
2595 len -= size;
2596 offset += size;
2597 count++;
96838a40 2598 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2599 }
2600 }
2601
2602 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2603 tx_ring->buffer_info[i].skb = skb;
2604 tx_ring->buffer_info[first].next_to_watch = i;
2605
2606 return count;
2607}
2608
e619d523 2609static void
581d708e
MC		 2610e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2611 int tx_flags, int count)
1da177e4 2612{
1da177e4
LT		 2613 struct e1000_tx_desc *tx_desc = NULL;
2614 struct e1000_buffer *buffer_info;
2615 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2616 unsigned int i;
2617
96838a40 2618 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 2619 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2620 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2621 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2622
96838a40 2623 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 2624 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2625 }
2626
96838a40 2627 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 2628 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2629 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2630 }
2631
96838a40 2632 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 2633 txd_lower |= E1000_TXD_CMD_VLE;
2634 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2635 }
2636
2637 i = tx_ring->next_to_use;
2638
96838a40 2639 while (count--) {
1da177e4
LT		 2640 buffer_info = &tx_ring->buffer_info[i];
2641 tx_desc = E1000_TX_DESC(*tx_ring, i);
2642 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2643 tx_desc->lower.data =
2644 cpu_to_le32(txd_lower | buffer_info->length);
2645 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 2646 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 2647 }
2648
2649 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2650
2651 /* Force memory writes to complete before letting h/w
2652 * know there are new descriptors to fetch. (Only
2653 * applicable for weak-ordered memory model archs,
2654 * such as IA-64). */
2655 wmb();
2656
2657 tx_ring->next_to_use = i;
581d708e 2658 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2659}
2660
2661/**
2662 * 82547 workaround to avoid controller hang in half-duplex environment.
2663 * The workaround is to avoid queuing a large packet that would span
2664 * the internal Tx FIFO ring boundary by notifying the stack to resend
2665 * the packet at a later time. This gives the Tx FIFO an opportunity to
2666 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2667 * to the beginning of the Tx FIFO.
2668 **/
2669
2670#define E1000_FIFO_HDR 0x10
2671#define E1000_82547_PAD_LEN 0x3E0
2672
e619d523 2673static int
1da177e4
LT		 2674e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2675{
2676 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2677 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2678
2679 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2680
96838a40 2681 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 2682 goto no_fifo_stall_required;
2683
96838a40 2684 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 2685 return 1;
2686
96838a40 2687 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 2688 atomic_set(&adapter->tx_fifo_stall, 1);
2689 return 1;
2690 }
2691
2692no_fifo_stall_required:
2693 adapter->tx_fifo_head += skb_fifo_len;
96838a40 2694 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 2695 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2696 return 0;
2697}
2698
2d7edb92 2699#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 2700static int
2d7edb92
MC		 2701e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2702{
2703 struct e1000_hw *hw = &adapter->hw;
2704 uint16_t length, offset;
96838a40
JB		 2705 if (vlan_tx_tag_present(skb)) {
2706 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 2707 ( adapter->hw.mng_cookie.status &
2708 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2709 return 0;
2710 }
20a44028 2711 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 2712 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 2713 if ((htons(ETH_P_IP) == eth->h_proto)) {
2714 const struct iphdr *ip =
2d7edb92 2715 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 2716 if (IPPROTO_UDP == ip->protocol) {
2717 struct udphdr *udp =
2718 (struct udphdr *)((uint8_t *)ip +
2d7edb92 2719 (ip->ihl << 2));
96838a40 2720 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 2721 offset = (uint8_t *)udp + 8 - skb->data;
2722 length = skb->len - offset;
2723
2724 return e1000_mng_write_dhcp_info(hw,
96838a40 2725 (uint8_t *)udp + 8,
2d7edb92
MC		 2726 length);
2727 }
2728 }
2729 }
2730 }
2731 return 0;
2732}
2733
1da177e4
LT		 2734#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2735static int
2736e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2737{
60490fe0 2738 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2739 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2740 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2741 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2742 unsigned int tx_flags = 0;
2743 unsigned int len = skb->len;
2744 unsigned long flags;
2745 unsigned int nr_frags = 0;
2746 unsigned int mss = 0;
2747 int count = 0;
76c224bc 2748 int tso;
1da177e4
LT		 2749 unsigned int f;
2750 len -= skb->data_len;
2751
581d708e 2752 tx_ring = adapter->tx_ring;
24025e4e 2753
581d708e 2754 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2755 dev_kfree_skb_any(skb);
2756 return NETDEV_TX_OK;
2757 }
2758
2759#ifdef NETIF_F_TSO
2760 mss = skb_shinfo(skb)->tso_size;
76c224bc 2761 /* The controller does a simple calculation to
1da177e4
LT		 2762 * make sure there is enough room in the FIFO before
2763 * initiating the DMA for each buffer. The calc is:
2764 * 4 = ceil(buffer len/mss). To make sure we don't
2765 * overrun the FIFO, adjust the max buffer len if mss
2766 * drops. */
96838a40 2767 if (mss) {
9a3056da 2768 uint8_t hdr_len;
1da177e4
LT		 2769 max_per_txd = min(mss << 2, max_per_txd);
2770 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 2771
9f687888 2772 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
9a3056da
JK		 2773 * points to just header, pull a few bytes of payload from
2774 * frags into skb->data */
2775 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
9f687888
JK		 2776 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
2777 switch (adapter->hw.mac_type) {
2778 unsigned int pull_size;
2779 case e1000_82571:
2780 case e1000_82572:
2781 case e1000_82573:
2782 pull_size = min((unsigned int)4, skb->data_len);
2783 if (!__pskb_pull_tail(skb, pull_size)) {
76c224bc 2784 printk(KERN_ERR
9f687888
JK		 2785 "__pskb_pull_tail failed.\n");
2786 dev_kfree_skb_any(skb);
749dfc70 2787 return NETDEV_TX_OK;
9f687888
JK		 2788 }
2789 len = skb->len - skb->data_len;
2790 break;
2791 default:
2792 /* do nothing */
2793 break;
d74bbd3b 2794 }
9a3056da 2795 }
1da177e4
LT		 2796 }
2797
9a3056da 2798 /* reserve a descriptor for the offload context */
96838a40 2799 if ((mss) || (skb->ip_summed == CHECKSUM_HW))
1da177e4 2800 count++;
2648345f 2801 count++;
1da177e4 2802#else
96838a40 2803 if (skb->ip_summed == CHECKSUM_HW)
1da177e4
LT		 2804 count++;
2805#endif
fd803241
JK		 2806
2807#ifdef NETIF_F_TSO
2808 /* Controller Erratum workaround */
2809 if (!skb->data_len && tx_ring->last_tx_tso &&
0f15a8fa 2810 !skb_shinfo(skb)->tso_size)
fd803241
JK		 2811 count++;
2812#endif
2813
1da177e4
LT		 2814 count += TXD_USE_COUNT(len, max_txd_pwr);
2815
96838a40 2816 if (adapter->pcix_82544)
1da177e4
LT		 2817 count++;
2818
96838a40 2819 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 2820 * in PCI-X mode, so add one more descriptor to the count
2821 */
96838a40 2822 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 2823 (len > 2015)))
2824 count++;
2825
1da177e4 2826 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 2827 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 2828 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2829 max_txd_pwr);
96838a40 2830 if (adapter->pcix_82544)
1da177e4
LT		 2831 count += nr_frags;
2832
0f15a8fa
JK		 2833
2834 if (adapter->hw.tx_pkt_filtering &&
2835 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 2836 e1000_transfer_dhcp_info(adapter, skb);
2837
581d708e
MC		 2838 local_irq_save(flags);
2839 if (!spin_trylock(&tx_ring->tx_lock)) {
2840 /* Collision - tell upper layer to requeue */
2841 local_irq_restore(flags);
2842 return NETDEV_TX_LOCKED;
2843 }
1da177e4
LT		 2844
2845 /* need: count + 2 desc gap to keep tail from touching
2846 * head, otherwise try next time */
581d708e 2847 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2848 netif_stop_queue(netdev);
581d708e 2849 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2850 return NETDEV_TX_BUSY;
2851 }
2852
96838a40
JB		 2853 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
2854 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4
LT		 2855 netif_stop_queue(netdev);
2856 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2857 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2858 return NETDEV_TX_BUSY;
2859 }
2860 }
2861
96838a40 2862 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 2863 tx_flags |= E1000_TX_FLAGS_VLAN;
2864 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2865 }
2866
581d708e 2867 first = tx_ring->next_to_use;
96838a40 2868
581d708e 2869 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2870 if (tso < 0) {
2871 dev_kfree_skb_any(skb);
581d708e 2872 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2873 return NETDEV_TX_OK;
2874 }
2875
fd803241
JK		 2876 if (likely(tso)) {
2877 tx_ring->last_tx_tso = 1;
1da177e4 2878 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 2879 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2880 tx_flags |= E1000_TX_FLAGS_CSUM;
2881
2d7edb92 2882 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2883 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2884 * no longer assume, we must. */
60828236 2885 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 2886 tx_flags |= E1000_TX_FLAGS_IPV4;
2887
581d708e
MC		 2888 e1000_tx_queue(adapter, tx_ring, tx_flags,
2889 e1000_tx_map(adapter, tx_ring, skb, first,
2890 max_per_txd, nr_frags, mss));
1da177e4
LT		 2891
2892 netdev->trans_start = jiffies;
2893
2894 /* Make sure there is space in the ring for the next send. */
581d708e 2895 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2896 netif_stop_queue(netdev);
2897
581d708e 2898 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2899 return NETDEV_TX_OK;
2900}
2901
2902/**
2903 * e1000_tx_timeout - Respond to a Tx Hang
2904 * @netdev: network interface device structure
2905 **/
2906
2907static void
2908e1000_tx_timeout(struct net_device *netdev)
2909{
60490fe0 2910 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2911
2912 /* Do the reset outside of interrupt context */
87041639
JK		 2913 adapter->tx_timeout_count++;
2914 schedule_work(&adapter->reset_task);
1da177e4
LT		 2915}
2916
2917static void
87041639 2918e1000_reset_task(struct net_device *netdev)
1da177e4 2919{
60490fe0 2920 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2921
2922 e1000_down(adapter);
2923 e1000_up(adapter);
2924}
2925
2926/**
2927 * e1000_get_stats - Get System Network Statistics
2928 * @netdev: network interface device structure
2929 *
2930 * Returns the address of the device statistics structure.
2931 * The statistics are actually updated from the timer callback.
2932 **/
2933
2934static struct net_device_stats *
2935e1000_get_stats(struct net_device *netdev)
2936{
60490fe0 2937 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2938
6b7660cd 2939 /* only return the current stats */
1da177e4
LT		 2940 return &adapter->net_stats;
2941}
2942
2943/**
2944 * e1000_change_mtu - Change the Maximum Transfer Unit
2945 * @netdev: network interface device structure
2946 * @new_mtu: new value for maximum frame size
2947 *
2948 * Returns 0 on success, negative on failure
2949 **/
2950
2951static int
2952e1000_change_mtu(struct net_device *netdev, int new_mtu)
2953{
60490fe0 2954 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2955 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 2956 uint16_t eeprom_data = 0;
1da177e4 2957
96838a40
JB		 2958 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
2959 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2960 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 2961 return -EINVAL;
2d7edb92 2962 }
1da177e4 2963
997f5cbd
JK		 2964 /* Adapter-specific max frame size limits. */
2965 switch (adapter->hw.mac_type) {
9e2feace 2966 case e1000_undefined ... e1000_82542_rev2_1:
997f5cbd
JK		 2967 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2968 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 2969 return -EINVAL;
2d7edb92 2970 }
997f5cbd 2971 break;
85b22eb6
JK		 2972 case e1000_82573:
2973 /* only enable jumbo frames if ASPM is disabled completely
2974 * this means both bits must be zero in 0x1A bits 3:2 */
2975 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
2976 &eeprom_data);
2977 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
2978 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2979 DPRINTK(PROBE, ERR,
2980 "Jumbo Frames not supported.\n");
2981 return -EINVAL;
2982 }
2983 break;
2984 }
2985 /* fall through to get support */
997f5cbd
JK		 2986 case e1000_82571:
2987 case e1000_82572:
87041639 2988 case e1000_80003es2lan:
997f5cbd
JK		 2989#define MAX_STD_JUMBO_FRAME_SIZE 9234
2990 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2991 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
2992 return -EINVAL;
2993 }
2994 break;
2995 default:
2996 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
2997 break;
1da177e4
LT		 2998 }
2999
9e2feace
AK		 3000 /* NOTE: dev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3001 * means we reserve 2 more, this pushes us to allocate from the next
3002 * larger slab size
3003 * i.e. RXBUFFER_2048 --> size-4096 slab */
3004
3005 if (max_frame <= E1000_RXBUFFER_256)
3006 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3007 else if (max_frame <= E1000_RXBUFFER_512)
3008 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3009 else if (max_frame <= E1000_RXBUFFER_1024)
3010 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3011 else if (max_frame <= E1000_RXBUFFER_2048)
3012 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3013 else if (max_frame <= E1000_RXBUFFER_4096)
3014 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3015 else if (max_frame <= E1000_RXBUFFER_8192)
3016 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3017 else if (max_frame <= E1000_RXBUFFER_16384)
3018 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3019
3020 /* adjust allocation if LPE protects us, and we aren't using SBP */
3021#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
3022 if (!adapter->hw.tbi_compatibility_on &&
3023 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3024 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3025 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3026
2d7edb92
MC		 3027 netdev->mtu = new_mtu;
3028
96838a40 3029 if (netif_running(netdev)) {
1da177e4
LT		 3030 e1000_down(adapter);
3031 e1000_up(adapter);
3032 }
3033
1da177e4
LT		 3034 adapter->hw.max_frame_size = max_frame;
3035
3036 return 0;
3037}
3038
3039/**
3040 * e1000_update_stats - Update the board statistics counters
3041 * @adapter: board private structure
3042 **/
3043
3044void
3045e1000_update_stats(struct e1000_adapter *adapter)
3046{
3047 struct e1000_hw *hw = &adapter->hw;
a487a8f7 3048 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3049 unsigned long flags;
3050 uint16_t phy_tmp;
3051
3052#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3053
a487a8f7
AK		 3054 /*
3055 * Prevent stats update while adapter is being reset, or if the pci
3056 * connection is down.
3057 */
9026729b 3058 if (adapter->link_speed == 0)
a487a8f7
AK		 3059 return;
3060 if (pdev->error_state && pdev->error_state != pci_channel_io_normal)
9026729b
AK		 3061 return;
3062
1da177e4
LT		 3063 spin_lock_irqsave(&adapter->stats_lock, flags);
3064
3065 /* these counters are modified from e1000_adjust_tbi_stats,
3066 * called from the interrupt context, so they must only
3067 * be written while holding adapter->stats_lock
3068 */
3069
3070 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3071 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3072 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3073 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3074 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3075 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3076 adapter->stats.roc += E1000_READ_REG(hw, ROC);
3077 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3078 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3079 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3080 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3081 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3082 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
3083
3084 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3085 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3086 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3087 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3088 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3089 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3090 adapter->stats.dc += E1000_READ_REG(hw, DC);
3091 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3092 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3093 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3094 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3095 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3096 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3097 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3098 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3099 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3100 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3101 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3102 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3103 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3104 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3105 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3106 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3107 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3108 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3109 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3110 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3111 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3112 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3113 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3114 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3115 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3116 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3117 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3118
3119 /* used for adaptive IFS */
3120
3121 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3122 adapter->stats.tpt += hw->tx_packet_delta;
3123 hw->collision_delta = E1000_READ_REG(hw, COLC);
3124 adapter->stats.colc += hw->collision_delta;
3125
96838a40 3126 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3127 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3128 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3129 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3130 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3131 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3132 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3133 }
96838a40 3134 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3135 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3136 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3137 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3138 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3139 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3140 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3141 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3142 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3143 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3144 }
1da177e4
LT		 3145
3146 /* Fill out the OS statistics structure */
3147
3148 adapter->net_stats.rx_packets = adapter->stats.gprc;
3149 adapter->net_stats.tx_packets = adapter->stats.gptc;
3150 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3151 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3152 adapter->net_stats.multicast = adapter->stats.mprc;
3153 adapter->net_stats.collisions = adapter->stats.colc;
3154
3155 /* Rx Errors */
3156
87041639
JK		 3157 /* RLEC on some newer hardware can be incorrect so build
3158 * our own version based on RUC and ROC */
1da177e4
LT		 3159 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3160 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3161 adapter->stats.ruc + adapter->stats.roc +
3162 adapter->stats.cexterr;
87041639
JK		 3163 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3164 adapter->stats.roc;
1da177e4
LT		 3165 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3166 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3167 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3168
3169 /* Tx Errors */
3170
3171 adapter->net_stats.tx_errors = adapter->stats.ecol +
3172 adapter->stats.latecol;
3173 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3174 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3175 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3176
3177 /* Tx Dropped needs to be maintained elsewhere */
3178
3179 /* Phy Stats */
3180
96838a40
JB		 3181 if (hw->media_type == e1000_media_type_copper) {
3182 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3183 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3184 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3185 adapter->phy_stats.idle_errors += phy_tmp;
3186 }
3187
96838a40 3188 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3189 (hw->phy_type == e1000_phy_m88) &&
3190 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3191 adapter->phy_stats.receive_errors += phy_tmp;
3192 }
3193
3194 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3195}
3196
3197/**
3198 * e1000_intr - Interrupt Handler
3199 * @irq: interrupt number
3200 * @data: pointer to a network interface device structure
3201 * @pt_regs: CPU registers structure
3202 **/
3203
3204static irqreturn_t
3205e1000_intr(int irq, void *data, struct pt_regs *regs)
3206{
3207 struct net_device *netdev = data;
60490fe0 3208 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3209 struct e1000_hw *hw = &adapter->hw;
87041639 3210 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3211#ifndef CONFIG_E1000_NAPI
581d708e 3212 int i;
1e613fd9
JK		 3213#else
3214 /* Interrupt Auto-Mask...upon reading ICR,
3215 * interrupts are masked. No need for the
3216 * IMC write, but it does mean we should
3217 * account for it ASAP. */
3218 if (likely(hw->mac_type >= e1000_82571))
3219 atomic_inc(&adapter->irq_sem);
be2b28ed 3220#endif
1da177e4 3221
1e613fd9
JK		 3222 if (unlikely(!icr)) {
3223#ifdef CONFIG_E1000_NAPI
3224 if (hw->mac_type >= e1000_82571)
3225 e1000_irq_enable(adapter);
3226#endif
1da177e4 3227 return IRQ_NONE; /* Not our interrupt */
1e613fd9 3228 }
1da177e4 3229
96838a40 3230 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3231 hw->get_link_status = 1;
87041639
JK		 3232 /* 80003ES2LAN workaround--
3233 * For packet buffer work-around on link down event;
3234 * disable receives here in the ISR and
3235 * reset adapter in watchdog
3236 */
3237 if (netif_carrier_ok(netdev) &&
3238 (adapter->hw.mac_type == e1000_80003es2lan)) {
3239 /* disable receives */
3240 rctl = E1000_READ_REG(hw, RCTL);
3241 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3242 }
1da177e4
LT		 3243 mod_timer(&adapter->watchdog_timer, jiffies);
3244 }
3245
3246#ifdef CONFIG_E1000_NAPI
1e613fd9
JK		 3247 if (unlikely(hw->mac_type < e1000_82571)) {
3248 atomic_inc(&adapter->irq_sem);
3249 E1000_WRITE_REG(hw, IMC, ~0);
3250 E1000_WRITE_FLUSH(hw);
3251 }
581d708e
MC		 3252 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3253 __netif_rx_schedule(&adapter->polling_netdev[0]);
3254 else
3255 e1000_irq_enable(adapter);
c1605eb3 3256#else
1da177e4 3257 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3258 * Due to Hub Link bus being occupied, an interrupt
3259 * de-assertion message is not able to be sent.
3260 * When an interrupt assertion message is generated later,
3261 * two messages are re-ordered and sent out.
3262 * That causes APIC to think 82547 is in de-assertion
3263 * state, while 82547 is in assertion state, resulting
3264 * in dead lock. Writing IMC forces 82547 into
3265 * de-assertion state.
3266 */
3267 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3268 atomic_inc(&adapter->irq_sem);
2648345f 3269 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3270 }
3271
96838a40
JB		 3272 for (i = 0; i < E1000_MAX_INTR; i++)
3273 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
581d708e 3274 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3275 break;
3276
96838a40 3277 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3278 e1000_irq_enable(adapter);
581d708e 3279
c1605eb3 3280#endif
1da177e4
LT		 3281
3282 return IRQ_HANDLED;
3283}
3284
3285#ifdef CONFIG_E1000_NAPI
3286/**
3287 * e1000_clean - NAPI Rx polling callback
3288 * @adapter: board private structure
3289 **/
3290
3291static int
581d708e 3292e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3293{
581d708e
MC		 3294 struct e1000_adapter *adapter;
3295 int work_to_do = min(*budget, poll_dev->quota);
38bd3b26 3296 int tx_cleaned = 0, i = 0, work_done = 0;
581d708e
MC		 3297
3298 /* Must NOT use netdev_priv macro here. */
3299 adapter = poll_dev->priv;
3300
3301 /* Keep link state information with original netdev */
3302 if (!netif_carrier_ok(adapter->netdev))
3303 goto quit_polling;
2648345f 3304
581d708e
MC		 3305 while (poll_dev != &adapter->polling_netdev[i]) {
3306 i++;
5d9428de 3307 BUG_ON(i == adapter->num_rx_queues);
581d708e
MC		 3308 }
3309
8241e35e
JK		 3310 if (likely(adapter->num_tx_queues == 1)) {
3311 /* e1000_clean is called per-cpu. This lock protects
3312 * tx_ring[0] from being cleaned by multiple cpus
3313 * simultaneously. A failure obtaining the lock means
3314 * tx_ring[0] is currently being cleaned anyway. */
3315 if (spin_trylock(&adapter->tx_queue_lock)) {
3316 tx_cleaned = e1000_clean_tx_irq(adapter,
3317 &adapter->tx_ring[0]);
3318 spin_unlock(&adapter->tx_queue_lock);
3319 }
3320 } else
3321 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3322
581d708e
MC		 3323 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3324 &work_done, work_to_do);
1da177e4
LT		 3325
3326 *budget -= work_done;
581d708e 3327 poll_dev->quota -= work_done;
96838a40 3328
2b02893e 3329 /* If no Tx and not enough Rx work done, exit the polling mode */
96838a40 3330 if ((!tx_cleaned && (work_done == 0)) ||
581d708e
MC		 3331 !netif_running(adapter->netdev)) {
3332quit_polling:
3333 netif_rx_complete(poll_dev);
1da177e4
LT		 3334 e1000_irq_enable(adapter);
3335 return 0;
3336 }
3337
3338 return 1;
3339}
3340
3341#endif
3342/**
3343 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3344 * @adapter: board private structure
3345 **/
3346
3347static boolean_t
581d708e
MC		 3348e1000_clean_tx_irq(struct e1000_adapter *adapter,
3349 struct e1000_tx_ring *tx_ring)
1da177e4 3350{
1da177e4
LT		 3351 struct net_device *netdev = adapter->netdev;
3352 struct e1000_tx_desc *tx_desc, *eop_desc;
3353 struct e1000_buffer *buffer_info;
3354 unsigned int i, eop;
2a1af5d7
JK		 3355#ifdef CONFIG_E1000_NAPI
3356 unsigned int count = 0;
3357#endif
1da177e4
LT		 3358 boolean_t cleaned = FALSE;
3359
3360 i = tx_ring->next_to_clean;
3361 eop = tx_ring->buffer_info[i].next_to_watch;
3362 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3363
581d708e 3364 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3365 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3366 tx_desc = E1000_TX_DESC(*tx_ring, i);
3367 buffer_info = &tx_ring->buffer_info[i];
3368 cleaned = (i == eop);
3369
fd803241 3370 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
8241e35e 3371 memset(tx_desc, 0, sizeof(struct e1000_tx_desc));
1da177e4 3372
96838a40 3373 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3374 }
581d708e 3375
7bfa4816 3376
1da177e4
LT		 3377 eop = tx_ring->buffer_info[i].next_to_watch;
3378 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3379#ifdef CONFIG_E1000_NAPI
3380#define E1000_TX_WEIGHT 64
3381 /* weight of a sort for tx, to avoid endless transmit cleanup */
3382 if (count++ == E1000_TX_WEIGHT) break;
3383#endif
1da177e4
LT		 3384 }
3385
3386 tx_ring->next_to_clean = i;
3387
77b2aad5 3388#define TX_WAKE_THRESHOLD 32
96838a40 3389 if (unlikely(cleaned && netif_queue_stopped(netdev) &&
77b2aad5
AK		 3390 netif_carrier_ok(netdev))) {
3391 spin_lock(&tx_ring->tx_lock);
3392 if (netif_queue_stopped(netdev) &&
3393 (E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))
3394 netif_wake_queue(netdev);
3395 spin_unlock(&tx_ring->tx_lock);
3396 }
2648345f 3397
581d708e 3398 if (adapter->detect_tx_hung) {
2648345f 3399 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3400 * check with the clearing of time_stamp and movement of i */
3401 adapter->detect_tx_hung = FALSE;
392137fa
JK		 3402 if (tx_ring->buffer_info[eop].dma &&
3403 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 3404 (adapter->tx_timeout_factor * HZ))
70b8f1e1 3405 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 3406 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 3407
3408 /* detected Tx unit hang */
c6963ef5 3409 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 3410 " Tx Queue <%lu>\n"
70b8f1e1
MC		 3411 " TDH <%x>\n"
3412 " TDT <%x>\n"
3413 " next_to_use <%x>\n"
3414 " next_to_clean <%x>\n"
3415 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 3416 " time_stamp <%lx>\n"
3417 " next_to_watch <%x>\n"
3418 " jiffies <%lx>\n"
3419 " next_to_watch.status <%x>\n",
7bfa4816
JK		 3420 (unsigned long)((tx_ring - adapter->tx_ring) /
3421 sizeof(struct e1000_tx_ring)),
581d708e
MC		 3422 readl(adapter->hw.hw_addr + tx_ring->tdh),
3423 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 3424 tx_ring->next_to_use,
392137fa
JK		 3425 tx_ring->next_to_clean,
3426 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 3427 eop,
3428 jiffies,
3429 eop_desc->upper.fields.status);
1da177e4 3430 netif_stop_queue(netdev);
70b8f1e1 3431 }
1da177e4 3432 }
1da177e4
LT		 3433 return cleaned;
3434}
3435
3436/**
3437 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3438 * @adapter: board private structure
3439 * @status_err: receive descriptor status and error fields
3440 * @csum: receive descriptor csum field
3441 * @sk_buff: socket buffer with received data
1da177e4
LT		 3442 **/
3443
e619d523 3444static void
1da177e4 3445e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3446 uint32_t status_err, uint32_t csum,
3447 struct sk_buff *skb)
1da177e4 3448{
2d7edb92
MC		 3449 uint16_t status = (uint16_t)status_err;
3450 uint8_t errors = (uint8_t)(status_err >> 24);
3451 skb->ip_summed = CHECKSUM_NONE;
3452
1da177e4 3453 /* 82543 or newer only */
96838a40 3454 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3455 /* Ignore Checksum bit is set */
96838a40 3456 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 3457 /* TCP/UDP checksum error bit is set */
96838a40 3458 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3459 /* let the stack verify checksum errors */
1da177e4 3460 adapter->hw_csum_err++;
2d7edb92
MC		 3461 return;
3462 }
3463 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 3464 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
3465 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 3466 return;
1da177e4 3467 } else {
96838a40 3468 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 3469 return;
3470 }
3471 /* It must be a TCP or UDP packet with a valid checksum */
3472 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3473 /* TCP checksum is good */
3474 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3475 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3476 /* IP fragment with UDP payload */
3477 /* Hardware complements the payload checksum, so we undo it
3478 * and then put the value in host order for further stack use.
3479 */
3480 csum = ntohl(csum ^ 0xFFFF);
3481 skb->csum = csum;
3482 skb->ip_summed = CHECKSUM_HW;
1da177e4 3483 }
2d7edb92 3484 adapter->hw_csum_good++;
1da177e4
LT		 3485}
3486
3487/**
2d7edb92 3488 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3489 * @adapter: board private structure
3490 **/
3491
3492static boolean_t
3493#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3494e1000_clean_rx_irq(struct e1000_adapter *adapter,
3495 struct e1000_rx_ring *rx_ring,
3496 int *work_done, int work_to_do)
1da177e4 3497#else
581d708e
MC		 3498e1000_clean_rx_irq(struct e1000_adapter *adapter,
3499 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3500#endif
3501{
1da177e4
LT		 3502 struct net_device *netdev = adapter->netdev;
3503 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 3504 struct e1000_rx_desc *rx_desc, *next_rxd;
3505 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 3506 unsigned long flags;
3507 uint32_t length;
3508 uint8_t last_byte;
3509 unsigned int i;
72d64a43 3510 int cleaned_count = 0;
a1415ee6 3511 boolean_t cleaned = FALSE;
1da177e4
LT		 3512
3513 i = rx_ring->next_to_clean;
3514 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 3515 buffer_info = &rx_ring->buffer_info[i];
1da177e4 3516
b92ff8ee 3517 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 3518 struct sk_buff *skb;
a292ca6e 3519 u8 status;
1da177e4 3520#ifdef CONFIG_E1000_NAPI
96838a40 3521 if (*work_done >= work_to_do)
1da177e4
LT		 3522 break;
3523 (*work_done)++;
3524#endif
a292ca6e 3525 status = rx_desc->status;
b92ff8ee 3526 skb = buffer_info->skb;
86c3d59f
JB		 3527 buffer_info->skb = NULL;
3528
30320be8
JK		 3529 prefetch(skb->data - NET_IP_ALIGN);
3530
86c3d59f
JB		 3531 if (++i == rx_ring->count) i = 0;
3532 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 3533 prefetch(next_rxd);
3534
86c3d59f 3535 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3536
72d64a43
JK		 3537 cleaned = TRUE;
3538 cleaned_count++;
a292ca6e
JK		 3539 pci_unmap_single(pdev,
3540 buffer_info->dma,
3541 buffer_info->length,
1da177e4
LT		 3542 PCI_DMA_FROMDEVICE);
3543
1da177e4
LT		 3544 length = le16_to_cpu(rx_desc->length);
3545
a1415ee6
JK		 3546 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
3547 /* All receives must fit into a single buffer */
3548 E1000_DBG("%s: Receive packet consumed multiple"
3549 " buffers\n", netdev->name);
3550 dev_kfree_skb_irq(skb);
1da177e4
LT		 3551 goto next_desc;
3552 }
3553
96838a40 3554 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 3555 last_byte = *(skb->data + length - 1);
b92ff8ee 3556 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 3557 rx_desc->errors, length, last_byte)) {
3558 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 3559 e1000_tbi_adjust_stats(&adapter->hw,
3560 &adapter->stats,
1da177e4
LT		 3561 length, skb->data);
3562 spin_unlock_irqrestore(&adapter->stats_lock,
3563 flags);
3564 length--;
3565 } else {
9e2feace
AK		 3566 /* recycle */
3567 buffer_info->skb = skb;
1da177e4
LT		 3568 goto next_desc;
3569 }
1cb5821f 3570 }
1da177e4 3571
a292ca6e
JK		 3572 /* code added for copybreak, this should improve
3573 * performance for small packets with large amounts
3574 * of reassembly being done in the stack */
3575#define E1000_CB_LENGTH 256
a1415ee6 3576 if (length < E1000_CB_LENGTH) {
a292ca6e
JK		 3577 struct sk_buff *new_skb =
3578 dev_alloc_skb(length + NET_IP_ALIGN);
3579 if (new_skb) {
3580 skb_reserve(new_skb, NET_IP_ALIGN);
3581 new_skb->dev = netdev;
3582 memcpy(new_skb->data - NET_IP_ALIGN,
3583 skb->data - NET_IP_ALIGN,
3584 length + NET_IP_ALIGN);
3585 /* save the skb in buffer_info as good */
3586 buffer_info->skb = skb;
3587 skb = new_skb;
3588 skb_put(skb, length);
3589 }
a1415ee6
JK		 3590 } else
3591 skb_put(skb, length);
a292ca6e
JK		 3592
3593 /* end copybreak code */
1da177e4
LT		 3594
3595 /* Receive Checksum Offload */
a292ca6e
JK		 3596 e1000_rx_checksum(adapter,
3597 (uint32_t)(status) |
2d7edb92 3598 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 3599 le16_to_cpu(rx_desc->csum), skb);
96838a40 3600
1da177e4
LT		 3601 skb->protocol = eth_type_trans(skb, netdev);
3602#ifdef CONFIG_E1000_NAPI
96838a40 3603 if (unlikely(adapter->vlgrp &&
a292ca6e 3604 (status & E1000_RXD_STAT_VP))) {
1da177e4 3605 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3606 le16_to_cpu(rx_desc->special) &
3607 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3608 } else {
3609 netif_receive_skb(skb);
3610 }
3611#else /* CONFIG_E1000_NAPI */
96838a40 3612 if (unlikely(adapter->vlgrp &&
b92ff8ee 3613 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 3614 vlan_hwaccel_rx(skb, adapter->vlgrp,
3615 le16_to_cpu(rx_desc->special) &
3616 E1000_RXD_SPC_VLAN_MASK);
3617 } else {
3618 netif_rx(skb);
3619 }
3620#endif /* CONFIG_E1000_NAPI */
3621 netdev->last_rx = jiffies;
3622
3623next_desc:
3624 rx_desc->status = 0;
1da177e4 3625
72d64a43
JK		 3626 /* return some buffers to hardware, one at a time is too slow */
3627 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3628 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3629 cleaned_count = 0;
3630 }
3631
30320be8 3632 /* use prefetched values */
86c3d59f
JB		 3633 rx_desc = next_rxd;
3634 buffer_info = next_buffer;
1da177e4 3635 }
1da177e4 3636 rx_ring->next_to_clean = i;
72d64a43
JK		 3637
3638 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3639 if (cleaned_count)
3640 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92
MC		 3641
3642 return cleaned;
3643}
3644
3645/**
3646 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3647 * @adapter: board private structure
3648 **/
3649
3650static boolean_t
3651#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3652e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3653 struct e1000_rx_ring *rx_ring,
3654 int *work_done, int work_to_do)
2d7edb92 3655#else
581d708e
MC		 3656e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3657 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3658#endif
3659{
86c3d59f 3660 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 3661 struct net_device *netdev = adapter->netdev;
3662 struct pci_dev *pdev = adapter->pdev;
86c3d59f 3663 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 3664 struct e1000_ps_page *ps_page;
3665 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 3666 struct sk_buff *skb;
2d7edb92
MC		 3667 unsigned int i, j;
3668 uint32_t length, staterr;
72d64a43 3669 int cleaned_count = 0;
2d7edb92
MC		 3670 boolean_t cleaned = FALSE;
3671
3672 i = rx_ring->next_to_clean;
3673 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3674 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 3675 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 3676
96838a40 3677 while (staterr & E1000_RXD_STAT_DD) {
30320be8 3678 buffer_info = &rx_ring->buffer_info[i];
2d7edb92
MC		 3679 ps_page = &rx_ring->ps_page[i];
3680 ps_page_dma = &rx_ring->ps_page_dma[i];
3681#ifdef CONFIG_E1000_NAPI
96838a40 3682 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 3683 break;
3684 (*work_done)++;
3685#endif
86c3d59f
JB		 3686 skb = buffer_info->skb;
3687
30320be8
JK		 3688 /* in the packet split case this is header only */
3689 prefetch(skb->data - NET_IP_ALIGN);
3690
86c3d59f
JB		 3691 if (++i == rx_ring->count) i = 0;
3692 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 3693 prefetch(next_rxd);
3694
86c3d59f 3695 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 3696
2d7edb92 3697 cleaned = TRUE;
72d64a43 3698 cleaned_count++;
2d7edb92
MC		 3699 pci_unmap_single(pdev, buffer_info->dma,
3700 buffer_info->length,
3701 PCI_DMA_FROMDEVICE);
3702
96838a40 3703 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 3704 E1000_DBG("%s: Packet Split buffers didn't pick up"
3705 " the full packet\n", netdev->name);
3706 dev_kfree_skb_irq(skb);
3707 goto next_desc;
3708 }
1da177e4 3709
96838a40 3710 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 3711 dev_kfree_skb_irq(skb);
3712 goto next_desc;
3713 }
3714
3715 length = le16_to_cpu(rx_desc->wb.middle.length0);
3716
96838a40 3717 if (unlikely(!length)) {
2d7edb92
MC		 3718 E1000_DBG("%s: Last part of the packet spanning"
3719 " multiple descriptors\n", netdev->name);
3720 dev_kfree_skb_irq(skb);
3721 goto next_desc;
3722 }
3723
3724 /* Good Receive */
3725 skb_put(skb, length);
3726
dc7c6add
JK		 3727 {
3728 /* this looks ugly, but it seems compiler issues make it
3729 more efficient than reusing j */
3730 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
3731
3732 /* page alloc/put takes too long and effects small packet
3733 * throughput, so unsplit small packets and save the alloc/put*/
9e2feace 3734 if (l1 && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 3735 u8 *vaddr;
76c224bc 3736 /* there is no documentation about how to call
dc7c6add
JK		 3737 * kmap_atomic, so we can't hold the mapping
3738 * very long */
3739 pci_dma_sync_single_for_cpu(pdev,
3740 ps_page_dma->ps_page_dma[0],
3741 PAGE_SIZE,
3742 PCI_DMA_FROMDEVICE);
3743 vaddr = kmap_atomic(ps_page->ps_page[0],
3744 KM_SKB_DATA_SOFTIRQ);
3745 memcpy(skb->tail, vaddr, l1);
3746 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
3747 pci_dma_sync_single_for_device(pdev,
3748 ps_page_dma->ps_page_dma[0],
3749 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3750 skb_put(skb, l1);
3751 length += l1;
3752 goto copydone;
3753 } /* if */
3754 }
3755
96838a40 3756 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 3757 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 3758 break;
2d7edb92
MC		 3759 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3760 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3761 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 3762 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
3763 length);
2d7edb92 3764 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 3765 skb->len += length;
3766 skb->data_len += length;
5d51b80f 3767 skb->truesize += length;
2d7edb92
MC		 3768 }
3769
dc7c6add 3770copydone:
2d7edb92 3771 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 3772 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 3773 skb->protocol = eth_type_trans(skb, netdev);
3774
96838a40 3775 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 3776 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 3777 adapter->rx_hdr_split++;
2d7edb92 3778#ifdef CONFIG_E1000_NAPI
96838a40 3779 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3780 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3781 le16_to_cpu(rx_desc->wb.middle.vlan) &
3782 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3783 } else {
3784 netif_receive_skb(skb);
3785 }
3786#else /* CONFIG_E1000_NAPI */
96838a40 3787 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 3788 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3789 le16_to_cpu(rx_desc->wb.middle.vlan) &
3790 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3791 } else {
3792 netif_rx(skb);
3793 }
3794#endif /* CONFIG_E1000_NAPI */
3795 netdev->last_rx = jiffies;
3796
3797next_desc:
c3d7a3a4 3798 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 3799 buffer_info->skb = NULL;
2d7edb92 3800
72d64a43
JK		 3801 /* return some buffers to hardware, one at a time is too slow */
3802 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
3803 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
3804 cleaned_count = 0;
3805 }
3806
30320be8 3807 /* use prefetched values */
86c3d59f
JB		 3808 rx_desc = next_rxd;
3809 buffer_info = next_buffer;
3810
683a38f3 3811 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3812 }
3813 rx_ring->next_to_clean = i;
72d64a43
JK		 3814
3815 cleaned_count = E1000_DESC_UNUSED(rx_ring);
3816 if (cleaned_count)
3817 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4
LT		 3818
3819 return cleaned;
3820}
3821
3822/**
2d7edb92 3823 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3824 * @adapter: address of board private structure
3825 **/
3826
3827static void
581d708e 3828e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 3829 struct e1000_rx_ring *rx_ring,
a292ca6e 3830 int cleaned_count)
1da177e4 3831{
1da177e4
LT		 3832 struct net_device *netdev = adapter->netdev;
3833 struct pci_dev *pdev = adapter->pdev;
3834 struct e1000_rx_desc *rx_desc;
3835 struct e1000_buffer *buffer_info;
3836 struct sk_buff *skb;
2648345f
MC		 3837 unsigned int i;
3838 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3839
3840 i = rx_ring->next_to_use;
3841 buffer_info = &rx_ring->buffer_info[i];
3842
a292ca6e
JK		 3843 while (cleaned_count--) {
3844 if (!(skb = buffer_info->skb))
3845 skb = dev_alloc_skb(bufsz);
3846 else {
3847 skb_trim(skb, 0);
3848 goto map_skb;
3849 }
3850
96838a40 3851 if (unlikely(!skb)) {
1da177e4 3852 /* Better luck next round */
72d64a43 3853 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 3854 break;
3855 }
3856
2648345f 3857 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3858 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3859 struct sk_buff *oldskb = skb;
2648345f
MC		 3860 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3861 "at %p\n", bufsz, skb->data);
3862 /* Try again, without freeing the previous */
1da177e4 3863 skb = dev_alloc_skb(bufsz);
2648345f 3864 /* Failed allocation, critical failure */
1da177e4
LT		 3865 if (!skb) {
3866 dev_kfree_skb(oldskb);
3867 break;
3868 }
2648345f 3869
1da177e4
LT		 3870 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3871 /* give up */
3872 dev_kfree_skb(skb);
3873 dev_kfree_skb(oldskb);
3874 break; /* while !buffer_info->skb */
3875 } else {
2648345f 3876 /* Use new allocation */
1da177e4
LT		 3877 dev_kfree_skb(oldskb);
3878 }
3879 }
1da177e4
LT		 3880 /* Make buffer alignment 2 beyond a 16 byte boundary
3881 * this will result in a 16 byte aligned IP header after
3882 * the 14 byte MAC header is removed
3883 */
3884 skb_reserve(skb, NET_IP_ALIGN);
3885
3886 skb->dev = netdev;
3887
3888 buffer_info->skb = skb;
3889 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 3890map_skb:
1da177e4
LT		 3891 buffer_info->dma = pci_map_single(pdev,
3892 skb->data,
3893 adapter->rx_buffer_len,
3894 PCI_DMA_FROMDEVICE);
3895
2648345f
MC		 3896 /* Fix for errata 23, can't cross 64kB boundary */
3897 if (!e1000_check_64k_bound(adapter,
3898 (void *)(unsigned long)buffer_info->dma,
3899 adapter->rx_buffer_len)) {
3900 DPRINTK(RX_ERR, ERR,
3901 "dma align check failed: %u bytes at %p\n",
3902 adapter->rx_buffer_len,
3903 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3904 dev_kfree_skb(skb);
3905 buffer_info->skb = NULL;
3906
2648345f 3907 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3908 adapter->rx_buffer_len,
3909 PCI_DMA_FROMDEVICE);
3910
3911 break; /* while !buffer_info->skb */
3912 }
1da177e4
LT		 3913 rx_desc = E1000_RX_DESC(*rx_ring, i);
3914 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3915
96838a40
JB		 3916 if (unlikely(++i == rx_ring->count))
3917 i = 0;
1da177e4
LT		 3918 buffer_info = &rx_ring->buffer_info[i];
3919 }
3920
b92ff8ee
JB		 3921 if (likely(rx_ring->next_to_use != i)) {
3922 rx_ring->next_to_use = i;
3923 if (unlikely(i-- == 0))
3924 i = (rx_ring->count - 1);
3925
3926 /* Force memory writes to complete before letting h/w
3927 * know there are new descriptors to fetch. (Only
3928 * applicable for weak-ordered memory model archs,
3929 * such as IA-64). */
3930 wmb();
3931 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
3932 }
1da177e4
LT		 3933}
3934
2d7edb92
MC		 3935/**
3936 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3937 * @adapter: address of board private structure
3938 **/
3939
3940static void
581d708e 3941e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 3942 struct e1000_rx_ring *rx_ring,
3943 int cleaned_count)
2d7edb92 3944{
2d7edb92
MC		 3945 struct net_device *netdev = adapter->netdev;
3946 struct pci_dev *pdev = adapter->pdev;
3947 union e1000_rx_desc_packet_split *rx_desc;
3948 struct e1000_buffer *buffer_info;
3949 struct e1000_ps_page *ps_page;
3950 struct e1000_ps_page_dma *ps_page_dma;
3951 struct sk_buff *skb;
3952 unsigned int i, j;
3953
3954 i = rx_ring->next_to_use;
3955 buffer_info = &rx_ring->buffer_info[i];
3956 ps_page = &rx_ring->ps_page[i];
3957 ps_page_dma = &rx_ring->ps_page_dma[i];
3958
72d64a43 3959 while (cleaned_count--) {
2d7edb92
MC		 3960 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3961
96838a40 3962 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 3963 if (j < adapter->rx_ps_pages) {
3964 if (likely(!ps_page->ps_page[j])) {
3965 ps_page->ps_page[j] =
3966 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 3967 if (unlikely(!ps_page->ps_page[j])) {
3968 adapter->alloc_rx_buff_failed++;
e4c811c9 3969 goto no_buffers;
b92ff8ee 3970 }
e4c811c9
MC		 3971 ps_page_dma->ps_page_dma[j] =
3972 pci_map_page(pdev,
3973 ps_page->ps_page[j],
3974 0, PAGE_SIZE,
3975 PCI_DMA_FROMDEVICE);
3976 }
3977 /* Refresh the desc even if buffer_addrs didn't
96838a40 3978 * change because each write-back erases
e4c811c9
MC		 3979 * this info.
3980 */
3981 rx_desc->read.buffer_addr[j+1] =
3982 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3983 } else
3984 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 3985 }
3986
3987 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3988
b92ff8ee
JB		 3989 if (unlikely(!skb)) {
3990 adapter->alloc_rx_buff_failed++;
2d7edb92 3991 break;
b92ff8ee 3992 }
2d7edb92
MC		 3993
3994 /* Make buffer alignment 2 beyond a 16 byte boundary
3995 * this will result in a 16 byte aligned IP header after
3996 * the 14 byte MAC header is removed
3997 */
3998 skb_reserve(skb, NET_IP_ALIGN);
3999
4000 skb->dev = netdev;
4001
4002 buffer_info->skb = skb;
4003 buffer_info->length = adapter->rx_ps_bsize0;
4004 buffer_info->dma = pci_map_single(pdev, skb->data,
4005 adapter->rx_ps_bsize0,
4006 PCI_DMA_FROMDEVICE);
4007
4008 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4009
96838a40 4010 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4011 buffer_info = &rx_ring->buffer_info[i];
4012 ps_page = &rx_ring->ps_page[i];
4013 ps_page_dma = &rx_ring->ps_page_dma[i];
4014 }
4015
4016no_buffers:
b92ff8ee
JB		 4017 if (likely(rx_ring->next_to_use != i)) {
4018 rx_ring->next_to_use = i;
4019 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4020
4021 /* Force memory writes to complete before letting h/w
4022 * know there are new descriptors to fetch. (Only
4023 * applicable for weak-ordered memory model archs,
4024 * such as IA-64). */
4025 wmb();
4026 /* Hardware increments by 16 bytes, but packet split
4027 * descriptors are 32 bytes...so we increment tail
4028 * twice as much.
4029 */
4030 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4031 }
2d7edb92
MC		 4032}
4033
1da177e4
LT		 4034/**
4035 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4036 * @adapter:
4037 **/
4038
4039static void
4040e1000_smartspeed(struct e1000_adapter *adapter)
4041{
4042 uint16_t phy_status;
4043 uint16_t phy_ctrl;
4044
96838a40 4045 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4046 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4047 return;
4048
96838a40 4049 if (adapter->smartspeed == 0) {
1da177e4
LT		 4050 /* If Master/Slave config fault is asserted twice,
4051 * we assume back-to-back */
4052 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4053 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4054 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4055 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4056 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4057 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4058 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4059 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4060 phy_ctrl);
4061 adapter->smartspeed++;
96838a40 4062 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4063 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4064 &phy_ctrl)) {
4065 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4066 MII_CR_RESTART_AUTO_NEG);
4067 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4068 phy_ctrl);
4069 }
4070 }
4071 return;
96838a40 4072 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4073 /* If still no link, perhaps using 2/3 pair cable */
4074 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4075 phy_ctrl |= CR_1000T_MS_ENABLE;
4076 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4077 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4078 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4079 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4080 MII_CR_RESTART_AUTO_NEG);
4081 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4082 }
4083 }
4084 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4085 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4086 adapter->smartspeed = 0;
4087}
4088
4089/**
4090 * e1000_ioctl -
4091 * @netdev:
4092 * @ifreq:
4093 * @cmd:
4094 **/
4095
4096static int
4097e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4098{
4099 switch (cmd) {
4100 case SIOCGMIIPHY:
4101 case SIOCGMIIREG:
4102 case SIOCSMIIREG:
4103 return e1000_mii_ioctl(netdev, ifr, cmd);
4104 default:
4105 return -EOPNOTSUPP;
4106 }
4107}
4108
4109/**
4110 * e1000_mii_ioctl -
4111 * @netdev:
4112 * @ifreq:
4113 * @cmd:
4114 **/
4115
4116static int
4117e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4118{
60490fe0 4119 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4120 struct mii_ioctl_data *data = if_mii(ifr);
4121 int retval;
4122 uint16_t mii_reg;
4123 uint16_t spddplx;
97876fc6 4124 unsigned long flags;
1da177e4 4125
96838a40 4126 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4127 return -EOPNOTSUPP;
4128
4129 switch (cmd) {
4130 case SIOCGMIIPHY:
4131 data->phy_id = adapter->hw.phy_addr;
4132 break;
4133 case SIOCGMIIREG:
96838a40 4134 if (!capable(CAP_NET_ADMIN))
1da177e4 4135 return -EPERM;
97876fc6 4136 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4137 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4138 &data->val_out)) {
4139 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4140 return -EIO;
97876fc6
MC		 4141 }
4142 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4143 break;
4144 case SIOCSMIIREG:
96838a40 4145 if (!capable(CAP_NET_ADMIN))
1da177e4 4146 return -EPERM;
96838a40 4147 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4148 return -EFAULT;
4149 mii_reg = data->val_in;
97876fc6 4150 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4151 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4152 mii_reg)) {
4153 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4154 return -EIO;
97876fc6 4155 }
dc86d32a 4156 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4157 switch (data->reg_num) {
4158 case PHY_CTRL:
96838a40 4159 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4160 break;
96838a40 4161 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4162 adapter->hw.autoneg = 1;
4163 adapter->hw.autoneg_advertised = 0x2F;
4164 } else {
4165 if (mii_reg & 0x40)
4166 spddplx = SPEED_1000;
4167 else if (mii_reg & 0x2000)
4168 spddplx = SPEED_100;
4169 else
4170 spddplx = SPEED_10;
4171 spddplx += (mii_reg & 0x100)
cb764326
JK		 4172 ? DUPLEX_FULL :
4173 DUPLEX_HALF;
1da177e4
LT		 4174 retval = e1000_set_spd_dplx(adapter,
4175 spddplx);
96838a40 4176 if (retval) {
97876fc6 4177 spin_unlock_irqrestore(
96838a40 4178 &adapter->stats_lock,
97876fc6 4179 flags);
1da177e4 4180 return retval;
97876fc6 4181 }
1da177e4 4182 }
96838a40 4183 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4184 e1000_down(adapter);
4185 e1000_up(adapter);
4186 } else
4187 e1000_reset(adapter);
4188 break;
4189 case M88E1000_PHY_SPEC_CTRL:
4190 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4191 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4192 spin_unlock_irqrestore(
4193 &adapter->stats_lock, flags);
1da177e4 4194 return -EIO;
97876fc6 4195 }
1da177e4
LT		 4196 break;
4197 }
4198 } else {
4199 switch (data->reg_num) {
4200 case PHY_CTRL:
96838a40 4201 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4202 break;
96838a40 4203 if (netif_running(adapter->netdev)) {
1da177e4
LT		 4204 e1000_down(adapter);
4205 e1000_up(adapter);
4206 } else
4207 e1000_reset(adapter);
4208 break;
4209 }
4210 }
97876fc6 4211 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4212 break;
4213 default:
4214 return -EOPNOTSUPP;
4215 }
4216 return E1000_SUCCESS;
4217}
4218
4219void
4220e1000_pci_set_mwi(struct e1000_hw *hw)
4221{
4222 struct e1000_adapter *adapter = hw->back;
2648345f 4223 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4224
96838a40 4225 if (ret_val)
2648345f 4226 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4227}
4228
4229void
4230e1000_pci_clear_mwi(struct e1000_hw *hw)
4231{
4232 struct e1000_adapter *adapter = hw->back;
4233
4234 pci_clear_mwi(adapter->pdev);
4235}
4236
4237void
4238e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4239{
4240 struct e1000_adapter *adapter = hw->back;
4241
4242 pci_read_config_word(adapter->pdev, reg, value);
4243}
4244
4245void
4246e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4247{
4248 struct e1000_adapter *adapter = hw->back;
4249
4250 pci_write_config_word(adapter->pdev, reg, *value);
4251}
4252
4253uint32_t
4254e1000_io_read(struct e1000_hw *hw, unsigned long port)
4255{
4256 return inl(port);
4257}
4258
4259void
4260e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4261{
4262 outl(value, port);
4263}
4264
4265static void
4266e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4267{
60490fe0 4268 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4269 uint32_t ctrl, rctl;
4270
4271 e1000_irq_disable(adapter);
4272 adapter->vlgrp = grp;
4273
96838a40 4274 if (grp) {
1da177e4
LT		 4275 /* enable VLAN tag insert/strip */
4276 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4277 ctrl |= E1000_CTRL_VME;
4278 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4279
4280 /* enable VLAN receive filtering */
4281 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4282 rctl |= E1000_RCTL_VFE;
4283 rctl &= ~E1000_RCTL_CFIEN;
4284 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4285 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4286 } else {
4287 /* disable VLAN tag insert/strip */
4288 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4289 ctrl &= ~E1000_CTRL_VME;
4290 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4291
4292 /* disable VLAN filtering */
4293 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4294 rctl &= ~E1000_RCTL_VFE;
4295 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
96838a40 4296 if (adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
2d7edb92
MC		 4297 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4298 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4299 }
1da177e4
LT		 4300 }
4301
4302 e1000_irq_enable(adapter);
4303}
4304
4305static void
4306e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4307{
60490fe0 4308 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4309 uint32_t vfta, index;
96838a40
JB		 4310
4311 if ((adapter->hw.mng_cookie.status &
4312 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4313 (vid == adapter->mng_vlan_id))
2d7edb92 4314 return;
1da177e4
LT		 4315 /* add VID to filter table */
4316 index = (vid >> 5) & 0x7F;
4317 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4318 vfta |= (1 << (vid & 0x1F));
4319 e1000_write_vfta(&adapter->hw, index, vfta);
4320}
4321
4322static void
4323e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4324{
60490fe0 4325 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4326 uint32_t vfta, index;
4327
4328 e1000_irq_disable(adapter);
4329
96838a40 4330 if (adapter->vlgrp)
1da177e4
LT		 4331 adapter->vlgrp->vlan_devices[vid] = NULL;
4332
4333 e1000_irq_enable(adapter);
4334
96838a40
JB		 4335 if ((adapter->hw.mng_cookie.status &
4336 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4337 (vid == adapter->mng_vlan_id)) {
4338 /* release control to f/w */
4339 e1000_release_hw_control(adapter);
2d7edb92 4340 return;
ff147013
JK		 4341 }
4342
1da177e4
LT		 4343 /* remove VID from filter table */
4344 index = (vid >> 5) & 0x7F;
4345 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4346 vfta &= ~(1 << (vid & 0x1F));
4347 e1000_write_vfta(&adapter->hw, index, vfta);
4348}
4349
4350static void
4351e1000_restore_vlan(struct e1000_adapter *adapter)
4352{
4353 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4354
96838a40 4355 if (adapter->vlgrp) {
1da177e4 4356 uint16_t vid;
96838a40
JB		 4357 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4358 if (!adapter->vlgrp->vlan_devices[vid])
1da177e4
LT		 4359 continue;
4360 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4361 }
4362 }
4363}
4364
4365int
4366e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4367{
4368 adapter->hw.autoneg = 0;
4369
6921368f 4370 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 4371 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 4372 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4373 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4374 return -EINVAL;
4375 }
4376
96838a40 4377 switch (spddplx) {
1da177e4
LT		 4378 case SPEED_10 + DUPLEX_HALF:
4379 adapter->hw.forced_speed_duplex = e1000_10_half;
4380 break;
4381 case SPEED_10 + DUPLEX_FULL:
4382 adapter->hw.forced_speed_duplex = e1000_10_full;
4383 break;
4384 case SPEED_100 + DUPLEX_HALF:
4385 adapter->hw.forced_speed_duplex = e1000_100_half;
4386 break;
4387 case SPEED_100 + DUPLEX_FULL:
4388 adapter->hw.forced_speed_duplex = e1000_100_full;
4389 break;
4390 case SPEED_1000 + DUPLEX_FULL:
4391 adapter->hw.autoneg = 1;
4392 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4393 break;
4394 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4395 default:
2648345f 4396 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4397 return -EINVAL;
4398 }
4399 return 0;
4400}
4401
b6a1d5f8 4402#ifdef CONFIG_PM
0f15a8fa
JK		 4403/* Save/restore 16 or 64 dwords of PCI config space depending on which
4404 * bus we're on (PCI(X) vs. PCI-E)
2f82665f
JB		 4405 */
4406#define PCIE_CONFIG_SPACE_LEN 256
4407#define PCI_CONFIG_SPACE_LEN 64
4408static int
4409e1000_pci_save_state(struct e1000_adapter *adapter)
4410{
4411 struct pci_dev *dev = adapter->pdev;
4412 int size;
4413 int i;
0f15a8fa 4414
2f82665f
JB		 4415 if (adapter->hw.mac_type >= e1000_82571)
4416 size = PCIE_CONFIG_SPACE_LEN;
4417 else
4418 size = PCI_CONFIG_SPACE_LEN;
4419
4420 WARN_ON(adapter->config_space != NULL);
4421
4422 adapter->config_space = kmalloc(size, GFP_KERNEL);
4423 if (!adapter->config_space) {
4424 DPRINTK(PROBE, ERR, "unable to allocate %d bytes\n", size);
4425 return -ENOMEM;
4426 }
4427 for (i = 0; i < (size / 4); i++)
4428 pci_read_config_dword(dev, i * 4, &adapter->config_space[i]);
4429 return 0;
4430}
4431
4432static void
4433e1000_pci_restore_state(struct e1000_adapter *adapter)
4434{
4435 struct pci_dev *dev = adapter->pdev;
4436 int size;
4437 int i;
0f15a8fa 4438
2f82665f
JB		 4439 if (adapter->config_space == NULL)
4440 return;
0f15a8fa 4441
2f82665f
JB		 4442 if (adapter->hw.mac_type >= e1000_82571)
4443 size = PCIE_CONFIG_SPACE_LEN;
4444 else
4445 size = PCI_CONFIG_SPACE_LEN;
4446 for (i = 0; i < (size / 4); i++)
4447 pci_write_config_dword(dev, i * 4, adapter->config_space[i]);
4448 kfree(adapter->config_space);
4449 adapter->config_space = NULL;
4450 return;
4451}
4452#endif /* CONFIG_PM */
4453
1da177e4 4454static int
829ca9a3 4455e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4456{
4457 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4458 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4459 uint32_t ctrl, ctrl_ext, rctl, manc, status;
1da177e4 4460 uint32_t wufc = adapter->wol;
240b1710 4461 int retval = 0;
1da177e4
LT		 4462
4463 netif_device_detach(netdev);
4464
96838a40 4465 if (netif_running(netdev))
1da177e4
LT		 4466 e1000_down(adapter);
4467
2f82665f 4468#ifdef CONFIG_PM
0f15a8fa
JK		 4469 /* Implement our own version of pci_save_state(pdev) because pci-
4470 * express adapters have 256-byte config spaces. */
2f82665f
JB		 4471 retval = e1000_pci_save_state(adapter);
4472 if (retval)
4473 return retval;
4474#endif
4475
1da177e4 4476 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 4477 if (status & E1000_STATUS_LU)
1da177e4
LT		 4478 wufc &= ~E1000_WUFC_LNKC;
4479
96838a40 4480 if (wufc) {
1da177e4
LT		 4481 e1000_setup_rctl(adapter);
4482 e1000_set_multi(netdev);
4483
4484 /* turn on all-multi mode if wake on multicast is enabled */
96838a40 4485 if (adapter->wol & E1000_WUFC_MC) {
1da177e4
LT		 4486 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4487 rctl |= E1000_RCTL_MPE;
4488 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4489 }
4490
96838a40 4491 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 4492 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4493 /* advertise wake from D3Cold */
4494 #define E1000_CTRL_ADVD3WUC 0x00100000
4495 /* phy power management enable */
4496 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4497 ctrl |= E1000_CTRL_ADVD3WUC |
4498 E1000_CTRL_EN_PHY_PWR_MGMT;
4499 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4500 }
4501
96838a40 4502 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 4503 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4504 /* keep the laser running in D3 */
4505 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4506 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4507 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4508 }
4509
2d7edb92
MC		 4510 /* Allow time for pending master requests to run */
4511 e1000_disable_pciex_master(&adapter->hw);
4512
1da177e4
LT		 4513 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4514 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 4515 pci_enable_wake(pdev, PCI_D3hot, 1);
4516 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4517 } else {
4518 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4519 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 4520 pci_enable_wake(pdev, PCI_D3hot, 0);
4521 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4522 }
4523
96838a40 4524 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4525 adapter->hw.media_type == e1000_media_type_copper) {
4526 manc = E1000_READ_REG(&adapter->hw, MANC);
96838a40 4527 if (manc & E1000_MANC_SMBUS_EN) {
1da177e4
LT		 4528 manc |= E1000_MANC_ARP_EN;
4529 E1000_WRITE_REG(&adapter->hw, MANC, manc);
d0e027db
AK		 4530 pci_enable_wake(pdev, PCI_D3hot, 1);
4531 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 4532 }
4533 }
4534
b55ccb35
JK		 4535 /* Release control of h/w to f/w. If f/w is AMT enabled, this
4536 * would have already happened in close and is redundant. */
4537 e1000_release_hw_control(adapter);
2d7edb92 4538
1da177e4 4539 pci_disable_device(pdev);
240b1710 4540
d0e027db 4541 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4542
4543 return 0;
4544}
4545
2f82665f 4546#ifdef CONFIG_PM
1da177e4
LT		 4547static int
4548e1000_resume(struct pci_dev *pdev)
4549{
4550 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4551 struct e1000_adapter *adapter = netdev_priv(netdev);
b55ccb35 4552 uint32_t manc, ret_val;
1da177e4 4553
d0e027db 4554 pci_set_power_state(pdev, PCI_D0);
2f82665f 4555 e1000_pci_restore_state(adapter);
2b02893e 4556 ret_val = pci_enable_device(pdev);
a4cb847d 4557 pci_set_master(pdev);
1da177e4 4558
d0e027db
AK		 4559 pci_enable_wake(pdev, PCI_D3hot, 0);
4560 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4561
4562 e1000_reset(adapter);
4563 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4564
96838a40 4565 if (netif_running(netdev))
1da177e4
LT		 4566 e1000_up(adapter);
4567
4568 netif_device_attach(netdev);
4569
96838a40 4570 if (adapter->hw.mac_type >= e1000_82540 &&
1da177e4
LT		 4571 adapter->hw.media_type == e1000_media_type_copper) {
4572 manc = E1000_READ_REG(&adapter->hw, MANC);
4573 manc &= ~(E1000_MANC_ARP_EN);
4574 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4575 }
4576
b55ccb35
JK		 4577 /* If the controller is 82573 and f/w is AMT, do not set
4578 * DRV_LOAD until the interface is up. For all other cases,
4579 * let the f/w know that the h/w is now under the control
4580 * of the driver. */
4581 if (adapter->hw.mac_type != e1000_82573 ||
4582 !e1000_check_mng_mode(&adapter->hw))
4583 e1000_get_hw_control(adapter);
2d7edb92 4584
1da177e4
LT		 4585 return 0;
4586}
4587#endif
c653e635
AK		 4588
4589static void e1000_shutdown(struct pci_dev *pdev)
4590{
4591 e1000_suspend(pdev, PMSG_SUSPEND);
4592}
4593
1da177e4
LT		 4594#ifdef CONFIG_NET_POLL_CONTROLLER
4595/*
4596 * Polling 'interrupt' - used by things like netconsole to send skbs
4597 * without having to re-enable interrupts. It's not called while
4598 * the interrupt routine is executing.
4599 */
4600static void
2648345f 4601e1000_netpoll(struct net_device *netdev)
1da177e4 4602{
60490fe0 4603 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4604 disable_irq(adapter->pdev->irq);
4605 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4606 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 4607#ifndef CONFIG_E1000_NAPI
4608 adapter->clean_rx(adapter, adapter->rx_ring);
4609#endif
1da177e4
LT		 4610 enable_irq(adapter->pdev->irq);
4611}
4612#endif
4613
9026729b
AK		 4614/**
4615 * e1000_io_error_detected - called when PCI error is detected
4616 * @pdev: Pointer to PCI device
4617 * @state: The current pci conneection state
4618 *
4619 * This function is called after a PCI bus error affecting
4620 * this device has been detected.
4621 */
4622static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4623{
4624 struct net_device *netdev = pci_get_drvdata(pdev);
4625 struct e1000_adapter *adapter = netdev->priv;
4626
4627 netif_device_detach(netdev);
4628
4629 if (netif_running(netdev))
4630 e1000_down(adapter);
4631
4632 /* Request a slot slot reset. */
4633 return PCI_ERS_RESULT_NEED_RESET;
4634}
4635
4636/**
4637 * e1000_io_slot_reset - called after the pci bus has been reset.
4638 * @pdev: Pointer to PCI device
4639 *
4640 * Restart the card from scratch, as if from a cold-boot. Implementation
4641 * resembles the first-half of the e1000_resume routine.
4642 */
4643static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
4644{
4645 struct net_device *netdev = pci_get_drvdata(pdev);
4646 struct e1000_adapter *adapter = netdev->priv;
4647
4648 if (pci_enable_device(pdev)) {
4649 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
4650 return PCI_ERS_RESULT_DISCONNECT;
4651 }
4652 pci_set_master(pdev);
4653
4654 pci_enable_wake(pdev, 3, 0);
4655 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
4656
4657 /* Perform card reset only on one instance of the card */
4658 if (PCI_FUNC (pdev->devfn) != 0)
4659 return PCI_ERS_RESULT_RECOVERED;
4660
4661 e1000_reset(adapter);
4662 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4663
4664 return PCI_ERS_RESULT_RECOVERED;
4665}
4666
4667/**
4668 * e1000_io_resume - called when traffic can start flowing again.
4669 * @pdev: Pointer to PCI device
4670 *
4671 * This callback is called when the error recovery driver tells us that
4672 * its OK to resume normal operation. Implementation resembles the
4673 * second-half of the e1000_resume routine.
4674 */
4675static void e1000_io_resume(struct pci_dev *pdev)
4676{
4677 struct net_device *netdev = pci_get_drvdata(pdev);
4678 struct e1000_adapter *adapter = netdev->priv;
4679 uint32_t manc, swsm;
4680
4681 if (netif_running(netdev)) {
4682 if (e1000_up(adapter)) {
4683 printk("e1000: can't bring device back up after reset\n");
4684 return;
4685 }
4686 }
4687
4688 netif_device_attach(netdev);
4689
4690 if (adapter->hw.mac_type >= e1000_82540 &&
4691 adapter->hw.media_type == e1000_media_type_copper) {
4692 manc = E1000_READ_REG(&adapter->hw, MANC);
4693 manc &= ~(E1000_MANC_ARP_EN);
4694 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4695 }
4696
4697 switch (adapter->hw.mac_type) {
4698 case e1000_82573:
4699 swsm = E1000_READ_REG(&adapter->hw, SWSM);
4700 E1000_WRITE_REG(&adapter->hw, SWSM,
4701 swsm | E1000_SWSM_DRV_LOAD);
4702 break;
4703 default:
4704 break;
4705 }
4706
4707 if (netif_running(netdev))
4708 mod_timer(&adapter->watchdog_timer, jiffies);
4709}
4710
1da177e4 4711/* e1000_main.c */
Empty description
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