[linux.git] / drivers / ide / ns87415.c

/*
 * Copyright (C) 1997-1998	Mark Lord <[email protected]>
 * Copyright (C) 1998		Eddie C. Dost <[email protected]>
 * Copyright (C) 1999-2000	Andre Hedrick <[email protected]>
 * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
 *
 * Inspired by an earlier effort from David S. Miller <[email protected]>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#define DRV_NAME "ns87415"

#ifdef CONFIG_SUPERIO
/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 * which use the integrated NS87514 cell for CD-ROM support.
 * i.e we have to support for CD-ROM installs.
 * See drivers/parisc/superio.c for more gory details.
 */
#include <asm/superio.h>

#define SUPERIO_IDE_MAX_RETRIES 25

/* Because of a defect in Super I/O, all reads of the PCI DMA status 
 * registers, IDE status register and the IDE select register need to be 
 * retried
 */
static u8 superio_ide_inb (unsigned long port)
{
	u8 tmp;
	int retries = SUPERIO_IDE_MAX_RETRIES;

	/* printk(" [ reading port 0x%x with retry ] ", port); */

	do {
		tmp = inb(port);
		if (tmp == 0)
			udelay(50);
	} while (tmp == 0 && retries-- > 0);

	return tmp;
}

static u8 superio_read_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->io_ports.status_addr);
}

static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
}

static void superio_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
{
	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
	struct ide_taskfile *tf = &cmd->tf;

	if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) {
		u16 data = inw(io_ports->data_addr);

		tf->data = data & 0xff;
		tf->hob_data = (data >> 8) & 0xff;
	}

	/* be sure we're looking at the low order bits */
	outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);

	if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE)
		tf->feature = inb(io_ports->feature_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
		tf->nsect  = inb(io_ports->nsect_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
		tf->lbal   = inb(io_ports->lbal_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
		tf->lbam   = inb(io_ports->lbam_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
		tf->lbah   = inb(io_ports->lbah_addr);
	if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
		tf->device = superio_ide_inb(io_ports->device_addr);

	if (cmd->tf_flags & IDE_TFLAG_LBA48) {
		outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);

		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
			tf->hob_feature = inb(io_ports->feature_addr);
		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
			tf->hob_nsect   = inb(io_ports->nsect_addr);
		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
			tf->hob_lbal    = inb(io_ports->lbal_addr);
		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
			tf->hob_lbam    = inb(io_ports->lbam_addr);
		if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
			tf->hob_lbah    = inb(io_ports->lbah_addr);
	}
}

static const struct ide_tp_ops superio_tp_ops = {
	.exec_command		= ide_exec_command,
	.read_status		= superio_read_status,
	.read_altstatus		= ide_read_altstatus,

	.set_irq		= ide_set_irq,

	.tf_load		= ide_tf_load,
	.tf_read		= superio_tf_read,

	.input_data		= ide_input_data,
	.output_data		= ide_output_data,
};

static void __devinit superio_init_iops(struct hwif_s *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u32 dma_stat;
	u8 port = hwif->channel, tmp;

	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);

	/* Clear error/interrupt, enable dma */
	tmp = superio_ide_inb(dma_stat);
	outb(tmp | 0x66, dma_stat);
}
#else
#define superio_dma_sff_read_status ide_dma_sff_read_status
#endif

static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };

/*
 * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
 * the IRQ associated with the port,
 * and selects either PIO or DMA handshaking for the next I/O operation.
 */
static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = drive->hwif;
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
	unsigned long flags;

	local_irq_save(flags);
	new = *old;

	/* Adjust IRQ enable bit */
	bit = 1 << (8 + hwif->channel);

	if (drive->dev_flags & IDE_DFLAG_PRESENT)
		new &= ~bit;
	else
		new |= bit;

	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	bit   = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
	other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);

	if (new != *old) {
		unsigned char stat;

		/*
		 * Don't change DMA engine settings while Write Buffers
		 * are busy.
		 */
		(void) pci_read_config_byte(dev, 0x43, &stat);
		while (stat & 0x03) {
			udelay(1);
			(void) pci_read_config_byte(dev, 0x43, &stat);
		}

		*old = new;
		(void) pci_write_config_dword(dev, 0x40, new);

		/*
		 * And let things settle...
		 */
		udelay(10);
	}

	local_irq_restore(flags);
}

static void ns87415_selectproc (ide_drive_t *drive)
{
	ns87415_prepare_drive(drive,
			      !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
}

static int ns87415_dma_end(ide_drive_t *drive)
{
	ide_hwif_t *hwif = drive->hwif;
	u8 dma_stat = 0, dma_cmd = 0;

	drive->waiting_for_dma = 0;
	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
	/* get DMA command mode */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
	/* and free any DMA resources */
	ide_destroy_dmatable(drive);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int ns87415_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
{
	/* select DMA xfer */
	ns87415_prepare_drive(drive, 1);
	if (ide_dma_setup(drive, cmd) == 0)
		return 0;
	/* DMA failed: select PIO xfer */
	ns87415_prepare_drive(drive, 0);
	return 1;
}

static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int ctrl, using_inta;
	u8 progif;
#ifdef __sparc_v9__
	int timeout;
	u8 stat;
#endif

	/*
	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
	 * Also, leave IRQ masked during drive probing, to prevent infinite
	 * interrupts from a potentially floating INTA..
	 *
	 * IRQs get unmasked in selectproc when drive is first used.
	 */
	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	(void) pci_read_config_byte(dev, 0x09, &progif);
	/* is irq in "native" mode? */
	using_inta = progif & (1 << (hwif->channel << 1));
	if (!using_inta)
		using_inta = ctrl & (1 << (4 + hwif->channel));
	if (hwif->mate) {
		hwif->select_data = hwif->mate->select_data;
	} else {
		hwif->select_data = (unsigned long)
					&ns87415_control[ns87415_count++];
		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
		if (using_inta)
			ctrl &= ~(1 << 6);	/* unmask INTA */
		*((unsigned int *)hwif->select_data) = ctrl;
		(void) pci_write_config_dword(dev, 0x40, ctrl);

		/*
		 * Set prefetch size to 512 bytes for both ports,
		 * but don't turn on/off prefetching here.
		 */
		pci_write_config_byte(dev, 0x55, 0xee);

#ifdef __sparc_v9__
		/*
		 * XXX: Reset the device, if we don't it will not respond to
		 *      SELECT_DRIVE() properly during first ide_probe_port().
		 */
		timeout = 10000;
		outb(12, hwif->io_ports.ctl_addr);
		udelay(10);
		outb(8, hwif->io_ports.ctl_addr);
		do {
			udelay(50);
			stat = hwif->tp_ops->read_status(hwif);
			if (stat == 0xff)
				break;
		} while ((stat & ATA_BUSY) && --timeout);
#endif
	}

	if (!using_inta)
		hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);

	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
}

static const struct ide_port_ops ns87415_port_ops = {
	.selectproc		= ns87415_selectproc,
};

static const struct ide_dma_ops ns87415_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ns87415_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= ide_dma_start,
	.dma_end		= ns87415_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timeout		= ide_dma_timeout,
	.dma_sff_read_status	= superio_dma_sff_read_status,
};

static const struct ide_port_info ns87415_chipset __devinitdata = {
	.name		= DRV_NAME,
	.init_hwif	= init_hwif_ns87415,
	.port_ops	= &ns87415_port_ops,
	.dma_ops	= &ns87415_dma_ops,
	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_NO_ATAPI_DMA,
};

static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	struct ide_port_info d = ns87415_chipset;

#ifdef CONFIG_SUPERIO
	if (PCI_SLOT(dev->devfn) == 0xE) {
		/* Built-in - assume it's under superio. */
		d.init_iops = superio_init_iops;
		d.tp_ops = &superio_tp_ops;
	}
#endif
	return ide_pci_init_one(dev, &d, NULL);
}

static const struct pci_device_id ns87415_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);

static struct pci_driver ns87415_pci_driver = {
	.name		= "NS87415_IDE",
	.id_table	= ns87415_pci_tbl,
	.probe		= ns87415_init_one,
	.remove		= ide_pci_remove,
	.suspend	= ide_pci_suspend,
	.resume		= ide_pci_resume,
};

static int __init ns87415_ide_init(void)
{
	return ide_pci_register_driver(&ns87415_pci_driver);
}

static void __exit ns87415_ide_exit(void)
{
	pci_unregister_driver(&ns87415_pci_driver);
}

module_init(ns87415_ide_init);
module_exit(ns87415_ide_exit);

MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1997-1998 Mark Lord <[email protected]>
	3	* Copyright (C) 1998 Eddie C. Dost <[email protected]>
	4	* Copyright (C) 1999-2000 Andre Hedrick <[email protected]>
	5	* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
	6	*
	7	* Inspired by an earlier effort from David S. Miller <[email protected]>
	8	*/
	9
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/types.h>
	12	#include <linux/kernel.h>
1da177e4	13	#include <linux/interrupt.h>
1da177e4 LT	14	#include <linux/pci.h>
	15	#include <linux/delay.h>
	16	#include <linux/ide.h>
	17	#include <linux/init.h>
	18
	19	#include <asm/io.h>
	20
ced3ec8a BZ	21	#define DRV_NAME "ns87415"
ced3ec8a BZ	22
1da177e4 LT	23	#ifdef CONFIG_SUPERIO
	24	/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
	25	* Unfortunately, it's built-in on all Astro-based PA-RISC workstations
	26	* which use the integrated NS87514 cell for CD-ROM support.
	27	* i.e we have to support for CD-ROM installs.
	28	* See drivers/parisc/superio.c for more gory details.
	29	*/
	30	#include <asm/superio.h>
	31
1da177e4 LT	32	#define SUPERIO_IDE_MAX_RETRIES 25
	33
	34	/* Because of a defect in Super I/O, all reads of the PCI DMA status
	35	* registers, IDE status register and the IDE select register need to be
	36	* retried
	37	*/
	38	static u8 superio_ide_inb (unsigned long port)
	39	{
761052e6 BZ	40	u8 tmp;
	41	int retries = SUPERIO_IDE_MAX_RETRIES;
	42
	43	/* printk(" [ reading port 0x%x with retry ] ", port); */
1da177e4	44
761052e6 BZ	45	do {
	46	tmp = inb(port);
	47	if (tmp == 0)
	48	udelay(50);
	49	} while (tmp == 0 && retries-- > 0);
	50
	51	return tmp;
1da177e4 LT	52	}
1da177e4 LT	53
b73c7ee2 BZ	54	static u8 superio_read_status(ide_hwif_t *hwif)
	55	{
	56	return superio_ide_inb(hwif->io_ports.status_addr);
	57	}
	58
592b5315	59	static u8 superio_dma_sff_read_status(ide_hwif_t *hwif)
b2f951aa	60	{
cab7f8ed	61	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
b2f951aa BZ	62	}
b2f951aa BZ	63
22aa4b32	64	static void superio_tf_read(ide_drive_t drive, struct ide_cmd cmd)
ea23b8ba BZ	65	{
ea23b8ba BZ	66	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
22aa4b32	67	struct ide_taskfile *tf = &cmd->tf;
ea23b8ba	68
22aa4b32	69	if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) {
ea23b8ba BZ	70	u16 data = inw(io_ports->data_addr);
	71
	72	tf->data = data & 0xff;
	73	tf->hob_data = (data >> 8) & 0xff;
	74	}
	75
	76	/* be sure we're looking at the low order bits */
ff074883	77	outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
ea23b8ba	78
22aa4b32	79	if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE)
92eb4380	80	tf->feature = inb(io_ports->feature_addr);
22aa4b32	81	if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
ea23b8ba	82	tf->nsect = inb(io_ports->nsect_addr);
22aa4b32	83	if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
ea23b8ba	84	tf->lbal = inb(io_ports->lbal_addr);
22aa4b32	85	if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
ea23b8ba	86	tf->lbam = inb(io_ports->lbam_addr);
22aa4b32	87	if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
ea23b8ba	88	tf->lbah = inb(io_ports->lbah_addr);
22aa4b32	89	if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
ea23b8ba BZ	90	tf->device = superio_ide_inb(io_ports->device_addr);
ea23b8ba BZ	91
22aa4b32	92	if (cmd->tf_flags & IDE_TFLAG_LBA48) {
ff074883	93	outb(ATA_DEVCTL_OBS \| 0x80, io_ports->ctl_addr);
ea23b8ba	94
22aa4b32	95	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
ea23b8ba	96	tf->hob_feature = inb(io_ports->feature_addr);
22aa4b32	97	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
ea23b8ba	98	tf->hob_nsect = inb(io_ports->nsect_addr);
22aa4b32	99	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
ea23b8ba	100	tf->hob_lbal = inb(io_ports->lbal_addr);
22aa4b32	101	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
ea23b8ba	102	tf->hob_lbam = inb(io_ports->lbam_addr);
22aa4b32	103	if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
ea23b8ba BZ	104	tf->hob_lbah = inb(io_ports->lbah_addr);
	105	}
	106	}
	107
374e042c BZ	108	static const struct ide_tp_ops superio_tp_ops = {
	109	.exec_command = ide_exec_command,
	110	.read_status = superio_read_status,
	111	.read_altstatus = ide_read_altstatus,
374e042c BZ	112
	113	.set_irq = ide_set_irq,
	114
	115	.tf_load = ide_tf_load,
	116	.tf_read = superio_tf_read,
	117
	118	.input_data = ide_input_data,
	119	.output_data = ide_output_data,
	120	};
	121
	122	static void __devinit superio_init_iops(struct hwif_s *hwif)
1da177e4	123	{
36501650	124	struct pci_dev *pdev = to_pci_dev(hwif->dev);
761052e6	125	u32 dma_stat;
36501650	126	u8 port = hwif->channel, tmp;
1da177e4	127
761052e6	128	dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
1da177e4 LT	129
1da177e4 LT	130	/* Clear error/interrupt, enable dma */
761052e6 BZ	131	tmp = superio_ide_inb(dma_stat);
761052e6 BZ	132	outb(tmp \| 0x66, dma_stat);
1da177e4	133	}
592b5315 SS	134	#else
592b5315 SS	135	#define superio_dma_sff_read_status ide_dma_sff_read_status
1da177e4 LT	136	#endif
	137
	138	static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
	139
	140	/*
97100fc8	141	* This routine either enables/disables (according to IDE_DFLAG_PRESENT)
898ec223	142	* the IRQ associated with the port,
1da177e4 LT	143	* and selects either PIO or DMA handshaking for the next I/O operation.
	144	*/
	145	static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
	146	{
898ec223	147	ide_hwif_t *hwif = drive->hwif;
36501650	148	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	149	unsigned int bit, other, new, old = (unsigned int ) hwif->select_data;
1da177e4 LT	150	unsigned long flags;
	151
	152	local_irq_save(flags);
	153	new = *old;
	154
	155	/* Adjust IRQ enable bit */
	156	bit = 1 << (8 + hwif->channel);
97100fc8 BZ	157
	158	if (drive->dev_flags & IDE_DFLAG_PRESENT)
	159	new &= ~bit;
	160	else
	161	new \|= bit;
1da177e4 LT	162
1da177e4 LT	163	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
123995b9 BZ	164	bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
123995b9 BZ	165	other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
1da177e4 LT	166	new = use_dma ? ((new & ~other) \| bit) : (new & ~bit);
	167
	168	if (new != *old) {
	169	unsigned char stat;
	170
	171	/*
	172	* Don't change DMA engine settings while Write Buffers
	173	* are busy.
	174	*/
	175	(void) pci_read_config_byte(dev, 0x43, &stat);
	176	while (stat & 0x03) {
	177	udelay(1);
	178	(void) pci_read_config_byte(dev, 0x43, &stat);
	179	}
	180
	181	*old = new;
	182	(void) pci_write_config_dword(dev, 0x40, new);
	183
	184	/*
	185	* And let things settle...
	186	*/
	187	udelay(10);
	188	}
	189
	190	local_irq_restore(flags);
	191	}
	192
	193	static void ns87415_selectproc (ide_drive_t *drive)
	194	{
97100fc8 BZ	195	ns87415_prepare_drive(drive,
97100fc8 BZ	196	!!(drive->dev_flags & IDE_DFLAG_USING_DMA));
1da177e4 LT	197	}
1da177e4 LT	198
5e37bdc0	199	static int ns87415_dma_end(ide_drive_t *drive)
1da177e4	200	{
898ec223	201	ide_hwif_t *hwif = drive->hwif;
1da177e4 LT	202	u8 dma_stat = 0, dma_cmd = 0;
	203
	204	drive->waiting_for_dma = 0;
592b5315	205	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
cab7f8ed BZ	206	/* get DMA command mode */
cab7f8ed BZ	207	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	208	/* stop DMA */
cab7f8ed	209	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	210	/* from ERRATA: clear the INTR & ERROR bits */
cab7f8ed BZ	211	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
cab7f8ed BZ	212	outb(dma_cmd \| 6, hwif->dma_base + ATA_DMA_CMD);
1da177e4 LT	213	/* and free any DMA resources */
	214	ide_destroy_dmatable(drive);
	215	/* verify good DMA status */
	216	return (dma_stat & 7) != 4;
	217	}
	218
22981694	219	static int ns87415_dma_setup(ide_drive_t drive, struct ide_cmd cmd)
1da177e4 LT	220	{
	221	/* select DMA xfer */
	222	ns87415_prepare_drive(drive, 1);
22981694	223	if (ide_dma_setup(drive, cmd) == 0)
1da177e4 LT	224	return 0;
	225	/* DMA failed: select PIO xfer */
	226	ns87415_prepare_drive(drive, 0);
	227	return 1;
	228	}
	229
c20530ed	230	static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
1da177e4	231	{
36501650	232	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	233	unsigned int ctrl, using_inta;
	234	u8 progif;
	235	#ifdef __sparc_v9__
	236	int timeout;
	237	u8 stat;
	238	#endif
	239
1da177e4 LT	240	/*
	241	* We cannot probe for IRQ: both ports share common IRQ on INTA.
	242	* Also, leave IRQ masked during drive probing, to prevent infinite
	243	* interrupts from a potentially floating INTA..
	244	*
	245	* IRQs get unmasked in selectproc when drive is first used.
	246	*/
	247	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	248	(void) pci_read_config_byte(dev, 0x09, &progif);
	249	/* is irq in "native" mode? */
	250	using_inta = progif & (1 << (hwif->channel << 1));
	251	if (!using_inta)
	252	using_inta = ctrl & (1 << (4 + hwif->channel));
	253	if (hwif->mate) {
	254	hwif->select_data = hwif->mate->select_data;
	255	} else {
	256	hwif->select_data = (unsigned long)
	257	&ns87415_control[ns87415_count++];
	258	ctrl \|= (1 << 8) \| (1 << 9); /* mask both IRQs */
	259	if (using_inta)
	260	ctrl &= ~(1 << 6); /* unmask INTA */
	261	((unsigned int )hwif->select_data) = ctrl;
	262	(void) pci_write_config_dword(dev, 0x40, ctrl);
	263
	264	/*
	265	* Set prefetch size to 512 bytes for both ports,
	266	* but don't turn on/off prefetching here.
	267	*/
	268	pci_write_config_byte(dev, 0x55, 0xee);
	269
	270	#ifdef __sparc_v9__
	271	/*
9d501529 BZ	272	* XXX: Reset the device, if we don't it will not respond to
9d501529 BZ	273	* SELECT_DRIVE() properly during first ide_probe_port().
1da177e4 LT	274	*/
1da177e4 LT	275	timeout = 10000;
4c3032d8	276	outb(12, hwif->io_ports.ctl_addr);
1da177e4	277	udelay(10);
4c3032d8	278	outb(8, hwif->io_ports.ctl_addr);
1da177e4 LT	279	do {
1da177e4 LT	280	udelay(50);
374e042c	281	stat = hwif->tp_ops->read_status(hwif);
3a7d2484 BZ	282	if (stat == 0xff)
	283	break;
	284	} while ((stat & ATA_BUSY) && --timeout);
1da177e4 LT	285	#endif
	286	}
	287
	288	if (!using_inta)
973d9e74	289	hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
1da177e4 LT	290
	291	if (!hwif->dma_base)
	292	return;
	293
cab7f8ed	294	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	295	}
1da177e4 LT	296
ac95beed BZ	297	static const struct ide_port_ops ns87415_port_ops = {
	298	.selectproc = ns87415_selectproc,
	299	};
	300
f37afdac BZ	301	static const struct ide_dma_ops ns87415_dma_ops = {
f37afdac BZ	302	.dma_host_set = ide_dma_host_set,
5e37bdc0	303	.dma_setup = ns87415_dma_setup,
f37afdac BZ	304	.dma_exec_cmd = ide_dma_exec_cmd,
f37afdac BZ	305	.dma_start = ide_dma_start,
5e37bdc0	306	.dma_end = ns87415_dma_end,
f37afdac BZ	307	.dma_test_irq = ide_dma_test_irq,
	308	.dma_lost_irq = ide_dma_lost_irq,
	309	.dma_timeout = ide_dma_timeout,
592b5315	310	.dma_sff_read_status = superio_dma_sff_read_status,
5e37bdc0 BZ	311	};
5e37bdc0 BZ	312
85620436	313	static const struct ide_port_info ns87415_chipset __devinitdata = {
ced3ec8a	314	.name = DRV_NAME,
1da177e4	315	.init_hwif = init_hwif_ns87415,
ac95beed	316	.port_ops = &ns87415_port_ops,
5e37bdc0	317	.dma_ops = &ns87415_dma_ops,
33c1002e	318	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
5e71d9c5	319	IDE_HFLAG_NO_ATAPI_DMA,
1da177e4 LT	320	};
	321
	322	static int __devinit ns87415_init_one(struct pci_dev dev, const struct pci_device_id id)
	323	{
374e042c BZ	324	struct ide_port_info d = ns87415_chipset;
	325
	326	#ifdef CONFIG_SUPERIO
	327	if (PCI_SLOT(dev->devfn) == 0xE) {
	328	/* Built-in - assume it's under superio. */
	329	d.init_iops = superio_init_iops;
	330	d.tp_ops = &superio_tp_ops;
	331	}
	332	#endif
6cdf6eb3	333	return ide_pci_init_one(dev, &d, NULL);
1da177e4 LT	334	}
1da177e4 LT	335
9cbcc5e3 BZ	336	static const struct pci_device_id ns87415_pci_tbl[] = {
9cbcc5e3 BZ	337	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
1da177e4 LT	338	{ 0, },
	339	};
	340	MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
	341
a9ab09e2	342	static struct pci_driver ns87415_pci_driver = {
1da177e4 LT	343	.name = "NS87415_IDE",
	344	.id_table = ns87415_pci_tbl,
	345	.probe = ns87415_init_one,
aa6e518d	346	.remove = ide_pci_remove,
feb22b7f BZ	347	.suspend = ide_pci_suspend,
feb22b7f BZ	348	.resume = ide_pci_resume,
1da177e4 LT	349	};
1da177e4 LT	350
82ab1eec	351	static int __init ns87415_ide_init(void)
1da177e4	352	{
a9ab09e2	353	return ide_pci_register_driver(&ns87415_pci_driver);
1da177e4 LT	354	}
1da177e4 LT	355
aa6e518d BZ	356	static void __exit ns87415_ide_exit(void)
aa6e518d BZ	357	{
a9ab09e2	358	pci_unregister_driver(&ns87415_pci_driver);
aa6e518d BZ	359	}
aa6e518d BZ	360
1da177e4	361	module_init(ns87415_ide_init);
aa6e518d	362	module_exit(ns87415_ide_exit);
1da177e4 LT	363
	364	MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
	365	MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
	366	MODULE_LICENSE("GPL");