[linux.git] / drivers / ide / pci / ns87415.c

/*
 * Copyright (C) 1997-1998	Mark Lord <[email protected]>
 * Copyright (C) 1998		Eddie C. Dost <[email protected]>
 * Copyright (C) 1999-2000	Andre Hedrick <[email protected]>
 * Copyright (C) 2004		Grant Grundler <grundler at parisc-linux.org>
 *
 * Inspired by an earlier effort from David S. Miller <[email protected]>
 */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/hdreg.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>

#ifdef CONFIG_SUPERIO
/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
 * which use the integrated NS87514 cell for CD-ROM support.
 * i.e we have to support for CD-ROM installs.
 * See drivers/parisc/superio.c for more gory details.
 */
#include <asm/superio.h>

static unsigned long superio_ide_status[2];
static unsigned long superio_ide_select[2];
static unsigned long superio_ide_dma_status[2];

#define SUPERIO_IDE_MAX_RETRIES 25

/* Because of a defect in Super I/O, all reads of the PCI DMA status 
 * registers, IDE status register and the IDE select register need to be 
 * retried
 */
static u8 superio_ide_inb (unsigned long port)
{
	if (port == superio_ide_status[0] ||
	    port == superio_ide_status[1] ||
	    port == superio_ide_select[0] ||
	    port == superio_ide_select[1] ||
	    port == superio_ide_dma_status[0] ||
	    port == superio_ide_dma_status[1]) {
		u8 tmp;
		int retries = SUPERIO_IDE_MAX_RETRIES;

		/* printk(" [ reading port 0x%x with retry ] ", port); */

		do {
			tmp = inb(port);
			if (tmp == 0)
				udelay(50);
		} while (tmp == 0 && retries-- > 0);

		return tmp;
	}

	return inb(port);
}

static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
{
	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
}

static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
{
	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
	struct ide_taskfile *tf = &task->tf;

	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
		u16 data = inw(io_ports->data_addr);

		tf->data = data & 0xff;
		tf->hob_data = (data >> 8) & 0xff;
	}

	/* be sure we're looking at the low order bits */
	outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);

	if (task->tf_flags & IDE_TFLAG_IN_NSECT)
		tf->nsect  = inb(io_ports->nsect_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAL)
		tf->lbal   = inb(io_ports->lbal_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAM)
		tf->lbam   = inb(io_ports->lbam_addr);
	if (task->tf_flags & IDE_TFLAG_IN_LBAH)
		tf->lbah   = inb(io_ports->lbah_addr);
	if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
		tf->device = superio_ide_inb(io_ports->device_addr);

	if (task->tf_flags & IDE_TFLAG_LBA48) {
		outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);

		if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
			tf->hob_feature = inb(io_ports->feature_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
			tf->hob_nsect   = inb(io_ports->nsect_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
			tf->hob_lbal    = inb(io_ports->lbal_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
			tf->hob_lbam    = inb(io_ports->lbam_addr);
		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
			tf->hob_lbah    = inb(io_ports->lbah_addr);
	}
}

static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
{
	struct pci_dev *pdev = to_pci_dev(hwif->dev);
	u32 base, dmabase;
	u8 port = hwif->channel, tmp;

	base = pci_resource_start(pdev, port * 2) & ~3;
	dmabase = pci_resource_start(pdev, 4) & ~3;

	superio_ide_status[port] = base + 7;
	superio_ide_select[port] = base + 6;
	superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);

	/* Clear error/interrupt, enable dma */
	tmp = superio_ide_inb(superio_ide_dma_status[port]);
	outb(tmp | 0x66, superio_ide_dma_status[port]);

	hwif->read_sff_dma_status = superio_read_sff_dma_status;

	hwif->tf_read = superio_tf_read;

	/* We need to override inb to workaround a SuperIO errata */
	hwif->INB = superio_ide_inb;
}

static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);

	if (PCI_SLOT(dev->devfn) == 0xE)
		/* Built-in - assume it's under superio. */
		superio_ide_init_iops(hwif);
}
#endif

static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };

/*
 * This routine either enables/disables (according to drive->present)
 * the IRQ associated with the port (HWIF(drive)),
 * and selects either PIO or DMA handshaking for the next I/O operation.
 */
static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
{
	ide_hwif_t *hwif = HWIF(drive);
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
	unsigned long flags;

	local_irq_save(flags);
	new = *old;

	/* Adjust IRQ enable bit */
	bit = 1 << (8 + hwif->channel);
	new = drive->present ? (new & ~bit) : (new | bit);

	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	bit   = 1 << (20 + drive->select.b.unit       + (hwif->channel << 1));
	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	new = use_dma ? ((new & ~other) | bit) : (new & ~bit);

	if (new != *old) {
		unsigned char stat;

		/*
		 * Don't change DMA engine settings while Write Buffers
		 * are busy.
		 */
		(void) pci_read_config_byte(dev, 0x43, &stat);
		while (stat & 0x03) {
			udelay(1);
			(void) pci_read_config_byte(dev, 0x43, &stat);
		}

		*old = new;
		(void) pci_write_config_dword(dev, 0x40, new);

		/*
		 * And let things settle...
		 */
		udelay(10);
	}

	local_irq_restore(flags);
}

static void ns87415_selectproc (ide_drive_t *drive)
{
	ns87415_prepare_drive (drive, drive->using_dma);
}

static int ns87415_dma_end(ide_drive_t *drive)
{
	ide_hwif_t      *hwif = HWIF(drive);
	u8 dma_stat = 0, dma_cmd = 0;

	drive->waiting_for_dma = 0;
	dma_stat = hwif->read_sff_dma_status(hwif);
	/* get DMA command mode */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	/* stop DMA */
	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
	/* from ERRATA: clear the INTR & ERROR bits */
	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
	outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
	/* and free any DMA resources */
	ide_destroy_dmatable(drive);
	/* verify good DMA status */
	return (dma_stat & 7) != 4;
}

static int ns87415_dma_setup(ide_drive_t *drive)
{
	/* select DMA xfer */
	ns87415_prepare_drive(drive, 1);
	if (!ide_dma_setup(drive))
		return 0;
	/* DMA failed: select PIO xfer */
	ns87415_prepare_drive(drive, 0);
	return 1;
}

static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
{
	struct pci_dev *dev = to_pci_dev(hwif->dev);
	unsigned int ctrl, using_inta;
	u8 progif;
#ifdef __sparc_v9__
	int timeout;
	u8 stat;
#endif

	/*
	 * We cannot probe for IRQ: both ports share common IRQ on INTA.
	 * Also, leave IRQ masked during drive probing, to prevent infinite
	 * interrupts from a potentially floating INTA..
	 *
	 * IRQs get unmasked in selectproc when drive is first used.
	 */
	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	(void) pci_read_config_byte(dev, 0x09, &progif);
	/* is irq in "native" mode? */
	using_inta = progif & (1 << (hwif->channel << 1));
	if (!using_inta)
		using_inta = ctrl & (1 << (4 + hwif->channel));
	if (hwif->mate) {
		hwif->select_data = hwif->mate->select_data;
	} else {
		hwif->select_data = (unsigned long)
					&ns87415_control[ns87415_count++];
		ctrl |= (1 << 8) | (1 << 9);	/* mask both IRQs */
		if (using_inta)
			ctrl &= ~(1 << 6);	/* unmask INTA */
		*((unsigned int *)hwif->select_data) = ctrl;
		(void) pci_write_config_dword(dev, 0x40, ctrl);

		/*
		 * Set prefetch size to 512 bytes for both ports,
		 * but don't turn on/off prefetching here.
		 */
		pci_write_config_byte(dev, 0x55, 0xee);

#ifdef __sparc_v9__
		/*
		 * XXX: Reset the device, if we don't it will not respond to
		 *      SELECT_DRIVE() properly during first ide_probe_port().
		 */
		timeout = 10000;
		outb(12, hwif->io_ports.ctl_addr);
		udelay(10);
		outb(8, hwif->io_ports.ctl_addr);
		do {
			udelay(50);
			stat = hwif->INB(hwif->io_ports.status_addr);
                	if (stat == 0xff)
                        	break;
        	} while ((stat & BUSY_STAT) && --timeout);
#endif
	}

	if (!using_inta)
		hwif->irq = __ide_default_irq(hwif->io_ports.data_addr);
	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
		hwif->irq = hwif->mate->irq;	/* share IRQ with mate */

	if (!hwif->dma_base)
		return;

	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
}

static const struct ide_port_ops ns87415_port_ops = {
	.selectproc		= ns87415_selectproc,
};

static const struct ide_dma_ops ns87415_dma_ops = {
	.dma_host_set		= ide_dma_host_set,
	.dma_setup		= ns87415_dma_setup,
	.dma_exec_cmd		= ide_dma_exec_cmd,
	.dma_start		= ide_dma_start,
	.dma_end		= ns87415_dma_end,
	.dma_test_irq		= ide_dma_test_irq,
	.dma_lost_irq		= ide_dma_lost_irq,
	.dma_timeout		= ide_dma_timeout,
};

static const struct ide_port_info ns87415_chipset __devinitdata = {
	.name		= "NS87415",
#ifdef CONFIG_SUPERIO
	.init_iops	= init_iops_ns87415,
#endif
	.init_hwif	= init_hwif_ns87415,
	.port_ops	= &ns87415_port_ops,
	.dma_ops	= &ns87415_dma_ops,
	.host_flags	= IDE_HFLAG_TRUST_BIOS_FOR_DMA |
			  IDE_HFLAG_NO_ATAPI_DMA,
};

static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	return ide_setup_pci_device(dev, &ns87415_chipset);
}

static const struct pci_device_id ns87415_pci_tbl[] = {
	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
	{ 0, },
};
MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);

static struct pci_driver driver = {
	.name		= "NS87415_IDE",
	.id_table	= ns87415_pci_tbl,
	.probe		= ns87415_init_one,
};

static int __init ns87415_ide_init(void)
{
	return ide_pci_register_driver(&driver);
}

module_init(ns87415_ide_init);

MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 1997-1998 Mark Lord <[email protected]>
	3	* Copyright (C) 1998 Eddie C. Dost <[email protected]>
	4	* Copyright (C) 1999-2000 Andre Hedrick <[email protected]>
	5	* Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
	6	*
	7	* Inspired by an earlier effort from David S. Miller <[email protected]>
	8	*/
	9
1da177e4 LT	10	#include <linux/module.h>
	11	#include <linux/types.h>
	12	#include <linux/kernel.h>
1da177e4	13	#include <linux/interrupt.h>
1da177e4 LT	14	#include <linux/hdreg.h>
	15	#include <linux/pci.h>
	16	#include <linux/delay.h>
	17	#include <linux/ide.h>
	18	#include <linux/init.h>
	19
	20	#include <asm/io.h>
	21
	22	#ifdef CONFIG_SUPERIO
	23	/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
	24	* Unfortunately, it's built-in on all Astro-based PA-RISC workstations
	25	* which use the integrated NS87514 cell for CD-ROM support.
	26	* i.e we have to support for CD-ROM installs.
	27	* See drivers/parisc/superio.c for more gory details.
	28	*/
	29	#include <asm/superio.h>
	30
	31	static unsigned long superio_ide_status[2];
	32	static unsigned long superio_ide_select[2];
	33	static unsigned long superio_ide_dma_status[2];
	34
	35	#define SUPERIO_IDE_MAX_RETRIES 25
	36
	37	/* Because of a defect in Super I/O, all reads of the PCI DMA status
	38	* registers, IDE status register and the IDE select register need to be
	39	* retried
	40	*/
	41	static u8 superio_ide_inb (unsigned long port)
	42	{
	43	if (port == superio_ide_status[0] \|\|
	44	port == superio_ide_status[1] \|\|
	45	port == superio_ide_select[0] \|\|
	46	port == superio_ide_select[1] \|\|
	47	port == superio_ide_dma_status[0] \|\|
	48	port == superio_ide_dma_status[1]) {
	49	u8 tmp;
	50	int retries = SUPERIO_IDE_MAX_RETRIES;
	51
	52	/* printk(" [ reading port 0x%x with retry ] ", port); */
	53
	54	do {
	55	tmp = inb(port);
	56	if (tmp == 0)
	57	udelay(50);
	58	} while (tmp == 0 && retries-- > 0);
	59
	60	return tmp;
	61	}
	62
	63	return inb(port);
	64	}
	65
b2f951aa BZ	66	static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
b2f951aa BZ	67	{
cab7f8ed	68	return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
b2f951aa BZ	69	}
b2f951aa BZ	70
ea23b8ba BZ	71	static void superio_tf_read(ide_drive_t drive, ide_task_t task)
	72	{
	73	struct ide_io_ports *io_ports = &drive->hwif->io_ports;
	74	struct ide_taskfile *tf = &task->tf;
	75
	76	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
	77	u16 data = inw(io_ports->data_addr);
	78
	79	tf->data = data & 0xff;
	80	tf->hob_data = (data >> 8) & 0xff;
	81	}
	82
	83	/* be sure we're looking at the low order bits */
ff074883	84	outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
ea23b8ba BZ	85
	86	if (task->tf_flags & IDE_TFLAG_IN_NSECT)
	87	tf->nsect = inb(io_ports->nsect_addr);
	88	if (task->tf_flags & IDE_TFLAG_IN_LBAL)
	89	tf->lbal = inb(io_ports->lbal_addr);
	90	if (task->tf_flags & IDE_TFLAG_IN_LBAM)
	91	tf->lbam = inb(io_ports->lbam_addr);
	92	if (task->tf_flags & IDE_TFLAG_IN_LBAH)
	93	tf->lbah = inb(io_ports->lbah_addr);
	94	if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
	95	tf->device = superio_ide_inb(io_ports->device_addr);
	96
	97	if (task->tf_flags & IDE_TFLAG_LBA48) {
ff074883	98	outb(ATA_DEVCTL_OBS \| 0x80, io_ports->ctl_addr);
ea23b8ba BZ	99
	100	if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
	101	tf->hob_feature = inb(io_ports->feature_addr);
	102	if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
	103	tf->hob_nsect = inb(io_ports->nsect_addr);
	104	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
	105	tf->hob_lbal = inb(io_ports->lbal_addr);
	106	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
	107	tf->hob_lbam = inb(io_ports->lbam_addr);
	108	if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
	109	tf->hob_lbah = inb(io_ports->lbah_addr);
	110	}
	111	}
	112
1da177e4 LT	113	static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
1da177e4 LT	114	{
36501650	115	struct pci_dev *pdev = to_pci_dev(hwif->dev);
1da177e4	116	u32 base, dmabase;
36501650	117	u8 port = hwif->channel, tmp;
1da177e4 LT	118
	119	base = pci_resource_start(pdev, port * 2) & ~3;
	120	dmabase = pci_resource_start(pdev, 4) & ~3;
	121
4c3032d8 BZ	122	superio_ide_status[port] = base + 7;
4c3032d8 BZ	123	superio_ide_select[port] = base + 6;
1da177e4 LT	124	superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
	125
	126	/* Clear error/interrupt, enable dma */
	127	tmp = superio_ide_inb(superio_ide_dma_status[port]);
	128	outb(tmp \| 0x66, superio_ide_dma_status[port]);
	129
b2f951aa BZ	130	hwif->read_sff_dma_status = superio_read_sff_dma_status;
b2f951aa BZ	131
ea23b8ba BZ	132	hwif->tf_read = superio_tf_read;
ea23b8ba BZ	133
1da177e4 LT	134	/* We need to override inb to workaround a SuperIO errata */
	135	hwif->INB = superio_ide_inb;
	136	}
	137
	138	static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
	139	{
36501650 BZ	140	struct pci_dev *dev = to_pci_dev(hwif->dev);
	141
	142	if (PCI_SLOT(dev->devfn) == 0xE)
1da177e4 LT	143	/* Built-in - assume it's under superio. */
1da177e4 LT	144	superio_ide_init_iops(hwif);
1da177e4 LT	145	}
	146	#endif
	147
	148	static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
	149
	150	/*
	151	* This routine either enables/disables (according to drive->present)
	152	* the IRQ associated with the port (HWIF(drive)),
	153	* and selects either PIO or DMA handshaking for the next I/O operation.
	154	*/
	155	static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
	156	{
	157	ide_hwif_t *hwif = HWIF(drive);
36501650	158	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4	159	unsigned int bit, other, new, old = (unsigned int ) hwif->select_data;
1da177e4 LT	160	unsigned long flags;
	161
	162	local_irq_save(flags);
	163	new = *old;
	164
	165	/* Adjust IRQ enable bit */
	166	bit = 1 << (8 + hwif->channel);
	167	new = drive->present ? (new & ~bit) : (new \| bit);
	168
	169	/* Select PIO or DMA, DMA may only be selected for one drive/channel. */
	170	bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1));
	171	other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
	172	new = use_dma ? ((new & ~other) \| bit) : (new & ~bit);
	173
	174	if (new != *old) {
	175	unsigned char stat;
	176
	177	/*
	178	* Don't change DMA engine settings while Write Buffers
	179	* are busy.
	180	*/
	181	(void) pci_read_config_byte(dev, 0x43, &stat);
	182	while (stat & 0x03) {
	183	udelay(1);
	184	(void) pci_read_config_byte(dev, 0x43, &stat);
	185	}
	186
	187	*old = new;
	188	(void) pci_write_config_dword(dev, 0x40, new);
	189
	190	/*
	191	* And let things settle...
	192	*/
	193	udelay(10);
	194	}
	195
	196	local_irq_restore(flags);
	197	}
	198
	199	static void ns87415_selectproc (ide_drive_t *drive)
	200	{
	201	ns87415_prepare_drive (drive, drive->using_dma);
	202	}
	203
5e37bdc0	204	static int ns87415_dma_end(ide_drive_t *drive)
1da177e4 LT	205	{
	206	ide_hwif_t *hwif = HWIF(drive);
	207	u8 dma_stat = 0, dma_cmd = 0;
	208
	209	drive->waiting_for_dma = 0;
b2f951aa	210	dma_stat = hwif->read_sff_dma_status(hwif);
cab7f8ed BZ	211	/* get DMA command mode */
cab7f8ed BZ	212	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
1da177e4	213	/* stop DMA */
cab7f8ed	214	outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
1da177e4	215	/* from ERRATA: clear the INTR & ERROR bits */
cab7f8ed BZ	216	dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
cab7f8ed BZ	217	outb(dma_cmd \| 6, hwif->dma_base + ATA_DMA_CMD);
1da177e4 LT	218	/* and free any DMA resources */
	219	ide_destroy_dmatable(drive);
	220	/* verify good DMA status */
	221	return (dma_stat & 7) != 4;
	222	}
	223
5e37bdc0	224	static int ns87415_dma_setup(ide_drive_t *drive)
1da177e4 LT	225	{
	226	/* select DMA xfer */
	227	ns87415_prepare_drive(drive, 1);
	228	if (!ide_dma_setup(drive))
	229	return 0;
	230	/* DMA failed: select PIO xfer */
	231	ns87415_prepare_drive(drive, 0);
	232	return 1;
	233	}
	234
c20530ed	235	static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
1da177e4	236	{
36501650	237	struct pci_dev *dev = to_pci_dev(hwif->dev);
1da177e4 LT	238	unsigned int ctrl, using_inta;
	239	u8 progif;
	240	#ifdef __sparc_v9__
	241	int timeout;
	242	u8 stat;
	243	#endif
	244
1da177e4 LT	245	/*
	246	* We cannot probe for IRQ: both ports share common IRQ on INTA.
	247	* Also, leave IRQ masked during drive probing, to prevent infinite
	248	* interrupts from a potentially floating INTA..
	249	*
	250	* IRQs get unmasked in selectproc when drive is first used.
	251	*/
	252	(void) pci_read_config_dword(dev, 0x40, &ctrl);
	253	(void) pci_read_config_byte(dev, 0x09, &progif);
	254	/* is irq in "native" mode? */
	255	using_inta = progif & (1 << (hwif->channel << 1));
	256	if (!using_inta)
	257	using_inta = ctrl & (1 << (4 + hwif->channel));
	258	if (hwif->mate) {
	259	hwif->select_data = hwif->mate->select_data;
	260	} else {
	261	hwif->select_data = (unsigned long)
	262	&ns87415_control[ns87415_count++];
	263	ctrl \|= (1 << 8) \| (1 << 9); /* mask both IRQs */
	264	if (using_inta)
	265	ctrl &= ~(1 << 6); /* unmask INTA */
	266	((unsigned int )hwif->select_data) = ctrl;
	267	(void) pci_write_config_dword(dev, 0x40, ctrl);
	268
	269	/*
	270	* Set prefetch size to 512 bytes for both ports,
	271	* but don't turn on/off prefetching here.
	272	*/
	273	pci_write_config_byte(dev, 0x55, 0xee);
	274
	275	#ifdef __sparc_v9__
	276	/*
9d501529 BZ	277	* XXX: Reset the device, if we don't it will not respond to
9d501529 BZ	278	* SELECT_DRIVE() properly during first ide_probe_port().
1da177e4 LT	279	*/
1da177e4 LT	280	timeout = 10000;
4c3032d8	281	outb(12, hwif->io_ports.ctl_addr);
1da177e4	282	udelay(10);
4c3032d8	283	outb(8, hwif->io_ports.ctl_addr);
1da177e4 LT	284	do {
1da177e4 LT	285	udelay(50);
4c3032d8	286	stat = hwif->INB(hwif->io_ports.status_addr);
1da177e4 LT	287	if (stat == 0xff)
	288	break;
	289	} while ((stat & BUSY_STAT) && --timeout);
	290	#endif
	291	}
	292
	293	if (!using_inta)
a861beb1	294	hwif->irq = __ide_default_irq(hwif->io_ports.data_addr);
1da177e4 LT	295	else if (!hwif->irq && hwif->mate && hwif->mate->irq)
	296	hwif->irq = hwif->mate->irq; /* share IRQ with mate */
	297
	298	if (!hwif->dma_base)
	299	return;
	300
cab7f8ed	301	outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
1da177e4 LT	302	}
1da177e4 LT	303
ac95beed BZ	304	static const struct ide_port_ops ns87415_port_ops = {
	305	.selectproc = ns87415_selectproc,
	306	};
	307
f37afdac BZ	308	static const struct ide_dma_ops ns87415_dma_ops = {
f37afdac BZ	309	.dma_host_set = ide_dma_host_set,
5e37bdc0	310	.dma_setup = ns87415_dma_setup,
f37afdac BZ	311	.dma_exec_cmd = ide_dma_exec_cmd,
f37afdac BZ	312	.dma_start = ide_dma_start,
5e37bdc0	313	.dma_end = ns87415_dma_end,
f37afdac BZ	314	.dma_test_irq = ide_dma_test_irq,
	315	.dma_lost_irq = ide_dma_lost_irq,
	316	.dma_timeout = ide_dma_timeout,
5e37bdc0 BZ	317	};
5e37bdc0 BZ	318
85620436	319	static const struct ide_port_info ns87415_chipset __devinitdata = {
1da177e4 LT	320	.name = "NS87415",
	321	#ifdef CONFIG_SUPERIO
	322	.init_iops = init_iops_ns87415,
	323	#endif
	324	.init_hwif = init_hwif_ns87415,
ac95beed	325	.port_ops = &ns87415_port_ops,
5e37bdc0	326	.dma_ops = &ns87415_dma_ops,
33c1002e	327	.host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA \|
5e71d9c5	328	IDE_HFLAG_NO_ATAPI_DMA,
1da177e4 LT	329	};
	330
	331	static int __devinit ns87415_init_one(struct pci_dev dev, const struct pci_device_id id)
	332	{
	333	return ide_setup_pci_device(dev, &ns87415_chipset);
	334	}
	335
9cbcc5e3 BZ	336	static const struct pci_device_id ns87415_pci_tbl[] = {
9cbcc5e3 BZ	337	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
1da177e4 LT	338	{ 0, },
	339	};
	340	MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
	341
	342	static struct pci_driver driver = {
	343	.name = "NS87415_IDE",
	344	.id_table = ns87415_pci_tbl,
	345	.probe = ns87415_init_one,
	346	};
	347
82ab1eec	348	static int __init ns87415_ide_init(void)
1da177e4 LT	349	{
	350	return ide_pci_register_driver(&driver);
	351	}
	352
	353	module_init(ns87415_ide_init);
	354
	355	MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
	356	MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
	357	MODULE_LICENSE("GPL");