[linux.git] / drivers / net / wireless / iwlwifi / iwl-agn-ucode.c

/******************************************************************************
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <[email protected]>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/sched.h>

#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-io.h"
#include "iwl-helpers.h"
#include "iwl-agn-hw.h"
#include "iwl-agn.h"
#include "iwl-agn-calib.h"
#include "iwl-trans.h"
#include "iwl-fh.h"

static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
	{COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
	 0, COEX_UNASSOC_IDLE_FLAGS},
	{COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
	 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
	{COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
	 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
	{COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
	 0, COEX_CALIBRATION_FLAGS},
	{COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
	 0, COEX_PERIODIC_CALIBRATION_FLAGS},
	{COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
	 0, COEX_CONNECTION_ESTAB_FLAGS},
	{COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
	 0, COEX_ASSOCIATED_IDLE_FLAGS},
	{COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
	 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
	{COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
	 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
	{COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
	 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
	{COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
	{COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
	{COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
	 0, COEX_STAND_ALONE_DEBUG_FLAGS},
	{COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
	 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
	{COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
	{COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
};

/*
 * ucode
 */
static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
				struct fw_desc *image, u32 dst_addr)
{
	dma_addr_t phy_addr = image->p_addr;
	u32 byte_cnt = image->len;
	int ret;

	priv->ucode_write_complete = 0;

	iwl_write_direct32(bus(priv),
		FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);

	iwl_write_direct32(bus(priv),
		FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);

	iwl_write_direct32(bus(priv),
		FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
		phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);

	iwl_write_direct32(bus(priv),
		FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
		(iwl_get_dma_hi_addr(phy_addr)
			<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);

	iwl_write_direct32(bus(priv),
		FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
		1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
		1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
		FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);

	iwl_write_direct32(bus(priv),
		FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE	|
		FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE	|
		FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);

	IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
	ret = wait_event_interruptible_timeout(priv->shrd->wait_command_queue,
					priv->ucode_write_complete, 5 * HZ);
	if (ret == -ERESTARTSYS) {
		IWL_ERR(priv, "Could not load the %s uCode section due "
			"to interrupt\n", name);
		return ret;
	}
	if (!ret) {
		IWL_ERR(priv, "Could not load the %s uCode section\n",
			name);
		return -ETIMEDOUT;
	}

	return 0;
}

static int iwlagn_load_given_ucode(struct iwl_priv *priv,
				   struct fw_img *image)
{
	int ret = 0;

	ret = iwlagn_load_section(priv, "INST", &image->code,
				   IWLAGN_RTC_INST_LOWER_BOUND);
	if (ret)
		return ret;

	return iwlagn_load_section(priv, "DATA", &image->data,
				    IWLAGN_RTC_DATA_LOWER_BOUND);
}

/*
 *  Calibration
 */
static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
{
	struct iwl_calib_xtal_freq_cmd cmd;
	__le16 *xtal_calib =
		(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);

	iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
	cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
	cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
	return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
			     (u8 *)&cmd, sizeof(cmd));
}

static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
{
	struct iwl_calib_temperature_offset_cmd cmd;
	__le16 *offset_calib =
		(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);

	memset(&cmd, 0, sizeof(cmd));
	iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
	memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(offset_calib));
	if (!(cmd.radio_sensor_offset))
		cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;

	IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
			le16_to_cpu(cmd.radio_sensor_offset));
	return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
			     (u8 *)&cmd, sizeof(cmd));
}

static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
{
	struct iwl_calib_cfg_cmd calib_cfg_cmd;
	struct iwl_host_cmd cmd = {
		.id = CALIBRATION_CFG_CMD,
		.len = { sizeof(struct iwl_calib_cfg_cmd), },
		.data = { &calib_cfg_cmd, },
	};

	memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
	calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
	calib_cfg_cmd.ucd_calib_cfg.flags =
		IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;

	return iwl_trans_send_cmd(trans(priv), &cmd);
}

void iwlagn_rx_calib_result(struct iwl_priv *priv,
			     struct iwl_rx_mem_buffer *rxb)
{
	struct iwl_rx_packet *pkt = rxb_addr(rxb);
	struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
	int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
	int index;

	/* reduce the size of the length field itself */
	len -= 4;

	/* Define the order in which the results will be sent to the runtime
	 * uCode. iwl_send_calib_results sends them in a row according to
	 * their index. We sort them here
	 */
	switch (hdr->op_code) {
	case IWL_PHY_CALIBRATE_DC_CMD:
		index = IWL_CALIB_DC;
		break;
	case IWL_PHY_CALIBRATE_LO_CMD:
		index = IWL_CALIB_LO;
		break;
	case IWL_PHY_CALIBRATE_TX_IQ_CMD:
		index = IWL_CALIB_TX_IQ;
		break;
	case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
		index = IWL_CALIB_TX_IQ_PERD;
		break;
	case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
		index = IWL_CALIB_BASE_BAND;
		break;
	default:
		IWL_ERR(priv, "Unknown calibration notification %d\n",
			  hdr->op_code);
		return;
	}
	iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
}

int iwlagn_init_alive_start(struct iwl_priv *priv)
{
	int ret;

	if (priv->cfg->bt_params &&
	    priv->cfg->bt_params->advanced_bt_coexist) {
		/*
		 * Tell uCode we are ready to perform calibration
		 * need to perform this before any calibration
		 * no need to close the envlope since we are going
		 * to load the runtime uCode later.
		 */
		ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
			BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
		if (ret)
			return ret;

	}

	ret = iwlagn_send_calib_cfg(priv);
	if (ret)
		return ret;

	/**
	 * temperature offset calibration is only needed for runtime ucode,
	 * so prepare the value now.
	 */
	if (priv->cfg->need_temp_offset_calib)
		return iwlagn_set_temperature_offset_calib(priv);

	return 0;
}

static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
{
	struct iwl_wimax_coex_cmd coex_cmd;

	if (priv->cfg->base_params->support_wimax_coexist) {
		/* UnMask wake up src at associated sleep */
		coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;

		/* UnMask wake up src at unassociated sleep */
		coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
		memcpy(coex_cmd.sta_prio, cu_priorities,
			sizeof(struct iwl_wimax_coex_event_entry) *
			 COEX_NUM_OF_EVENTS);

		/* enabling the coexistence feature */
		coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;

		/* enabling the priorities tables */
		coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
	} else {
		/* coexistence is disabled */
		memset(&coex_cmd, 0, sizeof(coex_cmd));
	}
	return iwl_trans_send_cmd_pdu(trans(priv),
				COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
				sizeof(coex_cmd), &coex_cmd);
}

static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
		(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	0, 0, 0, 0, 0, 0, 0
};

void iwlagn_send_prio_tbl(struct iwl_priv *priv)
{
	struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;

	memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
		sizeof(iwlagn_bt_prio_tbl));
	if (iwl_trans_send_cmd_pdu(trans(priv),
				REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
				sizeof(prio_tbl_cmd), &prio_tbl_cmd))
		IWL_ERR(priv, "failed to send BT prio tbl command\n");
}

int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
{
	struct iwl_bt_coex_prot_env_cmd env_cmd;
	int ret;

	env_cmd.action = action;
	env_cmd.type = type;
	ret = iwl_trans_send_cmd_pdu(trans(priv),
			       REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
			       sizeof(env_cmd), &env_cmd);
	if (ret)
		IWL_ERR(priv, "failed to send BT env command\n");
	return ret;
}


static int iwlagn_alive_notify(struct iwl_priv *priv)
{
	int ret;

	if (!priv->tx_cmd_pool)
		priv->tx_cmd_pool =
			kmem_cache_create("iwlagn_dev_cmd",
					  sizeof(struct iwl_device_cmd),
					  sizeof(void *), 0, NULL);

	if (!priv->tx_cmd_pool)
		return -ENOMEM;

	iwl_trans_tx_start(trans(priv));

	ret = iwlagn_send_wimax_coex(priv);
	if (ret)
		return ret;

	ret = iwlagn_set_Xtal_calib(priv);
	if (ret)
		return ret;

	return iwl_send_calib_results(priv);
}


/**
 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 *   using sample data 100 bytes apart.  If these sample points are good,
 *   it's a pretty good bet that everything between them is good, too.
 */
static int iwl_verify_inst_sparse(struct iwl_priv *priv,
				      struct fw_desc *fw_desc)
{
	__le32 *image = (__le32 *)fw_desc->v_addr;
	u32 len = fw_desc->len;
	u32 val;
	u32 i;

	IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);

	for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
		/* read data comes through single port, auto-incr addr */
		/* NOTE: Use the debugless read so we don't flood kernel log
		 * if IWL_DL_IO is set */
		iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
			i + IWLAGN_RTC_INST_LOWER_BOUND);
		val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
		if (val != le32_to_cpu(*image))
			return -EIO;
	}

	return 0;
}

static void iwl_print_mismatch_inst(struct iwl_priv *priv,
				    struct fw_desc *fw_desc)
{
	__le32 *image = (__le32 *)fw_desc->v_addr;
	u32 len = fw_desc->len;
	u32 val;
	u32 offs;
	int errors = 0;

	IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);

	iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
			   IWLAGN_RTC_INST_LOWER_BOUND);

	for (offs = 0;
	     offs < len && errors < 20;
	     offs += sizeof(u32), image++) {
		/* read data comes through single port, auto-incr addr */
		val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
		if (val != le32_to_cpu(*image)) {
			IWL_ERR(priv, "uCode INST section at "
				"offset 0x%x, is 0x%x, s/b 0x%x\n",
				offs, val, le32_to_cpu(*image));
			errors++;
		}
	}
}

/**
 * iwl_verify_ucode - determine which instruction image is in SRAM,
 *    and verify its contents
 */
static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
{
	if (!iwl_verify_inst_sparse(priv, &img->code)) {
		IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
		return 0;
	}

	IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");

	iwl_print_mismatch_inst(priv, &img->code);
	return -EIO;
}

struct iwlagn_alive_data {
	bool valid;
	u8 subtype;
};

static void iwlagn_alive_fn(struct iwl_priv *priv,
			    struct iwl_rx_packet *pkt,
			    void *data)
{
	struct iwlagn_alive_data *alive_data = data;
	struct iwl_alive_resp *palive;

	palive = &pkt->u.alive_frame;

	IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
		       "0x%01X 0x%01X\n",
		       palive->is_valid, palive->ver_type,
		       palive->ver_subtype);

	priv->device_pointers.error_event_table =
		le32_to_cpu(palive->error_event_table_ptr);
	priv->device_pointers.log_event_table =
		le32_to_cpu(palive->log_event_table_ptr);

	alive_data->subtype = palive->ver_subtype;
	alive_data->valid = palive->is_valid == UCODE_VALID_OK;
}

#define UCODE_ALIVE_TIMEOUT	HZ
#define UCODE_CALIB_TIMEOUT	(2*HZ)

int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
				 struct fw_img *image,
				 enum iwlagn_ucode_type ucode_type)
{
	struct iwl_notification_wait alive_wait;
	struct iwlagn_alive_data alive_data;
	int ret;
	enum iwlagn_ucode_type old_type;

	ret = iwl_trans_start_device(trans(priv));
	if (ret)
		return ret;

	iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
				      iwlagn_alive_fn, &alive_data);

	old_type = priv->ucode_type;
	priv->ucode_type = ucode_type;

	ret = iwlagn_load_given_ucode(priv, image);
	if (ret) {
		priv->ucode_type = old_type;
		iwlagn_remove_notification(priv, &alive_wait);
		return ret;
	}

	iwl_trans_kick_nic(trans(priv));

	/*
	 * Some things may run in the background now, but we
	 * just wait for the ALIVE notification here.
	 */
	ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
	if (ret) {
		priv->ucode_type = old_type;
		return ret;
	}

	if (!alive_data.valid) {
		IWL_ERR(priv, "Loaded ucode is not valid!\n");
		priv->ucode_type = old_type;
		return -EIO;
	}

	/*
	 * This step takes a long time (60-80ms!!) and
	 * WoWLAN image should be loaded quickly, so
	 * skip it for WoWLAN.
	 */
	if (ucode_type != IWL_UCODE_WOWLAN) {
		ret = iwl_verify_ucode(priv, image);
		if (ret) {
			priv->ucode_type = old_type;
			return ret;
		}

		/* delay a bit to give rfkill time to run */
		msleep(5);
	}

	ret = iwlagn_alive_notify(priv);
	if (ret) {
		IWL_WARN(priv,
			"Could not complete ALIVE transition: %d\n", ret);
		priv->ucode_type = old_type;
		return ret;
	}

	return 0;
}

int iwlagn_run_init_ucode(struct iwl_priv *priv)
{
	struct iwl_notification_wait calib_wait;
	int ret;

	lockdep_assert_held(&priv->shrd->mutex);

	/* No init ucode required? Curious, but maybe ok */
	if (!priv->ucode_init.code.len)
		return 0;

	if (priv->ucode_type != IWL_UCODE_NONE)
		return 0;

	iwlagn_init_notification_wait(priv, &calib_wait,
				      CALIBRATION_COMPLETE_NOTIFICATION,
				      NULL, NULL);

	/* Will also start the device */
	ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
					   IWL_UCODE_INIT);
	if (ret)
		goto error;

	ret = iwlagn_init_alive_start(priv);
	if (ret)
		goto error;

	/*
	 * Some things may run in the background now, but we
	 * just wait for the calibration complete notification.
	 */
	ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);

	goto out;

 error:
	iwlagn_remove_notification(priv, &calib_wait);
 out:
	/* Whatever happened, stop the device */
	iwl_trans_stop_device(trans(priv));
	return ret;
}
Commit	Line	Data
792bc3cb WYG	1	/******************************************************************************
	2	*
	3	* GPL LICENSE SUMMARY
	4	*
901069c7	5	* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
792bc3cb WYG	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of version 2 of the GNU General Public License as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
	19	* USA
	20	*
	21	* The full GNU General Public License is included in this distribution
	22	* in the file called LICENSE.GPL.
	23	*
	24	* Contact Information:
	25	* Intel Linux Wireless <[email protected]>
	26	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	27	*
	28	*****************************************************************************/
	29
	30	#include <linux/kernel.h>
	31	#include <linux/module.h>
	32	#include <linux/init.h>
81b8176e	33	#include <linux/sched.h>
792bc3cb WYG	34
	35	#include "iwl-dev.h"
	36	#include "iwl-core.h"
81b8176e	37	#include "iwl-io.h"
741a6266	38	#include "iwl-helpers.h"
19e6cda0	39	#include "iwl-agn-hw.h"
741a6266	40	#include "iwl-agn.h"
0de76736	41	#include "iwl-agn-calib.h"
bdfbf092	42	#include "iwl-trans.h"
dda61a44	43	#include "iwl-fh.h"
741a6266	44
f4012413 WYG	45	static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
	46	{COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
	47	0, COEX_UNASSOC_IDLE_FLAGS},
	48	{COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
	49	0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
	50	{COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
	51	0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
	52	{COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
	53	0, COEX_CALIBRATION_FLAGS},
	54	{COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
	55	0, COEX_PERIODIC_CALIBRATION_FLAGS},
	56	{COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
	57	0, COEX_CONNECTION_ESTAB_FLAGS},
	58	{COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
	59	0, COEX_ASSOCIATED_IDLE_FLAGS},
	60	{COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
	61	0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
	62	{COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
	63	0, COEX_ASSOC_AUTO_SCAN_FLAGS},
	64	{COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
	65	0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
	66	{COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
	67	{COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
	68	{COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
	69	0, COEX_STAND_ALONE_DEBUG_FLAGS},
	70	{COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
	71	0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
	72	{COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
	73	{COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
	74	};
	75
81b8176e WYG	76	/*
	77	* ucode
	78	*/
	79	static int iwlagn_load_section(struct iwl_priv priv, const char name,
	80	struct fw_desc *image, u32 dst_addr)
	81	{
	82	dma_addr_t phy_addr = image->p_addr;
	83	u32 byte_cnt = image->len;
	84	int ret;
	85
	86	priv->ucode_write_complete = 0;
	87
83ed9015	88	iwl_write_direct32(bus(priv),
81b8176e WYG	89	FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
	90	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
	91
83ed9015	92	iwl_write_direct32(bus(priv),
81b8176e WYG	93	FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
81b8176e WYG	94
83ed9015	95	iwl_write_direct32(bus(priv),
81b8176e WYG	96	FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
	97	phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
	98
83ed9015	99	iwl_write_direct32(bus(priv),
81b8176e WYG	100	FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
	101	(iwl_get_dma_hi_addr(phy_addr)
	102	<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) \| byte_cnt);
	103
83ed9015	104	iwl_write_direct32(bus(priv),
81b8176e WYG	105	FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
	106	1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM \|
	107	1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX \|
	108	FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
	109
83ed9015	110	iwl_write_direct32(bus(priv),
81b8176e WYG	111	FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
	112	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE \|
	113	FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE \|
	114	FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
	115
06bb8358	116	IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
3e10caeb	117	ret = wait_event_interruptible_timeout(priv->shrd->wait_command_queue,
81b8176e WYG	118	priv->ucode_write_complete, 5 * HZ);
	119	if (ret == -ERESTARTSYS) {
	120	IWL_ERR(priv, "Could not load the %s uCode section due "
	121	"to interrupt\n", name);
	122	return ret;
	123	}
	124	if (!ret) {
	125	IWL_ERR(priv, "Could not load the %s uCode section\n",
	126	name);
	127	return -ETIMEDOUT;
	128	}
	129
	130	return 0;
	131	}
	132
	133	static int iwlagn_load_given_ucode(struct iwl_priv *priv,
dbf28e21	134	struct fw_img *image)
81b8176e WYG	135	{
	136	int ret = 0;
	137
dbf28e21	138	ret = iwlagn_load_section(priv, "INST", &image->code,
19e6cda0	139	IWLAGN_RTC_INST_LOWER_BOUND);
81b8176e WYG	140	if (ret)
	141	return ret;
	142
dbf28e21	143	return iwlagn_load_section(priv, "DATA", &image->data,
19e6cda0	144	IWLAGN_RTC_DATA_LOWER_BOUND);
81b8176e WYG	145	}
81b8176e WYG	146
741a6266 WYG	147	/*
	148	* Calibration
	149	*/
	150	static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
	151	{
	152	struct iwl_calib_xtal_freq_cmd cmd;
	153	__le16 *xtal_calib =
7944f8e4	154	(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
741a6266	155
1f8bf039	156	iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
741a6266 WYG	157	cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
	158	cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
	159	return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
	160	(u8 *)&cmd, sizeof(cmd));
	161	}
	162
bf53f939 SZ	163	static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
	164	{
	165	struct iwl_calib_temperature_offset_cmd cmd;
	166	__le16 *offset_calib =
8d8854d9	167	(__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
1f8bf039 WYG	168
	169	memset(&cmd, 0, sizeof(cmd));
	170	iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
2e277996	171	memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(offset_calib));
bf53f939 SZ	172	if (!(cmd.radio_sensor_offset))
bf53f939 SZ	173	cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
1f8bf039	174
bf53f939	175	IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
2e277996	176	le16_to_cpu(cmd.radio_sensor_offset));
bf53f939 SZ	177	return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
	178	(u8 *)&cmd, sizeof(cmd));
	179	}
	180
741a6266 WYG	181	static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
	182	{
	183	struct iwl_calib_cfg_cmd calib_cfg_cmd;
	184	struct iwl_host_cmd cmd = {
	185	.id = CALIBRATION_CFG_CMD,
3fa50738 JB	186	.len = { sizeof(struct iwl_calib_cfg_cmd), },
3fa50738 JB	187	.data = { &calib_cfg_cmd, },
741a6266 WYG	188	};
	189
	190	memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
	191	calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
	192	calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
	193	calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
df2a4dc8 WYG	194	calib_cfg_cmd.ucd_calib_cfg.flags =
df2a4dc8 WYG	195	IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
741a6266	196
e6bb4c9c	197	return iwl_trans_send_cmd(trans(priv), &cmd);
741a6266 WYG	198	}
	199
	200	void iwlagn_rx_calib_result(struct iwl_priv *priv,
	201	struct iwl_rx_mem_buffer *rxb)
	202	{
	203	struct iwl_rx_packet *pkt = rxb_addr(rxb);
	204	struct iwl_calib_hdr hdr = (struct iwl_calib_hdr )pkt->u.raw;
	205	int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
	206	int index;
	207
	208	/* reduce the size of the length field itself */
	209	len -= 4;
	210
	211	/* Define the order in which the results will be sent to the runtime
	212	* uCode. iwl_send_calib_results sends them in a row according to
	213	* their index. We sort them here
	214	*/
	215	switch (hdr->op_code) {
	216	case IWL_PHY_CALIBRATE_DC_CMD:
	217	index = IWL_CALIB_DC;
	218	break;
	219	case IWL_PHY_CALIBRATE_LO_CMD:
	220	index = IWL_CALIB_LO;
	221	break;
	222	case IWL_PHY_CALIBRATE_TX_IQ_CMD:
	223	index = IWL_CALIB_TX_IQ;
	224	break;
	225	case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
	226	index = IWL_CALIB_TX_IQ_PERD;
	227	break;
	228	case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
	229	index = IWL_CALIB_BASE_BAND;
	230	break;
	231	default:
	232	IWL_ERR(priv, "Unknown calibration notification %d\n",
	233	hdr->op_code);
	234	return;
	235	}
	236	iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
	237	}
	238
4613e72d	239	int iwlagn_init_alive_start(struct iwl_priv *priv)
741a6266	240	{
ca7966c8	241	int ret;
741a6266	242
7cb1b088 WYG	243	if (priv->cfg->bt_params &&
7cb1b088 WYG	244	priv->cfg->bt_params->advanced_bt_coexist) {
f7322f8f WYG	245	/*
	246	* Tell uCode we are ready to perform calibration
	247	* need to perform this before any calibration
	248	* no need to close the envlope since we are going
	249	* to load the runtime uCode later.
	250	*/
ca7966c8	251	ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
f7322f8f	252	BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
ca7966c8 JB	253	if (ret)
ca7966c8 JB	254	return ret;
f7322f8f WYG	255
f7322f8f WYG	256	}
ca7966c8 JB	257
	258	ret = iwlagn_send_calib_cfg(priv);
	259	if (ret)
	260	return ret;
bf53f939 SZ	261
	262	/**
	263	* temperature offset calibration is only needed for runtime ucode,
	264	* so prepare the value now.
	265	*/
	266	if (priv->cfg->need_temp_offset_calib)
ca7966c8	267	return iwlagn_set_temperature_offset_calib(priv);
741a6266	268
ca7966c8	269	return 0;
741a6266 WYG	270	}
741a6266 WYG	271
f4012413 WYG	272	static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
	273	{
	274	struct iwl_wimax_coex_cmd coex_cmd;
	275
7cb1b088	276	if (priv->cfg->base_params->support_wimax_coexist) {
f4012413 WYG	277	/* UnMask wake up src at associated sleep */
	278	coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
	279
	280	/* UnMask wake up src at unassociated sleep */
	281	coex_cmd.flags \|= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
	282	memcpy(coex_cmd.sta_prio, cu_priorities,
	283	sizeof(struct iwl_wimax_coex_event_entry) *
	284	COEX_NUM_OF_EVENTS);
	285
	286	/* enabling the coexistence feature */
	287	coex_cmd.flags \|= COEX_FLAGS_COEX_ENABLE_MSK;
	288
	289	/* enabling the priorities tables */
	290	coex_cmd.flags \|= COEX_FLAGS_STA_TABLE_VALID_MSK;
	291	} else {
	292	/* coexistence is disabled */
	293	memset(&coex_cmd, 0, sizeof(coex_cmd));
	294	}
e6bb4c9c	295	return iwl_trans_send_cmd_pdu(trans(priv),
e419d62d	296	COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
f4012413 WYG	297	sizeof(coex_cmd), &coex_cmd);
	298	}
	299
aeb4a2ee WYG	300	static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
	301	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	302	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	303	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	304	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	305	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	306	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	307	((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	308	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	309	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	310	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	311	((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	312	(1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	313	((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	314	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	315	((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	316	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	317	((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) \|
	318	(0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
	319	0, 0, 0, 0, 0, 0, 0
	320	};
	321
f7322f8f	322	void iwlagn_send_prio_tbl(struct iwl_priv *priv)
aeb4a2ee WYG	323	{
	324	struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
	325
	326	memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
	327	sizeof(iwlagn_bt_prio_tbl));
e6bb4c9c	328	if (iwl_trans_send_cmd_pdu(trans(priv),
e419d62d	329	REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
aeb4a2ee WYG	330	sizeof(prio_tbl_cmd), &prio_tbl_cmd))
	331	IWL_ERR(priv, "failed to send BT prio tbl command\n");
	332	}
	333
ca7966c8	334	int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
aeb4a2ee WYG	335	{
aeb4a2ee WYG	336	struct iwl_bt_coex_prot_env_cmd env_cmd;
ca7966c8	337	int ret;
aeb4a2ee WYG	338
	339	env_cmd.action = action;
	340	env_cmd.type = type;
e6bb4c9c	341	ret = iwl_trans_send_cmd_pdu(trans(priv),
e419d62d	342	REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
ca7966c8 JB	343	sizeof(env_cmd), &env_cmd);
ca7966c8 JB	344	if (ret)
aeb4a2ee	345	IWL_ERR(priv, "failed to send BT env command\n");
ca7966c8	346	return ret;
aeb4a2ee WYG	347	}
	348
	349
ca7966c8	350	static int iwlagn_alive_notify(struct iwl_priv *priv)
741a6266	351	{
7415952f	352	int ret;
741a6266	353
dfa2bdba EG	354	if (!priv->tx_cmd_pool)
	355	priv->tx_cmd_pool =
	356	kmem_cache_create("iwlagn_dev_cmd",
	357	sizeof(struct iwl_device_cmd),
	358	sizeof(void *), 0, NULL);
	359
	360	if (!priv->tx_cmd_pool)
	361	return -ENOMEM;
	362
e6bb4c9c	363	iwl_trans_tx_start(trans(priv));
e7cad69c	364
7415952f WYG	365	ret = iwlagn_send_wimax_coex(priv);
	366	if (ret)
	367	return ret;
	368
	369	ret = iwlagn_set_Xtal_calib(priv);
	370	if (ret)
	371	return ret;
741a6266	372
36127db0	373	return iwl_send_calib_results(priv);
741a6266	374	}
db41dd27 WYG	375
	376
	377	/**
	378	* iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
	379	* using sample data 100 bytes apart. If these sample points are good,
	380	* it's a pretty good bet that everything between them is good, too.
	381	*/
b39488a9	382	static int iwl_verify_inst_sparse(struct iwl_priv *priv,
35b1d92d	383	struct fw_desc *fw_desc)
db41dd27	384	{
35b1d92d JB	385	__le32 image = (__le32 )fw_desc->v_addr;
35b1d92d JB	386	u32 len = fw_desc->len;
db41dd27	387	u32 val;
db41dd27 WYG	388	u32 i;
db41dd27 WYG	389
06bb8358	390	IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
db41dd27 WYG	391
	392	for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
	393	/* read data comes through single port, auto-incr addr */
	394	/* NOTE: Use the debugless read so we don't flood kernel log
	395	* if IWL_DL_IO is set */
83ed9015	396	iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
db41dd27	397	i + IWLAGN_RTC_INST_LOWER_BOUND);
83ed9015	398	val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
fb66216f JB	399	if (val != le32_to_cpu(*image))
fb66216f JB	400	return -EIO;
db41dd27 WYG	401	}
db41dd27 WYG	402
fb66216f	403	return 0;
db41dd27 WYG	404	}
db41dd27 WYG	405
fb66216f	406	static void iwl_print_mismatch_inst(struct iwl_priv *priv,
35b1d92d	407	struct fw_desc *fw_desc)
db41dd27	408	{
35b1d92d JB	409	__le32 image = (__le32 )fw_desc->v_addr;
35b1d92d JB	410	u32 len = fw_desc->len;
db41dd27	411	u32 val;
fb66216f JB	412	u32 offs;
fb66216f JB	413	int errors = 0;
db41dd27	414
06bb8358	415	IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
db41dd27	416
83ed9015	417	iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
db41dd27 WYG	418	IWLAGN_RTC_INST_LOWER_BOUND);
db41dd27 WYG	419
fb66216f JB	420	for (offs = 0;
	421	offs < len && errors < 20;
	422	offs += sizeof(u32), image++) {
db41dd27	423	/* read data comes through single port, auto-incr addr */
83ed9015	424	val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
db41dd27	425	if (val != le32_to_cpu(*image)) {
fb66216f JB	426	IWL_ERR(priv, "uCode INST section at "
	427	"offset 0x%x, is 0x%x, s/b 0x%x\n",
	428	offs, val, le32_to_cpu(*image));
	429	errors++;
db41dd27 WYG	430	}
db41dd27 WYG	431	}
db41dd27 WYG	432	}
	433
	434	/**
	435	* iwl_verify_ucode - determine which instruction image is in SRAM,
	436	* and verify its contents
	437	*/
dbf28e21	438	static int iwl_verify_ucode(struct iwl_priv priv, struct fw_img img)
db41dd27	439	{
b39488a9	440	if (!iwl_verify_inst_sparse(priv, &img->code)) {
06bb8358	441	IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
db41dd27 WYG	442	return 0;
	443	}
	444
35b1d92d	445	IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
fb66216f	446
dbf28e21	447	iwl_print_mismatch_inst(priv, &img->code);
fb66216f	448	return -EIO;
db41dd27	449	}
ca7966c8 JB	450
	451	struct iwlagn_alive_data {
	452	bool valid;
	453	u8 subtype;
	454	};
	455
	456	static void iwlagn_alive_fn(struct iwl_priv *priv,
	457	struct iwl_rx_packet *pkt,
	458	void *data)
	459	{
	460	struct iwlagn_alive_data *alive_data = data;
	461	struct iwl_alive_resp *palive;
	462
	463	palive = &pkt->u.alive_frame;
	464
06bb8358	465	IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
ca7966c8 JB	466	"0x%01X 0x%01X\n",
	467	palive->is_valid, palive->ver_type,
	468	palive->ver_subtype);
	469
	470	priv->device_pointers.error_event_table =
	471	le32_to_cpu(palive->error_event_table_ptr);
	472	priv->device_pointers.log_event_table =
	473	le32_to_cpu(palive->log_event_table_ptr);
	474
	475	alive_data->subtype = palive->ver_subtype;
	476	alive_data->valid = palive->is_valid == UCODE_VALID_OK;
	477	}
	478
	479	#define UCODE_ALIVE_TIMEOUT HZ
	480	#define UCODE_CALIB_TIMEOUT (2*HZ)
	481
	482	int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
dbf28e21	483	struct fw_img *image,
872907bb	484	enum iwlagn_ucode_type ucode_type)
ca7966c8 JB	485	{
	486	struct iwl_notification_wait alive_wait;
	487	struct iwlagn_alive_data alive_data;
	488	int ret;
872907bb	489	enum iwlagn_ucode_type old_type;
ca7966c8	490
e6bb4c9c	491	ret = iwl_trans_start_device(trans(priv));
ca7966c8 JB	492	if (ret)
	493	return ret;
	494
	495	iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
	496	iwlagn_alive_fn, &alive_data);
	497
	498	old_type = priv->ucode_type;
872907bb	499	priv->ucode_type = ucode_type;
ca7966c8	500
dbf28e21	501	ret = iwlagn_load_given_ucode(priv, image);
ca7966c8 JB	502	if (ret) {
	503	priv->ucode_type = old_type;
	504	iwlagn_remove_notification(priv, &alive_wait);
	505	return ret;
	506	}
	507
e6bb4c9c	508	iwl_trans_kick_nic(trans(priv));
ca7966c8 JB	509
	510	/*
	511	* Some things may run in the background now, but we
	512	* just wait for the ALIVE notification here.
	513	*/
	514	ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
	515	if (ret) {
	516	priv->ucode_type = old_type;
	517	return ret;
	518	}
	519
	520	if (!alive_data.valid) {
	521	IWL_ERR(priv, "Loaded ucode is not valid!\n");
	522	priv->ucode_type = old_type;
	523	return -EIO;
	524	}
	525
c8ac61cf JB	526	/*
	527	* This step takes a long time (60-80ms!!) and
	528	* WoWLAN image should be loaded quickly, so
	529	* skip it for WoWLAN.
	530	*/
	531	if (ucode_type != IWL_UCODE_WOWLAN) {
	532	ret = iwl_verify_ucode(priv, image);
	533	if (ret) {
	534	priv->ucode_type = old_type;
	535	return ret;
	536	}
ca7966c8	537
c8ac61cf JB	538	/* delay a bit to give rfkill time to run */
	539	msleep(5);
	540	}
ca7966c8 JB	541
	542	ret = iwlagn_alive_notify(priv);
	543	if (ret) {
	544	IWL_WARN(priv,
	545	"Could not complete ALIVE transition: %d\n", ret);
	546	priv->ucode_type = old_type;
	547	return ret;
	548	}
	549
	550	return 0;
	551	}
	552
	553	int iwlagn_run_init_ucode(struct iwl_priv *priv)
	554	{
	555	struct iwl_notification_wait calib_wait;
	556	int ret;
	557
6ac2f839	558	lockdep_assert_held(&priv->shrd->mutex);
ca7966c8 JB	559
ca7966c8 JB	560	/* No init ucode required? Curious, but maybe ok */
dbf28e21	561	if (!priv->ucode_init.code.len)
ca7966c8 JB	562	return 0;
ca7966c8 JB	563
872907bb	564	if (priv->ucode_type != IWL_UCODE_NONE)
ca7966c8 JB	565	return 0;
	566
	567	iwlagn_init_notification_wait(priv, &calib_wait,
	568	CALIBRATION_COMPLETE_NOTIFICATION,
	569	NULL, NULL);
	570
	571	/* Will also start the device */
	572	ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
872907bb	573	IWL_UCODE_INIT);
ca7966c8 JB	574	if (ret)
	575	goto error;
	576
	577	ret = iwlagn_init_alive_start(priv);
	578	if (ret)
	579	goto error;
	580
	581	/*
	582	* Some things may run in the background now, but we
	583	* just wait for the calibration complete notification.
	584	*/
	585	ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
	586
	587	goto out;
	588
	589	error:
	590	iwlagn_remove_notification(priv, &calib_wait);
	591	out:
	592	/* Whatever happened, stop the device */
e6bb4c9c	593	iwl_trans_stop_device(trans(priv));
ca7966c8 JB	594	return ret;
ca7966c8 JB	595	}