[linux.git] / drivers / pwm / pwm-cros-ec.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Expose a PWM controlled by the ChromeOS EC to the host processor.
 *
 * Copyright (C) 2016 Google, Inc.
 */

#include <linux/module.h>
#include <linux/platform_data/cros_ec_commands.h>
#include <linux/platform_data/cros_ec_proto.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

#include <dt-bindings/mfd/cros_ec.h>

/**
 * struct cros_ec_pwm_device - Driver data for EC PWM
 *
 * @dev: Device node
 * @ec: Pointer to EC device
 * @chip: PWM controller chip
 * @use_pwm_type: Use PWM types instead of generic channels
 */
struct cros_ec_pwm_device {
	struct device *dev;
	struct cros_ec_device *ec;
	struct pwm_chip chip;
	bool use_pwm_type;
};

/**
 * struct cros_ec_pwm - per-PWM driver data
 * @duty_cycle: cached duty cycle
 */
struct cros_ec_pwm {
	u16 duty_cycle;
};

static inline struct cros_ec_pwm_device *pwm_to_cros_ec_pwm(struct pwm_chip *c)
{
	return container_of(c, struct cros_ec_pwm_device, chip);
}

static int cros_ec_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct cros_ec_pwm *channel;

	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
	if (!channel)
		return -ENOMEM;

	pwm_set_chip_data(pwm, channel);

	return 0;
}

static void cros_ec_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);

	kfree(channel);
}

static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type)
{
	switch (dt_index) {
	case CROS_EC_PWM_DT_KB_LIGHT:
		*pwm_type = EC_PWM_TYPE_KB_LIGHT;
		return 0;
	case CROS_EC_PWM_DT_DISPLAY_LIGHT:
		*pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
		return 0;
	default:
		return -EINVAL;
	}
}

static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index,
				u16 duty)
{
	struct cros_ec_device *ec = ec_pwm->ec;
	struct {
		struct cros_ec_command msg;
		struct ec_params_pwm_set_duty params;
	} __packed buf;
	struct ec_params_pwm_set_duty *params = &buf.params;
	struct cros_ec_command *msg = &buf.msg;
	int ret;

	memset(&buf, 0, sizeof(buf));

	msg->version = 0;
	msg->command = EC_CMD_PWM_SET_DUTY;
	msg->insize = 0;
	msg->outsize = sizeof(*params);

	params->duty = duty;

	if (ec_pwm->use_pwm_type) {
		ret = cros_ec_dt_type_to_pwm_type(index, &params->pwm_type);
		if (ret) {
			dev_err(ec->dev, "Invalid PWM type index: %d\n", index);
			return ret;
		}
		params->index = 0;
	} else {
		params->pwm_type = EC_PWM_TYPE_GENERIC;
		params->index = index;
	}

	return cros_ec_cmd_xfer_status(ec, msg);
}

static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 index)
{
	struct cros_ec_device *ec = ec_pwm->ec;
	struct {
		struct cros_ec_command msg;
		union {
			struct ec_params_pwm_get_duty params;
			struct ec_response_pwm_get_duty resp;
		};
	} __packed buf;
	struct ec_params_pwm_get_duty *params = &buf.params;
	struct ec_response_pwm_get_duty *resp = &buf.resp;
	struct cros_ec_command *msg = &buf.msg;
	int ret;

	memset(&buf, 0, sizeof(buf));

	msg->version = 0;
	msg->command = EC_CMD_PWM_GET_DUTY;
	msg->insize = sizeof(*resp);
	msg->outsize = sizeof(*params);

	if (ec_pwm->use_pwm_type) {
		ret = cros_ec_dt_type_to_pwm_type(index, &params->pwm_type);
		if (ret) {
			dev_err(ec->dev, "Invalid PWM type index: %d\n", index);
			return ret;
		}
		params->index = 0;
	} else {
		params->pwm_type = EC_PWM_TYPE_GENERIC;
		params->index = index;
	}

	ret = cros_ec_cmd_xfer_status(ec, msg);
	if (ret < 0)
		return ret;

	return resp->duty;
}

static int cros_ec_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			     const struct pwm_state *state)
{
	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
	u16 duty_cycle;
	int ret;

	/* The EC won't let us change the period */
	if (state->period != EC_PWM_MAX_DUTY)
		return -EINVAL;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	/*
	 * EC doesn't separate the concept of duty cycle and enabled, but
	 * kernel does. Translate.
	 */
	duty_cycle = state->enabled ? state->duty_cycle : 0;

	ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle);
	if (ret < 0)
		return ret;

	channel->duty_cycle = state->duty_cycle;

	return 0;
}

static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				  struct pwm_state *state)
{
	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
	int ret;

	ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm);
	if (ret < 0) {
		dev_err(chip->dev, "error getting initial duty: %d\n", ret);
		return;
	}

	state->enabled = (ret > 0);
	state->period = EC_PWM_MAX_DUTY;

	/*
	 * Note that "disabled" and "duty cycle == 0" are treated the same. If
	 * the cached duty cycle is not zero, used the cached duty cycle. This
	 * ensures that the configured duty cycle is kept across a disable and
	 * enable operation and avoids potentially confusing consumers.
	 *
	 * For the case of the initial hardware readout, channel->duty_cycle
	 * will be 0 and the actual duty cycle read from the EC is used.
	 */
	if (ret == 0 && channel->duty_cycle > 0)
		state->duty_cycle = channel->duty_cycle;
	else
		state->duty_cycle = ret;
}

static struct pwm_device *
cros_ec_pwm_xlate(struct pwm_chip *pc, const struct of_phandle_args *args)
{
	struct pwm_device *pwm;

	if (args->args[0] >= pc->npwm)
		return ERR_PTR(-EINVAL);

	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
	if (IS_ERR(pwm))
		return pwm;

	/* The EC won't let us change the period */
	pwm->args.period = EC_PWM_MAX_DUTY;

	return pwm;
}

static const struct pwm_ops cros_ec_pwm_ops = {
	.request = cros_ec_pwm_request,
	.free = cros_ec_pwm_free,
	.get_state	= cros_ec_pwm_get_state,
	.apply		= cros_ec_pwm_apply,
	.owner		= THIS_MODULE,
};

/*
 * Determine the number of supported PWMs. The EC does not return the number
 * of PWMs it supports directly, so we have to read the pwm duty cycle for
 * subsequent channels until we get an error.
 */
static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm)
{
	int i, ret;

	/* The index field is only 8 bits */
	for (i = 0; i <= U8_MAX; i++) {
		ret = cros_ec_pwm_get_duty(ec_pwm, i);
		/*
		 * We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
		 * responses; everything else is treated as an error.
		 * The EC error codes map to -EOPNOTSUPP and -EINVAL,
		 * so check for those.
		 */
		switch (ret) {
		case -EOPNOTSUPP:	/* invalid command */
			return -ENODEV;
		case -EINVAL:		/* invalid parameter */
			return i;
		default:
			if (ret < 0)
				return ret;
			break;
		}
	}

	return U8_MAX;
}

static int cros_ec_pwm_probe(struct platform_device *pdev)
{
	struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
	struct device *dev = &pdev->dev;
	struct device_node *np = pdev->dev.of_node;
	struct cros_ec_pwm_device *ec_pwm;
	struct pwm_chip *chip;
	int ret;

	if (!ec) {
		dev_err(dev, "no parent EC device\n");
		return -EINVAL;
	}

	ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
	if (!ec_pwm)
		return -ENOMEM;
	chip = &ec_pwm->chip;
	ec_pwm->ec = ec;

	if (of_device_is_compatible(np, "google,cros-ec-pwm-type"))
		ec_pwm->use_pwm_type = true;

	/* PWM chip */
	chip->dev = dev;
	chip->ops = &cros_ec_pwm_ops;
	chip->of_xlate = cros_ec_pwm_xlate;
	chip->of_pwm_n_cells = 1;

	if (ec_pwm->use_pwm_type) {
		chip->npwm = CROS_EC_PWM_DT_COUNT;
	} else {
		ret = cros_ec_num_pwms(ec_pwm);
		if (ret < 0) {
			dev_err(dev, "Couldn't find PWMs: %d\n", ret);
			return ret;
		}
		chip->npwm = ret;
	}

	dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);

	ret = pwmchip_add(chip);
	if (ret < 0) {
		dev_err(dev, "cannot register PWM: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, ec_pwm);

	return ret;
}

static int cros_ec_pwm_remove(struct platform_device *dev)
{
	struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev);
	struct pwm_chip *chip = &ec_pwm->chip;

	pwmchip_remove(chip);

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id cros_ec_pwm_of_match[] = {
	{ .compatible = "google,cros-ec-pwm" },
	{ .compatible = "google,cros-ec-pwm-type" },
	{},
};
MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
#endif

static struct platform_driver cros_ec_pwm_driver = {
	.probe = cros_ec_pwm_probe,
	.remove = cros_ec_pwm_remove,
	.driver = {
		.name = "cros-ec-pwm",
		.of_match_table = of_match_ptr(cros_ec_pwm_of_match),
	},
};
module_platform_driver(cros_ec_pwm_driver);

MODULE_ALIAS("platform:cros-ec-pwm");
MODULE_DESCRIPTION("ChromeOS EC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
4964cb52	1	// SPDX-License-Identifier: GPL-2.0
1f0d3bb0	2	/*
1f0d3bb0	3	* Expose a PWM controlled by the ChromeOS EC to the host processor.
4964cb52 EBS	4	*
4964cb52 EBS	5	* Copyright (C) 2016 Google, Inc.
1f0d3bb0 BN	6	*/
	7
	8	#include <linux/module.h>
840d9f13 EBS	9	#include <linux/platform_data/cros_ec_commands.h>
840d9f13 EBS	10	#include <linux/platform_data/cros_ec_proto.h>
1f0d3bb0 BN	11	#include <linux/platform_device.h>
	12	#include <linux/pwm.h>
	13	#include <linux/slab.h>
	14
3d593b6e FB	15	#include <dt-bindings/mfd/cros_ec.h>
3d593b6e FB	16
1f0d3bb0 BN	17	/**
	18	* struct cros_ec_pwm_device - Driver data for EC PWM
	19	*
	20	* @dev: Device node
	21	* @ec: Pointer to EC device
	22	* @chip: PWM controller chip
3d593b6e	23	* @use_pwm_type: Use PWM types instead of generic channels
1f0d3bb0 BN	24	*/
	25	struct cros_ec_pwm_device {
	26	struct device *dev;
	27	struct cros_ec_device *ec;
	28	struct pwm_chip chip;
3d593b6e	29	bool use_pwm_type;
1f0d3bb0 BN	30	};
1f0d3bb0 BN	31
1db37f95 TR	32	/**
	33	* struct cros_ec_pwm - per-PWM driver data
	34	* @duty_cycle: cached duty cycle
	35	*/
	36	struct cros_ec_pwm {
	37	u16 duty_cycle;
	38	};
	39
1f0d3bb0 BN	40	static inline struct cros_ec_pwm_device pwm_to_cros_ec_pwm(struct pwm_chip c)
	41	{
	42	return container_of(c, struct cros_ec_pwm_device, chip);
	43	}
	44
1db37f95 TR	45	static int cros_ec_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	46	{
	47	struct cros_ec_pwm *channel;
	48
	49	channel = kzalloc(sizeof(*channel), GFP_KERNEL);
	50	if (!channel)
	51	return -ENOMEM;
	52
	53	pwm_set_chip_data(pwm, channel);
	54
	55	return 0;
	56	}
	57
	58	static void cros_ec_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	59	{
	60	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
	61
	62	kfree(channel);
	63	}
	64
3d593b6e	65	static int cros_ec_dt_type_to_pwm_type(u8 dt_index, u8 *pwm_type)
1f0d3bb0	66	{
3d593b6e FB	67	switch (dt_index) {
	68	case CROS_EC_PWM_DT_KB_LIGHT:
	69	*pwm_type = EC_PWM_TYPE_KB_LIGHT;
	70	return 0;
	71	case CROS_EC_PWM_DT_DISPLAY_LIGHT:
	72	*pwm_type = EC_PWM_TYPE_DISPLAY_LIGHT;
	73	return 0;
	74	default:
	75	return -EINVAL;
	76	}
	77	}
	78
	79	static int cros_ec_pwm_set_duty(struct cros_ec_pwm_device *ec_pwm, u8 index,
	80	u16 duty)
	81	{
	82	struct cros_ec_device *ec = ec_pwm->ec;
1f0d3bb0 BN	83	struct {
	84	struct cros_ec_command msg;
	85	struct ec_params_pwm_set_duty params;
065cfbbb	86	} __packed buf;
1f0d3bb0 BN	87	struct ec_params_pwm_set_duty *params = &buf.params;
1f0d3bb0 BN	88	struct cros_ec_command *msg = &buf.msg;
3d593b6e	89	int ret;
1f0d3bb0 BN	90
	91	memset(&buf, 0, sizeof(buf));
	92
	93	msg->version = 0;
	94	msg->command = EC_CMD_PWM_SET_DUTY;
	95	msg->insize = 0;
	96	msg->outsize = sizeof(*params);
	97
	98	params->duty = duty;
3d593b6e FB	99
	100	if (ec_pwm->use_pwm_type) {
	101	ret = cros_ec_dt_type_to_pwm_type(index, &params->pwm_type);
	102	if (ret) {
	103	dev_err(ec->dev, "Invalid PWM type index: %d\n", index);
	104	return ret;
	105	}
	106	params->index = 0;
	107	} else {
	108	params->pwm_type = EC_PWM_TYPE_GENERIC;
	109	params->index = index;
	110	}
1f0d3bb0 BN	111
	112	return cros_ec_cmd_xfer_status(ec, msg);
	113	}
	114
3d593b6e	115	static int cros_ec_pwm_get_duty(struct cros_ec_pwm_device *ec_pwm, u8 index)
1f0d3bb0	116	{
3d593b6e	117	struct cros_ec_device *ec = ec_pwm->ec;
1f0d3bb0 BN	118	struct {
	119	struct cros_ec_command msg;
	120	union {
	121	struct ec_params_pwm_get_duty params;
	122	struct ec_response_pwm_get_duty resp;
	123	};
065cfbbb	124	} __packed buf;
1f0d3bb0 BN	125	struct ec_params_pwm_get_duty *params = &buf.params;
	126	struct ec_response_pwm_get_duty *resp = &buf.resp;
	127	struct cros_ec_command *msg = &buf.msg;
	128	int ret;
	129
	130	memset(&buf, 0, sizeof(buf));
	131
	132	msg->version = 0;
	133	msg->command = EC_CMD_PWM_GET_DUTY;
e47866a1 NV	134	msg->insize = sizeof(*resp);
e47866a1 NV	135	msg->outsize = sizeof(*params);
1f0d3bb0	136
3d593b6e FB	137	if (ec_pwm->use_pwm_type) {
	138	ret = cros_ec_dt_type_to_pwm_type(index, &params->pwm_type);
	139	if (ret) {
	140	dev_err(ec->dev, "Invalid PWM type index: %d\n", index);
	141	return ret;
	142	}
	143	params->index = 0;
	144	} else {
	145	params->pwm_type = EC_PWM_TYPE_GENERIC;
	146	params->index = index;
	147	}
1f0d3bb0 BN	148
1f0d3bb0 BN	149	ret = cros_ec_cmd_xfer_status(ec, msg);
1f0d3bb0 BN	150	if (ret < 0)
	151	return ret;
	152
	153	return resp->duty;
	154	}
	155
1f0d3bb0	156	static int cros_ec_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	157	const struct pwm_state *state)
1f0d3bb0 BN	158	{
1f0d3bb0 BN	159	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
1db37f95 TR	160	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
	161	u16 duty_cycle;
	162	int ret;
1f0d3bb0 BN	163
	164	/* The EC won't let us change the period */
	165	if (state->period != EC_PWM_MAX_DUTY)
	166	return -EINVAL;
	167
9f0f6107 UKK	168	if (state->polarity != PWM_POLARITY_NORMAL)
	169	return -EINVAL;
	170
1f0d3bb0 BN	171	/*
	172	* EC doesn't separate the concept of duty cycle and enabled, but
	173	* kernel does. Translate.
	174	*/
	175	duty_cycle = state->enabled ? state->duty_cycle : 0;
	176
3d593b6e	177	ret = cros_ec_pwm_set_duty(ec_pwm, pwm->hwpwm, duty_cycle);
1db37f95 TR	178	if (ret < 0)
	179	return ret;
	180
	181	channel->duty_cycle = state->duty_cycle;
	182
	183	return 0;
1f0d3bb0 BN	184	}
	185
	186	static void cros_ec_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
	187	struct pwm_state *state)
	188	{
	189	struct cros_ec_pwm_device *ec_pwm = pwm_to_cros_ec_pwm(chip);
1db37f95	190	struct cros_ec_pwm *channel = pwm_get_chip_data(pwm);
1f0d3bb0 BN	191	int ret;
1f0d3bb0 BN	192
3d593b6e	193	ret = cros_ec_pwm_get_duty(ec_pwm, pwm->hwpwm);
1f0d3bb0 BN	194	if (ret < 0) {
	195	dev_err(chip->dev, "error getting initial duty: %d\n", ret);
	196	return;
	197	}
	198
	199	state->enabled = (ret > 0);
	200	state->period = EC_PWM_MAX_DUTY;
	201
1db37f95 TR	202	/*
	203	* Note that "disabled" and "duty cycle == 0" are treated the same. If
	204	* the cached duty cycle is not zero, used the cached duty cycle. This
	205	* ensures that the configured duty cycle is kept across a disable and
	206	* enable operation and avoids potentially confusing consumers.
	207	*
	208	* For the case of the initial hardware readout, channel->duty_cycle
	209	* will be 0 and the actual duty cycle read from the EC is used.
	210	*/
	211	if (ret == 0 && channel->duty_cycle > 0)
	212	state->duty_cycle = channel->duty_cycle;
	213	else
	214	state->duty_cycle = ret;
1f0d3bb0 BN	215	}
	216
	217	static struct pwm_device *
	218	cros_ec_pwm_xlate(struct pwm_chip pc, const struct of_phandle_args args)
	219	{
	220	struct pwm_device *pwm;
	221
	222	if (args->args[0] >= pc->npwm)
	223	return ERR_PTR(-EINVAL);
	224
	225	pwm = pwm_request_from_chip(pc, args->args[0], NULL);
	226	if (IS_ERR(pwm))
	227	return pwm;
	228
	229	/* The EC won't let us change the period */
	230	pwm->args.period = EC_PWM_MAX_DUTY;
	231
	232	return pwm;
	233	}
	234
	235	static const struct pwm_ops cros_ec_pwm_ops = {
1db37f95 TR	236	.request = cros_ec_pwm_request,
1db37f95 TR	237	.free = cros_ec_pwm_free,
1f0d3bb0 BN	238	.get_state = cros_ec_pwm_get_state,
	239	.apply = cros_ec_pwm_apply,
	240	.owner = THIS_MODULE,
	241	};
	242
d509f8a7 GR	243	/*
	244	* Determine the number of supported PWMs. The EC does not return the number
	245	* of PWMs it supports directly, so we have to read the pwm duty cycle for
	246	* subsequent channels until we get an error.
	247	*/
3d593b6e	248	static int cros_ec_num_pwms(struct cros_ec_pwm_device *ec_pwm)
1f0d3bb0 BN	249	{
	250	int i, ret;
	251
	252	/* The index field is only 8 bits */
	253	for (i = 0; i <= U8_MAX; i++) {
3d593b6e	254	ret = cros_ec_pwm_get_duty(ec_pwm, i);
1f0d3bb0 BN	255	/*
	256	* We look for SUCCESS, INVALID_COMMAND, or INVALID_PARAM
	257	* responses; everything else is treated as an error.
be020f0d GR	258	* The EC error codes map to -EOPNOTSUPP and -EINVAL,
be020f0d GR	259	* so check for those.
1f0d3bb0	260	*/
d509f8a7 GR	261	switch (ret) {
d509f8a7 GR	262	case -EOPNOTSUPP: /* invalid command */
1f0d3bb0	263	return -ENODEV;
d509f8a7	264	case -EINVAL: /* invalid parameter */
1f0d3bb0	265	return i;
d509f8a7 GR	266	default:
	267	if (ret < 0)
	268	return ret;
	269	break;
	270	}
1f0d3bb0 BN	271	}
	272
	273	return U8_MAX;
	274	}
	275
	276	static int cros_ec_pwm_probe(struct platform_device *pdev)
	277	{
	278	struct cros_ec_device *ec = dev_get_drvdata(pdev->dev.parent);
	279	struct device *dev = &pdev->dev;
3d593b6e	280	struct device_node *np = pdev->dev.of_node;
1f0d3bb0 BN	281	struct cros_ec_pwm_device *ec_pwm;
	282	struct pwm_chip *chip;
	283	int ret;
	284
	285	if (!ec) {
	286	dev_err(dev, "no parent EC device\n");
	287	return -EINVAL;
	288	}
	289
	290	ec_pwm = devm_kzalloc(dev, sizeof(*ec_pwm), GFP_KERNEL);
	291	if (!ec_pwm)
	292	return -ENOMEM;
	293	chip = &ec_pwm->chip;
	294	ec_pwm->ec = ec;
	295
3d593b6e FB	296	if (of_device_is_compatible(np, "google,cros-ec-pwm-type"))
	297	ec_pwm->use_pwm_type = true;
	298
1f0d3bb0 BN	299	/* PWM chip */
	300	chip->dev = dev;
	301	chip->ops = &cros_ec_pwm_ops;
	302	chip->of_xlate = cros_ec_pwm_xlate;
	303	chip->of_pwm_n_cells = 1;
3d593b6e FB	304
	305	if (ec_pwm->use_pwm_type) {
	306	chip->npwm = CROS_EC_PWM_DT_COUNT;
	307	} else {
	308	ret = cros_ec_num_pwms(ec_pwm);
	309	if (ret < 0) {
	310	dev_err(dev, "Couldn't find PWMs: %d\n", ret);
	311	return ret;
	312	}
	313	chip->npwm = ret;
1f0d3bb0	314	}
3d593b6e	315
1f0d3bb0 BN	316	dev_dbg(dev, "Probed %u PWMs\n", chip->npwm);
	317
	318	ret = pwmchip_add(chip);
	319	if (ret < 0) {
	320	dev_err(dev, "cannot register PWM: %d\n", ret);
	321	return ret;
	322	}
	323
	324	platform_set_drvdata(pdev, ec_pwm);
	325
	326	return ret;
	327	}
	328
	329	static int cros_ec_pwm_remove(struct platform_device *dev)
	330	{
	331	struct cros_ec_pwm_device *ec_pwm = platform_get_drvdata(dev);
	332	struct pwm_chip *chip = &ec_pwm->chip;
	333
a08be127 UKK	334	pwmchip_remove(chip);
	335
	336	return 0;
1f0d3bb0 BN	337	}
	338
	339	#ifdef CONFIG_OF
	340	static const struct of_device_id cros_ec_pwm_of_match[] = {
	341	{ .compatible = "google,cros-ec-pwm" },
3d593b6e	342	{ .compatible = "google,cros-ec-pwm-type" },
1f0d3bb0 BN	343	{},
	344	};
	345	MODULE_DEVICE_TABLE(of, cros_ec_pwm_of_match);
	346	#endif
	347
	348	static struct platform_driver cros_ec_pwm_driver = {
	349	.probe = cros_ec_pwm_probe,
	350	.remove = cros_ec_pwm_remove,
	351	.driver = {
	352	.name = "cros-ec-pwm",
	353	.of_match_table = of_match_ptr(cros_ec_pwm_of_match),
	354	},
	355	};
	356	module_platform_driver(cros_ec_pwm_driver);
	357
	358	MODULE_ALIAS("platform:cros-ec-pwm");
	359	MODULE_DESCRIPTION("ChromeOS EC PWM driver");
	360	MODULE_LICENSE("GPL v2");