[linux.git] / drivers / watchdog / shwdt.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * drivers/watchdog/shwdt.c
 *
 * Watchdog driver for integrated watchdog in the SuperH processors.
 *
 * Copyright (C) 2001 - 2012  Paul Mundt <[email protected]>
 *
 * 14-Dec-2001 Matt Domsch <[email protected]>
 *     Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
 *
 * 19-Apr-2002 Rob Radez <[email protected]>
 *     Added expect close support, made emulated timeout runtime changeable
 *     general cleanups, add some ioctls
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/watchdog.h>
#include <linux/pm_runtime.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <asm/watchdog.h>

#define DRV_NAME "sh-wdt"

/*
 * Default clock division ratio is 5.25 msecs. For an additional table of
 * values, consult the asm-sh/watchdog.h. Overload this at module load
 * time.
 *
 * In order for this to work reliably we need to have HZ set to 1000 or
 * something quite higher than 100 (or we need a proper high-res timer
 * implementation that will deal with this properly), otherwise the 10ms
 * resolution of a jiffy is enough to trigger the overflow. For things like
 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
 * necssary.
 *
 * As a result of this timing problem, the only modes that are particularly
 * feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
 * overflow periods respectively.
 *
 * Also, since we can't really expect userspace to be responsive enough
 * before the overflow happens, we maintain two separate timers .. One in
 * the kernel for clearing out WOVF every 2ms or so (again, this depends on
 * HZ == 1000), and another for monitoring userspace writes to the WDT device.
 *
 * As such, we currently use a configurable heartbeat interval which defaults
 * to 30s. In this case, the userspace daemon is only responsible for periodic
 * writes to the device before the next heartbeat is scheduled. If the daemon
 * misses its deadline, the kernel timer will allow the WDT to overflow.
 */
static int clock_division_ratio = WTCSR_CKS_4096;
#define next_ping_period(cks)	(jiffies + msecs_to_jiffies(cks - 4))

#define WATCHDOG_HEARTBEAT 30			/* 30 sec default heartbeat */
static int heartbeat = WATCHDOG_HEARTBEAT;	/* in seconds */
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned long next_heartbeat;

struct sh_wdt {
	void __iomem		*base;
	struct device		*dev;
	struct clk		*clk;
	spinlock_t		lock;

	struct timer_list	timer;
};

static int sh_wdt_start(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;
	u8 csr;

	pm_runtime_get_sync(wdt->dev);
	clk_enable(wdt->clk);

	spin_lock_irqsave(&wdt->lock, flags);

	next_heartbeat = jiffies + (heartbeat * HZ);
	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));

	csr = sh_wdt_read_csr();
	csr |= WTCSR_WT | clock_division_ratio;
	sh_wdt_write_csr(csr);

	sh_wdt_write_cnt(0);

	/*
	 * These processors have a bit of an inconsistent initialization
	 * process.. starting with SH-3, RSTS was moved to WTCSR, and the
	 * RSTCSR register was removed.
	 *
	 * On the SH-2 however, in addition with bits being in different
	 * locations, we must deal with RSTCSR outright..
	 */
	csr = sh_wdt_read_csr();
	csr |= WTCSR_TME;
	csr &= ~WTCSR_RSTS;
	sh_wdt_write_csr(csr);

#ifdef CONFIG_CPU_SH2
	csr = sh_wdt_read_rstcsr();
	csr &= ~RSTCSR_RSTS;
	sh_wdt_write_rstcsr(csr);
#endif
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static int sh_wdt_stop(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;
	u8 csr;

	spin_lock_irqsave(&wdt->lock, flags);

	del_timer(&wdt->timer);

	csr = sh_wdt_read_csr();
	csr &= ~WTCSR_TME;
	sh_wdt_write_csr(csr);

	spin_unlock_irqrestore(&wdt->lock, flags);

	clk_disable(wdt->clk);
	pm_runtime_put_sync(wdt->dev);

	return 0;
}

static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;

	spin_lock_irqsave(&wdt->lock, flags);
	next_heartbeat = jiffies + (heartbeat * HZ);
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;

	if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */
		return -EINVAL;

	spin_lock_irqsave(&wdt->lock, flags);
	heartbeat = t;
	wdt_dev->timeout = t;
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static void sh_wdt_ping(struct timer_list *t)
{
	struct sh_wdt *wdt = from_timer(wdt, t, timer);
	unsigned long flags;

	spin_lock_irqsave(&wdt->lock, flags);
	if (time_before(jiffies, next_heartbeat)) {
		u8 csr;

		csr = sh_wdt_read_csr();
		csr &= ~WTCSR_IOVF;
		sh_wdt_write_csr(csr);

		sh_wdt_write_cnt(0);

		mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
	} else
		dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
		         "the watchdog\n");
	spin_unlock_irqrestore(&wdt->lock, flags);
}

static const struct watchdog_info sh_wdt_info = {
	.options		= WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
				  WDIOF_MAGICCLOSE,
	.firmware_version	= 1,
	.identity		= "SH WDT",
};

static const struct watchdog_ops sh_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= sh_wdt_start,
	.stop		= sh_wdt_stop,
	.ping		= sh_wdt_keepalive,
	.set_timeout	= sh_wdt_set_heartbeat,
};

static struct watchdog_device sh_wdt_dev = {
	.info	= &sh_wdt_info,
	.ops	= &sh_wdt_ops,
};

static int sh_wdt_probe(struct platform_device *pdev)
{
	struct sh_wdt *wdt;
	int rc;

	/*
	 * As this driver only covers the global watchdog case, reject
	 * any attempts to register per-CPU watchdogs.
	 */
	if (pdev->id != -1)
		return -EINVAL;

	wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
	if (unlikely(!wdt))
		return -ENOMEM;

	wdt->dev = &pdev->dev;

	wdt->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdt->clk)) {
		/*
		 * Clock framework support is optional, continue on
		 * anyways if we don't find a matching clock.
		 */
		wdt->clk = NULL;
	}

	wdt->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	watchdog_set_nowayout(&sh_wdt_dev, nowayout);
	watchdog_set_drvdata(&sh_wdt_dev, wdt);
	sh_wdt_dev.parent = &pdev->dev;

	spin_lock_init(&wdt->lock);

	rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
	if (unlikely(rc)) {
		/* Default timeout if invalid */
		sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);

		dev_warn(&pdev->dev,
			 "heartbeat value must be 1<=x<=3600, using %d\n",
			 sh_wdt_dev.timeout);
	}

	dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
		 sh_wdt_dev.timeout, nowayout);

	rc = watchdog_register_device(&sh_wdt_dev);
	if (unlikely(rc)) {
		dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
		return rc;
	}

	timer_setup(&wdt->timer, sh_wdt_ping, 0);
	wdt->timer.expires	= next_ping_period(clock_division_ratio);

	dev_info(&pdev->dev, "initialized.\n");

	pm_runtime_enable(&pdev->dev);

	return 0;
}

static int sh_wdt_remove(struct platform_device *pdev)
{
	watchdog_unregister_device(&sh_wdt_dev);

	pm_runtime_disable(&pdev->dev);

	return 0;
}

static void sh_wdt_shutdown(struct platform_device *pdev)
{
	sh_wdt_stop(&sh_wdt_dev);
}

static struct platform_driver sh_wdt_driver = {
	.driver		= {
		.name	= DRV_NAME,
	},

	.probe		= sh_wdt_probe,
	.remove		= sh_wdt_remove,
	.shutdown	= sh_wdt_shutdown,
};

static int __init sh_wdt_init(void)
{
	if (unlikely(clock_division_ratio < 0x5 ||
		     clock_division_ratio > 0x7)) {
		clock_division_ratio = WTCSR_CKS_4096;

		pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
			clock_division_ratio);
	}

	return platform_driver_register(&sh_wdt_driver);
}

static void __exit sh_wdt_exit(void)
{
	platform_driver_unregister(&sh_wdt_driver);
}
module_init(sh_wdt_init);
module_exit(sh_wdt_exit);

MODULE_AUTHOR("Paul Mundt <[email protected]>");
MODULE_DESCRIPTION("SuperH watchdog driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);

module_param(clock_division_ratio, int, 0);
MODULE_PARM_DESC(clock_division_ratio,
	"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
	"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
	"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
				__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4	2	/*
b1fa888e	3	* drivers/watchdog/shwdt.c
1da177e4 LT	4	*
	5	* Watchdog driver for integrated watchdog in the SuperH processors.
	6	*
40968126	7	* Copyright (C) 2001 - 2012 Paul Mundt <[email protected]>
1da177e4	8	*
1da177e4 LT	9	* 14-Dec-2001 Matt Domsch <[email protected]>
	10	* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
	11	*
	12	* 19-Apr-2002 Rob Radez <[email protected]>
	13	* Added expect close support, made emulated timeout runtime changeable
	14	* general cleanups, add some ioctls
	15	*/
27c766aa JP	16
	17	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	18
1da177e4 LT	19	#include <linux/module.h>
1da177e4 LT	20	#include <linux/moduleparam.h>
8f5585ec	21	#include <linux/platform_device.h>
1da177e4 LT	22	#include <linux/init.h>
1da177e4 LT	23	#include <linux/types.h>
f9fb360c	24	#include <linux/spinlock.h>
1da177e4	25	#include <linux/watchdog.h>
8c013d96	26	#include <linux/pm_runtime.h>
1da177e4	27	#include <linux/fs.h>
f118420b	28	#include <linux/mm.h>
8f5585ec	29	#include <linux/slab.h>
70b814ec	30	#include <linux/io.h>
9ea64046	31	#include <linux/clk.h>
6330c707	32	#include <linux/err.h>
58cf4198	33	#include <asm/watchdog.h>
1da177e4	34
8f5585ec	35	#define DRV_NAME "sh-wdt"
1da177e4 LT	36
	37	/*
	38	* Default clock division ratio is 5.25 msecs. For an additional table of
	39	* values, consult the asm-sh/watchdog.h. Overload this at module load
	40	* time.
	41	*
	42	* In order for this to work reliably we need to have HZ set to 1000 or
	43	* something quite higher than 100 (or we need a proper high-res timer
	44	* implementation that will deal with this properly), otherwise the 10ms
	45	* resolution of a jiffy is enough to trigger the overflow. For things like
	46	* the SH-4 and SH-5, this isn't necessarily that big of a problem, though
	47	* for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
	48	* necssary.
	49	*
	50	* As a result of this timing problem, the only modes that are particularly
25985edc	51	* feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
1da177e4 LT	52	* overflow periods respectively.
	53	*
	54	* Also, since we can't really expect userspace to be responsive enough
ee0fc097	55	* before the overflow happens, we maintain two separate timers .. One in
1da177e4 LT	56	* the kernel for clearing out WOVF every 2ms or so (again, this depends on
	57	* HZ == 1000), and another for monitoring userspace writes to the WDT device.
	58	*
	59	* As such, we currently use a configurable heartbeat interval which defaults
	60	* to 30s. In this case, the userspace daemon is only responsible for periodic
	61	* writes to the device before the next heartbeat is scheduled. If the daemon
	62	* misses its deadline, the kernel timer will allow the WDT to overflow.
	63	*/
	64	static int clock_division_ratio = WTCSR_CKS_4096;
bea19066	65	#define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4))
1da177e4	66
1da177e4 LT	67	#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
1da177e4 LT	68	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
86a1e189	69	static bool nowayout = WATCHDOG_NOWAYOUT;
8f5585ec PM	70	static unsigned long next_heartbeat;
	71
	72	struct sh_wdt {
	73	void __iomem *base;
	74	struct device *dev;
9ea64046	75	struct clk *clk;
f9fb360c	76	spinlock_t lock;
1da177e4	77
8f5585ec	78	struct timer_list timer;
8f5585ec PM	79	};
8f5585ec PM	80
1950f499	81	static int sh_wdt_start(struct watchdog_device *wdt_dev)
1da177e4	82	{
1950f499	83	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec	84	unsigned long flags;
8f5585ec	85	u8 csr;
70b814ec	86
8c013d96	87	pm_runtime_get_sync(wdt->dev);
d42c9744	88	clk_enable(wdt->clk);
8c013d96	89
f9fb360c	90	spin_lock_irqsave(&wdt->lock, flags);
1da177e4 LT	91
1da177e4 LT	92	next_heartbeat = jiffies + (heartbeat * HZ);
8f5585ec	93	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
1da177e4 LT	94
	95	csr = sh_wdt_read_csr();
	96	csr \|= WTCSR_WT \| clock_division_ratio;
	97	sh_wdt_write_csr(csr);
	98
	99	sh_wdt_write_cnt(0);
	100
	101	/*
	102	* These processors have a bit of an inconsistent initialization
	103	* process.. starting with SH-3, RSTS was moved to WTCSR, and the
	104	* RSTCSR register was removed.
	105	*
	106	* On the SH-2 however, in addition with bits being in different
	107	* locations, we must deal with RSTCSR outright..
	108	*/
	109	csr = sh_wdt_read_csr();
	110	csr \|= WTCSR_TME;
	111	csr &= ~WTCSR_RSTS;
	112	sh_wdt_write_csr(csr);
	113
	114	#ifdef CONFIG_CPU_SH2
1da177e4 LT	115	csr = sh_wdt_read_rstcsr();
	116	csr &= ~RSTCSR_RSTS;
	117	sh_wdt_write_rstcsr(csr);
	118	#endif
f9fb360c	119	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499 PM	120
1950f499 PM	121	return 0;
1da177e4 LT	122	}
1da177e4 LT	123
1950f499	124	static int sh_wdt_stop(struct watchdog_device *wdt_dev)
1da177e4	125	{
1950f499	126	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec	127	unsigned long flags;
8f5585ec	128	u8 csr;
70b814ec	129
f9fb360c	130	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	131
8f5585ec	132	del_timer(&wdt->timer);
1da177e4 LT	133
	134	csr = sh_wdt_read_csr();
	135	csr &= ~WTCSR_TME;
	136	sh_wdt_write_csr(csr);
8f5585ec	137
f9fb360c	138	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499	139
d42c9744	140	clk_disable(wdt->clk);
8c013d96 PM	141	pm_runtime_put_sync(wdt->dev);
8c013d96 PM	142
1950f499	143	return 0;
1da177e4 LT	144	}
1da177e4 LT	145
1950f499	146	static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
1da177e4	147	{
f9fb360c	148	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec AC	149	unsigned long flags;
70b814ec AC	150
f9fb360c	151	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	152	next_heartbeat = jiffies + (heartbeat * HZ);
f9fb360c	153	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499 PM	154
1950f499 PM	155	return 0;
1da177e4 LT	156	}
1da177e4 LT	157
1950f499	158	static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
1da177e4	159	{
f9fb360c	160	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec AC	161	unsigned long flags;
	162
	163	if (unlikely(t < 1 \|\| t > 3600)) /* arbitrary upper limit */
1da177e4 LT	164	return -EINVAL;
1da177e4 LT	165
f9fb360c	166	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	167	heartbeat = t;
1950f499	168	wdt_dev->timeout = t;
f9fb360c	169	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499	170
1da177e4 LT	171	return 0;
	172	}
	173
e99e88a9	174	static void sh_wdt_ping(struct timer_list *t)
1da177e4	175	{
e99e88a9	176	struct sh_wdt *wdt = from_timer(wdt, t, timer);
70b814ec AC	177	unsigned long flags;
70b814ec AC	178
f9fb360c	179	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	180	if (time_before(jiffies, next_heartbeat)) {
8f5585ec	181	u8 csr;
1da177e4 LT	182
	183	csr = sh_wdt_read_csr();
	184	csr &= ~WTCSR_IOVF;
	185	sh_wdt_write_csr(csr);
	186
	187	sh_wdt_write_cnt(0);
	188
8f5585ec	189	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
e4c2cfee	190	} else
8f5585ec PM	191	dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
8f5585ec PM	192	"the watchdog\n");
f9fb360c	193	spin_unlock_irqrestore(&wdt->lock, flags);
1da177e4 LT	194	}
1da177e4 LT	195
70b814ec	196	static const struct watchdog_info sh_wdt_info = {
e4c2cfee PM	197	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \|
e4c2cfee PM	198	WDIOF_MAGICCLOSE,
1da177e4 LT	199	.firmware_version = 1,
	200	.identity = "SH WDT",
	201	};
	202
1950f499 PM	203	static const struct watchdog_ops sh_wdt_ops = {
	204	.owner = THIS_MODULE,
	205	.start = sh_wdt_start,
	206	.stop = sh_wdt_stop,
	207	.ping = sh_wdt_keepalive,
	208	.set_timeout = sh_wdt_set_heartbeat,
	209	};
	210
	211	static struct watchdog_device sh_wdt_dev = {
	212	.info = &sh_wdt_info,
	213	.ops = &sh_wdt_ops,
1da177e4 LT	214	};
1da177e4 LT	215
2d991a16	216	static int sh_wdt_probe(struct platform_device *pdev)
1da177e4	217	{
8f5585ec	218	struct sh_wdt *wdt;
1da177e4 LT	219	int rc;
1da177e4 LT	220
8f5585ec PM	221	/*
	222	* As this driver only covers the global watchdog case, reject
	223	* any attempts to register per-CPU watchdogs.
	224	*/
	225	if (pdev->id != -1)
	226	return -EINVAL;
	227
8f5585ec	228	wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
9ea64046 PM	229	if (unlikely(!wdt))
9ea64046 PM	230	return -ENOMEM;
1da177e4	231
8f5585ec PM	232	wdt->dev = &pdev->dev;
8f5585ec PM	233
2f7b9b48	234	wdt->clk = devm_clk_get(&pdev->dev, NULL);
9ea64046 PM	235	if (IS_ERR(wdt->clk)) {
	236	/*
	237	* Clock framework support is optional, continue on
	238	* anyways if we don't find a matching clock.
	239	*/
	240	wdt->clk = NULL;
	241	}
f9fb360c	242
0f0a6a28	243	wdt->base = devm_platform_ioremap_resource(pdev, 0);
2f7b9b48 JH	244	if (IS_ERR(wdt->base))
2f7b9b48 JH	245	return PTR_ERR(wdt->base);
1da177e4	246
9ea64046 PM	247	watchdog_set_nowayout(&sh_wdt_dev, nowayout);
9ea64046 PM	248	watchdog_set_drvdata(&sh_wdt_dev, wdt);
6551881c	249	sh_wdt_dev.parent = &pdev->dev;
9ea64046	250
f9fb360c PM	251	spin_lock_init(&wdt->lock);
f9fb360c PM	252
1950f499 PM	253	rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
	254	if (unlikely(rc)) {
	255	/* Default timeout if invalid */
	256	sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);
	257
	258	dev_warn(&pdev->dev,
	259	"heartbeat value must be 1<=x<=3600, using %d\n",
	260	sh_wdt_dev.timeout);
	261	}
	262
	263	dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
	264	sh_wdt_dev.timeout, nowayout);
8f5585ec	265
1950f499	266	rc = watchdog_register_device(&sh_wdt_dev);
e4c2cfee	267	if (unlikely(rc)) {
1950f499	268	dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
2f7b9b48	269	return rc;
1da177e4 LT	270	}
1da177e4 LT	271
e99e88a9	272	timer_setup(&wdt->timer, sh_wdt_ping, 0);
8f5585ec PM	273	wdt->timer.expires = next_ping_period(clock_division_ratio);
8f5585ec PM	274
8f5585ec	275	dev_info(&pdev->dev, "initialized.\n");
1da177e4	276
8c013d96 PM	277	pm_runtime_enable(&pdev->dev);
8c013d96 PM	278
1da177e4 LT	279	return 0;
	280	}
	281
4b12b896	282	static int sh_wdt_remove(struct platform_device *pdev)
1da177e4	283	{
1950f499	284	watchdog_unregister_device(&sh_wdt_dev);
8f5585ec	285
8c013d96	286	pm_runtime_disable(&pdev->dev);
8f5585ec PM	287
	288	return 0;
	289	}
	290
40968126 PM	291	static void sh_wdt_shutdown(struct platform_device *pdev)
40968126 PM	292	{
1950f499	293	sh_wdt_stop(&sh_wdt_dev);
40968126 PM	294	}
40968126 PM	295
8f5585ec PM	296	static struct platform_driver sh_wdt_driver = {
	297	.driver = {
	298	.name = DRV_NAME,
8f5585ec PM	299	},
8f5585ec PM	300
40968126	301	.probe = sh_wdt_probe,
82268714	302	.remove = sh_wdt_remove,
40968126	303	.shutdown = sh_wdt_shutdown,
8f5585ec PM	304	};
	305
	306	static int __init sh_wdt_init(void)
	307	{
8f5585ec PM	308	if (unlikely(clock_division_ratio < 0x5 \|\|
	309	clock_division_ratio > 0x7)) {
	310	clock_division_ratio = WTCSR_CKS_4096;
	311
27c766aa JP	312	pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
27c766aa JP	313	clock_division_ratio);
8f5585ec PM	314	}
8f5585ec PM	315
8f5585ec	316	return platform_driver_register(&sh_wdt_driver);
1da177e4 LT	317	}
1da177e4 LT	318
8f5585ec PM	319	static void __exit sh_wdt_exit(void)
	320	{
	321	platform_driver_unregister(&sh_wdt_driver);
	322	}
	323	module_init(sh_wdt_init);
	324	module_exit(sh_wdt_exit);
	325
1da177e4 LT	326	MODULE_AUTHOR("Paul Mundt <[email protected]>");
	327	MODULE_DESCRIPTION("SuperH watchdog driver");
	328	MODULE_LICENSE("GPL");
8f5585ec	329	MODULE_ALIAS("platform:" DRV_NAME);
1da177e4 LT	330
1da177e4 LT	331	module_param(clock_division_ratio, int, 0);
a77dba7e WVS	332	MODULE_PARM_DESC(clock_division_ratio,
a77dba7e WVS	333	"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
76550d32	334	"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");
1da177e4 LT	335
1da177e4 LT	336	module_param(heartbeat, int, 0);
70b814ec AC	337	MODULE_PARM_DESC(heartbeat,
	338	"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
	339	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
1da177e4	340
86a1e189	341	module_param(nowayout, bool, 0);
70b814ec AC	342	MODULE_PARM_DESC(nowayout,
	343	"Watchdog cannot be stopped once started (default="
	344	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");