[linux.git] / drivers / watchdog / shwdt.c

/*
 * drivers/watchdog/shwdt.c
 *
 * Watchdog driver for integrated watchdog in the SuperH processors.
 *
 * Copyright (C) 2001 - 2012  Paul Mundt <[email protected]>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * 14-Dec-2001 Matt Domsch <[email protected]>
 *     Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
 *
 * 19-Apr-2002 Rob Radez <[email protected]>
 *     Added expect close support, made emulated timeout runtime changeable
 *     general cleanups, add some ioctls
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/watchdog.h>
#include <linux/pm_runtime.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <asm/watchdog.h>

#define DRV_NAME "sh-wdt"

/*
 * Default clock division ratio is 5.25 msecs. For an additional table of
 * values, consult the asm-sh/watchdog.h. Overload this at module load
 * time.
 *
 * In order for this to work reliably we need to have HZ set to 1000 or
 * something quite higher than 100 (or we need a proper high-res timer
 * implementation that will deal with this properly), otherwise the 10ms
 * resolution of a jiffy is enough to trigger the overflow. For things like
 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
 * necssary.
 *
 * As a result of this timing problem, the only modes that are particularly
 * feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
 * overflow periods respectively.
 *
 * Also, since we can't really expect userspace to be responsive enough
 * before the overflow happens, we maintain two separate timers .. One in
 * the kernel for clearing out WOVF every 2ms or so (again, this depends on
 * HZ == 1000), and another for monitoring userspace writes to the WDT device.
 *
 * As such, we currently use a configurable heartbeat interval which defaults
 * to 30s. In this case, the userspace daemon is only responsible for periodic
 * writes to the device before the next heartbeat is scheduled. If the daemon
 * misses its deadline, the kernel timer will allow the WDT to overflow.
 */
static int clock_division_ratio = WTCSR_CKS_4096;
#define next_ping_period(cks)	(jiffies + msecs_to_jiffies(cks - 4))

#define WATCHDOG_HEARTBEAT 30			/* 30 sec default heartbeat */
static int heartbeat = WATCHDOG_HEARTBEAT;	/* in seconds */
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned long next_heartbeat;

struct sh_wdt {
	void __iomem		*base;
	struct device		*dev;
	struct clk		*clk;
	spinlock_t		lock;

	struct timer_list	timer;
};

static int sh_wdt_start(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;
	u8 csr;

	pm_runtime_get_sync(wdt->dev);
	clk_enable(wdt->clk);

	spin_lock_irqsave(&wdt->lock, flags);

	next_heartbeat = jiffies + (heartbeat * HZ);
	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));

	csr = sh_wdt_read_csr();
	csr |= WTCSR_WT | clock_division_ratio;
	sh_wdt_write_csr(csr);

	sh_wdt_write_cnt(0);

	/*
	 * These processors have a bit of an inconsistent initialization
	 * process.. starting with SH-3, RSTS was moved to WTCSR, and the
	 * RSTCSR register was removed.
	 *
	 * On the SH-2 however, in addition with bits being in different
	 * locations, we must deal with RSTCSR outright..
	 */
	csr = sh_wdt_read_csr();
	csr |= WTCSR_TME;
	csr &= ~WTCSR_RSTS;
	sh_wdt_write_csr(csr);

#ifdef CONFIG_CPU_SH2
	csr = sh_wdt_read_rstcsr();
	csr &= ~RSTCSR_RSTS;
	sh_wdt_write_rstcsr(csr);
#endif
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static int sh_wdt_stop(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;
	u8 csr;

	spin_lock_irqsave(&wdt->lock, flags);

	del_timer(&wdt->timer);

	csr = sh_wdt_read_csr();
	csr &= ~WTCSR_TME;
	sh_wdt_write_csr(csr);

	spin_unlock_irqrestore(&wdt->lock, flags);

	clk_disable(wdt->clk);
	pm_runtime_put_sync(wdt->dev);

	return 0;
}

static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;

	spin_lock_irqsave(&wdt->lock, flags);
	next_heartbeat = jiffies + (heartbeat * HZ);
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;

	if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */
		return -EINVAL;

	spin_lock_irqsave(&wdt->lock, flags);
	heartbeat = t;
	wdt_dev->timeout = t;
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static void sh_wdt_ping(unsigned long data)
{
	struct sh_wdt *wdt = (struct sh_wdt *)data;
	unsigned long flags;

	spin_lock_irqsave(&wdt->lock, flags);
	if (time_before(jiffies, next_heartbeat)) {
		u8 csr;

		csr = sh_wdt_read_csr();
		csr &= ~WTCSR_IOVF;
		sh_wdt_write_csr(csr);

		sh_wdt_write_cnt(0);

		mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
	} else
		dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
		         "the watchdog\n");
	spin_unlock_irqrestore(&wdt->lock, flags);
}

static const struct watchdog_info sh_wdt_info = {
	.options		= WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
				  WDIOF_MAGICCLOSE,
	.firmware_version	= 1,
	.identity		= "SH WDT",
};

static const struct watchdog_ops sh_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= sh_wdt_start,
	.stop		= sh_wdt_stop,
	.ping		= sh_wdt_keepalive,
	.set_timeout	= sh_wdt_set_heartbeat,
};

static struct watchdog_device sh_wdt_dev = {
	.info	= &sh_wdt_info,
	.ops	= &sh_wdt_ops,
};

static int sh_wdt_probe(struct platform_device *pdev)
{
	struct sh_wdt *wdt;
	struct resource *res;
	int rc;

	/*
	 * As this driver only covers the global watchdog case, reject
	 * any attempts to register per-CPU watchdogs.
	 */
	if (pdev->id != -1)
		return -EINVAL;

	wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
	if (unlikely(!wdt))
		return -ENOMEM;

	wdt->dev = &pdev->dev;

	wdt->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdt->clk)) {
		/*
		 * Clock framework support is optional, continue on
		 * anyways if we don't find a matching clock.
		 */
		wdt->clk = NULL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdt->base = devm_ioremap_resource(wdt->dev, res);
	if (IS_ERR(wdt->base))
		return PTR_ERR(wdt->base);

	watchdog_set_nowayout(&sh_wdt_dev, nowayout);
	watchdog_set_drvdata(&sh_wdt_dev, wdt);
	sh_wdt_dev.parent = &pdev->dev;

	spin_lock_init(&wdt->lock);

	rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
	if (unlikely(rc)) {
		/* Default timeout if invalid */
		sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);

		dev_warn(&pdev->dev,
			 "heartbeat value must be 1<=x<=3600, using %d\n",
			 sh_wdt_dev.timeout);
	}

	dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
		 sh_wdt_dev.timeout, nowayout);

	rc = watchdog_register_device(&sh_wdt_dev);
	if (unlikely(rc)) {
		dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
		return rc;
	}

	setup_timer(&wdt->timer, sh_wdt_ping, (unsigned long)wdt);
	wdt->timer.expires	= next_ping_period(clock_division_ratio);

	dev_info(&pdev->dev, "initialized.\n");

	pm_runtime_enable(&pdev->dev);

	return 0;
}

static int sh_wdt_remove(struct platform_device *pdev)
{
	watchdog_unregister_device(&sh_wdt_dev);

	pm_runtime_disable(&pdev->dev);

	return 0;
}

static void sh_wdt_shutdown(struct platform_device *pdev)
{
	sh_wdt_stop(&sh_wdt_dev);
}

static struct platform_driver sh_wdt_driver = {
	.driver		= {
		.name	= DRV_NAME,
	},

	.probe		= sh_wdt_probe,
	.remove		= sh_wdt_remove,
	.shutdown	= sh_wdt_shutdown,
};

static int __init sh_wdt_init(void)
{
	if (unlikely(clock_division_ratio < 0x5 ||
		     clock_division_ratio > 0x7)) {
		clock_division_ratio = WTCSR_CKS_4096;

		pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
			clock_division_ratio);
	}

	return platform_driver_register(&sh_wdt_driver);
}

static void __exit sh_wdt_exit(void)
{
	platform_driver_unregister(&sh_wdt_driver);
}
module_init(sh_wdt_init);
module_exit(sh_wdt_exit);

MODULE_AUTHOR("Paul Mundt <[email protected]>");
MODULE_DESCRIPTION("SuperH watchdog driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);

module_param(clock_division_ratio, int, 0);
MODULE_PARM_DESC(clock_division_ratio,
	"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
	"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
	"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
				__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
Commit	Line	Data
1da177e4	1	/*
b1fa888e	2	* drivers/watchdog/shwdt.c
1da177e4 LT	3	*
	4	* Watchdog driver for integrated watchdog in the SuperH processors.
	5	*
40968126	6	* Copyright (C) 2001 - 2012 Paul Mundt <[email protected]>
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* 14-Dec-2001 Matt Domsch <[email protected]>
	14	* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
	15	*
	16	* 19-Apr-2002 Rob Radez <[email protected]>
	17	* Added expect close support, made emulated timeout runtime changeable
	18	* general cleanups, add some ioctls
	19	*/
27c766aa JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
1da177e4 LT	23	#include <linux/module.h>
1da177e4 LT	24	#include <linux/moduleparam.h>
8f5585ec	25	#include <linux/platform_device.h>
1da177e4 LT	26	#include <linux/init.h>
1da177e4 LT	27	#include <linux/types.h>
f9fb360c	28	#include <linux/spinlock.h>
1da177e4	29	#include <linux/watchdog.h>
8c013d96	30	#include <linux/pm_runtime.h>
1da177e4	31	#include <linux/fs.h>
f118420b	32	#include <linux/mm.h>
8f5585ec	33	#include <linux/slab.h>
70b814ec	34	#include <linux/io.h>
9ea64046	35	#include <linux/clk.h>
6330c707	36	#include <linux/err.h>
58cf4198	37	#include <asm/watchdog.h>
1da177e4	38
8f5585ec	39	#define DRV_NAME "sh-wdt"
1da177e4 LT	40
	41	/*
	42	* Default clock division ratio is 5.25 msecs. For an additional table of
	43	* values, consult the asm-sh/watchdog.h. Overload this at module load
	44	* time.
	45	*
	46	* In order for this to work reliably we need to have HZ set to 1000 or
	47	* something quite higher than 100 (or we need a proper high-res timer
	48	* implementation that will deal with this properly), otherwise the 10ms
	49	* resolution of a jiffy is enough to trigger the overflow. For things like
	50	* the SH-4 and SH-5, this isn't necessarily that big of a problem, though
	51	* for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
	52	* necssary.
	53	*
	54	* As a result of this timing problem, the only modes that are particularly
25985edc	55	* feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
1da177e4 LT	56	* overflow periods respectively.
	57	*
	58	* Also, since we can't really expect userspace to be responsive enough
ee0fc097	59	* before the overflow happens, we maintain two separate timers .. One in
1da177e4 LT	60	* the kernel for clearing out WOVF every 2ms or so (again, this depends on
	61	* HZ == 1000), and another for monitoring userspace writes to the WDT device.
	62	*
	63	* As such, we currently use a configurable heartbeat interval which defaults
	64	* to 30s. In this case, the userspace daemon is only responsible for periodic
	65	* writes to the device before the next heartbeat is scheduled. If the daemon
	66	* misses its deadline, the kernel timer will allow the WDT to overflow.
	67	*/
	68	static int clock_division_ratio = WTCSR_CKS_4096;
bea19066	69	#define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4))
1da177e4	70
1da177e4 LT	71	#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
1da177e4 LT	72	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
86a1e189	73	static bool nowayout = WATCHDOG_NOWAYOUT;
8f5585ec PM	74	static unsigned long next_heartbeat;
	75
	76	struct sh_wdt {
	77	void __iomem *base;
	78	struct device *dev;
9ea64046	79	struct clk *clk;
f9fb360c	80	spinlock_t lock;
1da177e4	81
8f5585ec	82	struct timer_list timer;
8f5585ec PM	83	};
8f5585ec PM	84
1950f499	85	static int sh_wdt_start(struct watchdog_device *wdt_dev)
1da177e4	86	{
1950f499	87	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec	88	unsigned long flags;
8f5585ec	89	u8 csr;
70b814ec	90
8c013d96	91	pm_runtime_get_sync(wdt->dev);
d42c9744	92	clk_enable(wdt->clk);
8c013d96	93
f9fb360c	94	spin_lock_irqsave(&wdt->lock, flags);
1da177e4 LT	95
1da177e4 LT	96	next_heartbeat = jiffies + (heartbeat * HZ);
8f5585ec	97	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
1da177e4 LT	98
	99	csr = sh_wdt_read_csr();
	100	csr \|= WTCSR_WT \| clock_division_ratio;
	101	sh_wdt_write_csr(csr);
	102
	103	sh_wdt_write_cnt(0);
	104
	105	/*
	106	* These processors have a bit of an inconsistent initialization
	107	* process.. starting with SH-3, RSTS was moved to WTCSR, and the
	108	* RSTCSR register was removed.
	109	*
	110	* On the SH-2 however, in addition with bits being in different
	111	* locations, we must deal with RSTCSR outright..
	112	*/
	113	csr = sh_wdt_read_csr();
	114	csr \|= WTCSR_TME;
	115	csr &= ~WTCSR_RSTS;
	116	sh_wdt_write_csr(csr);
	117
	118	#ifdef CONFIG_CPU_SH2
1da177e4 LT	119	csr = sh_wdt_read_rstcsr();
	120	csr &= ~RSTCSR_RSTS;
	121	sh_wdt_write_rstcsr(csr);
	122	#endif
f9fb360c	123	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499 PM	124
1950f499 PM	125	return 0;
1da177e4 LT	126	}
1da177e4 LT	127
1950f499	128	static int sh_wdt_stop(struct watchdog_device *wdt_dev)
1da177e4	129	{
1950f499	130	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec	131	unsigned long flags;
8f5585ec	132	u8 csr;
70b814ec	133
f9fb360c	134	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	135
8f5585ec	136	del_timer(&wdt->timer);
1da177e4 LT	137
	138	csr = sh_wdt_read_csr();
	139	csr &= ~WTCSR_TME;
	140	sh_wdt_write_csr(csr);
8f5585ec	141
f9fb360c	142	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499	143
d42c9744	144	clk_disable(wdt->clk);
8c013d96 PM	145	pm_runtime_put_sync(wdt->dev);
8c013d96 PM	146
1950f499	147	return 0;
1da177e4 LT	148	}
1da177e4 LT	149
1950f499	150	static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
1da177e4	151	{
f9fb360c	152	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec AC	153	unsigned long flags;
70b814ec AC	154
f9fb360c	155	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	156	next_heartbeat = jiffies + (heartbeat * HZ);
f9fb360c	157	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499 PM	158
1950f499 PM	159	return 0;
1da177e4 LT	160	}
1da177e4 LT	161
1950f499	162	static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
1da177e4	163	{
f9fb360c	164	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec AC	165	unsigned long flags;
	166
	167	if (unlikely(t < 1 \|\| t > 3600)) /* arbitrary upper limit */
1da177e4 LT	168	return -EINVAL;
1da177e4 LT	169
f9fb360c	170	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	171	heartbeat = t;
1950f499	172	wdt_dev->timeout = t;
f9fb360c	173	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499	174
1da177e4 LT	175	return 0;
	176	}
	177
1da177e4 LT	178	static void sh_wdt_ping(unsigned long data)
1da177e4 LT	179	{
8f5585ec	180	struct sh_wdt wdt = (struct sh_wdt )data;
70b814ec AC	181	unsigned long flags;
70b814ec AC	182
f9fb360c	183	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	184	if (time_before(jiffies, next_heartbeat)) {
8f5585ec	185	u8 csr;
1da177e4 LT	186
	187	csr = sh_wdt_read_csr();
	188	csr &= ~WTCSR_IOVF;
	189	sh_wdt_write_csr(csr);
	190
	191	sh_wdt_write_cnt(0);
	192
8f5585ec	193	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
e4c2cfee	194	} else
8f5585ec PM	195	dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
8f5585ec PM	196	"the watchdog\n");
f9fb360c	197	spin_unlock_irqrestore(&wdt->lock, flags);
1da177e4 LT	198	}
1da177e4 LT	199
70b814ec	200	static const struct watchdog_info sh_wdt_info = {
e4c2cfee PM	201	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \|
e4c2cfee PM	202	WDIOF_MAGICCLOSE,
1da177e4 LT	203	.firmware_version = 1,
	204	.identity = "SH WDT",
	205	};
	206
1950f499 PM	207	static const struct watchdog_ops sh_wdt_ops = {
	208	.owner = THIS_MODULE,
	209	.start = sh_wdt_start,
	210	.stop = sh_wdt_stop,
	211	.ping = sh_wdt_keepalive,
	212	.set_timeout = sh_wdt_set_heartbeat,
	213	};
	214
	215	static struct watchdog_device sh_wdt_dev = {
	216	.info = &sh_wdt_info,
	217	.ops = &sh_wdt_ops,
1da177e4 LT	218	};
1da177e4 LT	219
2d991a16	220	static int sh_wdt_probe(struct platform_device *pdev)
1da177e4	221	{
8f5585ec PM	222	struct sh_wdt *wdt;
8f5585ec PM	223	struct resource *res;
1da177e4 LT	224	int rc;
1da177e4 LT	225
8f5585ec PM	226	/*
	227	* As this driver only covers the global watchdog case, reject
	228	* any attempts to register per-CPU watchdogs.
	229	*/
	230	if (pdev->id != -1)
	231	return -EINVAL;
	232
8f5585ec	233	wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
9ea64046 PM	234	if (unlikely(!wdt))
9ea64046 PM	235	return -ENOMEM;
1da177e4	236
8f5585ec PM	237	wdt->dev = &pdev->dev;
8f5585ec PM	238
2f7b9b48	239	wdt->clk = devm_clk_get(&pdev->dev, NULL);
9ea64046 PM	240	if (IS_ERR(wdt->clk)) {
	241	/*
	242	* Clock framework support is optional, continue on
	243	* anyways if we don't find a matching clock.
	244	*/
	245	wdt->clk = NULL;
	246	}
f9fb360c	247
2cdf25bb	248	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6330c707	249	wdt->base = devm_ioremap_resource(wdt->dev, res);
2f7b9b48 JH	250	if (IS_ERR(wdt->base))
2f7b9b48 JH	251	return PTR_ERR(wdt->base);
1da177e4	252
9ea64046 PM	253	watchdog_set_nowayout(&sh_wdt_dev, nowayout);
9ea64046 PM	254	watchdog_set_drvdata(&sh_wdt_dev, wdt);
6551881c	255	sh_wdt_dev.parent = &pdev->dev;
9ea64046	256
f9fb360c PM	257	spin_lock_init(&wdt->lock);
f9fb360c PM	258
1950f499 PM	259	rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
	260	if (unlikely(rc)) {
	261	/* Default timeout if invalid */
	262	sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);
	263
	264	dev_warn(&pdev->dev,
	265	"heartbeat value must be 1<=x<=3600, using %d\n",
	266	sh_wdt_dev.timeout);
	267	}
	268
	269	dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
	270	sh_wdt_dev.timeout, nowayout);
8f5585ec	271
1950f499	272	rc = watchdog_register_device(&sh_wdt_dev);
e4c2cfee	273	if (unlikely(rc)) {
1950f499	274	dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
2f7b9b48	275	return rc;
1da177e4 LT	276	}
1da177e4 LT	277
12fe36e2	278	setup_timer(&wdt->timer, sh_wdt_ping, (unsigned long)wdt);
8f5585ec PM	279	wdt->timer.expires = next_ping_period(clock_division_ratio);
8f5585ec PM	280
8f5585ec	281	dev_info(&pdev->dev, "initialized.\n");
1da177e4	282
8c013d96 PM	283	pm_runtime_enable(&pdev->dev);
8c013d96 PM	284
1da177e4 LT	285	return 0;
	286	}
	287
4b12b896	288	static int sh_wdt_remove(struct platform_device *pdev)
1da177e4	289	{
1950f499	290	watchdog_unregister_device(&sh_wdt_dev);
8f5585ec	291
8c013d96	292	pm_runtime_disable(&pdev->dev);
8f5585ec PM	293
	294	return 0;
	295	}
	296
40968126 PM	297	static void sh_wdt_shutdown(struct platform_device *pdev)
40968126 PM	298	{
1950f499	299	sh_wdt_stop(&sh_wdt_dev);
40968126 PM	300	}
40968126 PM	301
8f5585ec PM	302	static struct platform_driver sh_wdt_driver = {
	303	.driver = {
	304	.name = DRV_NAME,
8f5585ec PM	305	},
8f5585ec PM	306
40968126	307	.probe = sh_wdt_probe,
82268714	308	.remove = sh_wdt_remove,
40968126	309	.shutdown = sh_wdt_shutdown,
8f5585ec PM	310	};
	311
	312	static int __init sh_wdt_init(void)
	313	{
8f5585ec PM	314	if (unlikely(clock_division_ratio < 0x5 \|\|
	315	clock_division_ratio > 0x7)) {
	316	clock_division_ratio = WTCSR_CKS_4096;
	317
27c766aa JP	318	pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
27c766aa JP	319	clock_division_ratio);
8f5585ec PM	320	}
8f5585ec PM	321
8f5585ec	322	return platform_driver_register(&sh_wdt_driver);
1da177e4 LT	323	}
1da177e4 LT	324
8f5585ec PM	325	static void __exit sh_wdt_exit(void)
	326	{
	327	platform_driver_unregister(&sh_wdt_driver);
	328	}
	329	module_init(sh_wdt_init);
	330	module_exit(sh_wdt_exit);
	331
1da177e4 LT	332	MODULE_AUTHOR("Paul Mundt <[email protected]>");
	333	MODULE_DESCRIPTION("SuperH watchdog driver");
	334	MODULE_LICENSE("GPL");
8f5585ec	335	MODULE_ALIAS("platform:" DRV_NAME);
1da177e4 LT	336
1da177e4 LT	337	module_param(clock_division_ratio, int, 0);
a77dba7e WVS	338	MODULE_PARM_DESC(clock_division_ratio,
a77dba7e WVS	339	"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
76550d32	340	"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");
1da177e4 LT	341
1da177e4 LT	342	module_param(heartbeat, int, 0);
70b814ec AC	343	MODULE_PARM_DESC(heartbeat,
	344	"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
	345	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
1da177e4	346
86a1e189	347	module_param(nowayout, bool, 0);
70b814ec AC	348	MODULE_PARM_DESC(nowayout,
	349	"Watchdog cannot be stopped once started (default="
	350	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");