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[SERIAL] Add support for more Connect Tech PCI serial boards
[linux.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/sched.h>
20#include <linux/string.h>
21#include <linux/kernel.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24#include <linux/tty.h>
25#include <linux/serial_core.h>
26#include <linux/8250_pci.h>
27#include <linux/bitops.h>
28
29#include <asm/byteorder.h>
30#include <asm/io.h>
31
32#include "8250.h"
33
34#undef SERIAL_DEBUG_PCI
35
1da177e4
LT		 36/*
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
40 * < 0 - error
41 */
42struct pci_serial_quirk {
43 u32 vendor;
44 u32 device;
45 u32 subvendor;
46 u32 subdevice;
47 int (*init)(struct pci_dev *dev);
70db3d91 48 int (*setup)(struct serial_private *, struct pciserial_board *,
05caac58 49 struct uart_port *, int);
1da177e4
LT		 50 void (*exit)(struct pci_dev *dev);
51};
52
53#define PCI_NUM_BAR_RESOURCES 6
54
55struct serial_private {
70db3d91 56 struct pci_dev *dev;
1da177e4
LT		 57 unsigned int nr;
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
60 int line[0];
61};
62
63static void moan_device(const char *str, struct pci_dev *dev)
64{
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to [email protected].\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72}
73
74static int
70db3d91 75setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 76 int bar, int offset, int regshift)
77{
70db3d91 78 struct pci_dev *dev = priv->dev;
1da177e4
LT		 79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
72ce9a83
RK		 84 base = pci_resource_start(dev, bar);
85
1da177e4 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
94 port->iotype = UPIO_MEM;
72ce9a83 95 port->iobase = 0;
1da177e4
LT		 96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
99 } else {
1da177e4 100 port->iotype = UPIO_PORT;
72ce9a83
RK		 101 port->iobase = base + offset;
102 port->mapbase = 0;
103 port->membase = NULL;
104 port->regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
109/*
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
112 */
113static int
70db3d91 114afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 115 struct uart_port *port, int idx)
116{
117 unsigned int bar, offset = board->first_offset;
118
119 bar = FL_GET_BASE(board->flags);
120 if (idx < 4)
121 bar += idx;
122 else {
123 bar = 4;
124 offset += (idx - 4) * board->uart_offset;
125 }
126
70db3d91 127 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 128}
129
130/*
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
136 */
137static int __devinit pci_hp_diva_init(struct pci_dev *dev)
138{
139 int rc = 0;
140
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
146 rc = 3;
147 break;
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
149 rc = 2;
150 break;
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
152 rc = 4;
153 break;
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 155 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 156 rc = 1;
157 break;
158 }
159
160 return rc;
161}
162
163/*
164 * HP's Diva chip puts the 4th/5th serial port further out, and
165 * some serial ports are supposed to be hidden on certain models.
166 */
167static int
70db3d91 168pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 169 struct uart_port *port, int idx)
170{
171 unsigned int offset = board->first_offset;
172 unsigned int bar = FL_GET_BASE(board->flags);
173
70db3d91 174 switch (priv->dev->subsystem_device) {
1da177e4
LT		 175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 if (idx == 3)
177 idx++;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
180 if (idx > 0)
181 idx++;
182 if (idx > 2)
183 idx++;
184 break;
185 }
186 if (idx > 2)
187 offset = 0x18;
188
189 offset += idx * board->uart_offset;
190
70db3d91 191 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 192}
193
194/*
195 * Added for EKF Intel i960 serial boards
196 */
197static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
198{
199 unsigned long oldval;
200
201 if (!(dev->subsystem_device & 0x1000))
202 return -ENODEV;
203
204 /* is firmware started? */
205 pci_read_config_dword(dev, 0x44, (void*) &oldval);
206 if (oldval == 0x00001000L) { /* RESET value */
207 printk(KERN_DEBUG "Local i960 firmware missing");
208 return -ENODEV;
209 }
210 return 0;
211}
212
213/*
214 * Some PCI serial cards using the PLX 9050 PCI interface chip require
215 * that the card interrupt be explicitly enabled or disabled. This
216 * seems to be mainly needed on card using the PLX which also use I/O
217 * mapped memory.
218 */
219static int __devinit pci_plx9050_init(struct pci_dev *dev)
220{
221 u8 irq_config;
222 void __iomem *p;
223
224 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
225 moan_device("no memory in bar 0", dev);
226 return 0;
227 }
228
229 irq_config = 0x41;
add7b58e
BH		 230 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
231 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
1da177e4 232 irq_config = 0x43;
add7b58e 233 }
1da177e4
LT		 234 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
235 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
236 /*
237 * As the megawolf cards have the int pins active
238 * high, and have 2 UART chips, both ints must be
239 * enabled on the 9050. Also, the UARTS are set in
240 * 16450 mode by default, so we have to enable the
241 * 16C950 'enhanced' mode so that we can use the
242 * deep FIFOs
243 */
244 irq_config = 0x5b;
245 }
246
247 /*
248 * enable/disable interrupts
249 */
250 p = ioremap(pci_resource_start(dev, 0), 0x80);
251 if (p == NULL)
252 return -ENOMEM;
253 writel(irq_config, p + 0x4c);
254
255 /*
256 * Read the register back to ensure that it took effect.
257 */
258 readl(p + 0x4c);
259 iounmap(p);
260
261 return 0;
262}
263
264static void __devexit pci_plx9050_exit(struct pci_dev *dev)
265{
266 u8 __iomem *p;
267
268 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
269 return;
270
271 /*
272 * disable interrupts
273 */
274 p = ioremap(pci_resource_start(dev, 0), 0x80);
275 if (p != NULL) {
276 writel(0, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283 }
284}
285
286/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
287static int
70db3d91 288sbs_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 289 struct uart_port *port, int idx)
290{
291 unsigned int bar, offset = board->first_offset;
292
293 bar = 0;
294
295 if (idx < 4) {
296 /* first four channels map to 0, 0x100, 0x200, 0x300 */
297 offset += idx * board->uart_offset;
298 } else if (idx < 8) {
299 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
300 offset += idx * board->uart_offset + 0xC00;
301 } else /* we have only 8 ports on PMC-OCTALPRO */
302 return 1;
303
70db3d91 304 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 305}
306
307/*
308* This does initialization for PMC OCTALPRO cards:
309* maps the device memory, resets the UARTs (needed, bc
310* if the module is removed and inserted again, the card
311* is in the sleep mode) and enables global interrupt.
312*/
313
314/* global control register offset for SBS PMC-OctalPro */
315#define OCT_REG_CR_OFF 0x500
316
317static int __devinit sbs_init(struct pci_dev *dev)
318{
319 u8 __iomem *p;
320
321 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
322
323 if (p == NULL)
324 return -ENOMEM;
325 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
326 writeb(0x10,p + OCT_REG_CR_OFF);
327 udelay(50);
328 writeb(0x0,p + OCT_REG_CR_OFF);
329
330 /* Set bit-2 (INTENABLE) of Control Register */
331 writeb(0x4, p + OCT_REG_CR_OFF);
332 iounmap(p);
333
334 return 0;
335}
336
337/*
338 * Disables the global interrupt of PMC-OctalPro
339 */
340
341static void __devexit sbs_exit(struct pci_dev *dev)
342{
343 u8 __iomem *p;
344
345 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
346 if (p != NULL) {
347 writeb(0, p + OCT_REG_CR_OFF);
348 }
349 iounmap(p);
350}
351
352/*
353 * SIIG serial cards have an PCI interface chip which also controls
354 * the UART clocking frequency. Each UART can be clocked independently
355 * (except cards equiped with 4 UARTs) and initial clocking settings
356 * are stored in the EEPROM chip. It can cause problems because this
357 * version of serial driver doesn't support differently clocked UART's
358 * on single PCI card. To prevent this, initialization functions set
359 * high frequency clocking for all UART's on given card. It is safe (I
360 * hope) because it doesn't touch EEPROM settings to prevent conflicts
361 * with other OSes (like M$ DOS).
362 *
363 * SIIG support added by Andrey Panin <[email protected]>, 10/1999
364 *
365 * There is two family of SIIG serial cards with different PCI
366 * interface chip and different configuration methods:
367 * - 10x cards have control registers in IO and/or memory space;
368 * - 20x cards have control registers in standard PCI configuration space.
369 *
67d74b87
RK		 370 * Note: all 10x cards have PCI device ids 0x10..
371 * all 20x cards have PCI device ids 0x20..
372 *
fbc0dc0d
AP		 373 * There are also Quartet Serial cards which use Oxford Semiconductor
374 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
375 *
1da177e4
LT		 376 * Note: some SIIG cards are probed by the parport_serial object.
377 */
378
379#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
380#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
381
382static int pci_siig10x_init(struct pci_dev *dev)
383{
384 u16 data;
385 void __iomem *p;
386
387 switch (dev->device & 0xfff8) {
388 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
389 data = 0xffdf;
390 break;
391 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
392 data = 0xf7ff;
393 break;
394 default: /* 1S1P, 4S */
395 data = 0xfffb;
396 break;
397 }
398
399 p = ioremap(pci_resource_start(dev, 0), 0x80);
400 if (p == NULL)
401 return -ENOMEM;
402
403 writew(readw(p + 0x28) & data, p + 0x28);
404 readw(p + 0x28);
405 iounmap(p);
406 return 0;
407}
408
409#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
410#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
411
412static int pci_siig20x_init(struct pci_dev *dev)
413{
414 u8 data;
415
416 /* Change clock frequency for the first UART. */
417 pci_read_config_byte(dev, 0x6f, &data);
418 pci_write_config_byte(dev, 0x6f, data & 0xef);
419
420 /* If this card has 2 UART, we have to do the same with second UART. */
421 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
422 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
423 pci_read_config_byte(dev, 0x73, &data);
424 pci_write_config_byte(dev, 0x73, data & 0xef);
425 }
426 return 0;
427}
428
67d74b87
RK		 429static int pci_siig_init(struct pci_dev *dev)
430{
431 unsigned int type = dev->device & 0xff00;
432
433 if (type == 0x1000)
434 return pci_siig10x_init(dev);
435 else if (type == 0x2000)
436 return pci_siig20x_init(dev);
437
438 moan_device("Unknown SIIG card", dev);
439 return -ENODEV;
440}
441
1da177e4
LT		 442/*
443 * Timedia has an explosion of boards, and to avoid the PCI table from
444 * growing *huge*, we use this function to collapse some 70 entries
445 * in the PCI table into one, for sanity's and compactness's sake.
446 */
447static unsigned short timedia_single_port[] = {
448 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
449};
450
451static unsigned short timedia_dual_port[] = {
452 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
453 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
454 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
455 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
456 0xD079, 0
457};
458
459static unsigned short timedia_quad_port[] = {
460 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
461 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
462 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
463 0xB157, 0
464};
465
466static unsigned short timedia_eight_port[] = {
467 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
468 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
469};
470
cb3592be 471static const struct timedia_struct {
1da177e4
LT		 472 int num;
473 unsigned short *ids;
474} timedia_data[] = {
475 { 1, timedia_single_port },
476 { 2, timedia_dual_port },
477 { 4, timedia_quad_port },
478 { 8, timedia_eight_port },
479 { 0, NULL }
480};
481
482static int __devinit pci_timedia_init(struct pci_dev *dev)
483{
484 unsigned short *ids;
485 int i, j;
486
487 for (i = 0; timedia_data[i].num; i++) {
488 ids = timedia_data[i].ids;
489 for (j = 0; ids[j]; j++)
490 if (dev->subsystem_device == ids[j])
491 return timedia_data[i].num;
492 }
493 return 0;
494}
495
496/*
497 * Timedia/SUNIX uses a mixture of BARs and offsets
498 * Ugh, this is ugly as all hell --- TYT
499 */
500static int
70db3d91 501pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 502 struct uart_port *port, int idx)
503{
504 unsigned int bar = 0, offset = board->first_offset;
505
506 switch (idx) {
507 case 0:
508 bar = 0;
509 break;
510 case 1:
511 offset = board->uart_offset;
512 bar = 0;
513 break;
514 case 2:
515 bar = 1;
516 break;
517 case 3:
518 offset = board->uart_offset;
c2cd6d3c 519 /* FALLTHROUGH */
1da177e4
LT		 520 case 4: /* BAR 2 */
521 case 5: /* BAR 3 */
522 case 6: /* BAR 4 */
523 case 7: /* BAR 5 */
524 bar = idx - 2;
525 }
526
70db3d91 527 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 528}
529
530/*
531 * Some Titan cards are also a little weird
532 */
533static int
70db3d91 534titan_400l_800l_setup(struct serial_private *priv,
1c7c1fe5 535 struct pciserial_board *board,
1da177e4
LT		 536 struct uart_port *port, int idx)
537{
538 unsigned int bar, offset = board->first_offset;
539
540 switch (idx) {
541 case 0:
542 bar = 1;
543 break;
544 case 1:
545 bar = 2;
546 break;
547 default:
548 bar = 4;
549 offset = (idx - 2) * board->uart_offset;
550 }
551
70db3d91 552 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 553}
554
555static int __devinit pci_xircom_init(struct pci_dev *dev)
556{
557 msleep(100);
558 return 0;
559}
560
561static int __devinit pci_netmos_init(struct pci_dev *dev)
562{
563 /* subdevice 0x00PS means <P> parallel, <S> serial */
564 unsigned int num_serial = dev->subsystem_device & 0xf;
565
566 if (num_serial == 0)
567 return -ENODEV;
568 return num_serial;
569}
570
571static int
70db3d91 572pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 573 struct uart_port *port, int idx)
574{
575 unsigned int bar, offset = board->first_offset, maxnr;
576
577 bar = FL_GET_BASE(board->flags);
578 if (board->flags & FL_BASE_BARS)
579 bar += idx;
580 else
581 offset += idx * board->uart_offset;
582
70db3d91 583 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
1da177e4
LT		 584 (8 << board->reg_shift);
585
586 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
587 return 1;
588
70db3d91 589 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 590}
591
592/* This should be in linux/pci_ids.h */
593#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
594#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
595#define PCI_DEVICE_ID_OCTPRO 0x0001
596#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
597#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
598#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
599#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
600
601/*
602 * Master list of serial port init/setup/exit quirks.
603 * This does not describe the general nature of the port.
604 * (ie, baud base, number and location of ports, etc)
605 *
606 * This list is ordered alphabetically by vendor then device.
607 * Specific entries must come before more generic entries.
608 */
609static struct pci_serial_quirk pci_serial_quirks[] = {
610 /*
611 * AFAVLAB cards.
612 * It is not clear whether this applies to all products.
613 */
614 {
615 .vendor = PCI_VENDOR_ID_AFAVLAB,
616 .device = PCI_ANY_ID,
617 .subvendor = PCI_ANY_ID,
618 .subdevice = PCI_ANY_ID,
619 .setup = afavlab_setup,
620 },
621 /*
622 * HP Diva
623 */
624 {
625 .vendor = PCI_VENDOR_ID_HP,
626 .device = PCI_DEVICE_ID_HP_DIVA,
627 .subvendor = PCI_ANY_ID,
628 .subdevice = PCI_ANY_ID,
629 .init = pci_hp_diva_init,
630 .setup = pci_hp_diva_setup,
631 },
632 /*
633 * Intel
634 */
635 {
636 .vendor = PCI_VENDOR_ID_INTEL,
637 .device = PCI_DEVICE_ID_INTEL_80960_RP,
638 .subvendor = 0xe4bf,
639 .subdevice = PCI_ANY_ID,
640 .init = pci_inteli960ni_init,
641 .setup = pci_default_setup,
642 },
643 /*
644 * Panacom
645 */
646 {
647 .vendor = PCI_VENDOR_ID_PANACOM,
648 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
649 .subvendor = PCI_ANY_ID,
650 .subdevice = PCI_ANY_ID,
651 .init = pci_plx9050_init,
652 .setup = pci_default_setup,
653 .exit = __devexit_p(pci_plx9050_exit),
654 },
655 {
656 .vendor = PCI_VENDOR_ID_PANACOM,
657 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
658 .subvendor = PCI_ANY_ID,
659 .subdevice = PCI_ANY_ID,
660 .init = pci_plx9050_init,
661 .setup = pci_default_setup,
662 .exit = __devexit_p(pci_plx9050_exit),
663 },
664 /*
665 * PLX
666 */
add7b58e
BH		 667 {
668 .vendor = PCI_VENDOR_ID_PLX,
669 .device = PCI_DEVICE_ID_PLX_9050,
670 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
671 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
672 .init = pci_plx9050_init,
673 .setup = pci_default_setup,
674 .exit = __devexit_p(pci_plx9050_exit),
675 },
1da177e4
LT		 676 {
677 .vendor = PCI_VENDOR_ID_PLX,
678 .device = PCI_DEVICE_ID_PLX_9050,
679 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
680 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
681 .init = pci_plx9050_init,
682 .setup = pci_default_setup,
683 .exit = __devexit_p(pci_plx9050_exit),
684 },
685 {
686 .vendor = PCI_VENDOR_ID_PLX,
687 .device = PCI_DEVICE_ID_PLX_ROMULUS,
688 .subvendor = PCI_VENDOR_ID_PLX,
689 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
690 .init = pci_plx9050_init,
691 .setup = pci_default_setup,
692 .exit = __devexit_p(pci_plx9050_exit),
693 },
694 /*
695 * SBS Technologies, Inc., PMC-OCTALPRO 232
696 */
697 {
698 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
699 .device = PCI_DEVICE_ID_OCTPRO,
700 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
701 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
702 .init = sbs_init,
703 .setup = sbs_setup,
704 .exit = __devexit_p(sbs_exit),
705 },
706 /*
707 * SBS Technologies, Inc., PMC-OCTALPRO 422
708 */
709 {
710 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
711 .device = PCI_DEVICE_ID_OCTPRO,
712 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
713 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
714 .init = sbs_init,
715 .setup = sbs_setup,
716 .exit = __devexit_p(sbs_exit),
717 },
718 /*
719 * SBS Technologies, Inc., P-Octal 232
720 */
721 {
722 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
723 .device = PCI_DEVICE_ID_OCTPRO,
724 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
725 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
726 .init = sbs_init,
727 .setup = sbs_setup,
728 .exit = __devexit_p(sbs_exit),
729 },
730 /*
731 * SBS Technologies, Inc., P-Octal 422
732 */
733 {
734 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
735 .device = PCI_DEVICE_ID_OCTPRO,
736 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
737 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
738 .init = sbs_init,
739 .setup = sbs_setup,
740 .exit = __devexit_p(sbs_exit),
741 },
1da177e4
LT		 742 /*
743 * SIIG cards.
1da177e4
LT		 744 */
745 {
746 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 747 .device = PCI_ANY_ID,
1da177e4
LT		 748 .subvendor = PCI_ANY_ID,
749 .subdevice = PCI_ANY_ID,
67d74b87 750 .init = pci_siig_init,
1da177e4
LT		 751 .setup = pci_default_setup,
752 },
753 /*
754 * Titan cards
755 */
756 {
757 .vendor = PCI_VENDOR_ID_TITAN,
758 .device = PCI_DEVICE_ID_TITAN_400L,
759 .subvendor = PCI_ANY_ID,
760 .subdevice = PCI_ANY_ID,
761 .setup = titan_400l_800l_setup,
762 },
763 {
764 .vendor = PCI_VENDOR_ID_TITAN,
765 .device = PCI_DEVICE_ID_TITAN_800L,
766 .subvendor = PCI_ANY_ID,
767 .subdevice = PCI_ANY_ID,
768 .setup = titan_400l_800l_setup,
769 },
770 /*
771 * Timedia cards
772 */
773 {
774 .vendor = PCI_VENDOR_ID_TIMEDIA,
775 .device = PCI_DEVICE_ID_TIMEDIA_1889,
776 .subvendor = PCI_VENDOR_ID_TIMEDIA,
777 .subdevice = PCI_ANY_ID,
778 .init = pci_timedia_init,
779 .setup = pci_timedia_setup,
780 },
781 {
782 .vendor = PCI_VENDOR_ID_TIMEDIA,
783 .device = PCI_ANY_ID,
784 .subvendor = PCI_ANY_ID,
785 .subdevice = PCI_ANY_ID,
786 .setup = pci_timedia_setup,
787 },
788 /*
789 * Xircom cards
790 */
791 {
792 .vendor = PCI_VENDOR_ID_XIRCOM,
793 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
794 .subvendor = PCI_ANY_ID,
795 .subdevice = PCI_ANY_ID,
796 .init = pci_xircom_init,
797 .setup = pci_default_setup,
798 },
799 /*
800 * Netmos cards
801 */
802 {
803 .vendor = PCI_VENDOR_ID_NETMOS,
804 .device = PCI_ANY_ID,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .init = pci_netmos_init,
808 .setup = pci_default_setup,
809 },
810 /*
811 * Default "match everything" terminator entry
812 */
813 {
814 .vendor = PCI_ANY_ID,
815 .device = PCI_ANY_ID,
816 .subvendor = PCI_ANY_ID,
817 .subdevice = PCI_ANY_ID,
818 .setup = pci_default_setup,
819 }
820};
821
822static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
823{
824 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
825}
826
827static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
828{
829 struct pci_serial_quirk *quirk;
830
831 for (quirk = pci_serial_quirks; ; quirk++)
832 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
833 quirk_id_matches(quirk->device, dev->device) &&
834 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
835 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
836 break;
837 return quirk;
838}
839
840static _INLINE_ int
72ce9a83 841get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
1da177e4
LT		 842{
843 if (board->flags & FL_NOIRQ)
844 return 0;
845 else
846 return dev->irq;
847}
848
849/*
850 * This is the configuration table for all of the PCI serial boards
851 * which we support. It is directly indexed by the pci_board_num_t enum
852 * value, which is encoded in the pci_device_id PCI probe table's
853 * driver_data member.
854 *
855 * The makeup of these names are:
26e92861 856 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 857 *
26e92861
GH		 858 * bn = PCI BAR number
859 * bt = Index using PCI BARs
860 * n = number of serial ports
861 * baud = baud rate
862 * offsetinhex = offset for each sequential port (in hex)
1da177e4 863 *
26e92861 864 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 865 *
1da177e4
LT		 866 * Please note: in theory if n = 1, _bt infix should make no difference.
867 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
868 */
869enum pci_board_num_t {
870 pbn_default = 0,
871
872 pbn_b0_1_115200,
873 pbn_b0_2_115200,
874 pbn_b0_4_115200,
875 pbn_b0_5_115200,
876
877 pbn_b0_1_921600,
878 pbn_b0_2_921600,
879 pbn_b0_4_921600,
880
db1de159
DR		 881 pbn_b0_2_1130000,
882
fbc0dc0d
AP		 883 pbn_b0_4_1152000,
884
26e92861
GH		 885 pbn_b0_2_1843200,
886 pbn_b0_4_1843200,
887
888 pbn_b0_2_1843200_200,
889 pbn_b0_4_1843200_200,
890 pbn_b0_8_1843200_200,
891
1da177e4
LT		 892 pbn_b0_bt_1_115200,
893 pbn_b0_bt_2_115200,
894 pbn_b0_bt_8_115200,
895
896 pbn_b0_bt_1_460800,
897 pbn_b0_bt_2_460800,
898 pbn_b0_bt_4_460800,
899
900 pbn_b0_bt_1_921600,
901 pbn_b0_bt_2_921600,
902 pbn_b0_bt_4_921600,
903 pbn_b0_bt_8_921600,
904
905 pbn_b1_1_115200,
906 pbn_b1_2_115200,
907 pbn_b1_4_115200,
908 pbn_b1_8_115200,
909
910 pbn_b1_1_921600,
911 pbn_b1_2_921600,
912 pbn_b1_4_921600,
913 pbn_b1_8_921600,
914
26e92861
GH		 915 pbn_b1_2_1250000,
916
1da177e4
LT		 917 pbn_b1_bt_2_921600,
918
919 pbn_b1_1_1382400,
920 pbn_b1_2_1382400,
921 pbn_b1_4_1382400,
922 pbn_b1_8_1382400,
923
924 pbn_b2_1_115200,
925 pbn_b2_8_115200,
926
927 pbn_b2_1_460800,
928 pbn_b2_4_460800,
929 pbn_b2_8_460800,
930 pbn_b2_16_460800,
931
932 pbn_b2_1_921600,
933 pbn_b2_4_921600,
934 pbn_b2_8_921600,
935
936 pbn_b2_bt_1_115200,
937 pbn_b2_bt_2_115200,
938 pbn_b2_bt_4_115200,
939
940 pbn_b2_bt_2_921600,
941 pbn_b2_bt_4_921600,
942
943 pbn_b3_4_115200,
944 pbn_b3_8_115200,
945
946 /*
947 * Board-specific versions.
948 */
949 pbn_panacom,
950 pbn_panacom2,
951 pbn_panacom4,
add7b58e 952 pbn_exsys_4055,
1da177e4
LT		 953 pbn_plx_romulus,
954 pbn_oxsemi,
955 pbn_intel_i960,
956 pbn_sgi_ioc3,
957 pbn_nec_nile4,
958 pbn_computone_4,
959 pbn_computone_6,
960 pbn_computone_8,
961 pbn_sbsxrsio,
962 pbn_exar_XR17C152,
963 pbn_exar_XR17C154,
964 pbn_exar_XR17C158,
965};
966
967/*
968 * uart_offset - the space between channels
969 * reg_shift - describes how the UART registers are mapped
970 * to PCI memory by the card.
971 * For example IER register on SBS, Inc. PMC-OctPro is located at
972 * offset 0x10 from the UART base, while UART_IER is defined as 1
973 * in include/linux/serial_reg.h,
974 * see first lines of serial_in() and serial_out() in 8250.c
975*/
976
1c7c1fe5 977static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 978 [pbn_default] = {
979 .flags = FL_BASE0,
980 .num_ports = 1,
981 .base_baud = 115200,
982 .uart_offset = 8,
983 },
984 [pbn_b0_1_115200] = {
985 .flags = FL_BASE0,
986 .num_ports = 1,
987 .base_baud = 115200,
988 .uart_offset = 8,
989 },
990 [pbn_b0_2_115200] = {
991 .flags = FL_BASE0,
992 .num_ports = 2,
993 .base_baud = 115200,
994 .uart_offset = 8,
995 },
996 [pbn_b0_4_115200] = {
997 .flags = FL_BASE0,
998 .num_ports = 4,
999 .base_baud = 115200,
1000 .uart_offset = 8,
1001 },
1002 [pbn_b0_5_115200] = {
1003 .flags = FL_BASE0,
1004 .num_ports = 5,
1005 .base_baud = 115200,
1006 .uart_offset = 8,
1007 },
1008
1009 [pbn_b0_1_921600] = {
1010 .flags = FL_BASE0,
1011 .num_ports = 1,
1012 .base_baud = 921600,
1013 .uart_offset = 8,
1014 },
1015 [pbn_b0_2_921600] = {
1016 .flags = FL_BASE0,
1017 .num_ports = 2,
1018 .base_baud = 921600,
1019 .uart_offset = 8,
1020 },
1021 [pbn_b0_4_921600] = {
1022 .flags = FL_BASE0,
1023 .num_ports = 4,
1024 .base_baud = 921600,
1025 .uart_offset = 8,
1026 },
db1de159
DR		 1027
1028 [pbn_b0_2_1130000] = {
1029 .flags = FL_BASE0,
1030 .num_ports = 2,
1031 .base_baud = 1130000,
1032 .uart_offset = 8,
1033 },
1034
fbc0dc0d
AP		 1035 [pbn_b0_4_1152000] = {
1036 .flags = FL_BASE0,
1037 .num_ports = 4,
1038 .base_baud = 1152000,
1039 .uart_offset = 8,
1040 },
1da177e4 1041
26e92861
GH		 1042 [pbn_b0_2_1843200] = {
1043 .flags = FL_BASE0,
1044 .num_ports = 2,
1045 .base_baud = 1843200,
1046 .uart_offset = 8,
1047 },
1048 [pbn_b0_4_1843200] = {
1049 .flags = FL_BASE0,
1050 .num_ports = 4,
1051 .base_baud = 1843200,
1052 .uart_offset = 8,
1053 },
1054
1055 [pbn_b0_2_1843200_200] = {
1056 .flags = FL_BASE0,
1057 .num_ports = 2,
1058 .base_baud = 1843200,
1059 .uart_offset = 0x200,
1060 },
1061 [pbn_b0_4_1843200_200] = {
1062 .flags = FL_BASE0,
1063 .num_ports = 4,
1064 .base_baud = 1843200,
1065 .uart_offset = 0x200,
1066 },
1067 [pbn_b0_8_1843200_200] = {
1068 .flags = FL_BASE0,
1069 .num_ports = 8,
1070 .base_baud = 1843200,
1071 .uart_offset = 0x200,
1072 },
1073
1da177e4
LT		 1074 [pbn_b0_bt_1_115200] = {
1075 .flags = FL_BASE0|FL_BASE_BARS,
1076 .num_ports = 1,
1077 .base_baud = 115200,
1078 .uart_offset = 8,
1079 },
1080 [pbn_b0_bt_2_115200] = {
1081 .flags = FL_BASE0|FL_BASE_BARS,
1082 .num_ports = 2,
1083 .base_baud = 115200,
1084 .uart_offset = 8,
1085 },
1086 [pbn_b0_bt_8_115200] = {
1087 .flags = FL_BASE0|FL_BASE_BARS,
1088 .num_ports = 8,
1089 .base_baud = 115200,
1090 .uart_offset = 8,
1091 },
1092
1093 [pbn_b0_bt_1_460800] = {
1094 .flags = FL_BASE0|FL_BASE_BARS,
1095 .num_ports = 1,
1096 .base_baud = 460800,
1097 .uart_offset = 8,
1098 },
1099 [pbn_b0_bt_2_460800] = {
1100 .flags = FL_BASE0|FL_BASE_BARS,
1101 .num_ports = 2,
1102 .base_baud = 460800,
1103 .uart_offset = 8,
1104 },
1105 [pbn_b0_bt_4_460800] = {
1106 .flags = FL_BASE0|FL_BASE_BARS,
1107 .num_ports = 4,
1108 .base_baud = 460800,
1109 .uart_offset = 8,
1110 },
1111
1112 [pbn_b0_bt_1_921600] = {
1113 .flags = FL_BASE0|FL_BASE_BARS,
1114 .num_ports = 1,
1115 .base_baud = 921600,
1116 .uart_offset = 8,
1117 },
1118 [pbn_b0_bt_2_921600] = {
1119 .flags = FL_BASE0|FL_BASE_BARS,
1120 .num_ports = 2,
1121 .base_baud = 921600,
1122 .uart_offset = 8,
1123 },
1124 [pbn_b0_bt_4_921600] = {
1125 .flags = FL_BASE0|FL_BASE_BARS,
1126 .num_ports = 4,
1127 .base_baud = 921600,
1128 .uart_offset = 8,
1129 },
1130 [pbn_b0_bt_8_921600] = {
1131 .flags = FL_BASE0|FL_BASE_BARS,
1132 .num_ports = 8,
1133 .base_baud = 921600,
1134 .uart_offset = 8,
1135 },
1136
1137 [pbn_b1_1_115200] = {
1138 .flags = FL_BASE1,
1139 .num_ports = 1,
1140 .base_baud = 115200,
1141 .uart_offset = 8,
1142 },
1143 [pbn_b1_2_115200] = {
1144 .flags = FL_BASE1,
1145 .num_ports = 2,
1146 .base_baud = 115200,
1147 .uart_offset = 8,
1148 },
1149 [pbn_b1_4_115200] = {
1150 .flags = FL_BASE1,
1151 .num_ports = 4,
1152 .base_baud = 115200,
1153 .uart_offset = 8,
1154 },
1155 [pbn_b1_8_115200] = {
1156 .flags = FL_BASE1,
1157 .num_ports = 8,
1158 .base_baud = 115200,
1159 .uart_offset = 8,
1160 },
1161
1162 [pbn_b1_1_921600] = {
1163 .flags = FL_BASE1,
1164 .num_ports = 1,
1165 .base_baud = 921600,
1166 .uart_offset = 8,
1167 },
1168 [pbn_b1_2_921600] = {
1169 .flags = FL_BASE1,
1170 .num_ports = 2,
1171 .base_baud = 921600,
1172 .uart_offset = 8,
1173 },
1174 [pbn_b1_4_921600] = {
1175 .flags = FL_BASE1,
1176 .num_ports = 4,
1177 .base_baud = 921600,
1178 .uart_offset = 8,
1179 },
1180 [pbn_b1_8_921600] = {
1181 .flags = FL_BASE1,
1182 .num_ports = 8,
1183 .base_baud = 921600,
1184 .uart_offset = 8,
1185 },
26e92861
GH		 1186 [pbn_b1_2_1250000] = {
1187 .flags = FL_BASE1,
1188 .num_ports = 2,
1189 .base_baud = 1250000,
1190 .uart_offset = 8,
1191 },
1da177e4
LT		 1192
1193 [pbn_b1_bt_2_921600] = {
1194 .flags = FL_BASE1|FL_BASE_BARS,
1195 .num_ports = 2,
1196 .base_baud = 921600,
1197 .uart_offset = 8,
1198 },
1199
1200 [pbn_b1_1_1382400] = {
1201 .flags = FL_BASE1,
1202 .num_ports = 1,
1203 .base_baud = 1382400,
1204 .uart_offset = 8,
1205 },
1206 [pbn_b1_2_1382400] = {
1207 .flags = FL_BASE1,
1208 .num_ports = 2,
1209 .base_baud = 1382400,
1210 .uart_offset = 8,
1211 },
1212 [pbn_b1_4_1382400] = {
1213 .flags = FL_BASE1,
1214 .num_ports = 4,
1215 .base_baud = 1382400,
1216 .uart_offset = 8,
1217 },
1218 [pbn_b1_8_1382400] = {
1219 .flags = FL_BASE1,
1220 .num_ports = 8,
1221 .base_baud = 1382400,
1222 .uart_offset = 8,
1223 },
1224
1225 [pbn_b2_1_115200] = {
1226 .flags = FL_BASE2,
1227 .num_ports = 1,
1228 .base_baud = 115200,
1229 .uart_offset = 8,
1230 },
1231 [pbn_b2_8_115200] = {
1232 .flags = FL_BASE2,
1233 .num_ports = 8,
1234 .base_baud = 115200,
1235 .uart_offset = 8,
1236 },
1237
1238 [pbn_b2_1_460800] = {
1239 .flags = FL_BASE2,
1240 .num_ports = 1,
1241 .base_baud = 460800,
1242 .uart_offset = 8,
1243 },
1244 [pbn_b2_4_460800] = {
1245 .flags = FL_BASE2,
1246 .num_ports = 4,
1247 .base_baud = 460800,
1248 .uart_offset = 8,
1249 },
1250 [pbn_b2_8_460800] = {
1251 .flags = FL_BASE2,
1252 .num_ports = 8,
1253 .base_baud = 460800,
1254 .uart_offset = 8,
1255 },
1256 [pbn_b2_16_460800] = {
1257 .flags = FL_BASE2,
1258 .num_ports = 16,
1259 .base_baud = 460800,
1260 .uart_offset = 8,
1261 },
1262
1263 [pbn_b2_1_921600] = {
1264 .flags = FL_BASE2,
1265 .num_ports = 1,
1266 .base_baud = 921600,
1267 .uart_offset = 8,
1268 },
1269 [pbn_b2_4_921600] = {
1270 .flags = FL_BASE2,
1271 .num_ports = 4,
1272 .base_baud = 921600,
1273 .uart_offset = 8,
1274 },
1275 [pbn_b2_8_921600] = {
1276 .flags = FL_BASE2,
1277 .num_ports = 8,
1278 .base_baud = 921600,
1279 .uart_offset = 8,
1280 },
1281
1282 [pbn_b2_bt_1_115200] = {
1283 .flags = FL_BASE2|FL_BASE_BARS,
1284 .num_ports = 1,
1285 .base_baud = 115200,
1286 .uart_offset = 8,
1287 },
1288 [pbn_b2_bt_2_115200] = {
1289 .flags = FL_BASE2|FL_BASE_BARS,
1290 .num_ports = 2,
1291 .base_baud = 115200,
1292 .uart_offset = 8,
1293 },
1294 [pbn_b2_bt_4_115200] = {
1295 .flags = FL_BASE2|FL_BASE_BARS,
1296 .num_ports = 4,
1297 .base_baud = 115200,
1298 .uart_offset = 8,
1299 },
1300
1301 [pbn_b2_bt_2_921600] = {
1302 .flags = FL_BASE2|FL_BASE_BARS,
1303 .num_ports = 2,
1304 .base_baud = 921600,
1305 .uart_offset = 8,
1306 },
1307 [pbn_b2_bt_4_921600] = {
1308 .flags = FL_BASE2|FL_BASE_BARS,
1309 .num_ports = 4,
1310 .base_baud = 921600,
1311 .uart_offset = 8,
1312 },
1313
1314 [pbn_b3_4_115200] = {
1315 .flags = FL_BASE3,
1316 .num_ports = 4,
1317 .base_baud = 115200,
1318 .uart_offset = 8,
1319 },
1320 [pbn_b3_8_115200] = {
1321 .flags = FL_BASE3,
1322 .num_ports = 8,
1323 .base_baud = 115200,
1324 .uart_offset = 8,
1325 },
1326
1327 /*
1328 * Entries following this are board-specific.
1329 */
1330
1331 /*
1332 * Panacom - IOMEM
1333 */
1334 [pbn_panacom] = {
1335 .flags = FL_BASE2,
1336 .num_ports = 2,
1337 .base_baud = 921600,
1338 .uart_offset = 0x400,
1339 .reg_shift = 7,
1340 },
1341 [pbn_panacom2] = {
1342 .flags = FL_BASE2|FL_BASE_BARS,
1343 .num_ports = 2,
1344 .base_baud = 921600,
1345 .uart_offset = 0x400,
1346 .reg_shift = 7,
1347 },
1348 [pbn_panacom4] = {
1349 .flags = FL_BASE2|FL_BASE_BARS,
1350 .num_ports = 4,
1351 .base_baud = 921600,
1352 .uart_offset = 0x400,
1353 .reg_shift = 7,
1354 },
1355
add7b58e
BH		 1356 [pbn_exsys_4055] = {
1357 .flags = FL_BASE2,
1358 .num_ports = 4,
1359 .base_baud = 115200,
1360 .uart_offset = 8,
1361 },
1362
1da177e4
LT		 1363 /* I think this entry is broken - the first_offset looks wrong --rmk */
1364 [pbn_plx_romulus] = {
1365 .flags = FL_BASE2,
1366 .num_ports = 4,
1367 .base_baud = 921600,
1368 .uart_offset = 8 << 2,
1369 .reg_shift = 2,
1370 .first_offset = 0x03,
1371 },
1372
1373 /*
1374 * This board uses the size of PCI Base region 0 to
1375 * signal now many ports are available
1376 */
1377 [pbn_oxsemi] = {
1378 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1379 .num_ports = 32,
1380 .base_baud = 115200,
1381 .uart_offset = 8,
1382 },
1383
1384 /*
1385 * EKF addition for i960 Boards form EKF with serial port.
1386 * Max 256 ports.
1387 */
1388 [pbn_intel_i960] = {
1389 .flags = FL_BASE0,
1390 .num_ports = 32,
1391 .base_baud = 921600,
1392 .uart_offset = 8 << 2,
1393 .reg_shift = 2,
1394 .first_offset = 0x10000,
1395 },
1396 [pbn_sgi_ioc3] = {
1397 .flags = FL_BASE0|FL_NOIRQ,
1398 .num_ports = 1,
1399 .base_baud = 458333,
1400 .uart_offset = 8,
1401 .reg_shift = 0,
1402 .first_offset = 0x20178,
1403 },
1404
1405 /*
1406 * NEC Vrc-5074 (Nile 4) builtin UART.
1407 */
1408 [pbn_nec_nile4] = {
1409 .flags = FL_BASE0,
1410 .num_ports = 1,
1411 .base_baud = 520833,
1412 .uart_offset = 8 << 3,
1413 .reg_shift = 3,
1414 .first_offset = 0x300,
1415 },
1416
1417 /*
1418 * Computone - uses IOMEM.
1419 */
1420 [pbn_computone_4] = {
1421 .flags = FL_BASE0,
1422 .num_ports = 4,
1423 .base_baud = 921600,
1424 .uart_offset = 0x40,
1425 .reg_shift = 2,
1426 .first_offset = 0x200,
1427 },
1428 [pbn_computone_6] = {
1429 .flags = FL_BASE0,
1430 .num_ports = 6,
1431 .base_baud = 921600,
1432 .uart_offset = 0x40,
1433 .reg_shift = 2,
1434 .first_offset = 0x200,
1435 },
1436 [pbn_computone_8] = {
1437 .flags = FL_BASE0,
1438 .num_ports = 8,
1439 .base_baud = 921600,
1440 .uart_offset = 0x40,
1441 .reg_shift = 2,
1442 .first_offset = 0x200,
1443 },
1444 [pbn_sbsxrsio] = {
1445 .flags = FL_BASE0,
1446 .num_ports = 8,
1447 .base_baud = 460800,
1448 .uart_offset = 256,
1449 .reg_shift = 4,
1450 },
1451 /*
1452 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1453 * Only basic 16550A support.
1454 * XR17C15[24] are not tested, but they should work.
1455 */
1456 [pbn_exar_XR17C152] = {
1457 .flags = FL_BASE0,
1458 .num_ports = 2,
1459 .base_baud = 921600,
1460 .uart_offset = 0x200,
1461 },
1462 [pbn_exar_XR17C154] = {
1463 .flags = FL_BASE0,
1464 .num_ports = 4,
1465 .base_baud = 921600,
1466 .uart_offset = 0x200,
1467 },
1468 [pbn_exar_XR17C158] = {
1469 .flags = FL_BASE0,
1470 .num_ports = 8,
1471 .base_baud = 921600,
1472 .uart_offset = 0x200,
1473 },
1474};
1475
1476/*
1477 * Given a complete unknown PCI device, try to use some heuristics to
1478 * guess what the configuration might be, based on the pitiful PCI
1479 * serial specs. Returns 0 on success, 1 on failure.
1480 */
1481static int __devinit
1c7c1fe5 1482serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4
LT		 1483{
1484 int num_iomem, num_port, first_port = -1, i;
1485
1486 /*
1487 * If it is not a communications device or the programming
1488 * interface is greater than 6, give up.
1489 *
1490 * (Should we try to make guesses for multiport serial devices
1491 * later?)
1492 */
1493 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1494 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1495 (dev->class & 0xff) > 6)
1496 return -ENODEV;
1497
1498 num_iomem = num_port = 0;
1499 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1500 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1501 num_port++;
1502 if (first_port == -1)
1503 first_port = i;
1504 }
1505 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1506 num_iomem++;
1507 }
1508
1509 /*
1510 * If there is 1 or 0 iomem regions, and exactly one port,
1511 * use it. We guess the number of ports based on the IO
1512 * region size.
1513 */
1514 if (num_iomem <= 1 && num_port == 1) {
1515 board->flags = first_port;
1516 board->num_ports = pci_resource_len(dev, first_port) / 8;
1517 return 0;
1518 }
1519
1520 /*
1521 * Now guess if we've got a board which indexes by BARs.
1522 * Each IO BAR should be 8 bytes, and they should follow
1523 * consecutively.
1524 */
1525 first_port = -1;
1526 num_port = 0;
1527 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1528 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1529 pci_resource_len(dev, i) == 8 &&
1530 (first_port == -1 || (first_port + num_port) == i)) {
1531 num_port++;
1532 if (first_port == -1)
1533 first_port = i;
1534 }
1535 }
1536
1537 if (num_port > 1) {
1538 board->flags = first_port | FL_BASE_BARS;
1539 board->num_ports = num_port;
1540 return 0;
1541 }
1542
1543 return -ENODEV;
1544}
1545
1546static inline int
1c7c1fe5
RK		 1547serial_pci_matches(struct pciserial_board *board,
1548 struct pciserial_board *guessed)
1da177e4
LT		 1549{
1550 return
1551 board->num_ports == guessed->num_ports &&
1552 board->base_baud == guessed->base_baud &&
1553 board->uart_offset == guessed->uart_offset &&
1554 board->reg_shift == guessed->reg_shift &&
1555 board->first_offset == guessed->first_offset;
1556}
1557
241fc436
RK		 1558struct serial_private *
1559pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 1560{
72ce9a83 1561 struct uart_port serial_port;
1da177e4 1562 struct serial_private *priv;
1da177e4
LT		 1563 struct pci_serial_quirk *quirk;
1564 int rc, nr_ports, i;
1565
1da177e4
LT		 1566 nr_ports = board->num_ports;
1567
1568 /*
1569 * Find an init and setup quirks.
1570 */
1571 quirk = find_quirk(dev);
1572
1573 /*
1574 * Run the new-style initialization function.
1575 * The initialization function returns:
1576 * <0 - error
1577 * 0 - use board->num_ports
1578 * >0 - number of ports
1579 */
1580 if (quirk->init) {
1581 rc = quirk->init(dev);
241fc436
RK		 1582 if (rc < 0) {
1583 priv = ERR_PTR(rc);
1584 goto err_out;
1585 }
1da177e4
LT		 1586 if (rc)
1587 nr_ports = rc;
1588 }
1589
1590 priv = kmalloc(sizeof(struct serial_private) +
1591 sizeof(unsigned int) * nr_ports,
1592 GFP_KERNEL);
1593 if (!priv) {
241fc436
RK		 1594 priv = ERR_PTR(-ENOMEM);
1595 goto err_deinit;
1da177e4
LT		 1596 }
1597
1598 memset(priv, 0, sizeof(struct serial_private) +
1599 sizeof(unsigned int) * nr_ports);
1600
70db3d91 1601 priv->dev = dev;
1da177e4 1602 priv->quirk = quirk;
1da177e4 1603
72ce9a83
RK		 1604 memset(&serial_port, 0, sizeof(struct uart_port));
1605 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1606 serial_port.uartclk = board->base_baud * 16;
1607 serial_port.irq = get_pci_irq(dev, board);
1608 serial_port.dev = &dev->dev;
1609
1da177e4 1610 for (i = 0; i < nr_ports; i++) {
70db3d91 1611 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 1612 break;
72ce9a83 1613
1da177e4
LT		 1614#ifdef SERIAL_DEBUG_PCI
1615 printk("Setup PCI port: port %x, irq %d, type %d\n",
1616 serial_port.iobase, serial_port.irq, serial_port.iotype);
1617#endif
1618
1619 priv->line[i] = serial8250_register_port(&serial_port);
1620 if (priv->line[i] < 0) {
1621 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1622 break;
1623 }
1624 }
1625
1626 priv->nr = i;
1627
241fc436 1628 return priv;
1da177e4 1629
241fc436 1630 err_deinit:
1da177e4
LT		 1631 if (quirk->exit)
1632 quirk->exit(dev);
241fc436
RK		 1633 err_out:
1634 return priv;
1da177e4 1635}
241fc436 1636EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 1637
241fc436 1638void pciserial_remove_ports(struct serial_private *priv)
1da177e4 1639{
056a8763
RK		 1640 struct pci_serial_quirk *quirk;
1641 int i;
1da177e4 1642
056a8763
RK		 1643 for (i = 0; i < priv->nr; i++)
1644 serial8250_unregister_port(priv->line[i]);
1da177e4 1645
056a8763
RK		 1646 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1647 if (priv->remapped_bar[i])
1648 iounmap(priv->remapped_bar[i]);
1649 priv->remapped_bar[i] = NULL;
1650 }
1da177e4 1651
056a8763
RK		 1652 /*
1653 * Find the exit quirks.
1654 */
241fc436 1655 quirk = find_quirk(priv->dev);
056a8763 1656 if (quirk->exit)
241fc436
RK		 1657 quirk->exit(priv->dev);
1658
1659 kfree(priv);
1660}
1661EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1662
1663void pciserial_suspend_ports(struct serial_private *priv)
1664{
1665 int i;
1666
1667 for (i = 0; i < priv->nr; i++)
1668 if (priv->line[i] >= 0)
1669 serial8250_suspend_port(priv->line[i]);
1670}
1671EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1672
1673void pciserial_resume_ports(struct serial_private *priv)
1674{
1675 int i;
1676
1677 /*
1678 * Ensure that the board is correctly configured.
1679 */
1680 if (priv->quirk->init)
1681 priv->quirk->init(priv->dev);
1682
1683 for (i = 0; i < priv->nr; i++)
1684 if (priv->line[i] >= 0)
1685 serial8250_resume_port(priv->line[i]);
1686}
1687EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1688
1689/*
1690 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1691 * to the arrangement of serial ports on a PCI card.
1692 */
1693static int __devinit
1694pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1695{
1696 struct serial_private *priv;
1697 struct pciserial_board *board, tmp;
1698 int rc;
1699
1700 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1701 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1702 ent->driver_data);
1703 return -EINVAL;
1704 }
1705
1706 board = &pci_boards[ent->driver_data];
1707
1708 rc = pci_enable_device(dev);
1709 if (rc)
1710 return rc;
1711
1712 if (ent->driver_data == pbn_default) {
1713 /*
1714 * Use a copy of the pci_board entry for this;
1715 * avoid changing entries in the table.
1716 */
1717 memcpy(&tmp, board, sizeof(struct pciserial_board));
1718 board = &tmp;
1719
1720 /*
1721 * We matched one of our class entries. Try to
1722 * determine the parameters of this board.
1723 */
1724 rc = serial_pci_guess_board(dev, board);
1725 if (rc)
1726 goto disable;
1727 } else {
1728 /*
1729 * We matched an explicit entry. If we are able to
1730 * detect this boards settings with our heuristic,
1731 * then we no longer need this entry.
1732 */
1733 memcpy(&tmp, &pci_boards[pbn_default],
1734 sizeof(struct pciserial_board));
1735 rc = serial_pci_guess_board(dev, &tmp);
1736 if (rc == 0 && serial_pci_matches(board, &tmp))
1737 moan_device("Redundant entry in serial pci_table.",
1738 dev);
1739 }
1740
1741 priv = pciserial_init_ports(dev, board);
1742 if (!IS_ERR(priv)) {
1743 pci_set_drvdata(dev, priv);
1744 return 0;
1745 }
1746
1747 rc = PTR_ERR(priv);
1da177e4 1748
241fc436 1749 disable:
056a8763 1750 pci_disable_device(dev);
241fc436
RK		 1751 return rc;
1752}
1da177e4 1753
241fc436
RK		 1754static void __devexit pciserial_remove_one(struct pci_dev *dev)
1755{
1756 struct serial_private *priv = pci_get_drvdata(dev);
1757
1758 pci_set_drvdata(dev, NULL);
1759
1760 pciserial_remove_ports(priv);
1761
1762 pci_disable_device(dev);
1da177e4
LT		 1763}
1764
1765static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1766{
1767 struct serial_private *priv = pci_get_drvdata(dev);
1768
241fc436
RK		 1769 if (priv)
1770 pciserial_suspend_ports(priv);
1da177e4 1771
1da177e4
LT		 1772 pci_save_state(dev);
1773 pci_set_power_state(dev, pci_choose_state(dev, state));
1774 return 0;
1775}
1776
1777static int pciserial_resume_one(struct pci_dev *dev)
1778{
1779 struct serial_private *priv = pci_get_drvdata(dev);
1780
1781 pci_set_power_state(dev, PCI_D0);
1782 pci_restore_state(dev);
1783
1784 if (priv) {
1da177e4
LT		 1785 /*
1786 * The device may have been disabled. Re-enable it.
1787 */
1788 pci_enable_device(dev);
1789
241fc436 1790 pciserial_resume_ports(priv);
1da177e4
LT		 1791 }
1792 return 0;
1793}
1794
1795static struct pci_device_id serial_pci_tbl[] = {
1796 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1797 PCI_SUBVENDOR_ID_CONNECT_TECH,
1798 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1799 pbn_b1_8_1382400 },
1800 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1801 PCI_SUBVENDOR_ID_CONNECT_TECH,
1802 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1803 pbn_b1_4_1382400 },
1804 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1805 PCI_SUBVENDOR_ID_CONNECT_TECH,
1806 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1807 pbn_b1_2_1382400 },
1808 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1809 PCI_SUBVENDOR_ID_CONNECT_TECH,
1810 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1811 pbn_b1_8_1382400 },
1812 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1813 PCI_SUBVENDOR_ID_CONNECT_TECH,
1814 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1815 pbn_b1_4_1382400 },
1816 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1817 PCI_SUBVENDOR_ID_CONNECT_TECH,
1818 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1819 pbn_b1_2_1382400 },
1820 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1821 PCI_SUBVENDOR_ID_CONNECT_TECH,
1822 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1823 pbn_b1_8_921600 },
1824 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1825 PCI_SUBVENDOR_ID_CONNECT_TECH,
1826 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1827 pbn_b1_8_921600 },
1828 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1829 PCI_SUBVENDOR_ID_CONNECT_TECH,
1830 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1831 pbn_b1_4_921600 },
1832 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1833 PCI_SUBVENDOR_ID_CONNECT_TECH,
1834 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1835 pbn_b1_4_921600 },
1836 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1837 PCI_SUBVENDOR_ID_CONNECT_TECH,
1838 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1839 pbn_b1_2_921600 },
1840 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1841 PCI_SUBVENDOR_ID_CONNECT_TECH,
1842 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1843 pbn_b1_8_921600 },
1844 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1845 PCI_SUBVENDOR_ID_CONNECT_TECH,
1846 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1847 pbn_b1_8_921600 },
1848 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1849 PCI_SUBVENDOR_ID_CONNECT_TECH,
1850 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1851 pbn_b1_4_921600 },
26e92861
GH		 1852 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1853 PCI_SUBVENDOR_ID_CONNECT_TECH,
1854 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1855 pbn_b1_2_1250000 },
1856 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1857 PCI_SUBVENDOR_ID_CONNECT_TECH,
1858 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1859 pbn_b0_2_1843200 },
1860 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1861 PCI_SUBVENDOR_ID_CONNECT_TECH,
1862 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1863 pbn_b0_4_1843200 },
1864 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1865 PCI_SUBVENDOR_ID_CONNECT_TECH,
1866 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1867 pbn_b0_2_1843200_200 },
1868 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1869 PCI_SUBVENDOR_ID_CONNECT_TECH,
1870 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1871 pbn_b0_4_1843200_200 },
1872 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1873 PCI_SUBVENDOR_ID_CONNECT_TECH,
1874 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1875 pbn_b0_8_1843200_200 },
1876 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1877 PCI_SUBVENDOR_ID_CONNECT_TECH,
1878 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1879 pbn_b0_2_1843200_200 },
1880 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1881 PCI_SUBVENDOR_ID_CONNECT_TECH,
1882 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1883 pbn_b0_4_1843200_200 },
1884 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1885 PCI_SUBVENDOR_ID_CONNECT_TECH,
1886 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1887 pbn_b0_8_1843200_200 },
1888 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1889 PCI_SUBVENDOR_ID_CONNECT_TECH,
1890 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1891 pbn_b0_2_1843200_200 },
1892 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1893 PCI_SUBVENDOR_ID_CONNECT_TECH,
1894 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1895 pbn_b0_4_1843200_200 },
1896 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1897 PCI_SUBVENDOR_ID_CONNECT_TECH,
1898 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1899 pbn_b0_8_1843200_200 },
1900 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1901 PCI_SUBVENDOR_ID_CONNECT_TECH,
1902 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1903 pbn_b0_2_1843200_200 },
1904 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1905 PCI_SUBVENDOR_ID_CONNECT_TECH,
1906 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1907 pbn_b0_4_1843200_200 },
1908 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1909 PCI_SUBVENDOR_ID_CONNECT_TECH,
1910 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1911 pbn_b0_8_1843200_200 },
1da177e4
LT		 1912
1913 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1915 pbn_b2_bt_1_115200 },
1916 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1918 pbn_b2_bt_2_115200 },
1919 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1921 pbn_b2_bt_4_115200 },
1922 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1924 pbn_b2_bt_2_115200 },
1925 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1927 pbn_b2_bt_4_115200 },
1928 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1930 pbn_b2_8_115200 },
1931 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1933 pbn_b2_8_115200 },
1934
1935 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1937 pbn_b2_bt_2_115200 },
1938 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1940 pbn_b2_bt_2_921600 },
1941 /*
1942 * VScom SPCOM800, from [email protected]
1943 */
1944 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1946 pbn_b2_8_921600 },
1947 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1949 pbn_b2_4_921600 },
1950 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1951 PCI_SUBVENDOR_ID_KEYSPAN,
1952 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1953 pbn_panacom },
1954 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1956 pbn_panacom4 },
1957 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959 pbn_panacom2 },
1960 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1961 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1962 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1963 pbn_b2_4_460800 },
1964 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1965 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1966 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1967 pbn_b2_8_460800 },
1968 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1969 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1970 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1971 pbn_b2_16_460800 },
1972 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1973 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1974 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1975 pbn_b2_16_460800 },
1976 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1977 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1978 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1979 pbn_b2_4_460800 },
1980 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1981 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1982 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1983 pbn_b2_8_460800 },
add7b58e
BH		 1984 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1985 PCI_SUBVENDOR_ID_EXSYS,
1986 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
1987 pbn_exsys_4055 },
1da177e4
LT		 1988 /*
1989 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1990 * ([email protected])
1991 */
1992 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1993 0x10b5, 0x106a, 0, 0,
1994 pbn_plx_romulus },
1995 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1997 pbn_b1_4_115200 },
1998 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2000 pbn_b1_2_115200 },
2001 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2003 pbn_b1_8_115200 },
2004 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2006 pbn_b1_8_115200 },
2007 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2008 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2009 pbn_b0_4_921600 },
fbc0dc0d
AP		 2010 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2011 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2012 pbn_b0_4_1152000 },
db1de159
DR		 2013
2014 /*
2015 * The below card is a little controversial since it is the
2016 * subject of a PCI vendor/device ID clash. (See
2017 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2018 * For now just used the hex ID 0x950a.
2019 */
2020 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022 pbn_b0_2_1130000 },
1da177e4
LT		 2023 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2025 pbn_b0_4_115200 },
2026 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2028 pbn_b0_bt_2_921600 },
2029
2030 /*
2031 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2032 * from [email protected]
2033 */
2034 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2035 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2036 pbn_sbsxrsio },
2037 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2038 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2039 pbn_sbsxrsio },
2040 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2041 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2042 pbn_sbsxrsio },
2043 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2044 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2045 pbn_sbsxrsio },
2046
2047 /*
2048 * Digitan DS560-558, from [email protected]
2049 */
2050 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2052 pbn_b1_1_115200 },
2053
2054 /*
2055 * Titan Electronic cards
2056 * The 400L and 800L have a custom setup quirk.
2057 */
2058 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2060 pbn_b0_1_921600 },
2061 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2063 pbn_b0_2_921600 },
2064 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2066 pbn_b0_4_921600 },
2067 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2069 pbn_b0_4_921600 },
2070 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2072 pbn_b1_1_921600 },
2073 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2075 pbn_b1_bt_2_921600 },
2076 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2078 pbn_b0_bt_4_921600 },
2079 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2081 pbn_b0_bt_8_921600 },
2082
2083 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2085 pbn_b2_1_460800 },
2086 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2088 pbn_b2_1_460800 },
2089 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2091 pbn_b2_1_460800 },
2092 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2094 pbn_b2_bt_2_921600 },
2095 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2097 pbn_b2_bt_2_921600 },
2098 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2100 pbn_b2_bt_2_921600 },
2101 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2103 pbn_b2_bt_4_921600 },
2104 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2106 pbn_b2_bt_4_921600 },
2107 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2109 pbn_b2_bt_4_921600 },
2110 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2112 pbn_b0_1_921600 },
2113 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2115 pbn_b0_1_921600 },
2116 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2118 pbn_b0_1_921600 },
2119 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2121 pbn_b0_bt_2_921600 },
2122 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2124 pbn_b0_bt_2_921600 },
2125 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2127 pbn_b0_bt_2_921600 },
2128 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2130 pbn_b0_bt_4_921600 },
2131 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2133 pbn_b0_bt_4_921600 },
2134 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2136 pbn_b0_bt_4_921600 },
2137
2138 /*
2139 * Computone devices submitted by Doug McNash [email protected]
2140 */
2141 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2142 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2143 0, 0, pbn_computone_4 },
2144 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2145 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2146 0, 0, pbn_computone_8 },
2147 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2148 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2149 0, 0, pbn_computone_6 },
2150
2151 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2153 pbn_oxsemi },
2154 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2155 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2156 pbn_b0_bt_1_921600 },
2157
2158 /*
2159 * AFAVLAB serial card, from Harald Welte <[email protected]>
2160 */
2161 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2163 pbn_b0_bt_8_115200 },
2164 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2166 pbn_b0_bt_8_115200 },
2167
2168 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2170 pbn_b0_bt_2_115200 },
2171 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2173 pbn_b0_bt_2_115200 },
2174 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2176 pbn_b0_bt_2_115200 },
2177 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2179 pbn_b0_bt_4_460800 },
2180 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2182 pbn_b0_bt_4_460800 },
2183 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2185 pbn_b0_bt_2_460800 },
2186 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2188 pbn_b0_bt_2_460800 },
2189 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2191 pbn_b0_bt_2_460800 },
2192 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2194 pbn_b0_bt_1_115200 },
2195 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2197 pbn_b0_bt_1_460800 },
2198
2199 /*
2200 * Dell Remote Access Card 4 - [email protected]
2201 */
2202 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2204 pbn_b1_1_1382400 },
2205
2206 /*
2207 * Dell Remote Access Card III - [email protected]
2208 */
2209 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2211 pbn_b1_1_1382400 },
2212
2213 /*
2214 * RAStel 2 port modem, [email protected]
2215 */
2216 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2218 pbn_b2_bt_2_115200 },
2219
2220 /*
2221 * EKF addition for i960 Boards form EKF with serial port
2222 */
2223 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2224 0xE4BF, PCI_ANY_ID, 0, 0,
2225 pbn_intel_i960 },
2226
2227 /*
2228 * Xircom Cardbus/Ethernet combos
2229 */
2230 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2232 pbn_b0_1_115200 },
2233 /*
2234 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2235 */
2236 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2238 pbn_b0_1_115200 },
2239
2240 /*
2241 * Untested PCI modems, sent in from various folks...
2242 */
2243
2244 /*
2245 * Elsa Model 56K PCI Modem, from Andreas Rath <[email protected]>
2246 */
2247 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2248 0x1048, 0x1500, 0, 0,
2249 pbn_b1_1_115200 },
2250
2251 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2252 0xFF00, 0, 0, 0,
2253 pbn_sgi_ioc3 },
2254
2255 /*
2256 * HP Diva card
2257 */
2258 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2259 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2260 pbn_b1_1_115200 },
2261 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2263 pbn_b0_5_115200 },
2264 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2266 pbn_b2_1_115200 },
2267
2268 /*
2269 * NEC Vrc-5074 (Nile 4) builtin UART.
2270 */
2271 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2273 pbn_nec_nile4 },
2274
2275 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2277 pbn_b3_4_115200 },
2278 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2280 pbn_b3_8_115200 },
2281
2282 /*
2283 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2284 */
2285 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2286 PCI_ANY_ID, PCI_ANY_ID,
2287 0,
2288 0, pbn_exar_XR17C152 },
2289 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2290 PCI_ANY_ID, PCI_ANY_ID,
2291 0,
2292 0, pbn_exar_XR17C154 },
2293 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2294 PCI_ANY_ID, PCI_ANY_ID,
2295 0,
2296 0, pbn_exar_XR17C158 },
2297
2298 /*
2299 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2300 */
2301 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2303 pbn_b0_1_115200 },
2304
2305 /*
2306 * These entries match devices with class COMMUNICATION_SERIAL,
2307 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2308 */
2309 { PCI_ANY_ID, PCI_ANY_ID,
2310 PCI_ANY_ID, PCI_ANY_ID,
2311 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2312 0xffff00, pbn_default },
2313 { PCI_ANY_ID, PCI_ANY_ID,
2314 PCI_ANY_ID, PCI_ANY_ID,
2315 PCI_CLASS_COMMUNICATION_MODEM << 8,
2316 0xffff00, pbn_default },
2317 { PCI_ANY_ID, PCI_ANY_ID,
2318 PCI_ANY_ID, PCI_ANY_ID,
2319 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2320 0xffff00, pbn_default },
2321 { 0, }
2322};
2323
2324static struct pci_driver serial_pci_driver = {
2325 .name = "serial",
2326 .probe = pciserial_init_one,
2327 .remove = __devexit_p(pciserial_remove_one),
2328 .suspend = pciserial_suspend_one,
2329 .resume = pciserial_resume_one,
2330 .id_table = serial_pci_tbl,
2331};
2332
2333static int __init serial8250_pci_init(void)
2334{
2335 return pci_register_driver(&serial_pci_driver);
2336}
2337
2338static void __exit serial8250_pci_exit(void)
2339{
2340 pci_unregister_driver(&serial_pci_driver);
2341}
2342
2343module_init(serial8250_pci_init);
2344module_exit(serial8250_pci_exit);
2345
2346MODULE_LICENSE("GPL");
2347MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2348MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Empty description
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