]> Git Repo - linux.git/blame - drivers/serial/8250_pci.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] V4L/DVB (3087) fix analog NTSC for pcHDTV 3000
[linux.git] / drivers / serial / 8250_pci.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include <linux/sched.h>
20#include <linux/string.h>
21#include <linux/kernel.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24#include <linux/tty.h>
25#include <linux/serial_core.h>
26#include <linux/8250_pci.h>
27#include <linux/bitops.h>
28
29#include <asm/byteorder.h>
30#include <asm/io.h>
31
32#include "8250.h"
33
34#undef SERIAL_DEBUG_PCI
35
1da177e4
LT		 36/*
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
40 * < 0 - error
41 */
42struct pci_serial_quirk {
43 u32 vendor;
44 u32 device;
45 u32 subvendor;
46 u32 subdevice;
47 int (*init)(struct pci_dev *dev);
70db3d91 48 int (*setup)(struct serial_private *, struct pciserial_board *,
05caac58 49 struct uart_port *, int);
1da177e4
LT		 50 void (*exit)(struct pci_dev *dev);
51};
52
53#define PCI_NUM_BAR_RESOURCES 6
54
55struct serial_private {
70db3d91 56 struct pci_dev *dev;
1da177e4
LT		 57 unsigned int nr;
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
60 int line[0];
61};
62
63static void moan_device(const char *str, struct pci_dev *dev)
64{
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to [email protected].\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72}
73
74static int
70db3d91 75setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 76 int bar, int offset, int regshift)
77{
70db3d91 78 struct pci_dev *dev = priv->dev;
1da177e4
LT		 79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
72ce9a83
RK		 84 base = pci_resource_start(dev, bar);
85
1da177e4 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
94 port->iotype = UPIO_MEM;
72ce9a83 95 port->iobase = 0;
1da177e4
LT		 96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
99 } else {
1da177e4 100 port->iotype = UPIO_PORT;
72ce9a83
RK		 101 port->iobase = base + offset;
102 port->mapbase = 0;
103 port->membase = NULL;
104 port->regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
109/*
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
112 */
113static int
70db3d91 114afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 115 struct uart_port *port, int idx)
116{
117 unsigned int bar, offset = board->first_offset;
118
119 bar = FL_GET_BASE(board->flags);
120 if (idx < 4)
121 bar += idx;
122 else {
123 bar = 4;
124 offset += (idx - 4) * board->uart_offset;
125 }
126
70db3d91 127 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 128}
129
130/*
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
136 */
137static int __devinit pci_hp_diva_init(struct pci_dev *dev)
138{
139 int rc = 0;
140
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
146 rc = 3;
147 break;
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
149 rc = 2;
150 break;
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
152 rc = 4;
153 break;
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 155 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 156 rc = 1;
157 break;
158 }
159
160 return rc;
161}
162
163/*
164 * HP's Diva chip puts the 4th/5th serial port further out, and
165 * some serial ports are supposed to be hidden on certain models.
166 */
167static int
70db3d91 168pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 169 struct uart_port *port, int idx)
170{
171 unsigned int offset = board->first_offset;
172 unsigned int bar = FL_GET_BASE(board->flags);
173
70db3d91 174 switch (priv->dev->subsystem_device) {
1da177e4
LT		 175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 if (idx == 3)
177 idx++;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
180 if (idx > 0)
181 idx++;
182 if (idx > 2)
183 idx++;
184 break;
185 }
186 if (idx > 2)
187 offset = 0x18;
188
189 offset += idx * board->uart_offset;
190
70db3d91 191 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 192}
193
194/*
195 * Added for EKF Intel i960 serial boards
196 */
197static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
198{
199 unsigned long oldval;
200
201 if (!(dev->subsystem_device & 0x1000))
202 return -ENODEV;
203
204 /* is firmware started? */
205 pci_read_config_dword(dev, 0x44, (void*) &oldval);
206 if (oldval == 0x00001000L) { /* RESET value */
207 printk(KERN_DEBUG "Local i960 firmware missing");
208 return -ENODEV;
209 }
210 return 0;
211}
212
213/*
214 * Some PCI serial cards using the PLX 9050 PCI interface chip require
215 * that the card interrupt be explicitly enabled or disabled. This
216 * seems to be mainly needed on card using the PLX which also use I/O
217 * mapped memory.
218 */
219static int __devinit pci_plx9050_init(struct pci_dev *dev)
220{
221 u8 irq_config;
222 void __iomem *p;
223
224 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
225 moan_device("no memory in bar 0", dev);
226 return 0;
227 }
228
229 irq_config = 0x41;
add7b58e
BH		 230 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
231 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
1da177e4 232 irq_config = 0x43;
add7b58e 233 }
1da177e4
LT		 234 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
235 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
236 /*
237 * As the megawolf cards have the int pins active
238 * high, and have 2 UART chips, both ints must be
239 * enabled on the 9050. Also, the UARTS are set in
240 * 16450 mode by default, so we have to enable the
241 * 16C950 'enhanced' mode so that we can use the
242 * deep FIFOs
243 */
244 irq_config = 0x5b;
245 }
246
247 /*
248 * enable/disable interrupts
249 */
250 p = ioremap(pci_resource_start(dev, 0), 0x80);
251 if (p == NULL)
252 return -ENOMEM;
253 writel(irq_config, p + 0x4c);
254
255 /*
256 * Read the register back to ensure that it took effect.
257 */
258 readl(p + 0x4c);
259 iounmap(p);
260
261 return 0;
262}
263
264static void __devexit pci_plx9050_exit(struct pci_dev *dev)
265{
266 u8 __iomem *p;
267
268 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
269 return;
270
271 /*
272 * disable interrupts
273 */
274 p = ioremap(pci_resource_start(dev, 0), 0x80);
275 if (p != NULL) {
276 writel(0, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283 }
284}
285
286/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
287static int
70db3d91 288sbs_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 289 struct uart_port *port, int idx)
290{
291 unsigned int bar, offset = board->first_offset;
292
293 bar = 0;
294
295 if (idx < 4) {
296 /* first four channels map to 0, 0x100, 0x200, 0x300 */
297 offset += idx * board->uart_offset;
298 } else if (idx < 8) {
299 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
300 offset += idx * board->uart_offset + 0xC00;
301 } else /* we have only 8 ports on PMC-OCTALPRO */
302 return 1;
303
70db3d91 304 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 305}
306
307/*
308* This does initialization for PMC OCTALPRO cards:
309* maps the device memory, resets the UARTs (needed, bc
310* if the module is removed and inserted again, the card
311* is in the sleep mode) and enables global interrupt.
312*/
313
314/* global control register offset for SBS PMC-OctalPro */
315#define OCT_REG_CR_OFF 0x500
316
317static int __devinit sbs_init(struct pci_dev *dev)
318{
319 u8 __iomem *p;
320
321 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
322
323 if (p == NULL)
324 return -ENOMEM;
325 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
326 writeb(0x10,p + OCT_REG_CR_OFF);
327 udelay(50);
328 writeb(0x0,p + OCT_REG_CR_OFF);
329
330 /* Set bit-2 (INTENABLE) of Control Register */
331 writeb(0x4, p + OCT_REG_CR_OFF);
332 iounmap(p);
333
334 return 0;
335}
336
337/*
338 * Disables the global interrupt of PMC-OctalPro
339 */
340
341static void __devexit sbs_exit(struct pci_dev *dev)
342{
343 u8 __iomem *p;
344
345 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
346 if (p != NULL) {
347 writeb(0, p + OCT_REG_CR_OFF);
348 }
349 iounmap(p);
350}
351
352/*
353 * SIIG serial cards have an PCI interface chip which also controls
354 * the UART clocking frequency. Each UART can be clocked independently
355 * (except cards equiped with 4 UARTs) and initial clocking settings
356 * are stored in the EEPROM chip. It can cause problems because this
357 * version of serial driver doesn't support differently clocked UART's
358 * on single PCI card. To prevent this, initialization functions set
359 * high frequency clocking for all UART's on given card. It is safe (I
360 * hope) because it doesn't touch EEPROM settings to prevent conflicts
361 * with other OSes (like M$ DOS).
362 *
363 * SIIG support added by Andrey Panin <[email protected]>, 10/1999
364 *
365 * There is two family of SIIG serial cards with different PCI
366 * interface chip and different configuration methods:
367 * - 10x cards have control registers in IO and/or memory space;
368 * - 20x cards have control registers in standard PCI configuration space.
369 *
67d74b87
RK		 370 * Note: all 10x cards have PCI device ids 0x10..
371 * all 20x cards have PCI device ids 0x20..
372 *
fbc0dc0d
AP		 373 * There are also Quartet Serial cards which use Oxford Semiconductor
374 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
375 *
1da177e4
LT		 376 * Note: some SIIG cards are probed by the parport_serial object.
377 */
378
379#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
380#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
381
382static int pci_siig10x_init(struct pci_dev *dev)
383{
384 u16 data;
385 void __iomem *p;
386
387 switch (dev->device & 0xfff8) {
388 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
389 data = 0xffdf;
390 break;
391 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
392 data = 0xf7ff;
393 break;
394 default: /* 1S1P, 4S */
395 data = 0xfffb;
396 break;
397 }
398
399 p = ioremap(pci_resource_start(dev, 0), 0x80);
400 if (p == NULL)
401 return -ENOMEM;
402
403 writew(readw(p + 0x28) & data, p + 0x28);
404 readw(p + 0x28);
405 iounmap(p);
406 return 0;
407}
408
409#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
410#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
411
412static int pci_siig20x_init(struct pci_dev *dev)
413{
414 u8 data;
415
416 /* Change clock frequency for the first UART. */
417 pci_read_config_byte(dev, 0x6f, &data);
418 pci_write_config_byte(dev, 0x6f, data & 0xef);
419
420 /* If this card has 2 UART, we have to do the same with second UART. */
421 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
422 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
423 pci_read_config_byte(dev, 0x73, &data);
424 pci_write_config_byte(dev, 0x73, data & 0xef);
425 }
426 return 0;
427}
428
67d74b87
RK		 429static int pci_siig_init(struct pci_dev *dev)
430{
431 unsigned int type = dev->device & 0xff00;
432
433 if (type == 0x1000)
434 return pci_siig10x_init(dev);
435 else if (type == 0x2000)
436 return pci_siig20x_init(dev);
437
438 moan_device("Unknown SIIG card", dev);
439 return -ENODEV;
440}
441
1da177e4
LT		 442/*
443 * Timedia has an explosion of boards, and to avoid the PCI table from
444 * growing *huge*, we use this function to collapse some 70 entries
445 * in the PCI table into one, for sanity's and compactness's sake.
446 */
447static unsigned short timedia_single_port[] = {
448 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
449};
450
451static unsigned short timedia_dual_port[] = {
452 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
453 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
454 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
455 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
456 0xD079, 0
457};
458
459static unsigned short timedia_quad_port[] = {
460 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
461 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
462 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
463 0xB157, 0
464};
465
466static unsigned short timedia_eight_port[] = {
467 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
468 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
469};
470
cb3592be 471static const struct timedia_struct {
1da177e4
LT		 472 int num;
473 unsigned short *ids;
474} timedia_data[] = {
475 { 1, timedia_single_port },
476 { 2, timedia_dual_port },
477 { 4, timedia_quad_port },
478 { 8, timedia_eight_port },
479 { 0, NULL }
480};
481
482static int __devinit pci_timedia_init(struct pci_dev *dev)
483{
484 unsigned short *ids;
485 int i, j;
486
487 for (i = 0; timedia_data[i].num; i++) {
488 ids = timedia_data[i].ids;
489 for (j = 0; ids[j]; j++)
490 if (dev->subsystem_device == ids[j])
491 return timedia_data[i].num;
492 }
493 return 0;
494}
495
496/*
497 * Timedia/SUNIX uses a mixture of BARs and offsets
498 * Ugh, this is ugly as all hell --- TYT
499 */
500static int
70db3d91 501pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 502 struct uart_port *port, int idx)
503{
504 unsigned int bar = 0, offset = board->first_offset;
505
506 switch (idx) {
507 case 0:
508 bar = 0;
509 break;
510 case 1:
511 offset = board->uart_offset;
512 bar = 0;
513 break;
514 case 2:
515 bar = 1;
516 break;
517 case 3:
518 offset = board->uart_offset;
519 bar = 1;
520 case 4: /* BAR 2 */
521 case 5: /* BAR 3 */
522 case 6: /* BAR 4 */
523 case 7: /* BAR 5 */
524 bar = idx - 2;
525 }
526
70db3d91 527 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 528}
529
530/*
531 * Some Titan cards are also a little weird
532 */
533static int
70db3d91 534titan_400l_800l_setup(struct serial_private *priv,
1c7c1fe5 535 struct pciserial_board *board,
1da177e4
LT		 536 struct uart_port *port, int idx)
537{
538 unsigned int bar, offset = board->first_offset;
539
540 switch (idx) {
541 case 0:
542 bar = 1;
543 break;
544 case 1:
545 bar = 2;
546 break;
547 default:
548 bar = 4;
549 offset = (idx - 2) * board->uart_offset;
550 }
551
70db3d91 552 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 553}
554
555static int __devinit pci_xircom_init(struct pci_dev *dev)
556{
557 msleep(100);
558 return 0;
559}
560
561static int __devinit pci_netmos_init(struct pci_dev *dev)
562{
563 /* subdevice 0x00PS means <P> parallel, <S> serial */
564 unsigned int num_serial = dev->subsystem_device & 0xf;
565
566 if (num_serial == 0)
567 return -ENODEV;
568 return num_serial;
569}
570
571static int
70db3d91 572pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
1da177e4
LT		 573 struct uart_port *port, int idx)
574{
575 unsigned int bar, offset = board->first_offset, maxnr;
576
577 bar = FL_GET_BASE(board->flags);
578 if (board->flags & FL_BASE_BARS)
579 bar += idx;
580 else
581 offset += idx * board->uart_offset;
582
70db3d91 583 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
1da177e4
LT		 584 (8 << board->reg_shift);
585
586 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
587 return 1;
588
70db3d91 589 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 590}
591
592/* This should be in linux/pci_ids.h */
593#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
594#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
595#define PCI_DEVICE_ID_OCTPRO 0x0001
596#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
597#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
598#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
599#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
600
601/*
602 * Master list of serial port init/setup/exit quirks.
603 * This does not describe the general nature of the port.
604 * (ie, baud base, number and location of ports, etc)
605 *
606 * This list is ordered alphabetically by vendor then device.
607 * Specific entries must come before more generic entries.
608 */
609static struct pci_serial_quirk pci_serial_quirks[] = {
610 /*
611 * AFAVLAB cards.
612 * It is not clear whether this applies to all products.
613 */
614 {
615 .vendor = PCI_VENDOR_ID_AFAVLAB,
616 .device = PCI_ANY_ID,
617 .subvendor = PCI_ANY_ID,
618 .subdevice = PCI_ANY_ID,
619 .setup = afavlab_setup,
620 },
621 /*
622 * HP Diva
623 */
624 {
625 .vendor = PCI_VENDOR_ID_HP,
626 .device = PCI_DEVICE_ID_HP_DIVA,
627 .subvendor = PCI_ANY_ID,
628 .subdevice = PCI_ANY_ID,
629 .init = pci_hp_diva_init,
630 .setup = pci_hp_diva_setup,
631 },
632 /*
633 * Intel
634 */
635 {
636 .vendor = PCI_VENDOR_ID_INTEL,
637 .device = PCI_DEVICE_ID_INTEL_80960_RP,
638 .subvendor = 0xe4bf,
639 .subdevice = PCI_ANY_ID,
640 .init = pci_inteli960ni_init,
641 .setup = pci_default_setup,
642 },
643 /*
644 * Panacom
645 */
646 {
647 .vendor = PCI_VENDOR_ID_PANACOM,
648 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
649 .subvendor = PCI_ANY_ID,
650 .subdevice = PCI_ANY_ID,
651 .init = pci_plx9050_init,
652 .setup = pci_default_setup,
653 .exit = __devexit_p(pci_plx9050_exit),
654 },
655 {
656 .vendor = PCI_VENDOR_ID_PANACOM,
657 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
658 .subvendor = PCI_ANY_ID,
659 .subdevice = PCI_ANY_ID,
660 .init = pci_plx9050_init,
661 .setup = pci_default_setup,
662 .exit = __devexit_p(pci_plx9050_exit),
663 },
664 /*
665 * PLX
666 */
add7b58e
BH		 667 {
668 .vendor = PCI_VENDOR_ID_PLX,
669 .device = PCI_DEVICE_ID_PLX_9050,
670 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
671 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
672 .init = pci_plx9050_init,
673 .setup = pci_default_setup,
674 .exit = __devexit_p(pci_plx9050_exit),
675 },
1da177e4
LT		 676 {
677 .vendor = PCI_VENDOR_ID_PLX,
678 .device = PCI_DEVICE_ID_PLX_9050,
679 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
680 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
681 .init = pci_plx9050_init,
682 .setup = pci_default_setup,
683 .exit = __devexit_p(pci_plx9050_exit),
684 },
685 {
686 .vendor = PCI_VENDOR_ID_PLX,
687 .device = PCI_DEVICE_ID_PLX_ROMULUS,
688 .subvendor = PCI_VENDOR_ID_PLX,
689 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
690 .init = pci_plx9050_init,
691 .setup = pci_default_setup,
692 .exit = __devexit_p(pci_plx9050_exit),
693 },
694 /*
695 * SBS Technologies, Inc., PMC-OCTALPRO 232
696 */
697 {
698 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
699 .device = PCI_DEVICE_ID_OCTPRO,
700 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
701 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
702 .init = sbs_init,
703 .setup = sbs_setup,
704 .exit = __devexit_p(sbs_exit),
705 },
706 /*
707 * SBS Technologies, Inc., PMC-OCTALPRO 422
708 */
709 {
710 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
711 .device = PCI_DEVICE_ID_OCTPRO,
712 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
713 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
714 .init = sbs_init,
715 .setup = sbs_setup,
716 .exit = __devexit_p(sbs_exit),
717 },
718 /*
719 * SBS Technologies, Inc., P-Octal 232
720 */
721 {
722 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
723 .device = PCI_DEVICE_ID_OCTPRO,
724 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
725 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
726 .init = sbs_init,
727 .setup = sbs_setup,
728 .exit = __devexit_p(sbs_exit),
729 },
730 /*
731 * SBS Technologies, Inc., P-Octal 422
732 */
733 {
734 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
735 .device = PCI_DEVICE_ID_OCTPRO,
736 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
737 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
738 .init = sbs_init,
739 .setup = sbs_setup,
740 .exit = __devexit_p(sbs_exit),
741 },
1da177e4
LT		 742 /*
743 * SIIG cards.
1da177e4
LT		 744 */
745 {
746 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 747 .device = PCI_ANY_ID,
1da177e4
LT		 748 .subvendor = PCI_ANY_ID,
749 .subdevice = PCI_ANY_ID,
67d74b87 750 .init = pci_siig_init,
1da177e4
LT		 751 .setup = pci_default_setup,
752 },
753 /*
754 * Titan cards
755 */
756 {
757 .vendor = PCI_VENDOR_ID_TITAN,
758 .device = PCI_DEVICE_ID_TITAN_400L,
759 .subvendor = PCI_ANY_ID,
760 .subdevice = PCI_ANY_ID,
761 .setup = titan_400l_800l_setup,
762 },
763 {
764 .vendor = PCI_VENDOR_ID_TITAN,
765 .device = PCI_DEVICE_ID_TITAN_800L,
766 .subvendor = PCI_ANY_ID,
767 .subdevice = PCI_ANY_ID,
768 .setup = titan_400l_800l_setup,
769 },
770 /*
771 * Timedia cards
772 */
773 {
774 .vendor = PCI_VENDOR_ID_TIMEDIA,
775 .device = PCI_DEVICE_ID_TIMEDIA_1889,
776 .subvendor = PCI_VENDOR_ID_TIMEDIA,
777 .subdevice = PCI_ANY_ID,
778 .init = pci_timedia_init,
779 .setup = pci_timedia_setup,
780 },
781 {
782 .vendor = PCI_VENDOR_ID_TIMEDIA,
783 .device = PCI_ANY_ID,
784 .subvendor = PCI_ANY_ID,
785 .subdevice = PCI_ANY_ID,
786 .setup = pci_timedia_setup,
787 },
788 /*
789 * Xircom cards
790 */
791 {
792 .vendor = PCI_VENDOR_ID_XIRCOM,
793 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
794 .subvendor = PCI_ANY_ID,
795 .subdevice = PCI_ANY_ID,
796 .init = pci_xircom_init,
797 .setup = pci_default_setup,
798 },
799 /*
800 * Netmos cards
801 */
802 {
803 .vendor = PCI_VENDOR_ID_NETMOS,
804 .device = PCI_ANY_ID,
805 .subvendor = PCI_ANY_ID,
806 .subdevice = PCI_ANY_ID,
807 .init = pci_netmos_init,
808 .setup = pci_default_setup,
809 },
810 /*
811 * Default "match everything" terminator entry
812 */
813 {
814 .vendor = PCI_ANY_ID,
815 .device = PCI_ANY_ID,
816 .subvendor = PCI_ANY_ID,
817 .subdevice = PCI_ANY_ID,
818 .setup = pci_default_setup,
819 }
820};
821
822static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
823{
824 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
825}
826
827static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
828{
829 struct pci_serial_quirk *quirk;
830
831 for (quirk = pci_serial_quirks; ; quirk++)
832 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
833 quirk_id_matches(quirk->device, dev->device) &&
834 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
835 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
836 break;
837 return quirk;
838}
839
840static _INLINE_ int
72ce9a83 841get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
1da177e4
LT		 842{
843 if (board->flags & FL_NOIRQ)
844 return 0;
845 else
846 return dev->irq;
847}
848
849/*
850 * This is the configuration table for all of the PCI serial boards
851 * which we support. It is directly indexed by the pci_board_num_t enum
852 * value, which is encoded in the pci_device_id PCI probe table's
853 * driver_data member.
854 *
855 * The makeup of these names are:
856 * pbn_bn{_bt}_n_baud
857 *
858 * bn = PCI BAR number
859 * bt = Index using PCI BARs
860 * n = number of serial ports
861 * baud = baud rate
862 *
f1690f37
RK		 863 * This table is sorted by (in order): baud, bt, bn, n.
864 *
1da177e4
LT		 865 * Please note: in theory if n = 1, _bt infix should make no difference.
866 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
867 */
868enum pci_board_num_t {
869 pbn_default = 0,
870
871 pbn_b0_1_115200,
872 pbn_b0_2_115200,
873 pbn_b0_4_115200,
874 pbn_b0_5_115200,
875
876 pbn_b0_1_921600,
877 pbn_b0_2_921600,
878 pbn_b0_4_921600,
879
db1de159
DR		 880 pbn_b0_2_1130000,
881
fbc0dc0d
AP		 882 pbn_b0_4_1152000,
883
1da177e4
LT		 884 pbn_b0_bt_1_115200,
885 pbn_b0_bt_2_115200,
886 pbn_b0_bt_8_115200,
887
888 pbn_b0_bt_1_460800,
889 pbn_b0_bt_2_460800,
890 pbn_b0_bt_4_460800,
891
892 pbn_b0_bt_1_921600,
893 pbn_b0_bt_2_921600,
894 pbn_b0_bt_4_921600,
895 pbn_b0_bt_8_921600,
896
897 pbn_b1_1_115200,
898 pbn_b1_2_115200,
899 pbn_b1_4_115200,
900 pbn_b1_8_115200,
901
902 pbn_b1_1_921600,
903 pbn_b1_2_921600,
904 pbn_b1_4_921600,
905 pbn_b1_8_921600,
906
907 pbn_b1_bt_2_921600,
908
909 pbn_b1_1_1382400,
910 pbn_b1_2_1382400,
911 pbn_b1_4_1382400,
912 pbn_b1_8_1382400,
913
914 pbn_b2_1_115200,
915 pbn_b2_8_115200,
916
917 pbn_b2_1_460800,
918 pbn_b2_4_460800,
919 pbn_b2_8_460800,
920 pbn_b2_16_460800,
921
922 pbn_b2_1_921600,
923 pbn_b2_4_921600,
924 pbn_b2_8_921600,
925
926 pbn_b2_bt_1_115200,
927 pbn_b2_bt_2_115200,
928 pbn_b2_bt_4_115200,
929
930 pbn_b2_bt_2_921600,
931 pbn_b2_bt_4_921600,
932
933 pbn_b3_4_115200,
934 pbn_b3_8_115200,
935
936 /*
937 * Board-specific versions.
938 */
939 pbn_panacom,
940 pbn_panacom2,
941 pbn_panacom4,
add7b58e 942 pbn_exsys_4055,
1da177e4
LT		 943 pbn_plx_romulus,
944 pbn_oxsemi,
945 pbn_intel_i960,
946 pbn_sgi_ioc3,
947 pbn_nec_nile4,
948 pbn_computone_4,
949 pbn_computone_6,
950 pbn_computone_8,
951 pbn_sbsxrsio,
952 pbn_exar_XR17C152,
953 pbn_exar_XR17C154,
954 pbn_exar_XR17C158,
955};
956
957/*
958 * uart_offset - the space between channels
959 * reg_shift - describes how the UART registers are mapped
960 * to PCI memory by the card.
961 * For example IER register on SBS, Inc. PMC-OctPro is located at
962 * offset 0x10 from the UART base, while UART_IER is defined as 1
963 * in include/linux/serial_reg.h,
964 * see first lines of serial_in() and serial_out() in 8250.c
965*/
966
1c7c1fe5 967static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 968 [pbn_default] = {
969 .flags = FL_BASE0,
970 .num_ports = 1,
971 .base_baud = 115200,
972 .uart_offset = 8,
973 },
974 [pbn_b0_1_115200] = {
975 .flags = FL_BASE0,
976 .num_ports = 1,
977 .base_baud = 115200,
978 .uart_offset = 8,
979 },
980 [pbn_b0_2_115200] = {
981 .flags = FL_BASE0,
982 .num_ports = 2,
983 .base_baud = 115200,
984 .uart_offset = 8,
985 },
986 [pbn_b0_4_115200] = {
987 .flags = FL_BASE0,
988 .num_ports = 4,
989 .base_baud = 115200,
990 .uart_offset = 8,
991 },
992 [pbn_b0_5_115200] = {
993 .flags = FL_BASE0,
994 .num_ports = 5,
995 .base_baud = 115200,
996 .uart_offset = 8,
997 },
998
999 [pbn_b0_1_921600] = {
1000 .flags = FL_BASE0,
1001 .num_ports = 1,
1002 .base_baud = 921600,
1003 .uart_offset = 8,
1004 },
1005 [pbn_b0_2_921600] = {
1006 .flags = FL_BASE0,
1007 .num_ports = 2,
1008 .base_baud = 921600,
1009 .uart_offset = 8,
1010 },
1011 [pbn_b0_4_921600] = {
1012 .flags = FL_BASE0,
1013 .num_ports = 4,
1014 .base_baud = 921600,
1015 .uart_offset = 8,
1016 },
db1de159
DR		 1017
1018 [pbn_b0_2_1130000] = {
1019 .flags = FL_BASE0,
1020 .num_ports = 2,
1021 .base_baud = 1130000,
1022 .uart_offset = 8,
1023 },
1024
fbc0dc0d
AP		 1025 [pbn_b0_4_1152000] = {
1026 .flags = FL_BASE0,
1027 .num_ports = 4,
1028 .base_baud = 1152000,
1029 .uart_offset = 8,
1030 },
1da177e4
LT		 1031
1032 [pbn_b0_bt_1_115200] = {
1033 .flags = FL_BASE0|FL_BASE_BARS,
1034 .num_ports = 1,
1035 .base_baud = 115200,
1036 .uart_offset = 8,
1037 },
1038 [pbn_b0_bt_2_115200] = {
1039 .flags = FL_BASE0|FL_BASE_BARS,
1040 .num_ports = 2,
1041 .base_baud = 115200,
1042 .uart_offset = 8,
1043 },
1044 [pbn_b0_bt_8_115200] = {
1045 .flags = FL_BASE0|FL_BASE_BARS,
1046 .num_ports = 8,
1047 .base_baud = 115200,
1048 .uart_offset = 8,
1049 },
1050
1051 [pbn_b0_bt_1_460800] = {
1052 .flags = FL_BASE0|FL_BASE_BARS,
1053 .num_ports = 1,
1054 .base_baud = 460800,
1055 .uart_offset = 8,
1056 },
1057 [pbn_b0_bt_2_460800] = {
1058 .flags = FL_BASE0|FL_BASE_BARS,
1059 .num_ports = 2,
1060 .base_baud = 460800,
1061 .uart_offset = 8,
1062 },
1063 [pbn_b0_bt_4_460800] = {
1064 .flags = FL_BASE0|FL_BASE_BARS,
1065 .num_ports = 4,
1066 .base_baud = 460800,
1067 .uart_offset = 8,
1068 },
1069
1070 [pbn_b0_bt_1_921600] = {
1071 .flags = FL_BASE0|FL_BASE_BARS,
1072 .num_ports = 1,
1073 .base_baud = 921600,
1074 .uart_offset = 8,
1075 },
1076 [pbn_b0_bt_2_921600] = {
1077 .flags = FL_BASE0|FL_BASE_BARS,
1078 .num_ports = 2,
1079 .base_baud = 921600,
1080 .uart_offset = 8,
1081 },
1082 [pbn_b0_bt_4_921600] = {
1083 .flags = FL_BASE0|FL_BASE_BARS,
1084 .num_ports = 4,
1085 .base_baud = 921600,
1086 .uart_offset = 8,
1087 },
1088 [pbn_b0_bt_8_921600] = {
1089 .flags = FL_BASE0|FL_BASE_BARS,
1090 .num_ports = 8,
1091 .base_baud = 921600,
1092 .uart_offset = 8,
1093 },
1094
1095 [pbn_b1_1_115200] = {
1096 .flags = FL_BASE1,
1097 .num_ports = 1,
1098 .base_baud = 115200,
1099 .uart_offset = 8,
1100 },
1101 [pbn_b1_2_115200] = {
1102 .flags = FL_BASE1,
1103 .num_ports = 2,
1104 .base_baud = 115200,
1105 .uart_offset = 8,
1106 },
1107 [pbn_b1_4_115200] = {
1108 .flags = FL_BASE1,
1109 .num_ports = 4,
1110 .base_baud = 115200,
1111 .uart_offset = 8,
1112 },
1113 [pbn_b1_8_115200] = {
1114 .flags = FL_BASE1,
1115 .num_ports = 8,
1116 .base_baud = 115200,
1117 .uart_offset = 8,
1118 },
1119
1120 [pbn_b1_1_921600] = {
1121 .flags = FL_BASE1,
1122 .num_ports = 1,
1123 .base_baud = 921600,
1124 .uart_offset = 8,
1125 },
1126 [pbn_b1_2_921600] = {
1127 .flags = FL_BASE1,
1128 .num_ports = 2,
1129 .base_baud = 921600,
1130 .uart_offset = 8,
1131 },
1132 [pbn_b1_4_921600] = {
1133 .flags = FL_BASE1,
1134 .num_ports = 4,
1135 .base_baud = 921600,
1136 .uart_offset = 8,
1137 },
1138 [pbn_b1_8_921600] = {
1139 .flags = FL_BASE1,
1140 .num_ports = 8,
1141 .base_baud = 921600,
1142 .uart_offset = 8,
1143 },
1144
1145 [pbn_b1_bt_2_921600] = {
1146 .flags = FL_BASE1|FL_BASE_BARS,
1147 .num_ports = 2,
1148 .base_baud = 921600,
1149 .uart_offset = 8,
1150 },
1151
1152 [pbn_b1_1_1382400] = {
1153 .flags = FL_BASE1,
1154 .num_ports = 1,
1155 .base_baud = 1382400,
1156 .uart_offset = 8,
1157 },
1158 [pbn_b1_2_1382400] = {
1159 .flags = FL_BASE1,
1160 .num_ports = 2,
1161 .base_baud = 1382400,
1162 .uart_offset = 8,
1163 },
1164 [pbn_b1_4_1382400] = {
1165 .flags = FL_BASE1,
1166 .num_ports = 4,
1167 .base_baud = 1382400,
1168 .uart_offset = 8,
1169 },
1170 [pbn_b1_8_1382400] = {
1171 .flags = FL_BASE1,
1172 .num_ports = 8,
1173 .base_baud = 1382400,
1174 .uart_offset = 8,
1175 },
1176
1177 [pbn_b2_1_115200] = {
1178 .flags = FL_BASE2,
1179 .num_ports = 1,
1180 .base_baud = 115200,
1181 .uart_offset = 8,
1182 },
1183 [pbn_b2_8_115200] = {
1184 .flags = FL_BASE2,
1185 .num_ports = 8,
1186 .base_baud = 115200,
1187 .uart_offset = 8,
1188 },
1189
1190 [pbn_b2_1_460800] = {
1191 .flags = FL_BASE2,
1192 .num_ports = 1,
1193 .base_baud = 460800,
1194 .uart_offset = 8,
1195 },
1196 [pbn_b2_4_460800] = {
1197 .flags = FL_BASE2,
1198 .num_ports = 4,
1199 .base_baud = 460800,
1200 .uart_offset = 8,
1201 },
1202 [pbn_b2_8_460800] = {
1203 .flags = FL_BASE2,
1204 .num_ports = 8,
1205 .base_baud = 460800,
1206 .uart_offset = 8,
1207 },
1208 [pbn_b2_16_460800] = {
1209 .flags = FL_BASE2,
1210 .num_ports = 16,
1211 .base_baud = 460800,
1212 .uart_offset = 8,
1213 },
1214
1215 [pbn_b2_1_921600] = {
1216 .flags = FL_BASE2,
1217 .num_ports = 1,
1218 .base_baud = 921600,
1219 .uart_offset = 8,
1220 },
1221 [pbn_b2_4_921600] = {
1222 .flags = FL_BASE2,
1223 .num_ports = 4,
1224 .base_baud = 921600,
1225 .uart_offset = 8,
1226 },
1227 [pbn_b2_8_921600] = {
1228 .flags = FL_BASE2,
1229 .num_ports = 8,
1230 .base_baud = 921600,
1231 .uart_offset = 8,
1232 },
1233
1234 [pbn_b2_bt_1_115200] = {
1235 .flags = FL_BASE2|FL_BASE_BARS,
1236 .num_ports = 1,
1237 .base_baud = 115200,
1238 .uart_offset = 8,
1239 },
1240 [pbn_b2_bt_2_115200] = {
1241 .flags = FL_BASE2|FL_BASE_BARS,
1242 .num_ports = 2,
1243 .base_baud = 115200,
1244 .uart_offset = 8,
1245 },
1246 [pbn_b2_bt_4_115200] = {
1247 .flags = FL_BASE2|FL_BASE_BARS,
1248 .num_ports = 4,
1249 .base_baud = 115200,
1250 .uart_offset = 8,
1251 },
1252
1253 [pbn_b2_bt_2_921600] = {
1254 .flags = FL_BASE2|FL_BASE_BARS,
1255 .num_ports = 2,
1256 .base_baud = 921600,
1257 .uart_offset = 8,
1258 },
1259 [pbn_b2_bt_4_921600] = {
1260 .flags = FL_BASE2|FL_BASE_BARS,
1261 .num_ports = 4,
1262 .base_baud = 921600,
1263 .uart_offset = 8,
1264 },
1265
1266 [pbn_b3_4_115200] = {
1267 .flags = FL_BASE3,
1268 .num_ports = 4,
1269 .base_baud = 115200,
1270 .uart_offset = 8,
1271 },
1272 [pbn_b3_8_115200] = {
1273 .flags = FL_BASE3,
1274 .num_ports = 8,
1275 .base_baud = 115200,
1276 .uart_offset = 8,
1277 },
1278
1279 /*
1280 * Entries following this are board-specific.
1281 */
1282
1283 /*
1284 * Panacom - IOMEM
1285 */
1286 [pbn_panacom] = {
1287 .flags = FL_BASE2,
1288 .num_ports = 2,
1289 .base_baud = 921600,
1290 .uart_offset = 0x400,
1291 .reg_shift = 7,
1292 },
1293 [pbn_panacom2] = {
1294 .flags = FL_BASE2|FL_BASE_BARS,
1295 .num_ports = 2,
1296 .base_baud = 921600,
1297 .uart_offset = 0x400,
1298 .reg_shift = 7,
1299 },
1300 [pbn_panacom4] = {
1301 .flags = FL_BASE2|FL_BASE_BARS,
1302 .num_ports = 4,
1303 .base_baud = 921600,
1304 .uart_offset = 0x400,
1305 .reg_shift = 7,
1306 },
1307
add7b58e
BH		 1308 [pbn_exsys_4055] = {
1309 .flags = FL_BASE2,
1310 .num_ports = 4,
1311 .base_baud = 115200,
1312 .uart_offset = 8,
1313 },
1314
1da177e4
LT		 1315 /* I think this entry is broken - the first_offset looks wrong --rmk */
1316 [pbn_plx_romulus] = {
1317 .flags = FL_BASE2,
1318 .num_ports = 4,
1319 .base_baud = 921600,
1320 .uart_offset = 8 << 2,
1321 .reg_shift = 2,
1322 .first_offset = 0x03,
1323 },
1324
1325 /*
1326 * This board uses the size of PCI Base region 0 to
1327 * signal now many ports are available
1328 */
1329 [pbn_oxsemi] = {
1330 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1331 .num_ports = 32,
1332 .base_baud = 115200,
1333 .uart_offset = 8,
1334 },
1335
1336 /*
1337 * EKF addition for i960 Boards form EKF with serial port.
1338 * Max 256 ports.
1339 */
1340 [pbn_intel_i960] = {
1341 .flags = FL_BASE0,
1342 .num_ports = 32,
1343 .base_baud = 921600,
1344 .uart_offset = 8 << 2,
1345 .reg_shift = 2,
1346 .first_offset = 0x10000,
1347 },
1348 [pbn_sgi_ioc3] = {
1349 .flags = FL_BASE0|FL_NOIRQ,
1350 .num_ports = 1,
1351 .base_baud = 458333,
1352 .uart_offset = 8,
1353 .reg_shift = 0,
1354 .first_offset = 0x20178,
1355 },
1356
1357 /*
1358 * NEC Vrc-5074 (Nile 4) builtin UART.
1359 */
1360 [pbn_nec_nile4] = {
1361 .flags = FL_BASE0,
1362 .num_ports = 1,
1363 .base_baud = 520833,
1364 .uart_offset = 8 << 3,
1365 .reg_shift = 3,
1366 .first_offset = 0x300,
1367 },
1368
1369 /*
1370 * Computone - uses IOMEM.
1371 */
1372 [pbn_computone_4] = {
1373 .flags = FL_BASE0,
1374 .num_ports = 4,
1375 .base_baud = 921600,
1376 .uart_offset = 0x40,
1377 .reg_shift = 2,
1378 .first_offset = 0x200,
1379 },
1380 [pbn_computone_6] = {
1381 .flags = FL_BASE0,
1382 .num_ports = 6,
1383 .base_baud = 921600,
1384 .uart_offset = 0x40,
1385 .reg_shift = 2,
1386 .first_offset = 0x200,
1387 },
1388 [pbn_computone_8] = {
1389 .flags = FL_BASE0,
1390 .num_ports = 8,
1391 .base_baud = 921600,
1392 .uart_offset = 0x40,
1393 .reg_shift = 2,
1394 .first_offset = 0x200,
1395 },
1396 [pbn_sbsxrsio] = {
1397 .flags = FL_BASE0,
1398 .num_ports = 8,
1399 .base_baud = 460800,
1400 .uart_offset = 256,
1401 .reg_shift = 4,
1402 },
1403 /*
1404 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1405 * Only basic 16550A support.
1406 * XR17C15[24] are not tested, but they should work.
1407 */
1408 [pbn_exar_XR17C152] = {
1409 .flags = FL_BASE0,
1410 .num_ports = 2,
1411 .base_baud = 921600,
1412 .uart_offset = 0x200,
1413 },
1414 [pbn_exar_XR17C154] = {
1415 .flags = FL_BASE0,
1416 .num_ports = 4,
1417 .base_baud = 921600,
1418 .uart_offset = 0x200,
1419 },
1420 [pbn_exar_XR17C158] = {
1421 .flags = FL_BASE0,
1422 .num_ports = 8,
1423 .base_baud = 921600,
1424 .uart_offset = 0x200,
1425 },
1426};
1427
1428/*
1429 * Given a complete unknown PCI device, try to use some heuristics to
1430 * guess what the configuration might be, based on the pitiful PCI
1431 * serial specs. Returns 0 on success, 1 on failure.
1432 */
1433static int __devinit
1c7c1fe5 1434serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4
LT		 1435{
1436 int num_iomem, num_port, first_port = -1, i;
1437
1438 /*
1439 * If it is not a communications device or the programming
1440 * interface is greater than 6, give up.
1441 *
1442 * (Should we try to make guesses for multiport serial devices
1443 * later?)
1444 */
1445 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1446 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1447 (dev->class & 0xff) > 6)
1448 return -ENODEV;
1449
1450 num_iomem = num_port = 0;
1451 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1452 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1453 num_port++;
1454 if (first_port == -1)
1455 first_port = i;
1456 }
1457 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1458 num_iomem++;
1459 }
1460
1461 /*
1462 * If there is 1 or 0 iomem regions, and exactly one port,
1463 * use it. We guess the number of ports based on the IO
1464 * region size.
1465 */
1466 if (num_iomem <= 1 && num_port == 1) {
1467 board->flags = first_port;
1468 board->num_ports = pci_resource_len(dev, first_port) / 8;
1469 return 0;
1470 }
1471
1472 /*
1473 * Now guess if we've got a board which indexes by BARs.
1474 * Each IO BAR should be 8 bytes, and they should follow
1475 * consecutively.
1476 */
1477 first_port = -1;
1478 num_port = 0;
1479 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1480 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1481 pci_resource_len(dev, i) == 8 &&
1482 (first_port == -1 || (first_port + num_port) == i)) {
1483 num_port++;
1484 if (first_port == -1)
1485 first_port = i;
1486 }
1487 }
1488
1489 if (num_port > 1) {
1490 board->flags = first_port | FL_BASE_BARS;
1491 board->num_ports = num_port;
1492 return 0;
1493 }
1494
1495 return -ENODEV;
1496}
1497
1498static inline int
1c7c1fe5
RK		 1499serial_pci_matches(struct pciserial_board *board,
1500 struct pciserial_board *guessed)
1da177e4
LT		 1501{
1502 return
1503 board->num_ports == guessed->num_ports &&
1504 board->base_baud == guessed->base_baud &&
1505 board->uart_offset == guessed->uart_offset &&
1506 board->reg_shift == guessed->reg_shift &&
1507 board->first_offset == guessed->first_offset;
1508}
1509
241fc436
RK		 1510struct serial_private *
1511pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 1512{
72ce9a83 1513 struct uart_port serial_port;
1da177e4 1514 struct serial_private *priv;
1da177e4
LT		 1515 struct pci_serial_quirk *quirk;
1516 int rc, nr_ports, i;
1517
1da177e4
LT		 1518 nr_ports = board->num_ports;
1519
1520 /*
1521 * Find an init and setup quirks.
1522 */
1523 quirk = find_quirk(dev);
1524
1525 /*
1526 * Run the new-style initialization function.
1527 * The initialization function returns:
1528 * <0 - error
1529 * 0 - use board->num_ports
1530 * >0 - number of ports
1531 */
1532 if (quirk->init) {
1533 rc = quirk->init(dev);
241fc436
RK		 1534 if (rc < 0) {
1535 priv = ERR_PTR(rc);
1536 goto err_out;
1537 }
1da177e4
LT		 1538 if (rc)
1539 nr_ports = rc;
1540 }
1541
1542 priv = kmalloc(sizeof(struct serial_private) +
1543 sizeof(unsigned int) * nr_ports,
1544 GFP_KERNEL);
1545 if (!priv) {
241fc436
RK		 1546 priv = ERR_PTR(-ENOMEM);
1547 goto err_deinit;
1da177e4
LT		 1548 }
1549
1550 memset(priv, 0, sizeof(struct serial_private) +
1551 sizeof(unsigned int) * nr_ports);
1552
70db3d91 1553 priv->dev = dev;
1da177e4 1554 priv->quirk = quirk;
1da177e4 1555
72ce9a83
RK		 1556 memset(&serial_port, 0, sizeof(struct uart_port));
1557 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1558 serial_port.uartclk = board->base_baud * 16;
1559 serial_port.irq = get_pci_irq(dev, board);
1560 serial_port.dev = &dev->dev;
1561
1da177e4 1562 for (i = 0; i < nr_ports; i++) {
70db3d91 1563 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 1564 break;
72ce9a83 1565
1da177e4
LT		 1566#ifdef SERIAL_DEBUG_PCI
1567 printk("Setup PCI port: port %x, irq %d, type %d\n",
1568 serial_port.iobase, serial_port.irq, serial_port.iotype);
1569#endif
1570
1571 priv->line[i] = serial8250_register_port(&serial_port);
1572 if (priv->line[i] < 0) {
1573 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1574 break;
1575 }
1576 }
1577
1578 priv->nr = i;
1579
241fc436 1580 return priv;
1da177e4 1581
241fc436 1582 err_deinit:
1da177e4
LT		 1583 if (quirk->exit)
1584 quirk->exit(dev);
241fc436
RK		 1585 err_out:
1586 return priv;
1da177e4 1587}
241fc436 1588EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 1589
241fc436 1590void pciserial_remove_ports(struct serial_private *priv)
1da177e4 1591{
056a8763
RK		 1592 struct pci_serial_quirk *quirk;
1593 int i;
1da177e4 1594
056a8763
RK		 1595 for (i = 0; i < priv->nr; i++)
1596 serial8250_unregister_port(priv->line[i]);
1da177e4 1597
056a8763
RK		 1598 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1599 if (priv->remapped_bar[i])
1600 iounmap(priv->remapped_bar[i]);
1601 priv->remapped_bar[i] = NULL;
1602 }
1da177e4 1603
056a8763
RK		 1604 /*
1605 * Find the exit quirks.
1606 */
241fc436 1607 quirk = find_quirk(priv->dev);
056a8763 1608 if (quirk->exit)
241fc436
RK		 1609 quirk->exit(priv->dev);
1610
1611 kfree(priv);
1612}
1613EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1614
1615void pciserial_suspend_ports(struct serial_private *priv)
1616{
1617 int i;
1618
1619 for (i = 0; i < priv->nr; i++)
1620 if (priv->line[i] >= 0)
1621 serial8250_suspend_port(priv->line[i]);
1622}
1623EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1624
1625void pciserial_resume_ports(struct serial_private *priv)
1626{
1627 int i;
1628
1629 /*
1630 * Ensure that the board is correctly configured.
1631 */
1632 if (priv->quirk->init)
1633 priv->quirk->init(priv->dev);
1634
1635 for (i = 0; i < priv->nr; i++)
1636 if (priv->line[i] >= 0)
1637 serial8250_resume_port(priv->line[i]);
1638}
1639EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1640
1641/*
1642 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1643 * to the arrangement of serial ports on a PCI card.
1644 */
1645static int __devinit
1646pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1647{
1648 struct serial_private *priv;
1649 struct pciserial_board *board, tmp;
1650 int rc;
1651
1652 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1653 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1654 ent->driver_data);
1655 return -EINVAL;
1656 }
1657
1658 board = &pci_boards[ent->driver_data];
1659
1660 rc = pci_enable_device(dev);
1661 if (rc)
1662 return rc;
1663
1664 if (ent->driver_data == pbn_default) {
1665 /*
1666 * Use a copy of the pci_board entry for this;
1667 * avoid changing entries in the table.
1668 */
1669 memcpy(&tmp, board, sizeof(struct pciserial_board));
1670 board = &tmp;
1671
1672 /*
1673 * We matched one of our class entries. Try to
1674 * determine the parameters of this board.
1675 */
1676 rc = serial_pci_guess_board(dev, board);
1677 if (rc)
1678 goto disable;
1679 } else {
1680 /*
1681 * We matched an explicit entry. If we are able to
1682 * detect this boards settings with our heuristic,
1683 * then we no longer need this entry.
1684 */
1685 memcpy(&tmp, &pci_boards[pbn_default],
1686 sizeof(struct pciserial_board));
1687 rc = serial_pci_guess_board(dev, &tmp);
1688 if (rc == 0 && serial_pci_matches(board, &tmp))
1689 moan_device("Redundant entry in serial pci_table.",
1690 dev);
1691 }
1692
1693 priv = pciserial_init_ports(dev, board);
1694 if (!IS_ERR(priv)) {
1695 pci_set_drvdata(dev, priv);
1696 return 0;
1697 }
1698
1699 rc = PTR_ERR(priv);
1da177e4 1700
241fc436 1701 disable:
056a8763 1702 pci_disable_device(dev);
241fc436
RK		 1703 return rc;
1704}
1da177e4 1705
241fc436
RK		 1706static void __devexit pciserial_remove_one(struct pci_dev *dev)
1707{
1708 struct serial_private *priv = pci_get_drvdata(dev);
1709
1710 pci_set_drvdata(dev, NULL);
1711
1712 pciserial_remove_ports(priv);
1713
1714 pci_disable_device(dev);
1da177e4
LT		 1715}
1716
1717static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1718{
1719 struct serial_private *priv = pci_get_drvdata(dev);
1720
241fc436
RK		 1721 if (priv)
1722 pciserial_suspend_ports(priv);
1da177e4 1723
1da177e4
LT		 1724 pci_save_state(dev);
1725 pci_set_power_state(dev, pci_choose_state(dev, state));
1726 return 0;
1727}
1728
1729static int pciserial_resume_one(struct pci_dev *dev)
1730{
1731 struct serial_private *priv = pci_get_drvdata(dev);
1732
1733 pci_set_power_state(dev, PCI_D0);
1734 pci_restore_state(dev);
1735
1736 if (priv) {
1da177e4
LT		 1737 /*
1738 * The device may have been disabled. Re-enable it.
1739 */
1740 pci_enable_device(dev);
1741
241fc436 1742 pciserial_resume_ports(priv);
1da177e4
LT		 1743 }
1744 return 0;
1745}
1746
1747static struct pci_device_id serial_pci_tbl[] = {
1748 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1749 PCI_SUBVENDOR_ID_CONNECT_TECH,
1750 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1751 pbn_b1_8_1382400 },
1752 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1753 PCI_SUBVENDOR_ID_CONNECT_TECH,
1754 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1755 pbn_b1_4_1382400 },
1756 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1757 PCI_SUBVENDOR_ID_CONNECT_TECH,
1758 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1759 pbn_b1_2_1382400 },
1760 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1761 PCI_SUBVENDOR_ID_CONNECT_TECH,
1762 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1763 pbn_b1_8_1382400 },
1764 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1765 PCI_SUBVENDOR_ID_CONNECT_TECH,
1766 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1767 pbn_b1_4_1382400 },
1768 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1769 PCI_SUBVENDOR_ID_CONNECT_TECH,
1770 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1771 pbn_b1_2_1382400 },
1772 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1773 PCI_SUBVENDOR_ID_CONNECT_TECH,
1774 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1775 pbn_b1_8_921600 },
1776 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1777 PCI_SUBVENDOR_ID_CONNECT_TECH,
1778 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1779 pbn_b1_8_921600 },
1780 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1781 PCI_SUBVENDOR_ID_CONNECT_TECH,
1782 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1783 pbn_b1_4_921600 },
1784 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1785 PCI_SUBVENDOR_ID_CONNECT_TECH,
1786 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1787 pbn_b1_4_921600 },
1788 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1789 PCI_SUBVENDOR_ID_CONNECT_TECH,
1790 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1791 pbn_b1_2_921600 },
1792 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1793 PCI_SUBVENDOR_ID_CONNECT_TECH,
1794 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1795 pbn_b1_8_921600 },
1796 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1797 PCI_SUBVENDOR_ID_CONNECT_TECH,
1798 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1799 pbn_b1_8_921600 },
1800 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1801 PCI_SUBVENDOR_ID_CONNECT_TECH,
1802 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1803 pbn_b1_4_921600 },
1804
1805 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1807 pbn_b2_bt_1_115200 },
1808 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1810 pbn_b2_bt_2_115200 },
1811 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1813 pbn_b2_bt_4_115200 },
1814 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1816 pbn_b2_bt_2_115200 },
1817 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1819 pbn_b2_bt_4_115200 },
1820 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1822 pbn_b2_8_115200 },
1823 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1825 pbn_b2_8_115200 },
1826
1827 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1828 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1829 pbn_b2_bt_2_115200 },
1830 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1832 pbn_b2_bt_2_921600 },
1833 /*
1834 * VScom SPCOM800, from [email protected]
1835 */
1836 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1837 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1838 pbn_b2_8_921600 },
1839 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1841 pbn_b2_4_921600 },
1842 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1843 PCI_SUBVENDOR_ID_KEYSPAN,
1844 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1845 pbn_panacom },
1846 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1848 pbn_panacom4 },
1849 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1851 pbn_panacom2 },
1852 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1853 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1854 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1855 pbn_b2_4_460800 },
1856 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1857 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1858 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1859 pbn_b2_8_460800 },
1860 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1861 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1862 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1863 pbn_b2_16_460800 },
1864 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1865 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1866 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1867 pbn_b2_16_460800 },
1868 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1869 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1870 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1871 pbn_b2_4_460800 },
1872 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1873 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1874 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1875 pbn_b2_8_460800 },
add7b58e
BH		 1876 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1877 PCI_SUBVENDOR_ID_EXSYS,
1878 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
1879 pbn_exsys_4055 },
1da177e4
LT		 1880 /*
1881 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1882 * ([email protected])
1883 */
1884 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1885 0x10b5, 0x106a, 0, 0,
1886 pbn_plx_romulus },
1887 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1889 pbn_b1_4_115200 },
1890 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1892 pbn_b1_2_115200 },
1893 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1895 pbn_b1_8_115200 },
1896 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1898 pbn_b1_8_115200 },
1899 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1900 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1901 pbn_b0_4_921600 },
fbc0dc0d
AP		 1902 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1903 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
1904 pbn_b0_4_1152000 },
db1de159
DR		 1905
1906 /*
1907 * The below card is a little controversial since it is the
1908 * subject of a PCI vendor/device ID clash. (See
1909 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
1910 * For now just used the hex ID 0x950a.
1911 */
1912 { PCI_VENDOR_ID_OXSEMI, 0x950a,
1913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1914 pbn_b0_2_1130000 },
1da177e4
LT		 1915 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1917 pbn_b0_4_115200 },
1918 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1920 pbn_b0_bt_2_921600 },
1921
1922 /*
1923 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1924 * from [email protected]
1925 */
1926 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1927 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1928 pbn_sbsxrsio },
1929 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1930 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1931 pbn_sbsxrsio },
1932 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1933 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1934 pbn_sbsxrsio },
1935 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1936 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1937 pbn_sbsxrsio },
1938
1939 /*
1940 * Digitan DS560-558, from [email protected]
1941 */
1942 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1944 pbn_b1_1_115200 },
1945
1946 /*
1947 * Titan Electronic cards
1948 * The 400L and 800L have a custom setup quirk.
1949 */
1950 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1952 pbn_b0_1_921600 },
1953 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1955 pbn_b0_2_921600 },
1956 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1958 pbn_b0_4_921600 },
1959 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1961 pbn_b0_4_921600 },
1962 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1964 pbn_b1_1_921600 },
1965 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1967 pbn_b1_bt_2_921600 },
1968 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1970 pbn_b0_bt_4_921600 },
1971 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1973 pbn_b0_bt_8_921600 },
1974
1975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1977 pbn_b2_1_460800 },
1978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1980 pbn_b2_1_460800 },
1981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1983 pbn_b2_1_460800 },
1984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1986 pbn_b2_bt_2_921600 },
1987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989 pbn_b2_bt_2_921600 },
1990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992 pbn_b2_bt_2_921600 },
1993 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1995 pbn_b2_bt_4_921600 },
1996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1998 pbn_b2_bt_4_921600 },
1999 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001 pbn_b2_bt_4_921600 },
2002 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004 pbn_b0_1_921600 },
2005 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007 pbn_b0_1_921600 },
2008 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2010 pbn_b0_1_921600 },
2011 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2013 pbn_b0_bt_2_921600 },
2014 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2016 pbn_b0_bt_2_921600 },
2017 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2019 pbn_b0_bt_2_921600 },
2020 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2022 pbn_b0_bt_4_921600 },
2023 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2025 pbn_b0_bt_4_921600 },
2026 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2028 pbn_b0_bt_4_921600 },
2029
2030 /*
2031 * Computone devices submitted by Doug McNash [email protected]
2032 */
2033 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2034 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2035 0, 0, pbn_computone_4 },
2036 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2037 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2038 0, 0, pbn_computone_8 },
2039 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2040 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2041 0, 0, pbn_computone_6 },
2042
2043 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2045 pbn_oxsemi },
2046 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2047 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2048 pbn_b0_bt_1_921600 },
2049
2050 /*
2051 * AFAVLAB serial card, from Harald Welte <[email protected]>
2052 */
2053 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2055 pbn_b0_bt_8_115200 },
2056 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2058 pbn_b0_bt_8_115200 },
2059
2060 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062 pbn_b0_bt_2_115200 },
2063 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065 pbn_b0_bt_2_115200 },
2066 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2068 pbn_b0_bt_2_115200 },
2069 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071 pbn_b0_bt_4_460800 },
2072 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074 pbn_b0_bt_4_460800 },
2075 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2077 pbn_b0_bt_2_460800 },
2078 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2080 pbn_b0_bt_2_460800 },
2081 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2083 pbn_b0_bt_2_460800 },
2084 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086 pbn_b0_bt_1_115200 },
2087 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2089 pbn_b0_bt_1_460800 },
2090
2091 /*
2092 * Dell Remote Access Card 4 - [email protected]
2093 */
2094 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2096 pbn_b1_1_1382400 },
2097
2098 /*
2099 * Dell Remote Access Card III - [email protected]
2100 */
2101 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2103 pbn_b1_1_1382400 },
2104
2105 /*
2106 * RAStel 2 port modem, [email protected]
2107 */
2108 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2110 pbn_b2_bt_2_115200 },
2111
2112 /*
2113 * EKF addition for i960 Boards form EKF with serial port
2114 */
2115 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2116 0xE4BF, PCI_ANY_ID, 0, 0,
2117 pbn_intel_i960 },
2118
2119 /*
2120 * Xircom Cardbus/Ethernet combos
2121 */
2122 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2124 pbn_b0_1_115200 },
2125 /*
2126 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2127 */
2128 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2130 pbn_b0_1_115200 },
2131
2132 /*
2133 * Untested PCI modems, sent in from various folks...
2134 */
2135
2136 /*
2137 * Elsa Model 56K PCI Modem, from Andreas Rath <[email protected]>
2138 */
2139 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2140 0x1048, 0x1500, 0, 0,
2141 pbn_b1_1_115200 },
2142
2143 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2144 0xFF00, 0, 0, 0,
2145 pbn_sgi_ioc3 },
2146
2147 /*
2148 * HP Diva card
2149 */
2150 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2151 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2152 pbn_b1_1_115200 },
2153 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2155 pbn_b0_5_115200 },
2156 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2158 pbn_b2_1_115200 },
2159
2160 /*
2161 * NEC Vrc-5074 (Nile 4) builtin UART.
2162 */
2163 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2165 pbn_nec_nile4 },
2166
2167 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2169 pbn_b3_4_115200 },
2170 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2172 pbn_b3_8_115200 },
2173
2174 /*
2175 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2176 */
2177 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2178 PCI_ANY_ID, PCI_ANY_ID,
2179 0,
2180 0, pbn_exar_XR17C152 },
2181 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2182 PCI_ANY_ID, PCI_ANY_ID,
2183 0,
2184 0, pbn_exar_XR17C154 },
2185 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2186 PCI_ANY_ID, PCI_ANY_ID,
2187 0,
2188 0, pbn_exar_XR17C158 },
2189
2190 /*
2191 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2192 */
2193 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2195 pbn_b0_1_115200 },
2196
2197 /*
2198 * These entries match devices with class COMMUNICATION_SERIAL,
2199 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2200 */
2201 { PCI_ANY_ID, PCI_ANY_ID,
2202 PCI_ANY_ID, PCI_ANY_ID,
2203 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2204 0xffff00, pbn_default },
2205 { PCI_ANY_ID, PCI_ANY_ID,
2206 PCI_ANY_ID, PCI_ANY_ID,
2207 PCI_CLASS_COMMUNICATION_MODEM << 8,
2208 0xffff00, pbn_default },
2209 { PCI_ANY_ID, PCI_ANY_ID,
2210 PCI_ANY_ID, PCI_ANY_ID,
2211 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2212 0xffff00, pbn_default },
2213 { 0, }
2214};
2215
2216static struct pci_driver serial_pci_driver = {
2217 .name = "serial",
2218 .probe = pciserial_init_one,
2219 .remove = __devexit_p(pciserial_remove_one),
2220 .suspend = pciserial_suspend_one,
2221 .resume = pciserial_resume_one,
2222 .id_table = serial_pci_tbl,
2223};
2224
2225static int __init serial8250_pci_init(void)
2226{
2227 return pci_register_driver(&serial_pci_driver);
2228}
2229
2230static void __exit serial8250_pci_exit(void)
2231{
2232 pci_unregister_driver(&serial_pci_driver);
2233}
2234
2235module_init(serial8250_pci_init);
2236module_exit(serial8250_pci_exit);
2237
2238MODULE_LICENSE("GPL");
2239MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2240MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Empty description
This page took 0.384581 seconds and 4 git commands to generate.