[linux.git] / drivers / gpio / gpio-mxs.c

/*
 * MXC GPIO support. (c) 2008 Daniel Mack <[email protected]>
 * Copyright 2008 Juergen Beisert, [email protected]
 *
 * Based on code from Freescale,
 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/basic_mmio_gpio.h>
#include <linux/module.h>

#define MXS_SET		0x4
#define MXS_CLR		0x8

#define PINCTRL_DOUT(p)		((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
#define PINCTRL_DIN(p)		((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
#define PINCTRL_DOE(p)		((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
#define PINCTRL_PIN2IRQ(p)	((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
#define PINCTRL_IRQEN(p)	((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
#define PINCTRL_IRQLEV(p)	((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
#define PINCTRL_IRQPOL(p)	((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
#define PINCTRL_IRQSTAT(p)	((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)

#define GPIO_INT_FALL_EDGE	0x0
#define GPIO_INT_LOW_LEV	0x1
#define GPIO_INT_RISE_EDGE	0x2
#define GPIO_INT_HIGH_LEV	0x3
#define GPIO_INT_LEV_MASK	(1 << 0)
#define GPIO_INT_POL_MASK	(1 << 1)

enum mxs_gpio_id {
	IMX23_GPIO,
	IMX28_GPIO,
};

struct mxs_gpio_port {
	void __iomem *base;
	int id;
	int irq;
	struct irq_domain *domain;
	struct bgpio_chip bgc;
	enum mxs_gpio_id devid;
	u32 both_edges;
};

static inline int is_imx23_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX23_GPIO;
}

static inline int is_imx28_gpio(struct mxs_gpio_port *port)
{
	return port->devid == IMX28_GPIO;
}

/* Note: This driver assumes 32 GPIOs are handled in one register */

static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
{
	u32 val;
	u32 pin_mask = 1 << d->hwirq;
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxs_gpio_port *port = gc->private;
	void __iomem *pin_addr;
	int edge;

	port->both_edges &= ~pin_mask;
	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		val = gpio_get_value(port->bgc.gc.base + d->hwirq);
		if (val)
			edge = GPIO_INT_FALL_EDGE;
		else
			edge = GPIO_INT_RISE_EDGE;
		port->both_edges |= pin_mask;
		break;
	case IRQ_TYPE_EDGE_RISING:
		edge = GPIO_INT_RISE_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		edge = GPIO_INT_FALL_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		edge = GPIO_INT_LOW_LEV;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		edge = GPIO_INT_HIGH_LEV;
		break;
	default:
		return -EINVAL;
	}

	/* set level or edge */
	pin_addr = port->base + PINCTRL_IRQLEV(port);
	if (edge & GPIO_INT_LEV_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	/* set polarity */
	pin_addr = port->base + PINCTRL_IRQPOL(port);
	if (edge & GPIO_INT_POL_MASK)
		writel(pin_mask, pin_addr + MXS_SET);
	else
		writel(pin_mask, pin_addr + MXS_CLR);

	writel(pin_mask,
	       port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	return 0;
}

static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
{
	u32 bit, val, edge;
	void __iomem *pin_addr;

	bit = 1 << gpio;

	pin_addr = port->base + PINCTRL_IRQPOL(port);
	val = readl(pin_addr);
	edge = val & bit;

	if (edge)
		writel(bit, pin_addr + MXS_CLR);
	else
		writel(bit, pin_addr + MXS_SET);
}

/* MXS has one interrupt *per* gpio port */
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 irq_stat;
	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);

	desc->irq_data.chip->irq_ack(&desc->irq_data);

	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
			readl(port->base + PINCTRL_IRQEN(port));

	while (irq_stat != 0) {
		int irqoffset = fls(irq_stat) - 1;
		if (port->both_edges & (1 << irqoffset))
			mxs_flip_edge(port, irqoffset);

		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
		irq_stat &= ~(1 << irqoffset);
	}
}

/*
 * Set interrupt number "irq" in the GPIO as a wake-up source.
 * While system is running, all registered GPIO interrupts need to have
 * wake-up enabled. When system is suspended, only selected GPIO interrupts
 * need to have wake-up enabled.
 * @param  irq          interrupt source number
 * @param  enable       enable as wake-up if equal to non-zero
 * @return       This function returns 0 on success.
 */
static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct mxs_gpio_port *port = gc->private;

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
				    port->base, handle_level_irq);
	if (!gc)
		return -ENOMEM;

	gc->private = port;

	ct = gc->chip_types;
	ct->chip.irq_ack = irq_gc_ack_set_bit;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
	ct->regs.mask = PINCTRL_IRQEN(port);

	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
			       IRQ_NOREQUEST, 0);

	return 0;
}

static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct mxs_gpio_port *port =
		container_of(bgc, struct mxs_gpio_port, bgc);

	return irq_find_mapping(port->domain, offset);
}

static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
{
	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	struct mxs_gpio_port *port =
		container_of(bgc, struct mxs_gpio_port, bgc);
	u32 mask = 1 << offset;
	u32 dir;

	dir = readl(port->base + PINCTRL_DOE(port));
	return !(dir & mask);
}

static const struct platform_device_id mxs_gpio_ids[] = {
	{
		.name = "imx23-gpio",
		.driver_data = IMX23_GPIO,
	}, {
		.name = "imx28-gpio",
		.driver_data = IMX28_GPIO,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);

static const struct of_device_id mxs_gpio_dt_ids[] = {
	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);

static int mxs_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *of_id =
			of_match_device(mxs_gpio_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct device_node *parent;
	static void __iomem *base;
	struct mxs_gpio_port *port;
	int irq_base;
	int err;

	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->id = of_alias_get_id(np, "gpio");
	if (port->id < 0)
		return port->id;
	port->devid = (enum mxs_gpio_id) of_id->data;
	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	/*
	 * map memory region only once, as all the gpio ports
	 * share the same one
	 */
	if (!base) {
		parent = of_get_parent(np);
		base = of_iomap(parent, 0);
		of_node_put(parent);
		if (!base)
			return -EADDRNOTAVAIL;
	}
	port->base = base;

	/*
	 * select the pin interrupt functionality but initially
	 * disable the interrupts
	 */
	writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
	writel(0, port->base + PINCTRL_IRQEN(port));

	/* clear address has to be used to clear IRQSTAT bits */
	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);

	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
	if (irq_base < 0)
		return irq_base;

	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
					     &irq_domain_simple_ops, NULL);
	if (!port->domain) {
		err = -ENODEV;
		goto out_irqdesc_free;
	}

	/* gpio-mxs can be a generic irq chip */
	err = mxs_gpio_init_gc(port, irq_base);
	if (err < 0)
		goto out_irqdomain_remove;

	/* setup one handler for each entry */
	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
					 port);

	err = bgpio_init(&port->bgc, &pdev->dev, 4,
			 port->base + PINCTRL_DIN(port),
			 port->base + PINCTRL_DOUT(port) + MXS_SET,
			 port->base + PINCTRL_DOUT(port) + MXS_CLR,
			 port->base + PINCTRL_DOE(port), NULL, 0);
	if (err)
		goto out_irqdesc_free;

	port->bgc.gc.to_irq = mxs_gpio_to_irq;
	port->bgc.gc.get_direction = mxs_gpio_get_direction;
	port->bgc.gc.base = port->id * 32;

	err = gpiochip_add(&port->bgc.gc);
	if (err)
		goto out_bgpio_remove;

	return 0;

out_bgpio_remove:
	bgpio_remove(&port->bgc);
out_irqdomain_remove:
	irq_domain_remove(port->domain);
out_irqdesc_free:
	irq_free_descs(irq_base, 32);
	return err;
}

static struct platform_driver mxs_gpio_driver = {
	.driver		= {
		.name	= "gpio-mxs",
		.of_match_table = mxs_gpio_dt_ids,
	},
	.probe		= mxs_gpio_probe,
	.id_table	= mxs_gpio_ids,
};

static int __init mxs_gpio_init(void)
{
	return platform_driver_register(&mxs_gpio_driver);
}
postcore_initcall(mxs_gpio_init);

MODULE_AUTHOR("Freescale Semiconductor, "
	      "Daniel Mack <danielncaiaq.de>, "
	      "Juergen Beisert <[email protected]>");
MODULE_DESCRIPTION("Freescale MXS GPIO");
MODULE_LICENSE("GPL");
Commit	Line	Data
fba311fc SG	1	/*
	2	* MXC GPIO support. (c) 2008 Daniel Mack <[email protected]>
	3	* Copyright 2008 Juergen Beisert, [email protected]
	4	*
	5	* Based on code from Freescale,
	6	* Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	20	* MA 02110-1301, USA.
	21	*/
	22
641d0342	23	#include <linux/err.h>
fba311fc SG	24	#include <linux/init.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/io.h>
	27	#include <linux/irq.h>
0b76c541	28	#include <linux/irqdomain.h>
fba311fc	29	#include <linux/gpio.h>
4052d45e SG	30	#include <linux/of.h>
	31	#include <linux/of_address.h>
	32	#include <linux/of_device.h>
8d7cf837 SG	33	#include <linux/platform_device.h>
8d7cf837 SG	34	#include <linux/slab.h>
06f88a8a	35	#include <linux/basic_mmio_gpio.h>
bb207ef1	36	#include <linux/module.h>
fba311fc	37
8d7cf837 SG	38	#define MXS_SET 0x4
8d7cf837 SG	39	#define MXS_CLR 0x8
fba311fc	40
164387d2 SG	41	#define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
	42	#define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
	43	#define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
	44	#define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
	45	#define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
	46	#define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
	47	#define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
	48	#define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
fba311fc SG	49
	50	#define GPIO_INT_FALL_EDGE 0x0
	51	#define GPIO_INT_LOW_LEV 0x1
	52	#define GPIO_INT_RISE_EDGE 0x2
	53	#define GPIO_INT_HIGH_LEV 0x3
	54	#define GPIO_INT_LEV_MASK (1 << 0)
	55	#define GPIO_INT_POL_MASK (1 << 1)
	56
164387d2 SG	57	enum mxs_gpio_id {
	58	IMX23_GPIO,
	59	IMX28_GPIO,
	60	};
	61
7b2fa570 GL	62	struct mxs_gpio_port {
	63	void __iomem *base;
	64	int id;
	65	int irq;
0b76c541	66	struct irq_domain *domain;
06f88a8a	67	struct bgpio_chip bgc;
164387d2	68	enum mxs_gpio_id devid;
66d7990e	69	u32 both_edges;
7b2fa570 GL	70	};
7b2fa570 GL	71
164387d2 SG	72	static inline int is_imx23_gpio(struct mxs_gpio_port *port)
	73	{
	74	return port->devid == IMX23_GPIO;
	75	}
	76
	77	static inline int is_imx28_gpio(struct mxs_gpio_port *port)
	78	{
	79	return port->devid == IMX28_GPIO;
	80	}
	81
fba311fc SG	82	/* Note: This driver assumes 32 GPIOs are handled in one register */
fba311fc SG	83
bf0c1118	84	static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
fba311fc	85	{
66d7990e	86	u32 val;
0b76c541	87	u32 pin_mask = 1 << d->hwirq;
498c17cf SG	88	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498c17cf SG	89	struct mxs_gpio_port *port = gc->private;
fba311fc SG	90	void __iomem *pin_addr;
	91	int edge;
	92
66d7990e	93	port->both_edges &= ~pin_mask;
fba311fc	94	switch (type) {
66d7990e GGM	95	case IRQ_TYPE_EDGE_BOTH:
	96	val = gpio_get_value(port->bgc.gc.base + d->hwirq);
	97	if (val)
	98	edge = GPIO_INT_FALL_EDGE;
	99	else
	100	edge = GPIO_INT_RISE_EDGE;
	101	port->both_edges \|= pin_mask;
	102	break;
fba311fc SG	103	case IRQ_TYPE_EDGE_RISING:
	104	edge = GPIO_INT_RISE_EDGE;
	105	break;
	106	case IRQ_TYPE_EDGE_FALLING:
	107	edge = GPIO_INT_FALL_EDGE;
	108	break;
	109	case IRQ_TYPE_LEVEL_LOW:
	110	edge = GPIO_INT_LOW_LEV;
	111	break;
	112	case IRQ_TYPE_LEVEL_HIGH:
	113	edge = GPIO_INT_HIGH_LEV;
	114	break;
	115	default:
	116	return -EINVAL;
	117	}
	118
	119	/* set level or edge */
164387d2	120	pin_addr = port->base + PINCTRL_IRQLEV(port);
fba311fc	121	if (edge & GPIO_INT_LEV_MASK)
8d7cf837	122	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	123	else
8d7cf837	124	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc SG	125
fba311fc SG	126	/* set polarity */
164387d2	127	pin_addr = port->base + PINCTRL_IRQPOL(port);
fba311fc	128	if (edge & GPIO_INT_POL_MASK)
8d7cf837	129	writel(pin_mask, pin_addr + MXS_SET);
fba311fc	130	else
8d7cf837	131	writel(pin_mask, pin_addr + MXS_CLR);
fba311fc	132
0b76c541	133	writel(pin_mask,
164387d2	134	port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc SG	135
	136	return 0;
	137	}
	138
66d7990e GGM	139	static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
	140	{
	141	u32 bit, val, edge;
	142	void __iomem *pin_addr;
	143
	144	bit = 1 << gpio;
	145
	146	pin_addr = port->base + PINCTRL_IRQPOL(port);
	147	val = readl(pin_addr);
	148	edge = val & bit;
	149
	150	if (edge)
	151	writel(bit, pin_addr + MXS_CLR);
	152	else
	153	writel(bit, pin_addr + MXS_SET);
	154	}
	155
fba311fc SG	156	/* MXS has one interrupt per gpio port */
	157	static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
	158	{
	159	u32 irq_stat;
476f8b4c	160	struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
fba311fc	161
1f6b5dd4 UKK	162	desc->irq_data.chip->irq_ack(&desc->irq_data);
1f6b5dd4 UKK	163
164387d2 SG	164	irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
164387d2 SG	165	readl(port->base + PINCTRL_IRQEN(port));
fba311fc SG	166
	167	while (irq_stat != 0) {
	168	int irqoffset = fls(irq_stat) - 1;
66d7990e GGM	169	if (port->both_edges & (1 << irqoffset))
	170	mxs_flip_edge(port, irqoffset);
	171
0b76c541	172	generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
fba311fc SG	173	irq_stat &= ~(1 << irqoffset);
	174	}
	175	}
	176
	177	/*
	178	* Set interrupt number "irq" in the GPIO as a wake-up source.
	179	* While system is running, all registered GPIO interrupts need to have
	180	* wake-up enabled. When system is suspended, only selected GPIO interrupts
	181	* need to have wake-up enabled.
	182	* @param irq interrupt source number
	183	* @param enable enable as wake-up if equal to non-zero
	184	* @return This function returns 0 on success.
	185	*/
bf0c1118	186	static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
fba311fc	187	{
498c17cf SG	188	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498c17cf SG	189	struct mxs_gpio_port *port = gc->private;
fba311fc	190
6161715e SG	191	if (enable)
	192	enable_irq_wake(port->irq);
	193	else
	194	disable_irq_wake(port->irq);
fba311fc SG	195
	196	return 0;
	197	}
	198
1bbc557d	199	static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
498c17cf SG	200	{
	201	struct irq_chip_generic *gc;
	202	struct irq_chip_type *ct;
	203
0b76c541	204	gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
498c17cf	205	port->base, handle_level_irq);
1bbc557d PF	206	if (!gc)
	207	return -ENOMEM;
	208
498c17cf SG	209	gc->private = port;
	210
	211	ct = gc->chip_types;
591567a5	212	ct->chip.irq_ack = irq_gc_ack_set_bit;
498c17cf SG	213	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	214	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	215	ct->chip.irq_set_type = mxs_gpio_set_irq_type;
591567a5	216	ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
164387d2 SG	217	ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
164387d2 SG	218	ct->regs.mask = PINCTRL_IRQEN(port);
498c17cf	219
a585f87c MV	220	irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
a585f87c MV	221	IRQ_NOREQUEST, 0);
1bbc557d PF	222
1bbc557d PF	223	return 0;
498c17cf	224	}
fba311fc	225
06f88a8a	226	static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
fba311fc	227	{
06f88a8a	228	struct bgpio_chip *bgc = to_bgpio_chip(gc);
fba311fc	229	struct mxs_gpio_port *port =
06f88a8a	230	container_of(bgc, struct mxs_gpio_port, bgc);
fba311fc	231
0b76c541	232	return irq_find_mapping(port->domain, offset);
fba311fc SG	233	}
fba311fc SG	234
c8aaa1bf JU	235	static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
	236	{
	237	struct bgpio_chip *bgc = to_bgpio_chip(gc);
	238	struct mxs_gpio_port *port =
	239	container_of(bgc, struct mxs_gpio_port, bgc);
	240	u32 mask = 1 << offset;
	241	u32 dir;
	242
	243	dir = readl(port->base + PINCTRL_DOE(port));
	244	return !(dir & mask);
	245	}
	246
f4f79d40	247	static const struct platform_device_id mxs_gpio_ids[] = {
164387d2 SG	248	{
	249	.name = "imx23-gpio",
	250	.driver_data = IMX23_GPIO,
	251	}, {
	252	.name = "imx28-gpio",
	253	.driver_data = IMX28_GPIO,
	254	}, {
	255	/* sentinel */
	256	}
	257	};
	258	MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
	259
4052d45e SG	260	static const struct of_device_id mxs_gpio_dt_ids[] = {
	261	{ .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
	262	{ .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
	263	{ /* sentinel */ }
	264	};
	265	MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
	266
3836309d	267	static int mxs_gpio_probe(struct platform_device *pdev)
fba311fc	268	{
4052d45e SG	269	const struct of_device_id *of_id =
	270	of_match_device(mxs_gpio_dt_ids, &pdev->dev);
	271	struct device_node *np = pdev->dev.of_node;
	272	struct device_node *parent;
8d7cf837 SG	273	static void __iomem *base;
8d7cf837 SG	274	struct mxs_gpio_port *port;
0b76c541	275	int irq_base;
498c17cf	276	int err;
8d7cf837	277
940a4f7b	278	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
8d7cf837 SG	279	if (!port)
	280	return -ENOMEM;
	281
99357127 FE	282	port->id = of_alias_get_id(np, "gpio");
	283	if (port->id < 0)
	284	return port->id;
	285	port->devid = (enum mxs_gpio_id) of_id->data;
940a4f7b SG	286	port->irq = platform_get_irq(pdev, 0);
	287	if (port->irq < 0)
	288	return port->irq;
	289
8d7cf837 SG	290	/*
	291	* map memory region only once, as all the gpio ports
	292	* share the same one
	293	*/
	294	if (!base) {
99357127 FE	295	parent = of_get_parent(np);
	296	base = of_iomap(parent, 0);
	297	of_node_put(parent);
	298	if (!base)
	299	return -EADDRNOTAVAIL;
8d7cf837 SG	300	}
8d7cf837 SG	301	port->base = base;
fba311fc	302
498c17cf SG	303	/*
	304	* select the pin interrupt functionality but initially
	305	* disable the interrupts
	306	*/
164387d2 SG	307	writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
164387d2 SG	308	writel(0, port->base + PINCTRL_IRQEN(port));
fba311fc	309
8d7cf837	310	/* clear address has to be used to clear IRQSTAT bits */
164387d2	311	writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
fba311fc	312
0b76c541 SG	313	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
	314	if (irq_base < 0)
	315	return irq_base;
	316
	317	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
	318	&irq_domain_simple_ops, NULL);
	319	if (!port->domain) {
	320	err = -ENODEV;
	321	goto out_irqdesc_free;
	322	}
	323
498c17cf	324	/* gpio-mxs can be a generic irq chip */
1bbc557d PF	325	err = mxs_gpio_init_gc(port, irq_base);
	326	if (err < 0)
	327	goto out_irqdomain_remove;
fba311fc	328
8d7cf837	329	/* setup one handler for each entry */
a44735f4 RK	330	irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
a44735f4 RK	331	port);
fba311fc	332
06f88a8a	333	err = bgpio_init(&port->bgc, &pdev->dev, 4,
164387d2	334	port->base + PINCTRL_DIN(port),
90dae4eb MR	335	port->base + PINCTRL_DOUT(port) + MXS_SET,
90dae4eb MR	336	port->base + PINCTRL_DOUT(port) + MXS_CLR,
84a442b9	337	port->base + PINCTRL_DOE(port), NULL, 0);
8d7cf837	338	if (err)
0b76c541	339	goto out_irqdesc_free;
fba311fc	340
06f88a8a	341	port->bgc.gc.to_irq = mxs_gpio_to_irq;
c8aaa1bf	342	port->bgc.gc.get_direction = mxs_gpio_get_direction;
06f88a8a SG	343	port->bgc.gc.base = port->id * 32;
	344
	345	err = gpiochip_add(&port->bgc.gc);
0b76c541 SG	346	if (err)
0b76c541 SG	347	goto out_bgpio_remove;
06f88a8a	348
8d7cf837	349	return 0;
0b76c541 SG	350
	351	out_bgpio_remove:
	352	bgpio_remove(&port->bgc);
1bbc557d PF	353	out_irqdomain_remove:
1bbc557d PF	354	irq_domain_remove(port->domain);
0b76c541 SG	355	out_irqdesc_free:
	356	irq_free_descs(irq_base, 32);
	357	return err;
ef19660b	358	}
8d7cf837 SG	359
	360	static struct platform_driver mxs_gpio_driver = {
	361	.driver = {
	362	.name = "gpio-mxs",
4052d45e	363	.of_match_table = mxs_gpio_dt_ids,
8d7cf837 SG	364	},
8d7cf837 SG	365	.probe = mxs_gpio_probe,
164387d2	366	.id_table = mxs_gpio_ids,
fba311fc	367	};
ef19660b	368
8d7cf837	369	static int __init mxs_gpio_init(void)
ef19660b	370	{
8d7cf837	371	return platform_driver_register(&mxs_gpio_driver);
ef19660b	372	}
8d7cf837 SG	373	postcore_initcall(mxs_gpio_init);
	374
	375	MODULE_AUTHOR("Freescale Semiconductor, "
	376	"Daniel Mack <danielncaiaq.de>, "
	377	"Juergen Beisert <[email protected]>");
	378	MODULE_DESCRIPTION("Freescale MXS GPIO");
	379	MODULE_LICENSE("GPL");