[linux.git] / drivers / mfd / sta2x11-mfd.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * STA2x11 mfd for GPIO, SCTL and APBREG
 *
 * Copyright (c) 2009-2011 Wind River Systems, Inc.
 * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/export.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/seq_file.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/sta2x11-mfd.h>
#include <linux/regmap.h>

#include <asm/sta2x11.h>

static inline int __reg_within_range(unsigned int r,
				     unsigned int start,
				     unsigned int end)
{
	return ((r >= start) && (r <= end));
}

/* This describes STA2X11 MFD chip for us, we may have several */
struct sta2x11_mfd {
	struct sta2x11_instance *instance;
	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
	spinlock_t lock[sta2x11_n_mfd_plat_devs];
	struct list_head list;
	void __iomem *regs[sta2x11_n_mfd_plat_devs];
};

static LIST_HEAD(sta2x11_mfd_list);

/* Three functions to act on the list */
static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev)
{
	struct sta2x11_instance *instance;
	struct sta2x11_mfd *mfd;

	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
		pr_warn("%s: Unspecified device, using first instance\n",
			__func__);
		return list_entry(sta2x11_mfd_list.next,
				  struct sta2x11_mfd, list);
	}

	instance = sta2x11_get_instance(pdev);
	if (!instance)
		return NULL;
	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
		if (mfd->instance == instance)
			return mfd;
	}
	return NULL;
}

static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
{
	int i;
	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	struct sta2x11_instance *instance;

	if (mfd)
		return -EBUSY;
	instance = sta2x11_get_instance(pdev);
	if (!instance)
		return -EINVAL;
	mfd = kzalloc(sizeof(*mfd), flags);
	if (!mfd)
		return -ENOMEM;
	INIT_LIST_HEAD(&mfd->list);
	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
		spin_lock_init(&mfd->lock[i]);
	mfd->instance = instance;
	list_add(&mfd->list, &sta2x11_mfd_list);
	return 0;
}

/* This function is exported and is not expected to fail */
u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
		       enum sta2x11_mfd_plat_dev index)
{
	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	u32 r;
	unsigned long flags;
	void __iomem *regs;

	if (!mfd) {
		dev_warn(&pdev->dev, ": can't access sctl regs\n");
		return 0;
	}

	regs = mfd->regs[index];
	if (!regs) {
		dev_warn(&pdev->dev, ": system ctl not initialized\n");
		return 0;
	}
	spin_lock_irqsave(&mfd->lock[index], flags);
	r = readl(regs + reg);
	r &= ~mask;
	r |= val;
	if (mask)
		writel(r, regs + reg);
	spin_unlock_irqrestore(&mfd->lock[index], flags);
	return r;
}
EXPORT_SYMBOL(__sta2x11_mfd_mask);

int sta2x11_mfd_get_regs_data(struct platform_device *dev,
			      enum sta2x11_mfd_plat_dev index,
			      void __iomem **regs,
			      spinlock_t **lock)
{
	struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
	struct sta2x11_mfd *mfd;

	if (!pdev)
		return -ENODEV;
	mfd = sta2x11_mfd_find(pdev);
	if (!mfd)
		return -ENODEV;
	if (index >= sta2x11_n_mfd_plat_devs)
		return -ENODEV;
	*regs = mfd->regs[index];
	*lock = &mfd->lock[index];
	pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs);
	return *regs ? 0 : -ENODEV;
}
EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);

/*
 * Special sta2x11-mfd regmap lock/unlock functions
 */

static void sta2x11_regmap_lock(void *__lock)
{
	spinlock_t *lock = __lock;
	spin_lock(lock);
}

static void sta2x11_regmap_unlock(void *__lock)
{
	spinlock_t *lock = __lock;
	spin_unlock(lock);
}

/* OTP (one time programmable registers do not require locking */
static void sta2x11_regmap_nolock(void *__lock)
{
}

static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
};

static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
{
	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
}

static struct regmap_config sta2x11_sctl_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = SCTL_SCRSTSTA,
	.writeable_reg = sta2x11_sctl_writeable_reg,
};

static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
{
	return (reg == STA2X11_SECR_CR) ||
		__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
}

static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
{
	return false;
}

static struct regmap_config sta2x11_scr_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_nolock,
	.unlock = sta2x11_regmap_nolock,
	.max_register = STA2X11_SECR_FVR1,
	.readable_reg = sta2x11_scr_readable_reg,
	.writeable_reg = sta2x11_scr_writeable_reg,
};

static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
{
	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
	if (reg >= APBREG_BSR_SARAC)
		reg -= APBREG_BSR_SARAC;
	switch (reg) {
	case APBREG_BSR:
	case APBREG_PAER:
	case APBREG_PWAC:
	case APBREG_PRAC:
	case APBREG_PCG:
	case APBREG_PUR:
	case APBREG_EMU_PCG:
		return true;
	default:
		return false;
	}
}

static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
{
	if (reg >= APBREG_BSR_SARAC)
		reg -= APBREG_BSR_SARAC;
	if (!sta2x11_apbreg_readable_reg(dev, reg))
		return false;
	return reg != APBREG_PAER;
}

static struct regmap_config sta2x11_apbreg_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = APBREG_EMU_PCG_SARAC,
	.readable_reg = sta2x11_apbreg_readable_reg,
	.writeable_reg = sta2x11_apbreg_writeable_reg,
};

static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
					      unsigned int reg)
{
	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
		__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
		__reg_within_range(reg, MASTER_LOCK_REG,
				   SYSTEM_CONFIG_STATUS_REG) ||
		reg == MSP_CLK_CTRL_REG ||
		__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
}

static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
					       unsigned int reg)
{
	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
		return false;
	switch (reg) {
	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
	case SYSTEM_CONFIG_STATUS_REG:
	case COMPENSATION_REG1:
	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
		return false;
	default:
		return true;
	}
}

static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = TEST_CTL_REG,
	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
};

static struct regmap_config *
sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
	[sta2x11_scr] = &sta2x11_scr_regmap_config,
};

/* Probe for the four platform devices */

static int sta2x11_mfd_platform_probe(struct platform_device *dev,
				      enum sta2x11_mfd_plat_dev index)
{
	struct pci_dev **pdev;
	struct sta2x11_mfd *mfd;
	struct resource *res;
	const char *name = sta2x11_mfd_names[index];
	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];

	pdev = dev_get_platdata(&dev->dev);
	mfd = sta2x11_mfd_find(*pdev);
	if (!mfd)
		return -ENODEV;
	if (!regmap_config)
		return -ENODEV;

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOMEM;

	if (!request_mem_region(res->start, resource_size(res), name))
		return -EBUSY;

	mfd->regs[index] = ioremap(res->start, resource_size(res));
	if (!mfd->regs[index]) {
		release_mem_region(res->start, resource_size(res));
		return -ENOMEM;
	}
	regmap_config->lock_arg = &mfd->lock;
	/*
	   No caching, registers could be reached both via regmap and via
	   void __iomem *
	*/
	regmap_config->cache_type = REGCACHE_NONE;
	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
						   regmap_config);
	WARN_ON(IS_ERR(mfd->regmap[index]));

	return 0;
}

static int sta2x11_sctl_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
}

static int sta2x11_apbreg_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
}

static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
}

static int sta2x11_scr_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
}

/* The three platform drivers */
static struct platform_driver sta2x11_sctl_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_SCTL_NAME,
	},
	.probe		= sta2x11_sctl_probe,
};

static struct platform_driver sta2x11_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_APBREG_NAME,
	},
	.probe		= sta2x11_apbreg_probe,
};

static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_APB_SOC_REGS_NAME,
	},
	.probe		= sta2x11_apb_soc_regs_probe,
};

static struct platform_driver sta2x11_scr_platform_driver = {
	.driver = {
		.name = STA2X11_MFD_SCR_NAME,
	},
	.probe = sta2x11_scr_probe,
};

static struct platform_driver * const drivers[] = {
	&sta2x11_platform_driver,
	&sta2x11_sctl_platform_driver,
	&sta2x11_apb_soc_regs_platform_driver,
	&sta2x11_scr_platform_driver,
};

static int __init sta2x11_drivers_init(void)
{
	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}

/*
 * What follows are the PCI devices that host the above pdevs.
 * Each logic block is 4kB and they are all consecutive: we use this info.
 */

/* Mfd 0 device */

/* Mfd 0, Bar 0 */
enum mfd0_bar0_cells {
	STA2X11_GPIO_0 = 0,
	STA2X11_GPIO_1,
	STA2X11_GPIO_2,
	STA2X11_GPIO_3,
	STA2X11_SCTL,
	STA2X11_SCR,
	STA2X11_TIME,
};
/* Mfd 0 , Bar 1 */
enum mfd0_bar1_cells {
	STA2X11_APBREG = 0,
};
#define CELL_4K(_name, _cell) { \
		.name = _name, \
		.start = _cell * 4096, .end = _cell * 4096 + 4095, \
		.flags = IORESOURCE_MEM, \
		}

static const struct resource gpio_resources[] = {
	{
		/* 4 consecutive cells, 1 driver */
		.name = STA2X11_MFD_GPIO_NAME,
		.start = 0,
		.end = (4 * 4096) - 1,
		.flags = IORESOURCE_MEM,
	}
};
static const struct resource sctl_resources[] = {
	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
};
static const struct resource scr_resources[] = {
	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
};
static const struct resource time_resources[] = {
	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
};

static const struct resource apbreg_resources[] = {
	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
};

#define DEV(_name, _r) \
	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }

static struct mfd_cell sta2x11_mfd0_bar0[] = {
	/* offset 0: we add pdata later */
	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
	DEV(STA2X11_MFD_SCR_NAME,  scr_resources),
	DEV(STA2X11_MFD_TIME_NAME, time_resources),
};

static struct mfd_cell sta2x11_mfd0_bar1[] = {
	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
};

/* Mfd 1 devices */

/* Mfd 1, Bar 0 */
enum mfd1_bar0_cells {
	STA2X11_VIC = 0,
};

/* Mfd 1, Bar 1 */
enum mfd1_bar1_cells {
	STA2X11_APB_SOC_REGS = 0,
};

static const struct resource vic_resources[] = {
	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
};

static const struct resource apb_soc_regs_resources[] = {
	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
};

static struct mfd_cell sta2x11_mfd1_bar0[] = {
	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
};

static struct mfd_cell sta2x11_mfd1_bar1[] = {
	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
};


static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
{
	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, pci_choose_state(pdev, state));

	return 0;
}

static int sta2x11_mfd_resume(struct pci_dev *pdev)
{
	int err;

	pci_set_power_state(pdev, PCI_D0);
	err = pci_enable_device(pdev);
	if (err)
		return err;
	pci_restore_state(pdev);

	return 0;
}

struct sta2x11_mfd_bar_setup_data {
	struct mfd_cell *cells;
	int ncells;
};

struct sta2x11_mfd_setup_data {
	struct sta2x11_mfd_bar_setup_data bars[2];
};

#define STA2X11_MFD0 0
#define STA2X11_MFD1 1

static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
	[STA2X11_MFD0] = {
		.bars = {
			[0] = {
				.cells = sta2x11_mfd0_bar0,
				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
			},
			[1] = {
				.cells = sta2x11_mfd0_bar1,
				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
			},
		},
	},
	/* Mfd 1: vic / apb-soc-regs */
	[STA2X11_MFD1] = {
		.bars = {
			[0] = {
				.cells = sta2x11_mfd1_bar0,
				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
			},
			[1] = {
				.cells = sta2x11_mfd1_bar1,
				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
			},
		},
	},
};

static void sta2x11_mfd_setup(struct pci_dev *pdev,
			      struct sta2x11_mfd_setup_data *sd)
{
	int i, j;
	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
		for (j = 0; j < sd->bars[i].ncells; j++) {
			sd->bars[i].cells[j].pdata_size = sizeof(pdev);
			sd->bars[i].cells[j].platform_data = &pdev;
		}
}

static int sta2x11_mfd_probe(struct pci_dev *pdev,
			     const struct pci_device_id *pci_id)
{
	int err, i;
	struct sta2x11_mfd_setup_data *setup_data;

	dev_info(&pdev->dev, "%s\n", __func__);

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "Can't enable device.\n");
		return err;
	}

	err = pci_enable_msi(pdev);
	if (err)
		dev_info(&pdev->dev, "Enable msi failed\n");

	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
		&mfd_setup_data[STA2X11_MFD0] :
		&mfd_setup_data[STA2X11_MFD1];

	/* platform data is the pci device for all of them */
	sta2x11_mfd_setup(pdev, setup_data);

	/* Record this pdev before mfd_add_devices: their probe looks for it */
	if (!sta2x11_mfd_find(pdev))
		sta2x11_mfd_add(pdev, GFP_KERNEL);

	/* Just 2 bars for all mfd's at present */
	for (i = 0; i < 2; i++) {
		err = mfd_add_devices(&pdev->dev, -1,
				      setup_data->bars[i].cells,
				      setup_data->bars[i].ncells,
				      &pdev->resource[i],
				      0, NULL);
		if (err) {
			dev_err(&pdev->dev,
				"mfd_add_devices[%d] failed: %d\n", i, err);
			goto err_disable;
		}
	}

	return 0;

err_disable:
	mfd_remove_devices(&pdev->dev);
	pci_disable_device(pdev);
	pci_disable_msi(pdev);
	return err;
}

static const struct pci_device_id sta2x11_mfd_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
	{0,},
};

static struct pci_driver sta2x11_mfd_driver = {
	.name =		"sta2x11-mfd",
	.id_table =	sta2x11_mfd_tbl,
	.probe =	sta2x11_mfd_probe,
	.suspend =	sta2x11_mfd_suspend,
	.resume =	sta2x11_mfd_resume,
};

static int __init sta2x11_mfd_init(void)
{
	pr_info("%s\n", __func__);
	return pci_register_driver(&sta2x11_mfd_driver);
}

/*
 * All of this must be ready before "normal" devices like MMCI appear.
 * But MFD (the pci device) can't be too early. The following choice
 * prepares platform drivers very early and probe the PCI device later,
 * but before other PCI devices.
 */
subsys_initcall(sta2x11_drivers_init);
rootfs_initcall(sta2x11_mfd_init);
Commit	Line	Data
45051539	1	// SPDX-License-Identifier: GPL-2.0-only
35bdd290	2	/*
cf090914 PG	3	* STA2x11 mfd for GPIO, SCTL and APBREG
cf090914 PG	4	*
35bdd290	5	* Copyright (c) 2009-2011 Wind River Systems, Inc.
b73df698	6	* Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
35bdd290 AR	7	*/
	8
	9	#include <linux/kernel.h>
cf090914 PG	10	#include <linux/init.h>
cf090914 PG	11	#include <linux/export.h>
35bdd290 AR	12	#include <linux/spinlock.h>
	13	#include <linux/errno.h>
	14	#include <linux/device.h>
	15	#include <linux/slab.h>
	16	#include <linux/list.h>
	17	#include <linux/io.h>
	18	#include <linux/ioport.h>
	19	#include <linux/pci.h>
35bdd290 AR	20	#include <linux/seq_file.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/mfd/core.h>
	23	#include <linux/mfd/sta2x11-mfd.h>
d94e2553	24	#include <linux/regmap.h>
35bdd290 AR	25
	26	#include <asm/sta2x11.h>
	27
d94e2553 DC	28	static inline int __reg_within_range(unsigned int r,
	29	unsigned int start,
	30	unsigned int end)
	31	{
	32	return ((r >= start) && (r <= end));
	33	}
	34
35bdd290 AR	35	/* This describes STA2X11 MFD chip for us, we may have several */
	36	struct sta2x11_mfd {
	37	struct sta2x11_instance *instance;
d94e2553	38	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
e885ba29	39	spinlock_t lock[sta2x11_n_mfd_plat_devs];
35bdd290	40	struct list_head list;
1950c716	41	void __iomem *regs[sta2x11_n_mfd_plat_devs];
35bdd290 AR	42	};
	43
	44	static LIST_HEAD(sta2x11_mfd_list);
	45
	46	/* Three functions to act on the list */
	47	static struct sta2x11_mfd sta2x11_mfd_find(struct pci_dev pdev)
	48	{
	49	struct sta2x11_instance *instance;
	50	struct sta2x11_mfd *mfd;
	51
	52	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
81d30eda JP	53	pr_warn("%s: Unspecified device, using first instance\n",
81d30eda JP	54	__func__);
35bdd290 AR	55	return list_entry(sta2x11_mfd_list.next,
	56	struct sta2x11_mfd, list);
	57	}
	58
	59	instance = sta2x11_get_instance(pdev);
	60	if (!instance)
	61	return NULL;
	62	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
	63	if (mfd->instance == instance)
	64	return mfd;
	65	}
	66	return NULL;
	67	}
	68
f791be49	69	static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
35bdd290	70	{
e885ba29	71	int i;
35bdd290 AR	72	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	73	struct sta2x11_instance *instance;
	74
	75	if (mfd)
	76	return -EBUSY;
	77	instance = sta2x11_get_instance(pdev);
	78	if (!instance)
	79	return -EINVAL;
	80	mfd = kzalloc(sizeof(*mfd), flags);
	81	if (!mfd)
	82	return -ENOMEM;
	83	INIT_LIST_HEAD(&mfd->list);
e885ba29 DC	84	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
e885ba29 DC	85	spin_lock_init(&mfd->lock[i]);
35bdd290 AR	86	mfd->instance = instance;
	87	list_add(&mfd->list, &sta2x11_mfd_list);
	88	return 0;
	89	}
	90
1950c716 DC	91	/* This function is exported and is not expected to fail */
	92	u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
	93	enum sta2x11_mfd_plat_dev index)
35bdd290 AR	94	{
	95	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	96	u32 r;
	97	unsigned long flags;
709edecd	98	void __iomem *regs;
35bdd290 AR	99
	100	if (!mfd) {
	101	dev_warn(&pdev->dev, ": can't access sctl regs\n");
	102	return 0;
	103	}
709edecd WY	104
709edecd WY	105	regs = mfd->regs[index];
1950c716	106	if (!regs) {
35bdd290 AR	107	dev_warn(&pdev->dev, ": system ctl not initialized\n");
	108	return 0;
	109	}
e885ba29	110	spin_lock_irqsave(&mfd->lock[index], flags);
1950c716	111	r = readl(regs + reg);
35bdd290 AR	112	r &= ~mask;
	113	r \|= val;
	114	if (mask)
1950c716	115	writel(r, regs + reg);
e885ba29	116	spin_unlock_irqrestore(&mfd->lock[index], flags);
35bdd290 AR	117	return r;
35bdd290 AR	118	}
1950c716	119	EXPORT_SYMBOL(__sta2x11_mfd_mask);
35bdd290	120
29f5b5a3 DC	121	int sta2x11_mfd_get_regs_data(struct platform_device *dev,
	122	enum sta2x11_mfd_plat_dev index,
	123	void __iomem **regs,
	124	spinlock_t **lock)
35bdd290	125	{
334a41ce	126	struct pci_dev pdev = (struct pci_dev **)dev_get_platdata(&dev->dev);
29f5b5a3	127	struct sta2x11_mfd *mfd;
35bdd290	128
29f5b5a3 DC	129	if (!pdev)
	130	return -ENODEV;
	131	mfd = sta2x11_mfd_find(pdev);
	132	if (!mfd)
	133	return -ENODEV;
	134	if (index >= sta2x11_n_mfd_plat_devs)
	135	return -ENODEV;
	136	*regs = mfd->regs[index];
	137	*lock = &mfd->lock[index];
	138	pr_debug("%s %d regs = %p\n", __func__, __LINE__, regs);
	139	return *regs ? 0 : -ENODEV;
35bdd290	140	}
29f5b5a3	141	EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);
35bdd290	142
d94e2553 DC	143	/*
	144	* Special sta2x11-mfd regmap lock/unlock functions
	145	*/
35bdd290	146
d94e2553 DC	147	static void sta2x11_regmap_lock(void *__lock)
	148	{
	149	spinlock_t *lock = __lock;
	150	spin_lock(lock);
	151	}
35bdd290	152
d94e2553 DC	153	static void sta2x11_regmap_unlock(void *__lock)
	154	{
	155	spinlock_t *lock = __lock;
	156	spin_unlock(lock);
	157	}
35bdd290	158
dba6c1ae DC	159	/* OTP (one time programmable registers do not require locking */
	160	static void sta2x11_regmap_nolock(void *__lock)
	161	{
	162	}
	163
d94e2553	164	static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
b18adafc DC	165	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
	166	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
	167	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
dba6c1ae	168	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
35bdd290	169	};
35bdd290	170
d94e2553 DC	171	static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
	172	{
	173	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
	174	}
	175
	176	static struct regmap_config sta2x11_sctl_regmap_config = {
	177	.reg_bits = 32,
	178	.reg_stride = 4,
	179	.val_bits = 32,
	180	.lock = sta2x11_regmap_lock,
	181	.unlock = sta2x11_regmap_unlock,
	182	.max_register = SCTL_SCRSTSTA,
	183	.writeable_reg = sta2x11_sctl_writeable_reg,
35bdd290 AR	184	};
35bdd290 AR	185
dba6c1ae DC	186	static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
	187	{
	188	return (reg == STA2X11_SECR_CR) \|\|
	189	__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
	190	}
35bdd290	191
dba6c1ae	192	static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
35bdd290	193	{
dba6c1ae DC	194	return false;
dba6c1ae DC	195	}
35bdd290	196
dba6c1ae DC	197	static struct regmap_config sta2x11_scr_regmap_config = {
	198	.reg_bits = 32,
	199	.reg_stride = 4,
	200	.val_bits = 32,
	201	.lock = sta2x11_regmap_nolock,
	202	.unlock = sta2x11_regmap_nolock,
	203	.max_register = STA2X11_SECR_FVR1,
	204	.readable_reg = sta2x11_scr_readable_reg,
	205	.writeable_reg = sta2x11_scr_writeable_reg,
	206	};
35bdd290	207
d94e2553 DC	208	static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
	209	{
	210	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
	211	if (reg >= APBREG_BSR_SARAC)
	212	reg -= APBREG_BSR_SARAC;
	213	switch (reg) {
	214	case APBREG_BSR:
	215	case APBREG_PAER:
	216	case APBREG_PWAC:
	217	case APBREG_PRAC:
	218	case APBREG_PCG:
	219	case APBREG_PUR:
	220	case APBREG_EMU_PCG:
	221	return true;
	222	default:
	223	return false;
	224	}
	225	}
35bdd290	226
d94e2553 DC	227	static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
	228	{
	229	if (reg >= APBREG_BSR_SARAC)
	230	reg -= APBREG_BSR_SARAC;
	231	if (!sta2x11_apbreg_readable_reg(dev, reg))
	232	return false;
	233	return reg != APBREG_PAER;
	234	}
35bdd290	235
d94e2553 DC	236	static struct regmap_config sta2x11_apbreg_regmap_config = {
	237	.reg_bits = 32,
	238	.reg_stride = 4,
	239	.val_bits = 32,
	240	.lock = sta2x11_regmap_lock,
	241	.unlock = sta2x11_regmap_unlock,
	242	.max_register = APBREG_EMU_PCG_SARAC,
	243	.readable_reg = sta2x11_apbreg_readable_reg,
	244	.writeable_reg = sta2x11_apbreg_writeable_reg,
1950c716	245	};
35bdd290	246
d94e2553 DC	247	static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
	248	unsigned int reg)
	249	{
	250	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG \|\|
	251	__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) \|\|
	252	__reg_within_range(reg, MASTER_LOCK_REG,
	253	SYSTEM_CONFIG_STATUS_REG) \|\|
	254	reg == MSP_CLK_CTRL_REG \|\|
	255	__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
	256	}
35bdd290	257
d94e2553 DC	258	static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
	259	unsigned int reg)
	260	{
	261	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
	262	return false;
	263	switch (reg) {
	264	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
	265	case SYSTEM_CONFIG_STATUS_REG:
	266	case COMPENSATION_REG1:
	267	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
	268	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
	269	return false;
	270	default:
	271	return true;
35bdd290	272	}
35bdd290 AR	273	}
35bdd290 AR	274
d94e2553 DC	275	static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
	276	.reg_bits = 32,
	277	.reg_stride = 4,
	278	.val_bits = 32,
	279	.lock = sta2x11_regmap_lock,
	280	.unlock = sta2x11_regmap_unlock,
	281	.max_register = TEST_CTL_REG,
	282	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
	283	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
1950c716	284	};
35bdd290	285
d94e2553 DC	286	static struct regmap_config *
	287	sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
	288	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
	289	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
	290	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
dba6c1ae	291	[sta2x11_scr] = &sta2x11_scr_regmap_config,
1950c716	292	};
35bdd290	293
dba6c1ae	294	/* Probe for the four platform devices */
1950c716 DC	295
	296	static int sta2x11_mfd_platform_probe(struct platform_device *dev,
	297	enum sta2x11_mfd_plat_dev index)
35bdd290 AR	298	{
	299	struct pci_dev **pdev;
	300	struct sta2x11_mfd *mfd;
	301	struct resource *res;
1950c716	302	const char *name = sta2x11_mfd_names[index];
d94e2553	303	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
35bdd290	304
334a41ce	305	pdev = dev_get_platdata(&dev->dev);
35bdd290 AR	306	mfd = sta2x11_mfd_find(*pdev);
	307	if (!mfd)
	308	return -ENODEV;
d94e2553 DC	309	if (!regmap_config)
d94e2553 DC	310	return -ENODEV;
35bdd290 AR	311
	312	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	313	if (!res)
	314	return -ENOMEM;
	315
1950c716	316	if (!request_mem_region(res->start, resource_size(res), name))
35bdd290 AR	317	return -EBUSY;
35bdd290 AR	318
1950c716 DC	319	mfd->regs[index] = ioremap(res->start, resource_size(res));
1950c716 DC	320	if (!mfd->regs[index]) {
35bdd290 AR	321	release_mem_region(res->start, resource_size(res));
	322	return -ENOMEM;
	323	}
d94e2553 DC	324	regmap_config->lock_arg = &mfd->lock;
	325	/*
	326	No caching, registers could be reached both via regmap and via
	327	void __iomem *
	328	*/
	329	regmap_config->cache_type = REGCACHE_NONE;
	330	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
	331	regmap_config);
ec9e4ba6	332	WARN_ON(IS_ERR(mfd->regmap[index]));
35bdd290	333
35bdd290 AR	334	return 0;
	335	}
	336
1950c716 DC	337	static int sta2x11_sctl_probe(struct platform_device *dev)
	338	{
	339	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
	340	}
	341
	342	static int sta2x11_apbreg_probe(struct platform_device *dev)
	343	{
	344	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
	345	}
	346
	347	static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
	348	{
	349	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
	350	}
	351
dba6c1ae DC	352	static int sta2x11_scr_probe(struct platform_device *dev)
	353	{
	354	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
	355	}
	356
1950c716	357	/* The three platform drivers */
35bdd290 AR	358	static struct platform_driver sta2x11_sctl_platform_driver = {
35bdd290 AR	359	.driver = {
b18adafc	360	.name = STA2X11_MFD_SCTL_NAME,
35bdd290 AR	361	},
	362	.probe = sta2x11_sctl_probe,
	363	};
	364
35bdd290 AR	365	static struct platform_driver sta2x11_platform_driver = {
35bdd290 AR	366	.driver = {
b18adafc	367	.name = STA2X11_MFD_APBREG_NAME,
35bdd290 AR	368	},
	369	.probe = sta2x11_apbreg_probe,
	370	};
	371
1950c716 DC	372	static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
1950c716 DC	373	.driver = {
b18adafc	374	.name = STA2X11_MFD_APB_SOC_REGS_NAME,
1950c716 DC	375	},
	376	.probe = sta2x11_apb_soc_regs_probe,
	377	};
	378
dba6c1ae DC	379	static struct platform_driver sta2x11_scr_platform_driver = {
	380	.driver = {
	381	.name = STA2X11_MFD_SCR_NAME,
dba6c1ae DC	382	},
	383	.probe = sta2x11_scr_probe,
	384	};
	385
d91d76d8 TR	386	static struct platform_driver * const drivers[] = {
	387	&sta2x11_platform_driver,
	388	&sta2x11_sctl_platform_driver,
	389	&sta2x11_apb_soc_regs_platform_driver,
	390	&sta2x11_scr_platform_driver,
	391	};
	392
	393	static int __init sta2x11_drivers_init(void)
dba6c1ae	394	{
d91d76d8	395	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
dba6c1ae DC	396	}
dba6c1ae DC	397
35bdd290	398	/*
1950c716	399	* What follows are the PCI devices that host the above pdevs.
35bdd290 AR	400	* Each logic block is 4kB and they are all consecutive: we use this info.
	401	*/
	402
1950c716 DC	403	/* Mfd 0 device */
	404
	405	/* Mfd 0, Bar 0 */
	406	enum mfd0_bar0_cells {
35bdd290 AR	407	STA2X11_GPIO_0 = 0,
	408	STA2X11_GPIO_1,
	409	STA2X11_GPIO_2,
	410	STA2X11_GPIO_3,
	411	STA2X11_SCTL,
	412	STA2X11_SCR,
	413	STA2X11_TIME,
	414	};
1950c716 DC	415	/* Mfd 0 , Bar 1 */
1950c716 DC	416	enum mfd0_bar1_cells {
35bdd290 AR	417	STA2X11_APBREG = 0,
	418	};
	419	#define CELL_4K(_name, _cell) { \
	420	.name = _name, \
	421	.start = _cell * 4096, .end = _cell * 4096 + 4095, \
	422	.flags = IORESOURCE_MEM, \
	423	}
	424
a73e5df1	425	static const struct resource gpio_resources[] = {
35bdd290	426	{
b18adafc DC	427	/* 4 consecutive cells, 1 driver */
b18adafc DC	428	.name = STA2X11_MFD_GPIO_NAME,
35bdd290 AR	429	.start = 0,
	430	.end = (4 * 4096) - 1,
	431	.flags = IORESOURCE_MEM,
	432	}
	433	};
a73e5df1	434	static const struct resource sctl_resources[] = {
b18adafc	435	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
35bdd290	436	};
a73e5df1	437	static const struct resource scr_resources[] = {
b18adafc	438	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
35bdd290	439	};
a73e5df1	440	static const struct resource time_resources[] = {
b18adafc	441	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
35bdd290 AR	442	};
35bdd290 AR	443
a73e5df1	444	static const struct resource apbreg_resources[] = {
b18adafc	445	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
35bdd290 AR	446	};
	447
	448	#define DEV(_name, _r) \
	449	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
	450
2dfea380	451	static struct mfd_cell sta2x11_mfd0_bar0[] = {
b18adafc DC	452	/* offset 0: we add pdata later */
	453	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
	454	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
	455	DEV(STA2X11_MFD_SCR_NAME, scr_resources),
	456	DEV(STA2X11_MFD_TIME_NAME, time_resources),
35bdd290 AR	457	};
35bdd290 AR	458
2dfea380	459	static struct mfd_cell sta2x11_mfd0_bar1[] = {
b18adafc	460	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
35bdd290 AR	461	};
35bdd290 AR	462
1950c716 DC	463	/* Mfd 1 devices */
	464
	465	/* Mfd 1, Bar 0 */
	466	enum mfd1_bar0_cells {
	467	STA2X11_VIC = 0,
	468	};
	469
	470	/* Mfd 1, Bar 1 */
	471	enum mfd1_bar1_cells {
	472	STA2X11_APB_SOC_REGS = 0,
	473	};
	474
612b95cd	475	static const struct resource vic_resources[] = {
b18adafc	476	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
1950c716 DC	477	};
1950c716 DC	478
612b95cd	479	static const struct resource apb_soc_regs_resources[] = {
b18adafc	480	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
1950c716 DC	481	};
1950c716 DC	482
612b95cd	483	static struct mfd_cell sta2x11_mfd1_bar0[] = {
b18adafc	484	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
1950c716 DC	485	};
1950c716 DC	486
612b95cd	487	static struct mfd_cell sta2x11_mfd1_bar1[] = {
b18adafc	488	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
1950c716 DC	489	};
	490
	491
35bdd290 AR	492	static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
	493	{
	494	pci_save_state(pdev);
	495	pci_disable_device(pdev);
	496	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	497
	498	return 0;
	499	}
	500
	501	static int sta2x11_mfd_resume(struct pci_dev *pdev)
	502	{
	503	int err;
	504
4d1d9980	505	pci_set_power_state(pdev, PCI_D0);
35bdd290 AR	506	err = pci_enable_device(pdev);
	507	if (err)
	508	return err;
	509	pci_restore_state(pdev);
	510
	511	return 0;
	512	}
	513
1950c716 DC	514	struct sta2x11_mfd_bar_setup_data {
	515	struct mfd_cell *cells;
	516	int ncells;
	517	};
	518
	519	struct sta2x11_mfd_setup_data {
	520	struct sta2x11_mfd_bar_setup_data bars[2];
	521	};
	522
	523	#define STA2X11_MFD0 0
	524	#define STA2X11_MFD1 1
	525
	526	static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
	527	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
	528	[STA2X11_MFD0] = {
	529	.bars = {
	530	[0] = {
	531	.cells = sta2x11_mfd0_bar0,
	532	.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
	533	},
	534	[1] = {
	535	.cells = sta2x11_mfd0_bar1,
	536	.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
	537	},
	538	},
	539	},
	540	/* Mfd 1: vic / apb-soc-regs */
	541	[STA2X11_MFD1] = {
	542	.bars = {
	543	[0] = {
	544	.cells = sta2x11_mfd1_bar0,
	545	.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
	546	},
	547	[1] = {
	548	.cells = sta2x11_mfd1_bar1,
	549	.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
	550	},
	551	},
	552	},
	553	};
	554
2dfea380 LT	555	static void sta2x11_mfd_setup(struct pci_dev *pdev,
2dfea380 LT	556	struct sta2x11_mfd_setup_data *sd)
1950c716 DC	557	{
	558	int i, j;
	559	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
	560	for (j = 0; j < sd->bars[i].ncells; j++) {
	561	sd->bars[i].cells[j].pdata_size = sizeof(pdev);
	562	sd->bars[i].cells[j].platform_data = &pdev;
	563	}
	564	}
	565
f791be49	566	static int sta2x11_mfd_probe(struct pci_dev *pdev,
2dfea380	567	const struct pci_device_id *pci_id)
35bdd290 AR	568	{
35bdd290 AR	569	int err, i;
1950c716	570	struct sta2x11_mfd_setup_data *setup_data;
35bdd290 AR	571
	572	dev_info(&pdev->dev, "%s\n", __func__);
	573
	574	err = pci_enable_device(pdev);
	575	if (err) {
	576	dev_err(&pdev->dev, "Can't enable device.\n");
	577	return err;
	578	}
	579
	580	err = pci_enable_msi(pdev);
	581	if (err)
	582	dev_info(&pdev->dev, "Enable msi failed\n");
	583
1950c716 DC	584	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
	585	&mfd_setup_data[STA2X11_MFD0] :
	586	&mfd_setup_data[STA2X11_MFD1];
35bdd290 AR	587
35bdd290 AR	588	/* platform data is the pci device for all of them */
1950c716	589	sta2x11_mfd_setup(pdev, setup_data);
35bdd290 AR	590
35bdd290 AR	591	/* Record this pdev before mfd_add_devices: their probe looks for it */
8ec86a30	592	if (!sta2x11_mfd_find(pdev))
6ceb5f17	593	sta2x11_mfd_add(pdev, GFP_KERNEL);
35bdd290	594
1950c716 DC	595	/* Just 2 bars for all mfd's at present */
	596	for (i = 0; i < 2; i++) {
	597	err = mfd_add_devices(&pdev->dev, -1,
	598	setup_data->bars[i].cells,
	599	setup_data->bars[i].ncells,
	600	&pdev->resource[i],
	601	0, NULL);
	602	if (err) {
	603	dev_err(&pdev->dev,
	604	"mfd_add_devices[%d] failed: %d\n", i, err);
	605	goto err_disable;
	606	}
35bdd290 AR	607	}
	608
	609	return 0;
	610
	611	err_disable:
	612	mfd_remove_devices(&pdev->dev);
	613	pci_disable_device(pdev);
	614	pci_disable_msi(pdev);
	615	return err;
	616	}
	617
36fcd06c	618	static const struct pci_device_id sta2x11_mfd_tbl[] = {
35bdd290	619	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
1950c716	620	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
35bdd290 AR	621	{0,},
	622	};
	623
	624	static struct pci_driver sta2x11_mfd_driver = {
	625	.name = "sta2x11-mfd",
	626	.id_table = sta2x11_mfd_tbl,
	627	.probe = sta2x11_mfd_probe,
	628	.suspend = sta2x11_mfd_suspend,
	629	.resume = sta2x11_mfd_resume,
	630	};
	631
	632	static int __init sta2x11_mfd_init(void)
	633	{
	634	pr_info("%s\n", __func__);
	635	return pci_register_driver(&sta2x11_mfd_driver);
	636	}
	637
	638	/*
	639	* All of this must be ready before "normal" devices like MMCI appear.
	640	* But MFD (the pci device) can't be too early. The following choice
	641	* prepares platform drivers very early and probe the PCI device later,
	642	* but before other PCI devices.
	643	*/
d91d76d8	644	subsys_initcall(sta2x11_drivers_init);
35bdd290	645	rootfs_initcall(sta2x11_mfd_init);