[linux.git] / drivers / mfd / sta2x11-mfd.c

/*
 * Copyright (c) 2009-2011 Wind River Systems, Inc.
 * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/seq_file.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/sta2x11-mfd.h>
#include <linux/regmap.h>

#include <asm/sta2x11.h>

static inline int __reg_within_range(unsigned int r,
				     unsigned int start,
				     unsigned int end)
{
	return ((r >= start) && (r <= end));
}

/* This describes STA2X11 MFD chip for us, we may have several */
struct sta2x11_mfd {
	struct sta2x11_instance *instance;
	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
	spinlock_t lock[sta2x11_n_mfd_plat_devs];
	struct list_head list;
	void __iomem *regs[sta2x11_n_mfd_plat_devs];
};

static LIST_HEAD(sta2x11_mfd_list);

/* Three functions to act on the list */
static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev)
{
	struct sta2x11_instance *instance;
	struct sta2x11_mfd *mfd;

	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
		pr_warning("%s: Unspecified device, "
			    "using first instance\n", __func__);
		return list_entry(sta2x11_mfd_list.next,
				  struct sta2x11_mfd, list);
	}

	instance = sta2x11_get_instance(pdev);
	if (!instance)
		return NULL;
	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
		if (mfd->instance == instance)
			return mfd;
	}
	return NULL;
}

static int __devinit sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
{
	int i;
	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	struct sta2x11_instance *instance;

	if (mfd)
		return -EBUSY;
	instance = sta2x11_get_instance(pdev);
	if (!instance)
		return -EINVAL;
	mfd = kzalloc(sizeof(*mfd), flags);
	if (!mfd)
		return -ENOMEM;
	INIT_LIST_HEAD(&mfd->list);
	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
		spin_lock_init(&mfd->lock[i]);
	mfd->instance = instance;
	list_add(&mfd->list, &sta2x11_mfd_list);
	return 0;
}

static int __devexit mfd_remove(struct pci_dev *pdev)
{
	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);

	if (!mfd)
		return -ENODEV;
	list_del(&mfd->list);
	kfree(mfd);
	return 0;
}

/* This function is exported and is not expected to fail */
u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
		       enum sta2x11_mfd_plat_dev index)
{
	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	u32 r;
	unsigned long flags;
	void __iomem *regs = mfd->regs[index];

	if (!mfd) {
		dev_warn(&pdev->dev, ": can't access sctl regs\n");
		return 0;
	}
	if (!regs) {
		dev_warn(&pdev->dev, ": system ctl not initialized\n");
		return 0;
	}
	spin_lock_irqsave(&mfd->lock[index], flags);
	r = readl(regs + reg);
	r &= ~mask;
	r |= val;
	if (mask)
		writel(r, regs + reg);
	spin_unlock_irqrestore(&mfd->lock[index], flags);
	return r;
}
EXPORT_SYMBOL(__sta2x11_mfd_mask);

int sta2x11_mfd_get_regs_data(struct platform_device *dev,
			      enum sta2x11_mfd_plat_dev index,
			      void __iomem **regs,
			      spinlock_t **lock)
{
	struct pci_dev *pdev = *(struct pci_dev **)(dev->dev.platform_data);
	struct sta2x11_mfd *mfd;

	if (!pdev)
		return -ENODEV;
	mfd = sta2x11_mfd_find(pdev);
	if (!mfd)
		return -ENODEV;
	if (index >= sta2x11_n_mfd_plat_devs)
		return -ENODEV;
	*regs = mfd->regs[index];
	*lock = &mfd->lock[index];
	pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs);
	return *regs ? 0 : -ENODEV;
}
EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);

/*
 * Special sta2x11-mfd regmap lock/unlock functions
 */

static void sta2x11_regmap_lock(void *__lock)
{
	spinlock_t *lock = __lock;
	spin_lock(lock);
}

static void sta2x11_regmap_unlock(void *__lock)
{
	spinlock_t *lock = __lock;
	spin_unlock(lock);
}

/* OTP (one time programmable registers do not require locking */
static void sta2x11_regmap_nolock(void *__lock)
{
}

static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
};

static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
{
	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
}

static struct regmap_config sta2x11_sctl_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = SCTL_SCRSTSTA,
	.writeable_reg = sta2x11_sctl_writeable_reg,
};

static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
{
	return (reg == STA2X11_SECR_CR) ||
		__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
}

static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
{
	return false;
}

static struct regmap_config sta2x11_scr_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_nolock,
	.unlock = sta2x11_regmap_nolock,
	.max_register = STA2X11_SECR_FVR1,
	.readable_reg = sta2x11_scr_readable_reg,
	.writeable_reg = sta2x11_scr_writeable_reg,
};

static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
{
	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
	if (reg >= APBREG_BSR_SARAC)
		reg -= APBREG_BSR_SARAC;
	switch (reg) {
	case APBREG_BSR:
	case APBREG_PAER:
	case APBREG_PWAC:
	case APBREG_PRAC:
	case APBREG_PCG:
	case APBREG_PUR:
	case APBREG_EMU_PCG:
		return true;
	default:
		return false;
	}
}

static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
{
	if (reg >= APBREG_BSR_SARAC)
		reg -= APBREG_BSR_SARAC;
	if (!sta2x11_apbreg_readable_reg(dev, reg))
		return false;
	return reg != APBREG_PAER;
}

static struct regmap_config sta2x11_apbreg_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = APBREG_EMU_PCG_SARAC,
	.readable_reg = sta2x11_apbreg_readable_reg,
	.writeable_reg = sta2x11_apbreg_writeable_reg,
};

static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
					      unsigned int reg)
{
	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
		__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
		__reg_within_range(reg, MASTER_LOCK_REG,
				   SYSTEM_CONFIG_STATUS_REG) ||
		reg == MSP_CLK_CTRL_REG ||
		__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
}

static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
					       unsigned int reg)
{
	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
		return false;
	switch (reg) {
	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
	case SYSTEM_CONFIG_STATUS_REG:
	case COMPENSATION_REG1:
	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
		return false;
	default:
		return true;
	}
}

static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = TEST_CTL_REG,
	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
};

static struct regmap_config *
sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
	[sta2x11_scr] = &sta2x11_scr_regmap_config,
};

/* Probe for the four platform devices */

static int sta2x11_mfd_platform_probe(struct platform_device *dev,
				      enum sta2x11_mfd_plat_dev index)
{
	struct pci_dev **pdev;
	struct sta2x11_mfd *mfd;
	struct resource *res;
	const char *name = sta2x11_mfd_names[index];
	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];

	pdev = dev->dev.platform_data;
	mfd = sta2x11_mfd_find(*pdev);
	if (!mfd)
		return -ENODEV;
	if (!regmap_config)
		return -ENODEV;

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOMEM;

	if (!request_mem_region(res->start, resource_size(res), name))
		return -EBUSY;

	mfd->regs[index] = ioremap(res->start, resource_size(res));
	if (!mfd->regs[index]) {
		release_mem_region(res->start, resource_size(res));
		return -ENOMEM;
	}
	regmap_config->lock_arg = &mfd->lock;
	/*
	   No caching, registers could be reached both via regmap and via
	   void __iomem *
	*/
	regmap_config->cache_type = REGCACHE_NONE;
	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
						   regmap_config);
	WARN_ON(!mfd->regmap[index]);

	return 0;
}

static int sta2x11_sctl_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
}

static int sta2x11_apbreg_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
}

static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
}

static int sta2x11_scr_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
}

/* The three platform drivers */
static struct platform_driver sta2x11_sctl_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_SCTL_NAME,
		.owner	= THIS_MODULE,
	},
	.probe		= sta2x11_sctl_probe,
};

static int __init sta2x11_sctl_init(void)
{
	pr_info("%s\n", __func__);
	return platform_driver_register(&sta2x11_sctl_platform_driver);
}

static struct platform_driver sta2x11_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_APBREG_NAME,
		.owner	= THIS_MODULE,
	},
	.probe		= sta2x11_apbreg_probe,
};

static int __init sta2x11_apbreg_init(void)
{
	pr_info("%s\n", __func__);
	return platform_driver_register(&sta2x11_platform_driver);
}

static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_APB_SOC_REGS_NAME,
		.owner	= THIS_MODULE,
	},
	.probe		= sta2x11_apb_soc_regs_probe,
};

static int __init sta2x11_apb_soc_regs_init(void)
{
	pr_info("%s\n", __func__);
	return platform_driver_register(&sta2x11_apb_soc_regs_platform_driver);
}

static struct platform_driver sta2x11_scr_platform_driver = {
	.driver = {
		.name = STA2X11_MFD_SCR_NAME,
		.owner = THIS_MODULE,
	},
	.probe = sta2x11_scr_probe,
};

static int __init sta2x11_scr_init(void)
{
	pr_info("%s\n", __func__);
	return platform_driver_register(&sta2x11_scr_platform_driver);
}


/*
 * What follows are the PCI devices that host the above pdevs.
 * Each logic block is 4kB and they are all consecutive: we use this info.
 */

/* Mfd 0 device */

/* Mfd 0, Bar 0 */
enum mfd0_bar0_cells {
	STA2X11_GPIO_0 = 0,
	STA2X11_GPIO_1,
	STA2X11_GPIO_2,
	STA2X11_GPIO_3,
	STA2X11_SCTL,
	STA2X11_SCR,
	STA2X11_TIME,
};
/* Mfd 0 , Bar 1 */
enum mfd0_bar1_cells {
	STA2X11_APBREG = 0,
};
#define CELL_4K(_name, _cell) { \
		.name = _name, \
		.start = _cell * 4096, .end = _cell * 4096 + 4095, \
		.flags = IORESOURCE_MEM, \
		}

static const __devinitconst struct resource gpio_resources[] = {
	{
		/* 4 consecutive cells, 1 driver */
		.name = STA2X11_MFD_GPIO_NAME,
		.start = 0,
		.end = (4 * 4096) - 1,
		.flags = IORESOURCE_MEM,
	}
};
static const __devinitconst struct resource sctl_resources[] = {
	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
};
static const __devinitconst struct resource scr_resources[] = {
	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
};
static const __devinitconst struct resource time_resources[] = {
	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
};

static const __devinitconst struct resource apbreg_resources[] = {
	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
};

#define DEV(_name, _r) \
	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }

static __devinitdata struct mfd_cell sta2x11_mfd0_bar0[] = {
	/* offset 0: we add pdata later */
	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
	DEV(STA2X11_MFD_SCR_NAME,  scr_resources),
	DEV(STA2X11_MFD_TIME_NAME, time_resources),
};

static __devinitdata struct mfd_cell sta2x11_mfd0_bar1[] = {
	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
};

/* Mfd 1 devices */

/* Mfd 1, Bar 0 */
enum mfd1_bar0_cells {
	STA2X11_VIC = 0,
};

/* Mfd 1, Bar 1 */
enum mfd1_bar1_cells {
	STA2X11_APB_SOC_REGS = 0,
};

static const __devinitconst struct resource vic_resources[] = {
	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
};

static const __devinitconst struct resource apb_soc_regs_resources[] = {
	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
};

static __devinitdata struct mfd_cell sta2x11_mfd1_bar0[] = {
	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
};

static __devinitdata struct mfd_cell sta2x11_mfd1_bar1[] = {
	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
};


static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
{
	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, pci_choose_state(pdev, state));

	return 0;
}

static int sta2x11_mfd_resume(struct pci_dev *pdev)
{
	int err;

	pci_set_power_state(pdev, 0);
	err = pci_enable_device(pdev);
	if (err)
		return err;
	pci_restore_state(pdev);

	return 0;
}

struct sta2x11_mfd_bar_setup_data {
	struct mfd_cell *cells;
	int ncells;
};

struct sta2x11_mfd_setup_data {
	struct sta2x11_mfd_bar_setup_data bars[2];
};

#define STA2X11_MFD0 0
#define STA2X11_MFD1 1

static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
	[STA2X11_MFD0] = {
		.bars = {
			[0] = {
				.cells = sta2x11_mfd0_bar0,
				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
			},
			[1] = {
				.cells = sta2x11_mfd0_bar1,
				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
			},
		},
	},
	/* Mfd 1: vic / apb-soc-regs */
	[STA2X11_MFD1] = {
		.bars = {
			[0] = {
				.cells = sta2x11_mfd1_bar0,
				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
			},
			[1] = {
				.cells = sta2x11_mfd1_bar1,
				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
			},
		},
	},
};

static void __devinit sta2x11_mfd_setup(struct pci_dev *pdev,
					struct sta2x11_mfd_setup_data *sd)
{
	int i, j;
	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
		for (j = 0; j < sd->bars[i].ncells; j++) {
			sd->bars[i].cells[j].pdata_size = sizeof(pdev);
			sd->bars[i].cells[j].platform_data = &pdev;
		}
}

static int __devinit sta2x11_mfd_probe(struct pci_dev *pdev,
				       const struct pci_device_id *pci_id)
{
	int err, i;
	struct sta2x11_mfd_setup_data *setup_data;

	dev_info(&pdev->dev, "%s\n", __func__);

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "Can't enable device.\n");
		return err;
	}

	err = pci_enable_msi(pdev);
	if (err)
		dev_info(&pdev->dev, "Enable msi failed\n");

	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
		&mfd_setup_data[STA2X11_MFD0] :
		&mfd_setup_data[STA2X11_MFD1];

	/* platform data is the pci device for all of them */
	sta2x11_mfd_setup(pdev, setup_data);

	/* Record this pdev before mfd_add_devices: their probe looks for it */
	if (!sta2x11_mfd_find(pdev))
		sta2x11_mfd_add(pdev, GFP_ATOMIC);

	/* Just 2 bars for all mfd's at present */
	for (i = 0; i < 2; i++) {
		err = mfd_add_devices(&pdev->dev, -1,
				      setup_data->bars[i].cells,
				      setup_data->bars[i].ncells,
				      &pdev->resource[i],
				      0, NULL);
		if (err) {
			dev_err(&pdev->dev,
				"mfd_add_devices[%d] failed: %d\n", i, err);
			goto err_disable;
		}
	}

	return 0;

err_disable:
	mfd_remove_devices(&pdev->dev);
	pci_disable_device(pdev);
	pci_disable_msi(pdev);
	return err;
}

static DEFINE_PCI_DEVICE_TABLE(sta2x11_mfd_tbl) = {
	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
	{0,},
};

static struct pci_driver sta2x11_mfd_driver = {
	.name =		"sta2x11-mfd",
	.id_table =	sta2x11_mfd_tbl,
	.probe =	sta2x11_mfd_probe,
	.suspend =	sta2x11_mfd_suspend,
	.resume =	sta2x11_mfd_resume,
};

static int __init sta2x11_mfd_init(void)
{
	pr_info("%s\n", __func__);
	return pci_register_driver(&sta2x11_mfd_driver);
}

/*
 * All of this must be ready before "normal" devices like MMCI appear.
 * But MFD (the pci device) can't be too early. The following choice
 * prepares platform drivers very early and probe the PCI device later,
 * but before other PCI devices.
 */
subsys_initcall(sta2x11_apbreg_init);
subsys_initcall(sta2x11_sctl_init);
subsys_initcall(sta2x11_apb_soc_regs_init);
subsys_initcall(sta2x11_scr_init);
rootfs_initcall(sta2x11_mfd_init);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Wind River");
MODULE_DESCRIPTION("STA2x11 mfd for GPIO, SCTL and APBREG");
MODULE_DEVICE_TABLE(pci, sta2x11_mfd_tbl);
Commit	Line	Data
35bdd290 AR	1	/*
35bdd290 AR	2	* Copyright (c) 2009-2011 Wind River Systems, Inc.
b73df698	3	* Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
35bdd290 AR	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	12	* See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/errno.h>
	24	#include <linux/device.h>
	25	#include <linux/slab.h>
	26	#include <linux/list.h>
	27	#include <linux/io.h>
	28	#include <linux/ioport.h>
	29	#include <linux/pci.h>
35bdd290 AR	30	#include <linux/seq_file.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/mfd/core.h>
	33	#include <linux/mfd/sta2x11-mfd.h>
d94e2553	34	#include <linux/regmap.h>
35bdd290 AR	35
	36	#include <asm/sta2x11.h>
	37
d94e2553 DC	38	static inline int __reg_within_range(unsigned int r,
	39	unsigned int start,
	40	unsigned int end)
	41	{
	42	return ((r >= start) && (r <= end));
	43	}
	44
35bdd290 AR	45	/* This describes STA2X11 MFD chip for us, we may have several */
	46	struct sta2x11_mfd {
	47	struct sta2x11_instance *instance;
d94e2553	48	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
e885ba29	49	spinlock_t lock[sta2x11_n_mfd_plat_devs];
35bdd290	50	struct list_head list;
1950c716	51	void __iomem *regs[sta2x11_n_mfd_plat_devs];
35bdd290 AR	52	};
	53
	54	static LIST_HEAD(sta2x11_mfd_list);
	55
	56	/* Three functions to act on the list */
	57	static struct sta2x11_mfd sta2x11_mfd_find(struct pci_dev pdev)
	58	{
	59	struct sta2x11_instance *instance;
	60	struct sta2x11_mfd *mfd;
	61
	62	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
	63	pr_warning("%s: Unspecified device, "
	64	"using first instance\n", __func__);
	65	return list_entry(sta2x11_mfd_list.next,
	66	struct sta2x11_mfd, list);
	67	}
	68
	69	instance = sta2x11_get_instance(pdev);
	70	if (!instance)
	71	return NULL;
	72	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
	73	if (mfd->instance == instance)
	74	return mfd;
	75	}
	76	return NULL;
	77	}
	78
	79	static int __devinit sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
	80	{
e885ba29	81	int i;
35bdd290 AR	82	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	83	struct sta2x11_instance *instance;
	84
	85	if (mfd)
	86	return -EBUSY;
	87	instance = sta2x11_get_instance(pdev);
	88	if (!instance)
	89	return -EINVAL;
	90	mfd = kzalloc(sizeof(*mfd), flags);
	91	if (!mfd)
	92	return -ENOMEM;
	93	INIT_LIST_HEAD(&mfd->list);
e885ba29 DC	94	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
e885ba29 DC	95	spin_lock_init(&mfd->lock[i]);
35bdd290 AR	96	mfd->instance = instance;
	97	list_add(&mfd->list, &sta2x11_mfd_list);
	98	return 0;
	99	}
	100
	101	static int __devexit mfd_remove(struct pci_dev *pdev)
	102	{
	103	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	104
	105	if (!mfd)
	106	return -ENODEV;
	107	list_del(&mfd->list);
	108	kfree(mfd);
	109	return 0;
	110	}
	111
1950c716 DC	112	/* This function is exported and is not expected to fail */
	113	u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
	114	enum sta2x11_mfd_plat_dev index)
35bdd290 AR	115	{
	116	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	117	u32 r;
	118	unsigned long flags;
1950c716	119	void __iomem *regs = mfd->regs[index];
35bdd290 AR	120
	121	if (!mfd) {
	122	dev_warn(&pdev->dev, ": can't access sctl regs\n");
	123	return 0;
	124	}
1950c716	125	if (!regs) {
35bdd290 AR	126	dev_warn(&pdev->dev, ": system ctl not initialized\n");
	127	return 0;
	128	}
e885ba29	129	spin_lock_irqsave(&mfd->lock[index], flags);
1950c716	130	r = readl(regs + reg);
35bdd290 AR	131	r &= ~mask;
	132	r \|= val;
	133	if (mask)
1950c716	134	writel(r, regs + reg);
e885ba29	135	spin_unlock_irqrestore(&mfd->lock[index], flags);
35bdd290 AR	136	return r;
35bdd290 AR	137	}
1950c716	138	EXPORT_SYMBOL(__sta2x11_mfd_mask);
35bdd290	139
29f5b5a3 DC	140	int sta2x11_mfd_get_regs_data(struct platform_device *dev,
	141	enum sta2x11_mfd_plat_dev index,
	142	void __iomem **regs,
	143	spinlock_t **lock)
	144	{
	145	struct pci_dev pdev = (struct pci_dev **)(dev->dev.platform_data);
	146	struct sta2x11_mfd *mfd;
	147
	148	if (!pdev)
	149	return -ENODEV;
	150	mfd = sta2x11_mfd_find(pdev);
	151	if (!mfd)
	152	return -ENODEV;
	153	if (index >= sta2x11_n_mfd_plat_devs)
	154	return -ENODEV;
	155	*regs = mfd->regs[index];
	156	*lock = &mfd->lock[index];
	157	pr_debug("%s %d regs = %p\n", __func__, __LINE__, regs);
	158	return *regs ? 0 : -ENODEV;
	159	}
	160	EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);
	161
d94e2553 DC	162	/*
	163	* Special sta2x11-mfd regmap lock/unlock functions
	164	*/
35bdd290	165
d94e2553 DC	166	static void sta2x11_regmap_lock(void *__lock)
	167	{
	168	spinlock_t *lock = __lock;
	169	spin_lock(lock);
	170	}
35bdd290	171
d94e2553 DC	172	static void sta2x11_regmap_unlock(void *__lock)
	173	{
	174	spinlock_t *lock = __lock;
	175	spin_unlock(lock);
	176	}
35bdd290	177
dba6c1ae DC	178	/* OTP (one time programmable registers do not require locking */
	179	static void sta2x11_regmap_nolock(void *__lock)
	180	{
	181	}
	182
d94e2553	183	static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
b18adafc DC	184	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
	185	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
	186	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
dba6c1ae	187	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
35bdd290 AR	188	};
35bdd290 AR	189
d94e2553 DC	190	static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
	191	{
	192	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
	193	}
	194
	195	static struct regmap_config sta2x11_sctl_regmap_config = {
	196	.reg_bits = 32,
	197	.reg_stride = 4,
	198	.val_bits = 32,
	199	.lock = sta2x11_regmap_lock,
	200	.unlock = sta2x11_regmap_unlock,
	201	.max_register = SCTL_SCRSTSTA,
	202	.writeable_reg = sta2x11_sctl_writeable_reg,
1950c716	203	};
35bdd290	204
dba6c1ae DC	205	static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
	206	{
	207	return (reg == STA2X11_SECR_CR) \|\|
	208	__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
	209	}
	210
	211	static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
	212	{
	213	return false;
	214	}
	215
	216	static struct regmap_config sta2x11_scr_regmap_config = {
	217	.reg_bits = 32,
	218	.reg_stride = 4,
	219	.val_bits = 32,
	220	.lock = sta2x11_regmap_nolock,
	221	.unlock = sta2x11_regmap_nolock,
	222	.max_register = STA2X11_SECR_FVR1,
	223	.readable_reg = sta2x11_scr_readable_reg,
	224	.writeable_reg = sta2x11_scr_writeable_reg,
	225	};
	226
d94e2553 DC	227	static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
	228	{
	229	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
	230	if (reg >= APBREG_BSR_SARAC)
	231	reg -= APBREG_BSR_SARAC;
	232	switch (reg) {
	233	case APBREG_BSR:
	234	case APBREG_PAER:
	235	case APBREG_PWAC:
	236	case APBREG_PRAC:
	237	case APBREG_PCG:
	238	case APBREG_PUR:
	239	case APBREG_EMU_PCG:
	240	return true;
	241	default:
	242	return false;
	243	}
	244	}
	245
	246	static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
	247	{
	248	if (reg >= APBREG_BSR_SARAC)
	249	reg -= APBREG_BSR_SARAC;
	250	if (!sta2x11_apbreg_readable_reg(dev, reg))
	251	return false;
	252	return reg != APBREG_PAER;
	253	}
	254
	255	static struct regmap_config sta2x11_apbreg_regmap_config = {
	256	.reg_bits = 32,
	257	.reg_stride = 4,
	258	.val_bits = 32,
	259	.lock = sta2x11_regmap_lock,
	260	.unlock = sta2x11_regmap_unlock,
	261	.max_register = APBREG_EMU_PCG_SARAC,
	262	.readable_reg = sta2x11_apbreg_readable_reg,
	263	.writeable_reg = sta2x11_apbreg_writeable_reg,
1950c716	264	};
35bdd290	265
d94e2553 DC	266	static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
	267	unsigned int reg)
	268	{
	269	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG \|\|
	270	__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) \|\|
	271	__reg_within_range(reg, MASTER_LOCK_REG,
	272	SYSTEM_CONFIG_STATUS_REG) \|\|
	273	reg == MSP_CLK_CTRL_REG \|\|
	274	__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
	275	}
35bdd290	276
d94e2553 DC	277	static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
	278	unsigned int reg)
	279	{
	280	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
	281	return false;
	282	switch (reg) {
	283	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
	284	case SYSTEM_CONFIG_STATUS_REG:
	285	case COMPENSATION_REG1:
	286	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
	287	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
	288	return false;
	289	default:
	290	return true;
	291	}
	292	}
35bdd290	293
d94e2553 DC	294	static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
	295	.reg_bits = 32,
	296	.reg_stride = 4,
	297	.val_bits = 32,
	298	.lock = sta2x11_regmap_lock,
	299	.unlock = sta2x11_regmap_unlock,
	300	.max_register = TEST_CTL_REG,
	301	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
	302	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
1950c716	303	};
35bdd290	304
d94e2553 DC	305	static struct regmap_config *
	306	sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
	307	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
	308	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
	309	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
dba6c1ae	310	[sta2x11_scr] = &sta2x11_scr_regmap_config,
1950c716	311	};
35bdd290	312
dba6c1ae	313	/* Probe for the four platform devices */
1950c716 DC	314
	315	static int sta2x11_mfd_platform_probe(struct platform_device *dev,
	316	enum sta2x11_mfd_plat_dev index)
35bdd290 AR	317	{
	318	struct pci_dev **pdev;
	319	struct sta2x11_mfd *mfd;
	320	struct resource *res;
1950c716	321	const char *name = sta2x11_mfd_names[index];
d94e2553	322	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
35bdd290 AR	323
35bdd290 AR	324	pdev = dev->dev.platform_data;
35bdd290 AR	325	mfd = sta2x11_mfd_find(*pdev);
	326	if (!mfd)
	327	return -ENODEV;
d94e2553 DC	328	if (!regmap_config)
d94e2553 DC	329	return -ENODEV;
35bdd290 AR	330
	331	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	332	if (!res)
	333	return -ENOMEM;
	334
1950c716	335	if (!request_mem_region(res->start, resource_size(res), name))
35bdd290 AR	336	return -EBUSY;
35bdd290 AR	337
1950c716 DC	338	mfd->regs[index] = ioremap(res->start, resource_size(res));
1950c716 DC	339	if (!mfd->regs[index]) {
35bdd290 AR	340	release_mem_region(res->start, resource_size(res));
	341	return -ENOMEM;
	342	}
d94e2553 DC	343	regmap_config->lock_arg = &mfd->lock;
	344	/*
	345	No caching, registers could be reached both via regmap and via
	346	void __iomem *
	347	*/
	348	regmap_config->cache_type = REGCACHE_NONE;
	349	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
	350	regmap_config);
	351	WARN_ON(!mfd->regmap[index]);
	352
35bdd290 AR	353	return 0;
	354	}
	355
1950c716 DC	356	static int sta2x11_sctl_probe(struct platform_device *dev)
	357	{
	358	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
	359	}
	360
	361	static int sta2x11_apbreg_probe(struct platform_device *dev)
	362	{
	363	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
	364	}
	365
	366	static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
	367	{
	368	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
	369	}
	370
dba6c1ae DC	371	static int sta2x11_scr_probe(struct platform_device *dev)
	372	{
	373	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
	374	}
	375
1950c716	376	/* The three platform drivers */
35bdd290 AR	377	static struct platform_driver sta2x11_sctl_platform_driver = {
35bdd290 AR	378	.driver = {
b18adafc	379	.name = STA2X11_MFD_SCTL_NAME,
35bdd290 AR	380	.owner = THIS_MODULE,
	381	},
	382	.probe = sta2x11_sctl_probe,
	383	};
	384
	385	static int __init sta2x11_sctl_init(void)
	386	{
	387	pr_info("%s\n", __func__);
	388	return platform_driver_register(&sta2x11_sctl_platform_driver);
	389	}
	390
	391	static struct platform_driver sta2x11_platform_driver = {
	392	.driver = {
b18adafc	393	.name = STA2X11_MFD_APBREG_NAME,
35bdd290 AR	394	.owner = THIS_MODULE,
	395	},
	396	.probe = sta2x11_apbreg_probe,
	397	};
	398
	399	static int __init sta2x11_apbreg_init(void)
	400	{
	401	pr_info("%s\n", __func__);
	402	return platform_driver_register(&sta2x11_platform_driver);
	403	}
	404
1950c716 DC	405	static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
1950c716 DC	406	.driver = {
b18adafc	407	.name = STA2X11_MFD_APB_SOC_REGS_NAME,
1950c716 DC	408	.owner = THIS_MODULE,
	409	},
	410	.probe = sta2x11_apb_soc_regs_probe,
	411	};
	412
	413	static int __init sta2x11_apb_soc_regs_init(void)
	414	{
	415	pr_info("%s\n", __func__);
	416	return platform_driver_register(&sta2x11_apb_soc_regs_platform_driver);
	417	}
	418
dba6c1ae DC	419	static struct platform_driver sta2x11_scr_platform_driver = {
	420	.driver = {
	421	.name = STA2X11_MFD_SCR_NAME,
	422	.owner = THIS_MODULE,
	423	},
	424	.probe = sta2x11_scr_probe,
	425	};
	426
	427	static int __init sta2x11_scr_init(void)
	428	{
	429	pr_info("%s\n", __func__);
	430	return platform_driver_register(&sta2x11_scr_platform_driver);
	431	}
	432
	433
35bdd290	434	/*
1950c716	435	* What follows are the PCI devices that host the above pdevs.
35bdd290 AR	436	* Each logic block is 4kB and they are all consecutive: we use this info.
	437	*/
	438
1950c716 DC	439	/* Mfd 0 device */
	440
	441	/* Mfd 0, Bar 0 */
	442	enum mfd0_bar0_cells {
35bdd290 AR	443	STA2X11_GPIO_0 = 0,
	444	STA2X11_GPIO_1,
	445	STA2X11_GPIO_2,
	446	STA2X11_GPIO_3,
	447	STA2X11_SCTL,
	448	STA2X11_SCR,
	449	STA2X11_TIME,
	450	};
1950c716 DC	451	/* Mfd 0 , Bar 1 */
1950c716 DC	452	enum mfd0_bar1_cells {
35bdd290 AR	453	STA2X11_APBREG = 0,
	454	};
	455	#define CELL_4K(_name, _cell) { \
	456	.name = _name, \
	457	.start = _cell * 4096, .end = _cell * 4096 + 4095, \
	458	.flags = IORESOURCE_MEM, \
	459	}
	460
	461	static const __devinitconst struct resource gpio_resources[] = {
	462	{
b18adafc DC	463	/* 4 consecutive cells, 1 driver */
b18adafc DC	464	.name = STA2X11_MFD_GPIO_NAME,
35bdd290 AR	465	.start = 0,
	466	.end = (4 * 4096) - 1,
	467	.flags = IORESOURCE_MEM,
	468	}
	469	};
	470	static const __devinitconst struct resource sctl_resources[] = {
b18adafc	471	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
35bdd290 AR	472	};
35bdd290 AR	473	static const __devinitconst struct resource scr_resources[] = {
b18adafc	474	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
35bdd290 AR	475	};
35bdd290 AR	476	static const __devinitconst struct resource time_resources[] = {
b18adafc	477	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
35bdd290 AR	478	};
	479
	480	static const __devinitconst struct resource apbreg_resources[] = {
b18adafc	481	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
35bdd290 AR	482	};
	483
	484	#define DEV(_name, _r) \
	485	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
	486
1950c716	487	static __devinitdata struct mfd_cell sta2x11_mfd0_bar0[] = {
b18adafc DC	488	/* offset 0: we add pdata later */
	489	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
	490	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
	491	DEV(STA2X11_MFD_SCR_NAME, scr_resources),
	492	DEV(STA2X11_MFD_TIME_NAME, time_resources),
35bdd290 AR	493	};
35bdd290 AR	494
1950c716	495	static __devinitdata struct mfd_cell sta2x11_mfd0_bar1[] = {
b18adafc	496	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
35bdd290 AR	497	};
35bdd290 AR	498
1950c716 DC	499	/* Mfd 1 devices */
	500
	501	/* Mfd 1, Bar 0 */
	502	enum mfd1_bar0_cells {
	503	STA2X11_VIC = 0,
	504	};
	505
	506	/* Mfd 1, Bar 1 */
	507	enum mfd1_bar1_cells {
	508	STA2X11_APB_SOC_REGS = 0,
	509	};
	510
	511	static const __devinitconst struct resource vic_resources[] = {
b18adafc	512	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
1950c716 DC	513	};
	514
	515	static const __devinitconst struct resource apb_soc_regs_resources[] = {
b18adafc	516	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
1950c716 DC	517	};
	518
	519	static __devinitdata struct mfd_cell sta2x11_mfd1_bar0[] = {
b18adafc	520	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
1950c716 DC	521	};
	522
	523	static __devinitdata struct mfd_cell sta2x11_mfd1_bar1[] = {
b18adafc	524	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
1950c716 DC	525	};
	526
	527
35bdd290 AR	528	static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
	529	{
	530	pci_save_state(pdev);
	531	pci_disable_device(pdev);
	532	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	533
	534	return 0;
	535	}
	536
	537	static int sta2x11_mfd_resume(struct pci_dev *pdev)
	538	{
	539	int err;
	540
	541	pci_set_power_state(pdev, 0);
	542	err = pci_enable_device(pdev);
	543	if (err)
	544	return err;
	545	pci_restore_state(pdev);
	546
	547	return 0;
	548	}
	549
1950c716 DC	550	struct sta2x11_mfd_bar_setup_data {
	551	struct mfd_cell *cells;
	552	int ncells;
	553	};
	554
	555	struct sta2x11_mfd_setup_data {
	556	struct sta2x11_mfd_bar_setup_data bars[2];
	557	};
	558
	559	#define STA2X11_MFD0 0
	560	#define STA2X11_MFD1 1
	561
	562	static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
	563	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
	564	[STA2X11_MFD0] = {
	565	.bars = {
	566	[0] = {
	567	.cells = sta2x11_mfd0_bar0,
	568	.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
	569	},
	570	[1] = {
	571	.cells = sta2x11_mfd0_bar1,
	572	.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
	573	},
	574	},
	575	},
	576	/* Mfd 1: vic / apb-soc-regs */
	577	[STA2X11_MFD1] = {
	578	.bars = {
	579	[0] = {
	580	.cells = sta2x11_mfd1_bar0,
	581	.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
	582	},
	583	[1] = {
	584	.cells = sta2x11_mfd1_bar1,
	585	.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
	586	},
	587	},
	588	},
	589	};
	590
	591	static void __devinit sta2x11_mfd_setup(struct pci_dev *pdev,
	592	struct sta2x11_mfd_setup_data *sd)
	593	{
	594	int i, j;
	595	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
	596	for (j = 0; j < sd->bars[i].ncells; j++) {
	597	sd->bars[i].cells[j].pdata_size = sizeof(pdev);
	598	sd->bars[i].cells[j].platform_data = &pdev;
	599	}
	600	}
	601
35bdd290 AR	602	static int __devinit sta2x11_mfd_probe(struct pci_dev *pdev,
	603	const struct pci_device_id *pci_id)
	604	{
	605	int err, i;
1950c716	606	struct sta2x11_mfd_setup_data *setup_data;
35bdd290 AR	607
	608	dev_info(&pdev->dev, "%s\n", __func__);
	609
	610	err = pci_enable_device(pdev);
	611	if (err) {
	612	dev_err(&pdev->dev, "Can't enable device.\n");
	613	return err;
	614	}
	615
	616	err = pci_enable_msi(pdev);
	617	if (err)
	618	dev_info(&pdev->dev, "Enable msi failed\n");
	619
1950c716 DC	620	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
	621	&mfd_setup_data[STA2X11_MFD0] :
	622	&mfd_setup_data[STA2X11_MFD1];
	623
35bdd290	624	/* platform data is the pci device for all of them */
1950c716	625	sta2x11_mfd_setup(pdev, setup_data);
35bdd290 AR	626
35bdd290 AR	627	/* Record this pdev before mfd_add_devices: their probe looks for it */
8ec86a30 DC	628	if (!sta2x11_mfd_find(pdev))
8ec86a30 DC	629	sta2x11_mfd_add(pdev, GFP_ATOMIC);
35bdd290	630
1950c716 DC	631	/* Just 2 bars for all mfd's at present */
	632	for (i = 0; i < 2; i++) {
	633	err = mfd_add_devices(&pdev->dev, -1,
	634	setup_data->bars[i].cells,
	635	setup_data->bars[i].ncells,
	636	&pdev->resource[i],
	637	0, NULL);
	638	if (err) {
	639	dev_err(&pdev->dev,
	640	"mfd_add_devices[%d] failed: %d\n", i, err);
	641	goto err_disable;
	642	}
35bdd290 AR	643	}
	644
	645	return 0;
	646
	647	err_disable:
	648	mfd_remove_devices(&pdev->dev);
	649	pci_disable_device(pdev);
	650	pci_disable_msi(pdev);
	651	return err;
	652	}
	653
	654	static DEFINE_PCI_DEVICE_TABLE(sta2x11_mfd_tbl) = {
	655	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
1950c716	656	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
35bdd290 AR	657	{0,},
	658	};
	659
	660	static struct pci_driver sta2x11_mfd_driver = {
	661	.name = "sta2x11-mfd",
	662	.id_table = sta2x11_mfd_tbl,
	663	.probe = sta2x11_mfd_probe,
	664	.suspend = sta2x11_mfd_suspend,
	665	.resume = sta2x11_mfd_resume,
	666	};
	667
	668	static int __init sta2x11_mfd_init(void)
	669	{
	670	pr_info("%s\n", __func__);
	671	return pci_register_driver(&sta2x11_mfd_driver);
	672	}
	673
	674	/*
	675	* All of this must be ready before "normal" devices like MMCI appear.
	676	* But MFD (the pci device) can't be too early. The following choice
	677	* prepares platform drivers very early and probe the PCI device later,
	678	* but before other PCI devices.
	679	*/
	680	subsys_initcall(sta2x11_apbreg_init);
	681	subsys_initcall(sta2x11_sctl_init);
1950c716	682	subsys_initcall(sta2x11_apb_soc_regs_init);
dba6c1ae	683	subsys_initcall(sta2x11_scr_init);
35bdd290 AR	684	rootfs_initcall(sta2x11_mfd_init);
	685
	686	MODULE_LICENSE("GPL v2");
	687	MODULE_AUTHOR("Wind River");
	688	MODULE_DESCRIPTION("STA2x11 mfd for GPIO, SCTL and APBREG");
	689	MODULE_DEVICE_TABLE(pci, sta2x11_mfd_tbl);