[linux.git] / arch / arm / boot / dts / lpc18xx.dtsi

/*
 * Common base for NXP LPC18xx and LPC43xx devices.
 *
 * Copyright 2015 Joachim Eastwood <[email protected]>
 *
 * This code is released using a dual license strategy: BSD/GPL
 * You can choose the licence that better fits your requirements.
 *
 * Released under the terms of 3-clause BSD License
 * Released under the terms of GNU General Public License Version 2.0
 *
 */

#include "armv7-m.dtsi"

#include "dt-bindings/clock/lpc18xx-cgu.h"
#include "dt-bindings/clock/lpc18xx-ccu.h"

#define LPC_PIN(port, pin)	(0x##port * 32 + pin)
#define LPC_GPIO(port, pin)	(port * 32 + pin)

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-m3";
			device_type = "cpu";
			reg = <0x0>;
			clocks = <&ccu1 CLK_CPU_CORE>;
		};
	};

	clocks {
		xtal: xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		xtal32: xtal32 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		enet_rx_clk: enet_rx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_rx_clk";
		};

		enet_tx_clk: enet_tx_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "enet_tx_clk";
		};

		gp_clkin: gp_clkin {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
			clock-output-names = "gp_clkin";
		};
	};

	soc {
		sct_pwm: pwm@40000000 {
			compatible = "nxp,lpc1850-sct-pwm";
			reg = <0x40000000 0x1000>;
			clocks =<&ccu1 CLK_CPU_SCT>;
			clock-names = "pwm";
			resets = <&rgu 37>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		dmac: dma-controller@40002000 {
			compatible = "arm,pl080", "arm,primecell";
			arm,primecell-periphid = <0x00041080>;
			reg = <0x40002000 0x1000>;
			interrupts = <2>;
			clocks = <&ccu1 CLK_CPU_DMA>;
			clock-names = "apb_pclk";
			resets = <&rgu 19>;
			#dma-cells = <2>;
			dma-channels = <8>;
			dma-requests = <16>;
			lli-bus-interface-ahb1;
			lli-bus-interface-ahb2;
			mem-bus-interface-ahb1;
			mem-bus-interface-ahb2;
			memcpy-burst-size = <256>;
			memcpy-bus-width = <32>;
		};

		spifi: flash-controller@40003000 {
			compatible = "nxp,lpc1773-spifi";
			reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
			reg-names = "spifi", "flash";
			interrupts = <30>;
			clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
			clock-names = "spifi", "reg";
			resets = <&rgu 53>;
			status = "disabled";
		};

		mmcsd: mmcsd@40004000 {
			compatible = "snps,dw-mshc";
			reg = <0x40004000 0x1000>;
			interrupts = <6>;
			num-slots = <1>;
			clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
			clock-names = "ciu", "biu";
			resets = <&rgu 20>;
			status = "disabled";
		};

		usb0: ehci@40006100 {
			compatible = "nxp,lpc1850-ehci", "generic-ehci";
			reg = <0x40006100 0x100>;
			interrupts = <8>;
			clocks = <&ccu1 CLK_CPU_USB0>;
			resets = <&rgu 17>;
			phys = <&usb0_otg_phy>;
			phy-names = "usb";
			has-transaction-translator;
			status = "disabled";
		};

		usb1: ehci@40007100 {
			compatible = "nxp,lpc1850-ehci", "generic-ehci";
			reg = <0x40007100 0x100>;
			interrupts = <9>;
			clocks = <&ccu1 CLK_CPU_USB1>;
			resets = <&rgu 18>;
			status = "disabled";
		};

		emc: memory-controller@40005000 {
			compatible = "arm,pl172", "arm,primecell";
			reg = <0x40005000 0x1000>;
			clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
			clock-names = "mpmcclk", "apb_pclk";
			resets = <&rgu 21>;
			#address-cells = <2>;
			#size-cells = <1>;
			ranges = <0 0 0x1c000000 0x1000000
				  1 0 0x1d000000 0x1000000
				  2 0 0x1e000000 0x1000000
				  3 0 0x1f000000 0x1000000>;
			status = "disabled";
		};

		lcdc: lcd-controller@40008000 {
			compatible = "arm,pl111", "arm,primecell";
			reg = <0x40008000 0x1000>;
			interrupts = <7>;
			interrupt-names = "combined";
			clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
			clock-names = "clcdclk", "apb_pclk";
			resets = <&rgu 16>;
			status = "disabled";
		};

		eeprom: eeprom@4000e000 {
			compatible = "nxp,lpc1857-eeprom";
			reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
			reg-names = "reg", "mem";
			clocks = <&ccu1 CLK_CPU_EEPROM>;
			clock-names = "eeprom";
			resets = <&rgu 27>;
			interrupts = <4>;
			status = "disabled";
		};

		mac: ethernet@40010000 {
			compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
			reg = <0x40010000 0x2000>;
			interrupts = <5>;
			interrupt-names	= "macirq";
			clocks = <&ccu1 CLK_CPU_ETHERNET>;
			clock-names = "stmmaceth";
			resets = <&rgu 22>;
			reset-names = "stmmaceth";
			rx-fifo-depth = <256>;
			tx-fifo-depth = <256>;
			snps,pbl = <4>; /* 32 (8x mode) */
			snps,force_thresh_dma_mode;
			status = "disabled";
		};

		creg: syscon@40043000 {
			compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
			reg = <0x40043000 0x1000>;
			clocks = <&ccu1 CLK_CPU_CREG>;
			resets = <&rgu 5>;

			creg_clk: clock-controller {
				compatible = "nxp,lpc1850-creg-clk";
				clocks = <&xtal32>;
				#clock-cells = <1>;
			};

			usb0_otg_phy: phy {
				compatible = "nxp,lpc1850-usb-otg-phy";
				clocks = <&ccu1 CLK_USB0>;
				#phy-cells = <0>;
			};

			dmamux: dma-mux {
				compatible = "nxp,lpc1850-dmamux";
				#dma-cells = <3>;
				dma-requests = <64>;
				dma-masters = <&dmac>;
			};
		};

		rtc: rtc@40046000 {
			compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
			reg = <0x40046000 0x1000>;
			interrupts = <47>;
			clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
			clock-names = "rtc", "reg";
		};

		cgu: clock-controller@40050000 {
			compatible = "nxp,lpc1850-cgu";
			reg = <0x40050000 0x1000>;
			#clock-cells = <1>;
			clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
		};

		ccu1: clock-controller@40051000 {
			compatible = "nxp,lpc1850-ccu";
			reg = <0x40051000 0x1000>;
			#clock-cells = <1>;
			clocks = <&cgu BASE_APB3_CLK>,   <&cgu BASE_APB1_CLK>,
				 <&cgu BASE_SPIFI_CLK>,  <&cgu BASE_CPU_CLK>,
				 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
				 <&cgu BASE_USB1_CLK>,   <&cgu BASE_SPI_CLK>;
			clock-names = "base_apb3_clk",   "base_apb1_clk",
				      "base_spifi_clk",  "base_cpu_clk",
				      "base_periph_clk", "base_usb0_clk",
				      "base_usb1_clk",   "base_spi_clk";
		};

		ccu2: clock-controller@40052000 {
			compatible = "nxp,lpc1850-ccu";
			reg = <0x40052000 0x1000>;
			#clock-cells = <1>;
			clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
				 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
				 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
				 <&cgu BASE_SSP0_CLK>,  <&cgu BASE_SDIO_CLK>;
			clock-names = "base_audio_clk", "base_uart3_clk",
				      "base_uart2_clk", "base_uart1_clk",
				      "base_uart0_clk", "base_ssp1_clk",
				      "base_ssp0_clk",  "base_sdio_clk";
		};

		rgu: reset-controller@40053000 {
			compatible = "nxp,lpc1850-rgu";
			reg = <0x40053000 0x1000>;
			clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
			clock-names = "delay", "reg";
			#reset-cells = <1>;
		};

		watchdog@40080000 {
			compatible = "nxp,lpc1850-wwdt";
			reg = <0x40080000 0x24>;
			interrupts = <49>;
			clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
			clock-names = "wdtclk", "reg";
		};

		uart0: serial@40081000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x40081000 0x1000>;
			reg-shift = <2>;
			interrupts = <24>;
			clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
			clock-names = "uartclk", "reg";
			resets = <&rgu 44>;
			dmas = <&dmamux  1 1 2
				&dmamux  2 1 2
				&dmamux 11 2 2
				&dmamux 12 2 2>;
			dma-names = "tx", "rx", "tx", "rx";
			status = "disabled";
		};

		uart1: serial@40082000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x40082000 0x1000>;
			reg-shift = <2>;
			interrupts = <25>;
			clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
			clock-names = "uartclk", "reg";
			resets = <&rgu 45>;
			dmas = <&dmamux 3 1 2
				&dmamux 4 1 2>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		ssp0: spi@40083000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x40083000 0x1000>;
			interrupts = <22>;
			clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&rgu 50>;
			dmas = <&dmamux  9 0 2
				&dmamux 10 0 2>;
			dma-names = "rx", "tx";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		timer0: timer@40084000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x40084000 0x1000>;
			interrupts = <12>;
			clocks = <&ccu1 CLK_CPU_TIMER0>;
			clock-names = "timerclk";
			resets = <&rgu 32>;
		};

		timer1: timer@40085000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x40085000 0x1000>;
			interrupts = <13>;
			clocks = <&ccu1 CLK_CPU_TIMER1>;
			clock-names = "timerclk";
			resets = <&rgu 33>;
		};

		pinctrl: pinctrl@40086000 {
			compatible = "nxp,lpc1850-scu";
			reg = <0x40086000 0x1000>;
			clocks = <&ccu1 CLK_CPU_SCU>;
		};

		i2c0: i2c@400a1000 {
			compatible = "nxp,lpc1788-i2c";
			reg = <0x400a1000 0x1000>;
			interrupts = <18>;
			clocks = <&ccu1 CLK_APB1_I2C0>;
			resets = <&rgu 48>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can1: can@400a4000 {
			compatible = "bosch,c_can";
			reg = <0x400a4000 0x1000>;
			interrupts = <43>;
			clocks = <&ccu1 CLK_APB1_CAN1>;
			resets = <&rgu 54>;
			status = "disabled";
		};

		uart2: serial@400c1000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x400c1000 0x1000>;
			reg-shift = <2>;
			interrupts = <26>;
			clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
			clock-names = "uartclk", "reg";
			resets = <&rgu 46>;
			dmas = <&dmamux 5 1 2
				&dmamux 6 1 2>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart3: serial@400c2000 {
			compatible = "nxp,lpc1850-uart", "ns16550a";
			reg = <0x400c2000 0x1000>;
			reg-shift = <2>;
			interrupts = <27>;
			clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
			clock-names = "uartclk", "reg";
			resets = <&rgu 47>;
			dmas = <&dmamux  7 1 2
				&dmamux  8 1 2
				&dmamux 13 3 2
				&dmamux 14 3 2>;
			dma-names = "tx", "rx", "rx", "tx";
			status = "disabled";
		};

		timer2: timer@400c3000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x400c3000 0x1000>;
			interrupts = <14>;
			clocks = <&ccu1 CLK_CPU_TIMER2>;
			clock-names = "timerclk";
			resets = <&rgu 34>;
		};

		timer3: timer@400c4000 {
			compatible = "nxp,lpc3220-timer";
			reg = <0x400c4000 0x1000>;
			interrupts = <15>;
			clocks = <&ccu1 CLK_CPU_TIMER3>;
			clock-names = "timerclk";
			resets = <&rgu 35>;
		};

		ssp1: spi@400c5000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x400c5000 0x1000>;
			interrupts = <23>;
			clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
			clock-names = "sspclk", "apb_pclk";
			resets = <&rgu 51>;
			dmas = <&dmamux 11 2 2
				&dmamux 12 2 2
				&dmamux  3 3 2
				&dmamux  4 3 2
				&dmamux  5 2 2
				&dmamux  6 2 2
				&dmamux 13 2 2
				&dmamux 14 2 2>;
			dma-names = "rx", "tx", "tx", "rx",
				    "tx", "rx", "rx", "tx";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@400e0000 {
			compatible = "nxp,lpc1788-i2c";
			reg = <0x400e0000 0x1000>;
			interrupts = <19>;
			clocks = <&ccu1 CLK_APB3_I2C1>;
			resets = <&rgu 49>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dac: dac@400e1000 {
			compatible = "nxp,lpc1850-dac";
			reg = <0x400e1000 0x1000>;
			interrupts = <0>;
			clocks = <&ccu1 CLK_APB3_DAC>;
			resets = <&rgu 42>;
			status = "disabled";
		};

		can0: can@400e2000 {
			compatible = "bosch,c_can";
			reg = <0x400e2000 0x1000>;
			interrupts = <51>;
			clocks = <&ccu1 CLK_APB3_CAN0>;
			resets = <&rgu 55>;
			status = "disabled";
		};

		adc0: adc@400e3000 {
			compatible = "nxp,lpc1850-adc";
			reg = <0x400e3000 0x1000>;
			interrupts = <17>;
			clocks = <&ccu1 CLK_APB3_ADC0>;
			resets = <&rgu 40>;
			status = "disabled";
		};

		adc1: adc@400e4000 {
			compatible = "nxp,lpc1850-adc";
			reg = <0x400e4000 0x1000>;
			interrupts = <21>;
			clocks = <&ccu1 CLK_APB3_ADC1>;
			resets = <&rgu 41>;
			status = "disabled";
		};

		gpio: gpio@400f4000 {
			compatible = "nxp,lpc1850-gpio";
			reg = <0x400f4000 0x4000>;
			clocks = <&ccu1 CLK_CPU_GPIO>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges =	<&pinctrl LPC_GPIO(0,0)  LPC_PIN(0,0)  2>,
					<&pinctrl LPC_GPIO(0,4)  LPC_PIN(1,0)  1>,
					<&pinctrl LPC_GPIO(0,8)  LPC_PIN(1,1)  4>,
					<&pinctrl LPC_GPIO(1,8)  LPC_PIN(1,5)  2>,
					<&pinctrl LPC_GPIO(1,0)  LPC_PIN(1,7)  8>,
					<&pinctrl LPC_GPIO(0,2)  LPC_PIN(1,15) 2>,
					<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
					<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
					<&pinctrl LPC_GPIO(5,0)  LPC_PIN(2,0)  7>,
					<&pinctrl LPC_GPIO(0,7)  LPC_PIN(2,7)  1>,
					<&pinctrl LPC_GPIO(5,7)  LPC_PIN(2,8)  1>,
					<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9)  1>,
					<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
					<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
					<&pinctrl LPC_GPIO(5,8)  LPC_PIN(3,1)  2>,
					<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4)  2>,
					<&pinctrl LPC_GPIO(0,6)  LPC_PIN(3,6)  1>,
					<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7)  2>,
					<&pinctrl LPC_GPIO(2,0)  LPC_PIN(4,0)  7>,
					<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8)  3>,
					<&pinctrl LPC_GPIO(2,9)  LPC_PIN(5,0)  7>,
					<&pinctrl LPC_GPIO(2,7)  LPC_PIN(5,7)  1>,
					<&pinctrl LPC_GPIO(3,0)  LPC_PIN(6,1)  5>,
					<&pinctrl LPC_GPIO(0,5)  LPC_PIN(6,6)  1>,
					<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7)  2>,
					<&pinctrl LPC_GPIO(3,5)  LPC_PIN(6,9)  3>,
					<&pinctrl LPC_GPIO(2,8)  LPC_PIN(6,12) 1>,
					<&pinctrl LPC_GPIO(3,8)  LPC_PIN(7,0)  8>,
					<&pinctrl LPC_GPIO(4,0)  LPC_PIN(8,0)  8>,
					<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0)  4>,
					<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4)  2>,
					<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6)  1>,
					<&pinctrl LPC_GPIO(4,8)  LPC_PIN(a,1)  3>,
					<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4)  1>,
					<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0)  7>,
					<&pinctrl LPC_GPIO(6,0)  LPC_PIN(c,1) 14>,
					<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
					<&pinctrl LPC_GPIO(7,0)  LPC_PIN(e,0) 16>,
					<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1)  3>,
					<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5)  7>;
		};
	};
};
Commit	Line	Data
804a5dd6 JE	1	/*
	2	* Common base for NXP LPC18xx and LPC43xx devices.
	3	*
	4	* Copyright 2015 Joachim Eastwood <[email protected]>
	5	*
	6	* This code is released using a dual license strategy: BSD/GPL
	7	* You can choose the licence that better fits your requirements.
	8	*
	9	* Released under the terms of 3-clause BSD License
	10	* Released under the terms of GNU General Public License Version 2.0
	11	*
	12	*/
	13
	14	#include "armv7-m.dtsi"
	15
ba2db535 JE	16	#include "dt-bindings/clock/lpc18xx-cgu.h"
	17	#include "dt-bindings/clock/lpc18xx-ccu.h"
	18
7836dce4 JE	19	#define LPC_PIN(port, pin) (0x##port * 32 + pin)
	20	#define LPC_GPIO(port, pin) (port * 32 + pin)
	21
804a5dd6	22	/ {
0555a6be JE	23	#address-cells = <1>;
	24	#size-cells = <1>;
	25
804a5dd6 JE	26	cpus {
	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29
	30	cpu@0 {
	31	compatible = "arm,cortex-m3";
	32	device_type = "cpu";
	33	reg = <0x0>;
ba2db535	34	clocks = <&ccu1 CLK_CPU_CORE>;
804a5dd6 JE	35	};
	36	};
	37
	38	clocks {
	39	xtal: xtal {
	40	compatible = "fixed-clock";
	41	#clock-cells = <0>;
	42	clock-frequency = <12000000>;
	43	};
	44
ba2db535 JE	45	xtal32: xtal32 {
	46	compatible = "fixed-clock";
	47	#clock-cells = <0>;
	48	clock-frequency = <32768>;
	49	};
	50
	51	enet_rx_clk: enet_rx_clk {
	52	compatible = "fixed-clock";
	53	#clock-cells = <0>;
	54	clock-frequency = <0>;
	55	clock-output-names = "enet_rx_clk";
	56	};
	57
	58	enet_tx_clk: enet_tx_clk {
	59	compatible = "fixed-clock";
	60	#clock-cells = <0>;
	61	clock-frequency = <0>;
	62	clock-output-names = "enet_tx_clk";
	63	};
	64
	65	gp_clkin: gp_clkin {
	66	compatible = "fixed-clock";
804a5dd6	67	#clock-cells = <0>;
ba2db535 JE	68	clock-frequency = <0>;
ba2db535 JE	69	clock-output-names = "gp_clkin";
804a5dd6 JE	70	};
	71	};
	72
	73	soc {
b8da65d1 AA	74	sct_pwm: pwm@40000000 {
	75	compatible = "nxp,lpc1850-sct-pwm";
	76	reg = <0x40000000 0x1000>;
	77	clocks =<&ccu1 CLK_CPU_SCT>;
	78	clock-names = "pwm";
	79	resets = <&rgu 37>;
	80	#pwm-cells = <3>;
	81	status = "disabled";
	82	};
	83
5924007c JE	84	dmac: dma-controller@40002000 {
	85	compatible = "arm,pl080", "arm,primecell";
	86	arm,primecell-periphid = <0x00041080>;
	87	reg = <0x40002000 0x1000>;
	88	interrupts = <2>;
	89	clocks = <&ccu1 CLK_CPU_DMA>;
	90	clock-names = "apb_pclk";
	91	resets = <&rgu 19>;
	92	#dma-cells = <2>;
	93	dma-channels = <8>;
	94	dma-requests = <16>;
	95	lli-bus-interface-ahb1;
	96	lli-bus-interface-ahb2;
	97	mem-bus-interface-ahb1;
	98	mem-bus-interface-ahb2;
	99	memcpy-burst-size = <256>;
	100	memcpy-bus-width = <32>;
	101	};
	102
4f85dd16 JE	103	spifi: flash-controller@40003000 {
	104	compatible = "nxp,lpc1773-spifi";
	105	reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
	106	reg-names = "spifi", "flash";
	107	interrupts = <30>;
	108	clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
	109	clock-names = "spifi", "reg";
	110	resets = <&rgu 53>;
	111	status = "disabled";
	112	};
	113
cd07154f JE	114	mmcsd: mmcsd@40004000 {
	115	compatible = "snps,dw-mshc";
	116	reg = <0x40004000 0x1000>;
	117	interrupts = <6>;
	118	num-slots = <1>;
	119	clocks = <&ccu2 CLK_SDIO>, <&ccu1 CLK_CPU_SDIO>;
	120	clock-names = "ciu", "biu";
2300830f	121	resets = <&rgu 20>;
cd07154f JE	122	status = "disabled";
	123	};
	124
b06cdb79 JE	125	usb0: ehci@40006100 {
	126	compatible = "nxp,lpc1850-ehci", "generic-ehci";
	127	reg = <0x40006100 0x100>;
	128	interrupts = <8>;
	129	clocks = <&ccu1 CLK_CPU_USB0>;
2300830f	130	resets = <&rgu 17>;
6d6d6b55 JE	131	phys = <&usb0_otg_phy>;
6d6d6b55 JE	132	phy-names = "usb";
b06cdb79 JE	133	has-transaction-translator;
	134	status = "disabled";
	135	};
	136
	137	usb1: ehci@40007100 {
	138	compatible = "nxp,lpc1850-ehci", "generic-ehci";
	139	reg = <0x40007100 0x100>;
	140	interrupts = <9>;
	141	clocks = <&ccu1 CLK_CPU_USB1>;
2300830f	142	resets = <&rgu 18>;
b06cdb79 JE	143	status = "disabled";
	144	};
	145
50016385 JE	146	emc: memory-controller@40005000 {
	147	compatible = "arm,pl172", "arm,primecell";
	148	reg = <0x40005000 0x1000>;
	149	clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
	150	clock-names = "mpmcclk", "apb_pclk";
2300830f	151	resets = <&rgu 21>;
50016385 JE	152	#address-cells = <2>;
	153	#size-cells = <1>;
	154	ranges = <0 0 0x1c000000 0x1000000
	155	1 0 0x1d000000 0x1000000
	156	2 0 0x1e000000 0x1000000
	157	3 0 0x1f000000 0x1000000>;
	158	status = "disabled";
	159	};
	160
9cf6267d JE	161	lcdc: lcd-controller@40008000 {
	162	compatible = "arm,pl111", "arm,primecell";
	163	reg = <0x40008000 0x1000>;
	164	interrupts = <7>;
	165	interrupt-names = "combined";
	166	clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
	167	clock-names = "clcdclk", "apb_pclk";
2300830f	168	resets = <&rgu 16>;
9cf6267d JE	169	status = "disabled";
	170	};
	171
5c36aa6f AA	172	eeprom: eeprom@4000e000 {
	173	compatible = "nxp,lpc1857-eeprom";
	174	reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
	175	reg-names = "reg", "mem";
	176	clocks = <&ccu1 CLK_CPU_EEPROM>;
	177	clock-names = "eeprom";
	178	resets = <&rgu 27>;
	179	interrupts = <4>;
	180	status = "disabled";
	181	};
	182
fe968589 JE	183	mac: ethernet@40010000 {
	184	compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
	185	reg = <0x40010000 0x2000>;
	186	interrupts = <5>;
	187	interrupt-names = "macirq";
	188	clocks = <&ccu1 CLK_CPU_ETHERNET>;
	189	clock-names = "stmmaceth";
2300830f JE	190	resets = <&rgu 22>;
2300830f JE	191	reset-names = "stmmaceth";
3ed6d3cb JE	192	rx-fifo-depth = <256>;
	193	tx-fifo-depth = <256>;
	194	snps,pbl = <4>; /* 32 (8x mode) */
	195	snps,force_thresh_dma_mode;
fe968589 JE	196	status = "disabled";
	197	};
	198
16df2b86 JE	199	creg: syscon@40043000 {
	200	compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
	201	reg = <0x40043000 0x1000>;
	202	clocks = <&ccu1 CLK_CPU_CREG>;
2300830f	203	resets = <&rgu 5>;
6d6d6b55	204
52d7c426 JE	205	creg_clk: clock-controller {
	206	compatible = "nxp,lpc1850-creg-clk";
	207	clocks = <&xtal32>;
	208	#clock-cells = <1>;
	209	};
	210
472a5a3d	211	usb0_otg_phy: phy {
6d6d6b55 JE	212	compatible = "nxp,lpc1850-usb-otg-phy";
	213	clocks = <&ccu1 CLK_USB0>;
	214	#phy-cells = <0>;
	215	};
5913f559	216
472a5a3d	217	dmamux: dma-mux {
5913f559 JE	218	compatible = "nxp,lpc1850-dmamux";
	219	#dma-cells = <3>;
	220	dma-requests = <64>;
	221	dma-masters = <&dmac>;
	222	};
16df2b86 JE	223	};
16df2b86 JE	224
246fee6c JE	225	rtc: rtc@40046000 {
	226	compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
	227	reg = <0x40046000 0x1000>;
	228	interrupts = <47>;
	229	clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
	230	clock-names = "rtc", "reg";
	231	};
	232
ba2db535 JE	233	cgu: clock-controller@40050000 {
	234	compatible = "nxp,lpc1850-cgu";
	235	reg = <0x40050000 0x1000>;
	236	#clock-cells = <1>;
52d7c426	237	clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
ba2db535 JE	238	};
	239
	240	ccu1: clock-controller@40051000 {
	241	compatible = "nxp,lpc1850-ccu";
	242	reg = <0x40051000 0x1000>;
	243	#clock-cells = <1>;
	244	clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
	245	<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
	246	<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
	247	<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
	248	clock-names = "base_apb3_clk", "base_apb1_clk",
	249	"base_spifi_clk", "base_cpu_clk",
	250	"base_periph_clk", "base_usb0_clk",
	251	"base_usb1_clk", "base_spi_clk";
	252	};
	253
	254	ccu2: clock-controller@40052000 {
	255	compatible = "nxp,lpc1850-ccu";
	256	reg = <0x40052000 0x1000>;
	257	#clock-cells = <1>;
	258	clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
	259	<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
	260	<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
	261	<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
	262	clock-names = "base_audio_clk", "base_uart3_clk",
	263	"base_uart2_clk", "base_uart1_clk",
	264	"base_uart0_clk", "base_ssp1_clk",
	265	"base_ssp0_clk", "base_sdio_clk";
	266	};
	267
0745c702 JE	268	rgu: reset-controller@40053000 {
	269	compatible = "nxp,lpc1850-rgu";
	270	reg = <0x40053000 0x1000>;
	271	clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
	272	clock-names = "delay", "reg";
	273	#reset-cells = <1>;
	274	};
	275
9c8a5cdc AA	276	watchdog@40080000 {
	277	compatible = "nxp,lpc1850-wwdt";
	278	reg = <0x40080000 0x24>;
	279	interrupts = <49>;
	280	clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
	281	clock-names = "wdtclk", "reg";
	282	};
	283
804a5dd6	284	uart0: serial@40081000 {
f2b1c507	285	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	286	reg = <0x40081000 0x1000>;
	287	reg-shift = <2>;
	288	interrupts = <24>;
ba2db535	289	clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
f2b1c507	290	clock-names = "uartclk", "reg";
2300830f	291	resets = <&rgu 44>;
4e9c5aa8 JE	292	dmas = <&dmamux 1 1 2
	293	&dmamux 2 1 2
	294	&dmamux 11 2 2
	295	&dmamux 12 2 2>;
	296	dma-names = "tx", "rx", "tx", "rx";
804a5dd6 JE	297	status = "disabled";
	298	};
	299
	300	uart1: serial@40082000 {
f2b1c507	301	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	302	reg = <0x40082000 0x1000>;
	303	reg-shift = <2>;
	304	interrupts = <25>;
ba2db535	305	clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
f2b1c507	306	clock-names = "uartclk", "reg";
2300830f	307	resets = <&rgu 45>;
4e9c5aa8 JE	308	dmas = <&dmamux 3 1 2
	309	&dmamux 4 1 2>;
	310	dma-names = "tx", "rx";
804a5dd6 JE	311	status = "disabled";
	312	};
	313
5d2ea79c JE	314	ssp0: spi@40083000 {
	315	compatible = "arm,pl022", "arm,primecell";
	316	reg = <0x40083000 0x1000>;
	317	interrupts = <22>;
	318	clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
	319	clock-names = "sspclk", "apb_pclk";
2300830f	320	resets = <&rgu 50>;
c5288091 JE	321	dmas = <&dmamux 9 0 2
	322	&dmamux 10 0 2>;
	323	dma-names = "rx", "tx";
5d2ea79c JE	324	#address-cells = <1>;
	325	#size-cells = <0>;
	326	status = "disabled";
	327	};
	328
804a5dd6 JE	329	timer0: timer@40084000 {
	330	compatible = "nxp,lpc3220-timer";
	331	reg = <0x40084000 0x1000>;
	332	interrupts = <12>;
ba2db535	333	clocks = <&ccu1 CLK_CPU_TIMER0>;
804a5dd6	334	clock-names = "timerclk";
2300830f	335	resets = <&rgu 32>;
804a5dd6 JE	336	};
	337
	338	timer1: timer@40085000 {
	339	compatible = "nxp,lpc3220-timer";
	340	reg = <0x40085000 0x1000>;
	341	interrupts = <13>;
ba2db535	342	clocks = <&ccu1 CLK_CPU_TIMER1>;
804a5dd6	343	clock-names = "timerclk";
2300830f	344	resets = <&rgu 33>;
804a5dd6 JE	345	};
804a5dd6 JE	346
d881f5e2 JE	347	pinctrl: pinctrl@40086000 {
	348	compatible = "nxp,lpc1850-scu";
	349	reg = <0x40086000 0x1000>;
	350	clocks = <&ccu1 CLK_CPU_SCU>;
	351	};
	352
06713a94 JE	353	i2c0: i2c@400a1000 {
	354	compatible = "nxp,lpc1788-i2c";
	355	reg = <0x400a1000 0x1000>;
	356	interrupts = <18>;
	357	clocks = <&ccu1 CLK_APB1_I2C0>;
	358	resets = <&rgu 48>;
	359	#address-cells = <1>;
	360	#size-cells = <0>;
	361	status = "disabled";
	362	};
	363
7e6c8376 JE	364	can1: can@400a4000 {
	365	compatible = "bosch,c_can";
	366	reg = <0x400a4000 0x1000>;
	367	interrupts = <43>;
	368	clocks = <&ccu1 CLK_APB1_CAN1>;
2300830f	369	resets = <&rgu 54>;
7e6c8376 JE	370	status = "disabled";
	371	};
	372
804a5dd6	373	uart2: serial@400c1000 {
f2b1c507	374	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	375	reg = <0x400c1000 0x1000>;
	376	reg-shift = <2>;
	377	interrupts = <26>;
ba2db535	378	clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
f2b1c507	379	clock-names = "uartclk", "reg";
2300830f	380	resets = <&rgu 46>;
4e9c5aa8 JE	381	dmas = <&dmamux 5 1 2
	382	&dmamux 6 1 2>;
	383	dma-names = "tx", "rx";
804a5dd6 JE	384	status = "disabled";
	385	};
	386
	387	uart3: serial@400c2000 {
f2b1c507	388	compatible = "nxp,lpc1850-uart", "ns16550a";
804a5dd6 JE	389	reg = <0x400c2000 0x1000>;
	390	reg-shift = <2>;
	391	interrupts = <27>;
ba2db535	392	clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
f2b1c507	393	clock-names = "uartclk", "reg";
2300830f	394	resets = <&rgu 47>;
4e9c5aa8 JE	395	dmas = <&dmamux 7 1 2
	396	&dmamux 8 1 2
	397	&dmamux 13 3 2
	398	&dmamux 14 3 2>;
	399	dma-names = "tx", "rx", "rx", "tx";
804a5dd6 JE	400	status = "disabled";
	401	};
	402
	403	timer2: timer@400c3000 {
	404	compatible = "nxp,lpc3220-timer";
	405	reg = <0x400c3000 0x1000>;
	406	interrupts = <14>;
ba2db535	407	clocks = <&ccu1 CLK_CPU_TIMER2>;
804a5dd6	408	clock-names = "timerclk";
2300830f	409	resets = <&rgu 34>;
804a5dd6 JE	410	};
	411
	412	timer3: timer@400c4000 {
	413	compatible = "nxp,lpc3220-timer";
	414	reg = <0x400c4000 0x1000>;
	415	interrupts = <15>;
ba2db535	416	clocks = <&ccu1 CLK_CPU_TIMER3>;
804a5dd6	417	clock-names = "timerclk";
2300830f	418	resets = <&rgu 35>;
804a5dd6	419	};
7836dce4	420
5d2ea79c JE	421	ssp1: spi@400c5000 {
	422	compatible = "arm,pl022", "arm,primecell";
	423	reg = <0x400c5000 0x1000>;
	424	interrupts = <23>;
	425	clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
	426	clock-names = "sspclk", "apb_pclk";
2300830f	427	resets = <&rgu 51>;
c5288091 JE	428	dmas = <&dmamux 11 2 2
	429	&dmamux 12 2 2
	430	&dmamux 3 3 2
	431	&dmamux 4 3 2
	432	&dmamux 5 2 2
	433	&dmamux 6 2 2
	434	&dmamux 13 2 2
	435	&dmamux 14 2 2>;
	436	dma-names = "rx", "tx", "tx", "rx",
	437	"tx", "rx", "rx", "tx";
5d2ea79c JE	438	#address-cells = <1>;
	439	#size-cells = <0>;
	440	status = "disabled";
	441	};
	442
06713a94 JE	443	i2c1: i2c@400e0000 {
	444	compatible = "nxp,lpc1788-i2c";
	445	reg = <0x400e0000 0x1000>;
	446	interrupts = <19>;
	447	clocks = <&ccu1 CLK_APB3_I2C1>;
	448	resets = <&rgu 49>;
	449	#address-cells = <1>;
	450	#size-cells = <0>;
	451	status = "disabled";
	452	};
	453
8c938004 JE	454	dac: dac@400e1000 {
	455	compatible = "nxp,lpc1850-dac";
	456	reg = <0x400e1000 0x1000>;
	457	interrupts = <0>;
	458	clocks = <&ccu1 CLK_APB3_DAC>;
	459	resets = <&rgu 42>;
	460	status = "disabled";
	461	};
	462
7e6c8376 JE	463	can0: can@400e2000 {
	464	compatible = "bosch,c_can";
	465	reg = <0x400e2000 0x1000>;
	466	interrupts = <51>;
	467	clocks = <&ccu1 CLK_APB3_CAN0>;
2300830f	468	resets = <&rgu 55>;
7e6c8376 JE	469	status = "disabled";
	470	};
	471
e162f9c2 JE	472	adc0: adc@400e3000 {
	473	compatible = "nxp,lpc1850-adc";
	474	reg = <0x400e3000 0x1000>;
	475	interrupts = <17>;
	476	clocks = <&ccu1 CLK_APB3_ADC0>;
	477	resets = <&rgu 40>;
	478	status = "disabled";
	479	};
	480
	481	adc1: adc@400e4000 {
	482	compatible = "nxp,lpc1850-adc";
	483	reg = <0x400e4000 0x1000>;
	484	interrupts = <21>;
	485	clocks = <&ccu1 CLK_APB3_ADC1>;
	486	resets = <&rgu 41>;
	487	status = "disabled";
	488	};
	489
7836dce4 JE	490	gpio: gpio@400f4000 {
	491	compatible = "nxp,lpc1850-gpio";
	492	reg = <0x400f4000 0x4000>;
	493	clocks = <&ccu1 CLK_CPU_GPIO>;
	494	gpio-controller;
	495	#gpio-cells = <2>;
	496	gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
	497	<&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
	498	<&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
	499	<&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
	500	<&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
	501	<&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
	502	<&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
	503	<&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
	504	<&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
	505	<&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
	506	<&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
	507	<&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
	508	<&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
	509	<&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
	510	<&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
	511	<&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
	512	<&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
	513	<&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
	514	<&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
	515	<&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
	516	<&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
	517	<&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
	518	<&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
	519	<&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
	520	<&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
	521	<&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
	522	<&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
	523	<&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
	524	<&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
	525	<&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
	526	<&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
	527	<&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
	528	<&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
	529	<&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
	530	<&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
	531	<&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
	532	<&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
	533	<&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
	534	<&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
	535	<&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
	536	};
804a5dd6 JE	537	};
804a5dd6 JE	538	};