[linux.git] / drivers / ata / pata_cmd64x.c

/*
 * pata_cmd64x.c 	- CMD64x PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <[email protected]>
 *			  (C) 2009-2010 Bartlomiej Zolnierkiewicz
 *			  (C) 2012 MontaVista Software, LLC <[email protected]>
 *
 * Based upon
 * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  ([email protected])
 * Copyright (C) 1998		David S. Miller ([email protected])
 *
 * Copyright (C) 1999-2002	Andre Hedrick <[email protected]>
 *
 * TODO
 *	Testing work
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_cmd64x"
#define DRV_VERSION "0.2.18"

/*
 * CMD64x specific registers definition.
 */

enum {
	CFR 		= 0x50,
		CFR_INTR_CH0  = 0x04,
	CNTRL		= 0x51,
		CNTRL_CH0     = 0x04,
		CNTRL_CH1     = 0x08,
	CMDTIM 		= 0x52,
	ARTTIM0 	= 0x53,
	DRWTIM0 	= 0x54,
	ARTTIM1 	= 0x55,
	DRWTIM1 	= 0x56,
	ARTTIM23 	= 0x57,
		ARTTIM23_DIS_RA2  = 0x04,
		ARTTIM23_DIS_RA3  = 0x08,
		ARTTIM23_INTR_CH1 = 0x10,
	DRWTIM2 	= 0x58,
	BRST 		= 0x59,
	DRWTIM3 	= 0x5b,
	BMIDECR0	= 0x70,
	MRDMODE		= 0x71,
		MRDMODE_INTR_CH0 = 0x04,
		MRDMODE_INTR_CH1 = 0x08,
	BMIDESR0	= 0x72,
	UDIDETCR0	= 0x73,
	DTPR0		= 0x74,
	BMIDECR1	= 0x78,
	BMIDECSR	= 0x79,
	UDIDETCR1	= 0x7B,
	DTPR1		= 0x7C
};

static int cmd648_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 r;

	/* Check cable detect bits */
	pci_read_config_byte(pdev, BMIDECSR, &r);
	if (r & (1 << ap->port_no))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	cmd64x_set_timing	-	set PIO and MWDMA timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: mode
 *
 *	Called to do the PIO and MWDMA mode setup.
 */

static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_timing t;
	const unsigned long T = 1000000 / 33;
	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };

	u8 reg;

	/* Port layout is not logical so use a table */
	const u8 arttim_port[2][2] = {
		{ ARTTIM0, ARTTIM1 },
		{ ARTTIM23, ARTTIM23 }
	};
	const u8 drwtim_port[2][2] = {
		{ DRWTIM0, DRWTIM1 },
		{ DRWTIM2, DRWTIM3 }
	};

	int arttim = arttim_port[ap->port_no][adev->devno];
	int drwtim = drwtim_port[ap->port_no][adev->devno];

	/* ata_timing_compute is smart and will produce timings for MWDMA
	   that don't violate the drives PIO capabilities. */
	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
		return;
	}
	if (ap->port_no) {
		/* Slave has shared address setup */
		struct ata_device *pair = ata_dev_pair(adev);

		if (pair) {
			struct ata_timing tp;
			ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
			ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
		}
	}

	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
		t.active, t.recover, t.setup);
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)
		t.active = 16;

	/* Now convert the clocks into values we can actually stuff into
	   the chip */

	if (t.recover == 16)
		t.recover = 0;
	else if (t.recover > 1)
		t.recover--;
	else
		t.recover = 15;

	if (t.setup > 4)
		t.setup = 0xC0;
	else
		t.setup = setup_data[t.setup];

	t.active &= 0x0F;	/* 0 = 16 */

	/* Load setup timing */
	pci_read_config_byte(pdev, arttim, &reg);
	reg &= 0x3F;
	reg |= t.setup;
	pci_write_config_byte(pdev, arttim, reg);

	/* Load active/recovery */
	pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}

/**
 *	cmd64x_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Used when configuring the devices ot set the PIO timings. All the
 *	actual work is done by the PIO/MWDMA setting helper
 */

static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	cmd64x_set_timing(ap, adev, adev->pio_mode);
}

/**
 *	cmd64x_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup.
 */

static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 udma_data[] = {
		0x30, 0x20, 0x10, 0x20, 0x10, 0x00
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 regU, regD;

	int pciU = UDIDETCR0 + 8 * ap->port_no;
	int pciD = BMIDESR0 + 8 * ap->port_no;
	int shift = 2 * adev->devno;

	pci_read_config_byte(pdev, pciD, &regD);
	pci_read_config_byte(pdev, pciU, &regU);

	/* DMA bits off */
	regD &= ~(0x20 << adev->devno);
	/* DMA control bits */
	regU &= ~(0x30 << shift);
	/* DMA timing bits */
	regU &= ~(0x05 << adev->devno);

	if (adev->dma_mode >= XFER_UDMA_0) {
		/* Merge the timing value */
		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
		/* Merge the control bits */
		regU |= 1 << adev->devno; /* UDMA on */
		if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
			regU |= 4 << adev->devno;
	} else {
		regU &= ~ (1 << adev->devno);	/* UDMA off */
		cmd64x_set_timing(ap, adev, adev->dma_mode);
	}

	regD |= 0x20 << adev->devno;

	pci_write_config_byte(pdev, pciU, regU);
	pci_write_config_byte(pdev, pciD, regD);
}

/**
 *	cmd64x_sff_irq_check	-	check IDE interrupt
 *	@ap: ATA interface
 *
 *	Check IDE interrupt in CFR/ARTTIM23 registers.
 */

static bool cmd64x_sff_irq_check(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
	int irq_reg  = ap->port_no ? ARTTIM23 : CFR;
	u8 irq_stat;

	/* NOTE: reading the register should clear the interrupt */
	pci_read_config_byte(pdev, irq_reg, &irq_stat);

	return irq_stat & irq_mask;
}

/**
 *	cmd64x_sff_irq_clear	-	clear IDE interrupt
 *	@ap: ATA interface
 *
 *	Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers.
 */

static void cmd64x_sff_irq_clear(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int irq_reg = ap->port_no ? ARTTIM23 : CFR;
	u8 irq_stat;

	ata_bmdma_irq_clear(ap);

	/* Reading the register should be enough to clear the interrupt */
	pci_read_config_byte(pdev, irq_reg, &irq_stat);
}

/**
 *	cmd648_sff_irq_check	-	check IDE interrupt
 *	@ap: ATA interface
 *
 *	Check IDE interrupt in MRDMODE register.
 */

static bool cmd648_sff_irq_check(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long base = pci_resource_start(pdev, 4);
	int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
	u8 mrdmode = inb(base + 1);

	return mrdmode & irq_mask;
}

/**
 *	cmd648_sff_irq_clear	-	clear IDE interrupt
 *	@ap: ATA interface
 *
 *	Clear IDE interrupt in MRDMODE and DMA status registers.
 */

static void cmd648_sff_irq_clear(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned long base = pci_resource_start(pdev, 4);
	int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
	u8 mrdmode;

	ata_bmdma_irq_clear(ap);

	/* Clear this port's interrupt bit (leaving the other port alone) */
	mrdmode  = inb(base + 1);
	mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1);
	outb(mrdmode | irq_mask, base + 1);
}

/**
 *	cmd646r1_bmdma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	Stub for now while investigating the r1 quirk in the old driver.
 */

static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
{
	ata_bmdma_stop(qc);
}

static struct scsi_host_template cmd64x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations cmd64x_base_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
};

static struct ata_port_operations cmd64x_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.sff_irq_check	= cmd64x_sff_irq_check,
	.sff_irq_clear	= cmd64x_sff_irq_clear,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd646r1_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.sff_irq_check	= cmd64x_sff_irq_check,
	.sff_irq_clear	= cmd64x_sff_irq_clear,
	.bmdma_stop	= cmd646r1_bmdma_stop,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd646r3_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.sff_irq_check	= cmd648_sff_irq_check,
	.sff_irq_clear	= cmd648_sff_irq_clear,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd648_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.sff_irq_check	= cmd648_sff_irq_check,
	.sff_irq_clear	= cmd648_sff_irq_clear,
	.cable_detect	= cmd648_cable_detect,
};

static void cmd64x_fixup(struct pci_dev *pdev)
{
	u8 mrdmode;

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);

	/* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
}

static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info cmd_info[7] = {
		{	/* CMD 643 - no UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with broken UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646U with broken UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd646r3_port_ops
		},
		{	/* CMD 646U2 with working UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &cmd646r3_port_ops
		},
		{	/* CMD 646 rev 1  */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd646r1_port_ops
		},
		{	/* CMD 648 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &cmd648_port_ops
		},
		{	/* CMD 649 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &cmd648_port_ops
		}
	};
	const struct ata_port_info *ppi[] = {
		&cmd_info[id->driver_data],
		&cmd_info[id->driver_data],
		NULL
	};
	u8 reg;
	int rc;
	struct pci_dev *bridge = pdev->bus->self;
	/* mobility split bridges don't report enabled ports correctly */
	int port_ok = !(bridge && bridge->vendor ==
			PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
	/* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
	int cntrl_ch0_ok = (id->driver_data != 0);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (id->driver_data == 0)	/* 643 */
		ata_pci_bmdma_clear_simplex(pdev);

	if (pdev->device == PCI_DEVICE_ID_CMD_646)
		switch (pdev->revision) {
		/* UDMA works since rev 5 */
		default:
			ppi[0] = &cmd_info[3];
			ppi[1] = &cmd_info[3];
			break;
		/* Interrupts in MRDMODE since rev 3 */
		case 3:
		case 4:
			ppi[0] = &cmd_info[2];
			ppi[1] = &cmd_info[2];
			break;
		/* Rev 1 with other problems? */
		case 1:
			ppi[0] = &cmd_info[4];
			ppi[1] = &cmd_info[4];
			/* FALL THRU */
		/* Early revs have no CNTRL_CH0 */
		case 2:
		case 0:
			cntrl_ch0_ok = 0;
			break;
		}

	cmd64x_fixup(pdev);

	/* check for enabled ports */
	pci_read_config_byte(pdev, CNTRL, &reg);
	if (!port_ok)
		dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
	if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
		dev_notice(&pdev->dev, "Primary port is disabled\n");
		ppi[0] = &ata_dummy_port_info;

	}
	if (port_ok && !(reg & CNTRL_CH1)) {
		dev_notice(&pdev->dev, "Secondary port is disabled\n");
		ppi[1] = &ata_dummy_port_info;
	}

	return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
}

#ifdef CONFIG_PM
static int cmd64x_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = pci_get_drvdata(pdev);
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	cmd64x_fixup(pdev);

	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id cmd64x[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 },

	{ },
};

static struct pci_driver cmd64x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cmd64x,
	.probe 		= cmd64x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cmd64x_reinit_one,
#endif
};

module_pci_driver(cmd64x_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cmd64x);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4	1	/*
fb9f8905	2	* pata_cmd64x.c - CMD64x PATA for new ATA layer
669a5db4	3	* (C) 2005 Red Hat Inc
ab771630	4	* Alan Cox <[email protected]>
a2bd6220	5	* (C) 2009-2010 Bartlomiej Zolnierkiewicz
8a686bc9	6	* (C) 2012 MontaVista Software, LLC <[email protected]>
669a5db4 JG	7	*
	8	* Based upon
	9	* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
	10	*
	11	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
	12	* Note, this driver is not used at all on other systems because
	13	* there the "BIOS" has done all of the following already.
	14	* Due to massive hardware bugs, UltraDMA is only supported
	15	* on the 646U2 and not on the 646U.
	16	*
	17	* Copyright (C) 1998 Eddie C. Dost ([email protected])
	18	* Copyright (C) 1998 David S. Miller ([email protected])
	19	*
	20	* Copyright (C) 1999-2002 Andre Hedrick <[email protected]>
	21	*
	22	* TODO
	23	* Testing work
	24	*/
85cd7251	25
669a5db4 JG	26	#include <linux/kernel.h>
	27	#include <linux/module.h>
	28	#include <linux/pci.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
	31	#include <linux/delay.h>
	32	#include <scsi/scsi_host.h>
	33	#include <linux/libata.h>
	34
	35	#define DRV_NAME "pata_cmd64x"
b8cec3c2	36	#define DRV_VERSION "0.2.18"
669a5db4 JG	37
	38	/*
	39	* CMD64x specific registers definition.
	40	*/
85cd7251	41
669a5db4 JG	42	enum {
669a5db4 JG	43	CFR = 0x50,
03a849e6	44	CFR_INTR_CH0 = 0x04,
9281b16c JB	45	CNTRL = 0x51,
	46	CNTRL_CH0 = 0x04,
	47	CNTRL_CH1 = 0x08,
669a5db4 JG	48	CMDTIM = 0x52,
	49	ARTTIM0 = 0x53,
	50	DRWTIM0 = 0x54,
	51	ARTTIM1 = 0x55,
	52	DRWTIM1 = 0x56,
	53	ARTTIM23 = 0x57,
	54	ARTTIM23_DIS_RA2 = 0x04,
	55	ARTTIM23_DIS_RA3 = 0x08,
	56	ARTTIM23_INTR_CH1 = 0x10,
669a5db4 JG	57	DRWTIM2 = 0x58,
	58	BRST = 0x59,
	59	DRWTIM3 = 0x5b,
	60	BMIDECR0 = 0x70,
	61	MRDMODE = 0x71,
	62	MRDMODE_INTR_CH0 = 0x04,
	63	MRDMODE_INTR_CH1 = 0x08,
669a5db4 JG	64	BMIDESR0 = 0x72,
	65	UDIDETCR0 = 0x73,
	66	DTPR0 = 0x74,
	67	BMIDECR1 = 0x78,
	68	BMIDECSR = 0x79,
669a5db4 JG	69	UDIDETCR1 = 0x7B,
	70	DTPR1 = 0x7C
	71	};
	72
a73984a0	73	static int cmd648_cable_detect(struct ata_port *ap)
669a5db4 JG	74	{
	75	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	76	u8 r;
	77
	78	/* Check cable detect bits */
	79	pci_read_config_byte(pdev, BMIDECSR, &r);
	80	if (r & (1 << ap->port_no))
a73984a0 JG	81	return ATA_CBL_PATA80;
a73984a0 JG	82	return ATA_CBL_PATA40;
669a5db4 JG	83	}
	84
	85	/**
57242762	86	* cmd64x_set_timing - set PIO and MWDMA timing
669a5db4 JG	87	* @ap: ATA interface
669a5db4 JG	88	* @adev: ATA device
05d1efff	89	* @mode: mode
669a5db4	90	*
05d1efff	91	* Called to do the PIO and MWDMA mode setup.
669a5db4	92	*/
85cd7251	93
05d1efff	94	static void cmd64x_set_timing(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	95	{
	96	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	97	struct ata_timing t;
	98	const unsigned long T = 1000000 / 33;
	99	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
85cd7251	100
669a5db4	101	u8 reg;
85cd7251	102
669a5db4	103	/* Port layout is not logical so use a table */
85cd7251	104	const u8 arttim_port[2][2] = {
669a5db4 JG	105	{ ARTTIM0, ARTTIM1 },
	106	{ ARTTIM23, ARTTIM23 }
	107	};
	108	const u8 drwtim_port[2][2] = {
	109	{ DRWTIM0, DRWTIM1 },
	110	{ DRWTIM2, DRWTIM3 }
	111	};
85cd7251	112
669a5db4 JG	113	int arttim = arttim_port[ap->port_no][adev->devno];
669a5db4 JG	114	int drwtim = drwtim_port[ap->port_no][adev->devno];
85cd7251	115
05d1efff AC	116	/* ata_timing_compute is smart and will produce timings for MWDMA
	117	that don't violate the drives PIO capabilities. */
	118	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
669a5db4 JG	119	printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
	120	return;
	121	}
	122	if (ap->port_no) {
	123	/* Slave has shared address setup */
	124	struct ata_device *pair = ata_dev_pair(adev);
85cd7251	125
669a5db4 JG	126	if (pair) {
	127	struct ata_timing tp;
	128	ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
	129	ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
	130	}
	131	}
85cd7251	132
669a5db4 JG	133	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
	134	t.active, t.recover, t.setup);
	135	if (t.recover > 16) {
	136	t.active += t.recover - 16;
	137	t.recover = 16;
	138	}
	139	if (t.active > 16)
	140	t.active = 16;
85cd7251	141
669a5db4 JG	142	/* Now convert the clocks into values we can actually stuff into
669a5db4 JG	143	the chip */
85cd7251	144
a2bd6220 BZ	145	if (t.recover == 16)
	146	t.recover = 0;
	147	else if (t.recover > 1)
669a5db4 JG	148	t.recover--;
	149	else
	150	t.recover = 15;
85cd7251	151
669a5db4 JG	152	if (t.setup > 4)
	153	t.setup = 0xC0;
	154	else
	155	t.setup = setup_data[t.setup];
85cd7251	156
669a5db4	157	t.active &= 0x0F; /* 0 = 16 */
85cd7251	158
669a5db4 JG	159	/* Load setup timing */
	160	pci_read_config_byte(pdev, arttim, &reg);
	161	reg &= 0x3F;
	162	reg \|= t.setup;
	163	pci_write_config_byte(pdev, arttim, reg);
85cd7251	164
669a5db4	165	/* Load active/recovery */
85cd7251	166	pci_write_config_byte(pdev, drwtim, (t.active << 4) \| t.recover);
669a5db4 JG	167	}
669a5db4 JG	168
05d1efff AC	169	/**
	170	* cmd64x_set_piomode - set initial PIO mode data
	171	* @ap: ATA interface
	172	* @adev: ATA device
	173	*
	174	* Used when configuring the devices ot set the PIO timings. All the
	175	* actual work is done by the PIO/MWDMA setting helper
	176	*/
	177
	178	static void cmd64x_set_piomode(struct ata_port ap, struct ata_device adev)
	179	{
	180	cmd64x_set_timing(ap, adev, adev->pio_mode);
	181	}
	182
669a5db4 JG	183	/**
	184	* cmd64x_set_dmamode - set initial DMA mode data
	185	* @ap: ATA interface
	186	* @adev: ATA device
	187	*
	188	* Called to do the DMA mode setup.
	189	*/
85cd7251	190
669a5db4 JG	191	static void cmd64x_set_dmamode(struct ata_port ap, struct ata_device adev)
	192	{
	193	static const u8 udma_data[] = {
6a40da02	194	0x30, 0x20, 0x10, 0x20, 0x10, 0x00
669a5db4	195	};
85cd7251	196
669a5db4 JG	197	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	198	u8 regU, regD;
	199
	200	int pciU = UDIDETCR0 + 8 * ap->port_no;
	201	int pciD = BMIDESR0 + 8 * ap->port_no;
	202	int shift = 2 * adev->devno;
85cd7251	203
669a5db4 JG	204	pci_read_config_byte(pdev, pciD, &regD);
	205	pci_read_config_byte(pdev, pciU, &regU);
	206
6a40da02 AC	207	/* DMA bits off */
	208	regD &= ~(0x20 << adev->devno);
	209	/* DMA control bits */
	210	regU &= ~(0x30 << shift);
	211	/* DMA timing bits */
	212	regU &= ~(0x05 << adev->devno);
85cd7251	213
6a40da02	214	if (adev->dma_mode >= XFER_UDMA_0) {
24b7ce98	215	/* Merge the timing value */
669a5db4	216	regU \|= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
6a40da02 AC	217	/* Merge the control bits */
6a40da02 AC	218	regU \|= 1 << adev->devno; /* UDMA on */
509426bd	219	if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
6a40da02	220	regU \|= 4 << adev->devno;
05d1efff AC	221	} else {
	222	regU &= ~ (1 << adev->devno); /* UDMA off */
	223	cmd64x_set_timing(ap, adev, adev->dma_mode);
	224	}
669a5db4 JG	225
	226	regD \|= 0x20 << adev->devno;
	227
	228	pci_write_config_byte(pdev, pciU, regU);
	229	pci_write_config_byte(pdev, pciD, regD);
	230	}
	231
b8cec3c2 SS	232	/**
	233	* cmd64x_sff_irq_check - check IDE interrupt
	234	* @ap: ATA interface
	235	*
	236	* Check IDE interrupt in CFR/ARTTIM23 registers.
	237	*/
	238
	239	static bool cmd64x_sff_irq_check(struct ata_port *ap)
	240	{
	241	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	242	int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
	243	int irq_reg = ap->port_no ? ARTTIM23 : CFR;
	244	u8 irq_stat;
	245
	246	/* NOTE: reading the register should clear the interrupt */
	247	pci_read_config_byte(pdev, irq_reg, &irq_stat);
	248
	249	return irq_stat & irq_mask;
	250	}
	251
669a5db4	252	/**
419fd246 SS	253	* cmd64x_sff_irq_clear - clear IDE interrupt
419fd246 SS	254	* @ap: ATA interface
8a686bc9	255	*
419fd246	256	* Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers.
8a686bc9 SS	257	*/
8a686bc9 SS	258
419fd246	259	static void cmd64x_sff_irq_clear(struct ata_port *ap)
8a686bc9	260	{
8a686bc9 SS	261	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	262	int irq_reg = ap->port_no ? ARTTIM23 : CFR;
	263	u8 irq_stat;
	264
419fd246	265	ata_bmdma_irq_clear(ap);
8a686bc9 SS	266
	267	/* Reading the register should be enough to clear the interrupt */
	268	pci_read_config_byte(pdev, irq_reg, &irq_stat);
	269	}
	270
b8cec3c2 SS	271	/**
	272	* cmd648_sff_irq_check - check IDE interrupt
	273	* @ap: ATA interface
	274	*
	275	* Check IDE interrupt in MRDMODE register.
	276	*/
	277
	278	static bool cmd648_sff_irq_check(struct ata_port *ap)
	279	{
	280	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	281	unsigned long base = pci_resource_start(pdev, 4);
	282	int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
	283	u8 mrdmode = inb(base + 1);
	284
	285	return mrdmode & irq_mask;
	286	}
	287
8a686bc9	288	/**
419fd246 SS	289	* cmd648_sff_irq_clear - clear IDE interrupt
419fd246 SS	290	* @ap: ATA interface
669a5db4	291	*
419fd246	292	* Clear IDE interrupt in MRDMODE and DMA status registers.
669a5db4 JG	293	*/
669a5db4 JG	294
419fd246	295	static void cmd648_sff_irq_clear(struct ata_port *ap)
669a5db4	296	{
669a5db4	297	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
8a686bc9 SS	298	unsigned long base = pci_resource_start(pdev, 4);
	299	int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
	300	u8 mrdmode;
85cd7251	301
419fd246	302	ata_bmdma_irq_clear(ap);
85cd7251	303
8a686bc9 SS	304	/* Clear this port's interrupt bit (leaving the other port alone) */
	305	mrdmode = inb(base + 1);
	306	mrdmode &= ~(MRDMODE_INTR_CH0 \| MRDMODE_INTR_CH1);
	307	outb(mrdmode \| irq_mask, base + 1);
669a5db4	308	}
85cd7251	309
669a5db4	310	/**
8a686bc9	311	* cmd646r1_bmdma_stop - DMA stop callback
669a5db4 JG	312	* @qc: Command in progress
669a5db4 JG	313	*
06393afd	314	* Stub for now while investigating the r1 quirk in the old driver.
669a5db4 JG	315	*/
669a5db4 JG	316
06393afd	317	static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
669a5db4 JG	318	{
	319	ata_bmdma_stop(qc);
	320	}
85cd7251	321
669a5db4	322	static struct scsi_host_template cmd64x_sht = {
68d1d07b	323	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	324	};
669a5db4 JG	325
029cfd6b TH	326	static const struct ata_port_operations cmd64x_base_ops = {
029cfd6b TH	327	.inherits = &ata_bmdma_port_ops,
669a5db4 JG	328	.set_piomode = cmd64x_set_piomode,
669a5db4 JG	329	.set_dmamode = cmd64x_set_dmamode,
85cd7251	330	};
669a5db4	331
029cfd6b TH	332	static struct ata_port_operations cmd64x_port_ops = {
029cfd6b TH	333	.inherits = &cmd64x_base_ops,
b8cec3c2	334	.sff_irq_check = cmd64x_sff_irq_check,
419fd246	335	.sff_irq_clear = cmd64x_sff_irq_clear,
a73984a0	336	.cable_detect = ata_cable_40wire,
029cfd6b	337	};
669a5db4	338
029cfd6b TH	339	static struct ata_port_operations cmd646r1_port_ops = {
029cfd6b TH	340	.inherits = &cmd64x_base_ops,
b8cec3c2	341	.sff_irq_check = cmd64x_sff_irq_check,
419fd246	342	.sff_irq_clear = cmd64x_sff_irq_clear,
06393afd	343	.bmdma_stop = cmd646r1_bmdma_stop,
029cfd6b	344	.cable_detect = ata_cable_40wire,
85cd7251	345	};
669a5db4	346
8a686bc9 SS	347	static struct ata_port_operations cmd646r3_port_ops = {
8a686bc9 SS	348	.inherits = &cmd64x_base_ops,
b8cec3c2	349	.sff_irq_check = cmd648_sff_irq_check,
419fd246	350	.sff_irq_clear = cmd648_sff_irq_clear,
8a686bc9 SS	351	.cable_detect = ata_cable_40wire,
	352	};
	353
669a5db4	354	static struct ata_port_operations cmd648_port_ops = {
029cfd6b	355	.inherits = &cmd64x_base_ops,
b8cec3c2	356	.sff_irq_check = cmd648_sff_irq_check,
419fd246	357	.sff_irq_clear = cmd648_sff_irq_clear,
029cfd6b	358	.cable_detect = cmd648_cable_detect,
85cd7251 JG	359	};
85cd7251 JG	360
f4c6ae50 BZ	361	static void cmd64x_fixup(struct pci_dev *pdev)
	362	{
	363	u8 mrdmode;
	364
	365	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	366	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	367	mrdmode &= ~0x30; /* IRQ set up */
	368	mrdmode \|= 0x02; /* Memory read line enable */
	369	pci_write_config_byte(pdev, MRDMODE, mrdmode);
	370
	371	/* PPC specific fixup copied from old driver */
	372	#ifdef CONFIG_PPC
	373	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	374	#endif
	375	}
	376
669a5db4 JG	377	static int cmd64x_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4 JG	378	{
8a686bc9	379	static const struct ata_port_info cmd_info[7] = {
669a5db4	380	{ /* CMD 643 - no UDMA */
1d2808fd	381	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	382	.pio_mask = ATA_PIO4,
14bdef98 EIB	383	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	384	.port_ops = &cmd64x_port_ops
	385	},
	386	{ /* CMD 646 with broken UDMA */
1d2808fd	387	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	388	.pio_mask = ATA_PIO4,
14bdef98 EIB	389	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	390	.port_ops = &cmd64x_port_ops
669a5db4 JG	391	},
8a686bc9 SS	392	{ /* CMD 646U with broken UDMA */
	393	.flags = ATA_FLAG_SLAVE_POSS,
	394	.pio_mask = ATA_PIO4,
	395	.mwdma_mask = ATA_MWDMA2,
	396	.port_ops = &cmd646r3_port_ops
	397	},
	398	{ /* CMD 646U2 with working UDMA */
1d2808fd	399	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	400	.pio_mask = ATA_PIO4,
14bdef98 EIB	401	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	402	.udma_mask = ATA_UDMA2,
8a686bc9	403	.port_ops = &cmd646r3_port_ops
669a5db4 JG	404	},
669a5db4 JG	405	{ /* CMD 646 rev 1 */
1d2808fd	406	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	407	.pio_mask = ATA_PIO4,
14bdef98 EIB	408	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	409	.port_ops = &cmd646r1_port_ops
	410	},
	411	{ /* CMD 648 */
1d2808fd	412	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	413	.pio_mask = ATA_PIO4,
14bdef98 EIB	414	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	415	.udma_mask = ATA_UDMA4,
669a5db4 JG	416	.port_ops = &cmd648_port_ops
	417	},
	418	{ /* CMD 649 */
1d2808fd	419	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	420	.pio_mask = ATA_PIO4,
14bdef98 EIB	421	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	422	.udma_mask = ATA_UDMA5,
669a5db4 JG	423	.port_ops = &cmd648_port_ops
	424	}
	425	};
641589bf	426	const struct ata_port_info *ppi[] = {
9281b16c JB	427	&cmd_info[id->driver_data],
	428	&cmd_info[id->driver_data],
	429	NULL
	430	};
f4c6ae50	431	u8 reg;
f08048e9	432	int rc;
9281b16c JB	433	struct pci_dev *bridge = pdev->bus->self;
	434	/* mobility split bridges don't report enabled ports correctly */
	435	int port_ok = !(bridge && bridge->vendor ==
	436	PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
	437	/* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
	438	int cntrl_ch0_ok = (id->driver_data != 0);
f08048e9 TH	439
	440	rc = pcim_enable_device(pdev);
	441	if (rc)
	442	return rc;
85cd7251	443
669a5db4	444	if (id->driver_data == 0) /* 643 */
9363c382	445	ata_pci_bmdma_clear_simplex(pdev);
85cd7251	446
8fcfa7bd SS	447	if (pdev->device == PCI_DEVICE_ID_CMD_646)
	448	switch (pdev->revision) {
	449	/* UDMA works since rev 5 */
	450	default:
8a686bc9 SS	451	ppi[0] = &cmd_info[3];
8a686bc9 SS	452	ppi[1] = &cmd_info[3];
8fcfa7bd	453	break;
8a686bc9	454	/* Interrupts in MRDMODE since rev 3 */
8fcfa7bd SS	455	case 3:
8fcfa7bd SS	456	case 4:
8a686bc9 SS	457	ppi[0] = &cmd_info[2];
8a686bc9 SS	458	ppi[1] = &cmd_info[2];
8fcfa7bd SS	459	break;
	460	/* Rev 1 with other problems? */
	461	case 1:
8a686bc9 SS	462	ppi[0] = &cmd_info[4];
8a686bc9 SS	463	ppi[1] = &cmd_info[4];
8fcfa7bd SS	464	/* FALL THRU */
	465	/* Early revs have no CNTRL_CH0 */
	466	case 2:
	467	case 0:
9281b16c	468	cntrl_ch0_ok = 0;
8fcfa7bd SS	469	break;
8fcfa7bd SS	470	}
669a5db4	471
f4c6ae50	472	cmd64x_fixup(pdev);
85cd7251	473
9281b16c JB	474	/* check for enabled ports */
	475	pci_read_config_byte(pdev, CNTRL, &reg);
	476	if (!port_ok)
a52f514c	477	dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
9281b16c	478	if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
a52f514c	479	dev_notice(&pdev->dev, "Primary port is disabled\n");
9281b16c	480	ppi[0] = &ata_dummy_port_info;
641589bf	481
9281b16c JB	482	}
9281b16c JB	483	if (port_ok && !(reg & CNTRL_CH1)) {
a52f514c	484	dev_notice(&pdev->dev, "Secondary port is disabled\n");
9281b16c JB	485	ppi[1] = &ata_dummy_port_info;
	486	}
	487
1c5afdf7	488	return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
669a5db4 JG	489	}
669a5db4 JG	490
438ac6d5	491	#ifdef CONFIG_PM
7f72a379 AC	492	static int cmd64x_reinit_one(struct pci_dev *pdev)
7f72a379 AC	493	{
0a86e1c8	494	struct ata_host *host = pci_get_drvdata(pdev);
f08048e9 TH	495	int rc;
	496
	497	rc = ata_pci_device_do_resume(pdev);
	498	if (rc)
	499	return rc;
	500
f4c6ae50 BZ	501	cmd64x_fixup(pdev);
f4c6ae50 BZ	502
f08048e9 TH	503	ata_host_resume(host);
f08048e9 TH	504	return 0;
7f72a379	505	}
438ac6d5	506	#endif
7f72a379	507
2d2744fc JG	508	static const struct pci_device_id cmd64x[] = {
	509	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	510	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
8a686bc9 SS	511	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 },
8a686bc9 SS	512	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 },
2d2744fc JG	513
2d2744fc JG	514	{ },
669a5db4 JG	515	};
	516
	517	static struct pci_driver cmd64x_pci_driver = {
2d2744fc	518	.name = DRV_NAME,
669a5db4 JG	519	.id_table = cmd64x,
669a5db4 JG	520	.probe = cmd64x_init_one,
7f72a379	521	.remove = ata_pci_remove_one,
438ac6d5	522	#ifdef CONFIG_PM
7f72a379 AC	523	.suspend = ata_pci_device_suspend,
7f72a379 AC	524	.resume = cmd64x_reinit_one,
438ac6d5	525	#endif
669a5db4 JG	526	};
669a5db4 JG	527
2fc75da0	528	module_pci_driver(cmd64x_pci_driver);
669a5db4	529
669a5db4 JG	530	MODULE_AUTHOR("Alan Cox");
	531	MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
	532	MODULE_LICENSE("GPL");
	533	MODULE_DEVICE_TABLE(pci, cmd64x);
	534	MODULE_VERSION(DRV_VERSION);