[linux.git] / drivers / ata / pata_cmd64x.c

/*
 * pata_cmd64x.c 	- CMD64x PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <[email protected]>
 *			  (C) 2009-2010 Bartlomiej Zolnierkiewicz
 *
 * Based upon
 * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  ([email protected])
 * Copyright (C) 1998		David S. Miller ([email protected])
 *
 * Copyright (C) 1999-2002	Andre Hedrick <[email protected]>
 *
 * TODO
 *	Testing work
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_cmd64x"
#define DRV_VERSION "0.2.5"

/*
 * CMD64x specific registers definition.
 */

enum {
	CFR 		= 0x50,
		CFR_INTR_CH0  = 0x04,
	CMDTIM 		= 0x52,
	ARTTIM0 	= 0x53,
	DRWTIM0 	= 0x54,
	ARTTIM1 	= 0x55,
	DRWTIM1 	= 0x56,
	ARTTIM23 	= 0x57,
		ARTTIM23_DIS_RA2  = 0x04,
		ARTTIM23_DIS_RA3  = 0x08,
		ARTTIM23_INTR_CH1 = 0x10,
	DRWTIM2 	= 0x58,
	BRST 		= 0x59,
	DRWTIM3 	= 0x5b,
	BMIDECR0	= 0x70,
	MRDMODE		= 0x71,
		MRDMODE_INTR_CH0 = 0x04,
		MRDMODE_INTR_CH1 = 0x08,
	BMIDESR0	= 0x72,
	UDIDETCR0	= 0x73,
	DTPR0		= 0x74,
	BMIDECR1	= 0x78,
	BMIDECSR	= 0x79,
	UDIDETCR1	= 0x7B,
	DTPR1		= 0x7C
};

static int cmd648_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 r;

	/* Check cable detect bits */
	pci_read_config_byte(pdev, BMIDECSR, &r);
	if (r & (1 << ap->port_no))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	cmd64x_set_piomode	-	set PIO and MWDMA timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: mode
 *
 *	Called to do the PIO and MWDMA mode setup.
 */

static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_timing t;
	const unsigned long T = 1000000 / 33;
	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };

	u8 reg;

	/* Port layout is not logical so use a table */
	const u8 arttim_port[2][2] = {
		{ ARTTIM0, ARTTIM1 },
		{ ARTTIM23, ARTTIM23 }
	};
	const u8 drwtim_port[2][2] = {
		{ DRWTIM0, DRWTIM1 },
		{ DRWTIM2, DRWTIM3 }
	};

	int arttim = arttim_port[ap->port_no][adev->devno];
	int drwtim = drwtim_port[ap->port_no][adev->devno];

	/* ata_timing_compute is smart and will produce timings for MWDMA
	   that don't violate the drives PIO capabilities. */
	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
		return;
	}
	if (ap->port_no) {
		/* Slave has shared address setup */
		struct ata_device *pair = ata_dev_pair(adev);

		if (pair) {
			struct ata_timing tp;

			ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
			ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
			if (pair->dma_mode) {
				ata_timing_compute(pair, pair->dma_mode,
						&tp, T, 0);
				ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP);
			}
		}
	}

	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
		t.active, t.recover, t.setup);
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)
		t.active = 16;

	/* Now convert the clocks into values we can actually stuff into
	   the chip */

	if (t.recover == 16)
		t.recover = 0;
	else if (t.recover > 1)
		t.recover--;
	else
		t.recover = 15;

	if (t.setup > 4)
		t.setup = 0xC0;
	else
		t.setup = setup_data[t.setup];

	t.active &= 0x0F;	/* 0 = 16 */

	/* Load setup timing */
	pci_read_config_byte(pdev, arttim, &reg);
	reg &= 0x3F;
	reg |= t.setup;
	pci_write_config_byte(pdev, arttim, reg);

	/* Load active/recovery */
	pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}

/**
 *	cmd64x_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Used when configuring the devices ot set the PIO timings. All the
 *	actual work is done by the PIO/MWDMA setting helper
 */

static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	cmd64x_set_timing(ap, adev, adev->pio_mode);
}

/**
 *	cmd64x_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup.
 */

static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 udma_data[] = {
		0x30, 0x20, 0x10, 0x20, 0x10, 0x00
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 regU, regD;

	int pciU = UDIDETCR0 + 8 * ap->port_no;
	int pciD = BMIDESR0 + 8 * ap->port_no;
	int shift = 2 * adev->devno;

	pci_read_config_byte(pdev, pciD, &regD);
	pci_read_config_byte(pdev, pciU, &regU);

	/* DMA bits off */
	regD &= ~(0x20 << adev->devno);
	/* DMA control bits */
	regU &= ~(0x30 << shift);
	/* DMA timing bits */
	regU &= ~(0x05 << adev->devno);

	if (adev->dma_mode >= XFER_UDMA_0) {
		/* Merge the timing value */
		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
		/* Merge the control bits */
		regU |= 1 << adev->devno; /* UDMA on */
		if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
			regU |= 4 << adev->devno;
	} else {
		regU &= ~ (1 << adev->devno);	/* UDMA off */
		cmd64x_set_timing(ap, adev, adev->dma_mode);
	}

	regD |= 0x20 << adev->devno;

	pci_write_config_byte(pdev, pciU, regU);
	pci_write_config_byte(pdev, pciD, regD);
}

/**
 *	cmd648_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	DMA has completed.
 */

static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 dma_intr;
	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
	int dma_reg = ap->port_no ? ARTTIM23 : CFR;

	ata_bmdma_stop(qc);

	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}

/**
 *	cmd646r1_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	Stub for now while investigating the r1 quirk in the old driver.
 */

static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
{
	ata_bmdma_stop(qc);
}

static struct scsi_host_template cmd64x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations cmd64x_base_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
};

static struct ata_port_operations cmd64x_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd646r1_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.bmdma_stop	= cmd646r1_bmdma_stop,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd648_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.bmdma_stop	= cmd648_bmdma_stop,
	.cable_detect	= cmd648_cable_detect,
};

static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info cmd_info[6] = {
		{	/* CMD 643 - no UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with broken UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with working UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 rev 1  */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd646r1_port_ops
		},
		{	/* CMD 648 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &cmd648_port_ops
		},
		{	/* CMD 649 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &cmd648_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
	u8 mrdmode;
	int rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (id->driver_data == 0)	/* 643 */
		ata_pci_bmdma_clear_simplex(pdev);

	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
		/* Does UDMA work ? */
		if (pdev->revision > 4)
			ppi[0] = &cmd_info[2];
		/* Early rev with other problems ? */
		else if (pdev->revision == 1)
			ppi[0] = &cmd_info[3];
	}

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);

	/* Force PIO 0 here.. */

	/* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif

	return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
}

#ifdef CONFIG_PM
static int cmd64x_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	u8 mrdmode;
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id cmd64x[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },

	{ },
};

static struct pci_driver cmd64x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cmd64x,
	.probe 		= cmd64x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cmd64x_reinit_one,
#endif
};

static int __init cmd64x_init(void)
{
	return pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cmd64x);
MODULE_VERSION(DRV_VERSION);

module_init(cmd64x_init);
module_exit(cmd64x_exit);
Commit	Line	Data
669a5db4	1	/*
fb9f8905	2	* pata_cmd64x.c - CMD64x PATA for new ATA layer
669a5db4	3	* (C) 2005 Red Hat Inc
ab771630	4	* Alan Cox <[email protected]>
a2bd6220	5	* (C) 2009-2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based upon
	8	* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
	9	*
	10	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
	11	* Note, this driver is not used at all on other systems because
	12	* there the "BIOS" has done all of the following already.
	13	* Due to massive hardware bugs, UltraDMA is only supported
	14	* on the 646U2 and not on the 646U.
	15	*
	16	* Copyright (C) 1998 Eddie C. Dost ([email protected])
	17	* Copyright (C) 1998 David S. Miller ([email protected])
	18	*
	19	* Copyright (C) 1999-2002 Andre Hedrick <[email protected]>
	20	*
	21	* TODO
	22	* Testing work
	23	*/
85cd7251	24
669a5db4 JG	25	#include <linux/kernel.h>
	26	#include <linux/module.h>
	27	#include <linux/pci.h>
	28	#include <linux/init.h>
	29	#include <linux/blkdev.h>
	30	#include <linux/delay.h>
	31	#include <scsi/scsi_host.h>
	32	#include <linux/libata.h>
	33
	34	#define DRV_NAME "pata_cmd64x"
06393afd	35	#define DRV_VERSION "0.2.5"
669a5db4 JG	36
	37	/*
	38	* CMD64x specific registers definition.
	39	*/
85cd7251	40
669a5db4 JG	41	enum {
669a5db4 JG	42	CFR = 0x50,
03a849e6	43	CFR_INTR_CH0 = 0x04,
669a5db4 JG	44	CMDTIM = 0x52,
	45	ARTTIM0 = 0x53,
	46	DRWTIM0 = 0x54,
	47	ARTTIM1 = 0x55,
	48	DRWTIM1 = 0x56,
	49	ARTTIM23 = 0x57,
	50	ARTTIM23_DIS_RA2 = 0x04,
	51	ARTTIM23_DIS_RA3 = 0x08,
	52	ARTTIM23_INTR_CH1 = 0x10,
669a5db4 JG	53	DRWTIM2 = 0x58,
	54	BRST = 0x59,
	55	DRWTIM3 = 0x5b,
	56	BMIDECR0 = 0x70,
	57	MRDMODE = 0x71,
	58	MRDMODE_INTR_CH0 = 0x04,
	59	MRDMODE_INTR_CH1 = 0x08,
669a5db4 JG	60	BMIDESR0 = 0x72,
	61	UDIDETCR0 = 0x73,
	62	DTPR0 = 0x74,
	63	BMIDECR1 = 0x78,
	64	BMIDECSR = 0x79,
669a5db4 JG	65	UDIDETCR1 = 0x7B,
	66	DTPR1 = 0x7C
	67	};
	68
a73984a0	69	static int cmd648_cable_detect(struct ata_port *ap)
669a5db4 JG	70	{
	71	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	72	u8 r;
	73
	74	/* Check cable detect bits */
	75	pci_read_config_byte(pdev, BMIDECSR, &r);
	76	if (r & (1 << ap->port_no))
a73984a0 JG	77	return ATA_CBL_PATA80;
a73984a0 JG	78	return ATA_CBL_PATA40;
669a5db4 JG	79	}
	80
	81	/**
05d1efff	82	* cmd64x_set_piomode - set PIO and MWDMA timing
669a5db4 JG	83	* @ap: ATA interface
669a5db4 JG	84	* @adev: ATA device
05d1efff	85	* @mode: mode
669a5db4	86	*
05d1efff	87	* Called to do the PIO and MWDMA mode setup.
669a5db4	88	*/
85cd7251	89
05d1efff	90	static void cmd64x_set_timing(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	91	{
	92	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	93	struct ata_timing t;
	94	const unsigned long T = 1000000 / 33;
	95	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
85cd7251	96
669a5db4	97	u8 reg;
85cd7251	98
669a5db4	99	/* Port layout is not logical so use a table */
85cd7251	100	const u8 arttim_port[2][2] = {
669a5db4 JG	101	{ ARTTIM0, ARTTIM1 },
	102	{ ARTTIM23, ARTTIM23 }
	103	};
	104	const u8 drwtim_port[2][2] = {
	105	{ DRWTIM0, DRWTIM1 },
	106	{ DRWTIM2, DRWTIM3 }
	107	};
85cd7251	108
669a5db4 JG	109	int arttim = arttim_port[ap->port_no][adev->devno];
669a5db4 JG	110	int drwtim = drwtim_port[ap->port_no][adev->devno];
85cd7251	111
05d1efff AC	112	/* ata_timing_compute is smart and will produce timings for MWDMA
	113	that don't violate the drives PIO capabilities. */
	114	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
669a5db4 JG	115	printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
	116	return;
	117	}
	118	if (ap->port_no) {
	119	/* Slave has shared address setup */
	120	struct ata_device *pair = ata_dev_pair(adev);
85cd7251	121
669a5db4 JG	122	if (pair) {
669a5db4 JG	123	struct ata_timing tp;
d62f5576	124
669a5db4 JG	125	ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
669a5db4 JG	126	ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
d62f5576 BZ	127	if (pair->dma_mode) {
	128	ata_timing_compute(pair, pair->dma_mode,
	129	&tp, T, 0);
	130	ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP);
	131	}
669a5db4 JG	132	}
669a5db4 JG	133	}
85cd7251	134
669a5db4 JG	135	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
	136	t.active, t.recover, t.setup);
	137	if (t.recover > 16) {
	138	t.active += t.recover - 16;
	139	t.recover = 16;
	140	}
	141	if (t.active > 16)
	142	t.active = 16;
85cd7251	143
669a5db4 JG	144	/* Now convert the clocks into values we can actually stuff into
669a5db4 JG	145	the chip */
85cd7251	146
a2bd6220 BZ	147	if (t.recover == 16)
	148	t.recover = 0;
	149	else if (t.recover > 1)
669a5db4 JG	150	t.recover--;
	151	else
	152	t.recover = 15;
85cd7251	153
669a5db4 JG	154	if (t.setup > 4)
	155	t.setup = 0xC0;
	156	else
	157	t.setup = setup_data[t.setup];
85cd7251	158
669a5db4	159	t.active &= 0x0F; /* 0 = 16 */
85cd7251	160
669a5db4 JG	161	/* Load setup timing */
	162	pci_read_config_byte(pdev, arttim, &reg);
	163	reg &= 0x3F;
	164	reg \|= t.setup;
	165	pci_write_config_byte(pdev, arttim, reg);
85cd7251	166
669a5db4	167	/* Load active/recovery */
85cd7251	168	pci_write_config_byte(pdev, drwtim, (t.active << 4) \| t.recover);
669a5db4 JG	169	}
669a5db4 JG	170
05d1efff AC	171	/**
	172	* cmd64x_set_piomode - set initial PIO mode data
	173	* @ap: ATA interface
	174	* @adev: ATA device
	175	*
	176	* Used when configuring the devices ot set the PIO timings. All the
	177	* actual work is done by the PIO/MWDMA setting helper
	178	*/
	179
	180	static void cmd64x_set_piomode(struct ata_port ap, struct ata_device adev)
	181	{
	182	cmd64x_set_timing(ap, adev, adev->pio_mode);
	183	}
	184
669a5db4 JG	185	/**
	186	* cmd64x_set_dmamode - set initial DMA mode data
	187	* @ap: ATA interface
	188	* @adev: ATA device
	189	*
	190	* Called to do the DMA mode setup.
	191	*/
85cd7251	192
669a5db4 JG	193	static void cmd64x_set_dmamode(struct ata_port ap, struct ata_device adev)
	194	{
	195	static const u8 udma_data[] = {
6a40da02	196	0x30, 0x20, 0x10, 0x20, 0x10, 0x00
669a5db4	197	};
85cd7251	198
669a5db4 JG	199	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	200	u8 regU, regD;
	201
	202	int pciU = UDIDETCR0 + 8 * ap->port_no;
	203	int pciD = BMIDESR0 + 8 * ap->port_no;
	204	int shift = 2 * adev->devno;
85cd7251	205
669a5db4 JG	206	pci_read_config_byte(pdev, pciD, &regD);
	207	pci_read_config_byte(pdev, pciU, &regU);
	208
6a40da02 AC	209	/* DMA bits off */
	210	regD &= ~(0x20 << adev->devno);
	211	/* DMA control bits */
	212	regU &= ~(0x30 << shift);
	213	/* DMA timing bits */
	214	regU &= ~(0x05 << adev->devno);
85cd7251	215
6a40da02	216	if (adev->dma_mode >= XFER_UDMA_0) {
24b7ce98	217	/* Merge the timing value */
669a5db4	218	regU \|= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
6a40da02 AC	219	/* Merge the control bits */
6a40da02 AC	220	regU \|= 1 << adev->devno; /* UDMA on */
509426bd	221	if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
6a40da02	222	regU \|= 4 << adev->devno;
05d1efff AC	223	} else {
	224	regU &= ~ (1 << adev->devno); /* UDMA off */
	225	cmd64x_set_timing(ap, adev, adev->dma_mode);
	226	}
669a5db4 JG	227
	228	regD \|= 0x20 << adev->devno;
	229
	230	pci_write_config_byte(pdev, pciU, regU);
	231	pci_write_config_byte(pdev, pciD, regD);
	232	}
	233
	234	/**
	235	* cmd648_dma_stop - DMA stop callback
	236	* @qc: Command in progress
	237	*
	238	* DMA has completed.
	239	*/
	240
	241	static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
	242	{
	243	struct ata_port *ap = qc->ap;
	244	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	245	u8 dma_intr;
6a40da02	246	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
c754d9b6	247	int dma_reg = ap->port_no ? ARTTIM23 : CFR;
85cd7251	248
669a5db4	249	ata_bmdma_stop(qc);
85cd7251	250
669a5db4 JG	251	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	252	pci_write_config_byte(pdev, dma_reg, dma_intr \| dma_mask);
	253	}
85cd7251	254
669a5db4	255	/**
06393afd	256	* cmd646r1_dma_stop - DMA stop callback
669a5db4 JG	257	* @qc: Command in progress
669a5db4 JG	258	*
06393afd	259	* Stub for now while investigating the r1 quirk in the old driver.
669a5db4 JG	260	*/
669a5db4 JG	261
06393afd	262	static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
669a5db4 JG	263	{
	264	ata_bmdma_stop(qc);
	265	}
85cd7251	266
669a5db4	267	static struct scsi_host_template cmd64x_sht = {
68d1d07b	268	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	269	};
669a5db4 JG	270
029cfd6b TH	271	static const struct ata_port_operations cmd64x_base_ops = {
029cfd6b TH	272	.inherits = &ata_bmdma_port_ops,
669a5db4 JG	273	.set_piomode = cmd64x_set_piomode,
669a5db4 JG	274	.set_dmamode = cmd64x_set_dmamode,
85cd7251	275	};
669a5db4	276
029cfd6b TH	277	static struct ata_port_operations cmd64x_port_ops = {
029cfd6b TH	278	.inherits = &cmd64x_base_ops,
a73984a0	279	.cable_detect = ata_cable_40wire,
029cfd6b	280	};
669a5db4	281
029cfd6b TH	282	static struct ata_port_operations cmd646r1_port_ops = {
029cfd6b TH	283	.inherits = &cmd64x_base_ops,
06393afd	284	.bmdma_stop = cmd646r1_bmdma_stop,
029cfd6b	285	.cable_detect = ata_cable_40wire,
85cd7251	286	};
669a5db4 JG	287
669a5db4 JG	288	static struct ata_port_operations cmd648_port_ops = {
029cfd6b	289	.inherits = &cmd64x_base_ops,
669a5db4	290	.bmdma_stop = cmd648_bmdma_stop,
029cfd6b	291	.cable_detect = cmd648_cable_detect,
85cd7251 JG	292	};
85cd7251 JG	293
669a5db4 JG	294	static int cmd64x_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4 JG	295	{
1626aeb8	296	static const struct ata_port_info cmd_info[6] = {
669a5db4	297	{ /* CMD 643 - no UDMA */
1d2808fd	298	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	299	.pio_mask = ATA_PIO4,
14bdef98 EIB	300	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	301	.port_ops = &cmd64x_port_ops
	302	},
	303	{ /* CMD 646 with broken UDMA */
1d2808fd	304	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	305	.pio_mask = ATA_PIO4,
14bdef98 EIB	306	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	307	.port_ops = &cmd64x_port_ops
	308	},
	309	{ /* CMD 646 with working UDMA */
1d2808fd	310	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	311	.pio_mask = ATA_PIO4,
14bdef98 EIB	312	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	313	.udma_mask = ATA_UDMA2,
669a5db4 JG	314	.port_ops = &cmd64x_port_ops
	315	},
	316	{ /* CMD 646 rev 1 */
1d2808fd	317	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	318	.pio_mask = ATA_PIO4,
14bdef98 EIB	319	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	320	.port_ops = &cmd646r1_port_ops
	321	},
	322	{ /* CMD 648 */
1d2808fd	323	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	324	.pio_mask = ATA_PIO4,
14bdef98 EIB	325	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	326	.udma_mask = ATA_UDMA4,
669a5db4 JG	327	.port_ops = &cmd648_port_ops
	328	},
	329	{ /* CMD 649 */
1d2808fd	330	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	331	.pio_mask = ATA_PIO4,
14bdef98 EIB	332	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	333	.udma_mask = ATA_UDMA5,
669a5db4 JG	334	.port_ops = &cmd648_port_ops
	335	}
	336	};
1626aeb8	337	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
669a5db4	338	u8 mrdmode;
f08048e9 TH	339	int rc;
	340
	341	rc = pcim_enable_device(pdev);
	342	if (rc)
	343	return rc;
85cd7251	344
669a5db4	345	if (id->driver_data == 0) /* 643 */
9363c382	346	ata_pci_bmdma_clear_simplex(pdev);
85cd7251	347
669a5db4 JG	348	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
669a5db4 JG	349	/* Does UDMA work ? */
89d3b360	350	if (pdev->revision > 4)
1626aeb8	351	ppi[0] = &cmd_info[2];
669a5db4	352	/* Early rev with other problems ? */
89d3b360	353	else if (pdev->revision == 1)
1626aeb8	354	ppi[0] = &cmd_info[3];
669a5db4 JG	355	}
	356
	357	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	358	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	359	mrdmode &= ~ 0x30; /* IRQ set up */
	360	mrdmode \|= 0x02; /* Memory read line enable */
	361	pci_write_config_byte(pdev, MRDMODE, mrdmode);
85cd7251	362
06393afd JG	363	/* Force PIO 0 here.. */
06393afd JG	364
669a5db4 JG	365	/* PPC specific fixup copied from old driver */
	366	#ifdef CONFIG_PPC
	367	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	368	#endif
85cd7251	369
16ea0fc9	370	return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
669a5db4 JG	371	}
669a5db4 JG	372
438ac6d5	373	#ifdef CONFIG_PM
7f72a379 AC	374	static int cmd64x_reinit_one(struct pci_dev *pdev)
7f72a379 AC	375	{
f08048e9	376	struct ata_host *host = dev_get_drvdata(&pdev->dev);
7f72a379	377	u8 mrdmode;
f08048e9 TH	378	int rc;
	379
	380	rc = ata_pci_device_do_resume(pdev);
	381	if (rc)
	382	return rc;
	383
7f72a379 AC	384	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	385	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	386	mrdmode &= ~ 0x30; /* IRQ set up */
	387	mrdmode \|= 0x02; /* Memory read line enable */
	388	pci_write_config_byte(pdev, MRDMODE, mrdmode);
	389	#ifdef CONFIG_PPC
	390	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	391	#endif
f08048e9 TH	392	ata_host_resume(host);
f08048e9 TH	393	return 0;
7f72a379	394	}
438ac6d5	395	#endif
7f72a379	396
2d2744fc JG	397	static const struct pci_device_id cmd64x[] = {
	398	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	399	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	400	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	401	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
	402
	403	{ },
669a5db4 JG	404	};
	405
	406	static struct pci_driver cmd64x_pci_driver = {
2d2744fc	407	.name = DRV_NAME,
669a5db4 JG	408	.id_table = cmd64x,
669a5db4 JG	409	.probe = cmd64x_init_one,
7f72a379	410	.remove = ata_pci_remove_one,
438ac6d5	411	#ifdef CONFIG_PM
7f72a379 AC	412	.suspend = ata_pci_device_suspend,
7f72a379 AC	413	.resume = cmd64x_reinit_one,
438ac6d5	414	#endif
669a5db4 JG	415	};
	416
	417	static int __init cmd64x_init(void)
	418	{
	419	return pci_register_driver(&cmd64x_pci_driver);
	420	}
	421
669a5db4 JG	422	static void __exit cmd64x_exit(void)
	423	{
	424	pci_unregister_driver(&cmd64x_pci_driver);
	425	}
	426
669a5db4 JG	427	MODULE_AUTHOR("Alan Cox");
	428	MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
	429	MODULE_LICENSE("GPL");
	430	MODULE_DEVICE_TABLE(pci, cmd64x);
	431	MODULE_VERSION(DRV_VERSION);
	432
	433	module_init(cmd64x_init);
	434	module_exit(cmd64x_exit);