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drm/i915: Move compute part of __intel_set_mode() to separate function
[linux.git] / drivers / gpu / drm / i915 / intel_display.c
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79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <[email protected]>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
SV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
SV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 108static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
109 int num_connectors);
ce22dba9
ML		 110static void intel_crtc_enable_planes(struct drm_crtc *crtc);
111static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 112
0e32b39c
DA		 113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
d2acd215
SV		 136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
021357ac
CW		 146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
8b99e68c
CW		 149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
021357ac
CW		 154}
155
5d536e28 156static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 157 .dot = { .min = 25000, .max = 350000 },
9c333719 158 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 159 .n = { .min = 2, .max = 16 },
0206e353
AJ		 160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 167};
168
5d536e28
SV		 169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
9c333719 171 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 172 .n = { .min = 2, .max = 16 },
5d536e28
SV		 173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
e4b36699 182static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 183 .dot = { .min = 25000, .max = 350000 },
9c333719 184 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 185 .n = { .min = 2, .max = 16 },
0206e353
AJ		 186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
e4b36699 193};
273e27ca 194
e4b36699 195static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 219};
220
273e27ca 221
e4b36699 222static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
044c7c41 234 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
044c7c41 261 },
e4b36699
KP		 262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
044c7c41 275 },
e4b36699
KP		 276};
277
f2b115e6 278static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 281 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
273e27ca 284 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 291};
292
f2b115e6 293static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 304};
305
273e27ca
EA		 306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
b91ad0ec 311static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 322};
323
b91ad0ec 324static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 348};
349
273e27ca 350/* LVDS 100mhz refclk limits. */
b91ad0ec 351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
0206e353 359 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
0206e353 372 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 375};
376
dc730512 377static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 385 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 386 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
b99ab663 389 .p1 = { .min = 2, .max = 3 },
5fdc9c49 390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 391};
392
ef9348c8
CML		 393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 401 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
5ab7b0b7
ID		 409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
6b4bf1c4
VS		 421static void vlv_clock(int refclk, intel_clock_t *clock)
422{
423 clock->m = clock->m1 * clock->m2;
424 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 425 if (WARN_ON(clock->n == 0 || clock->p == 0))
426 return;
fb03ac01
VS		 427 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
428 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 429}
430
e0638cdf
PZ		 431/**
432 * Returns whether any output on the specified pipe is of the specified type
433 */
4093561b 434bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 435{
409ee761 436 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 437 struct intel_encoder *encoder;
438
409ee761 439 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 440 if (encoder->type == type)
441 return true;
442
443 return false;
444}
445
d0737e1d
ACO		 446/**
447 * Returns whether any output on the specified pipe will have the specified
448 * type after a staged modeset is complete, i.e., the same as
449 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
450 * encoder->crtc.
451 */
a93e255f
ACO		 452static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
453 int type)
d0737e1d 454{
a93e255f 455 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 456 struct drm_connector *connector;
a93e255f 457 struct drm_connector_state *connector_state;
d0737e1d 458 struct intel_encoder *encoder;
a93e255f
ACO		 459 int i, num_connectors = 0;
460
da3ced29 461 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 462 if (connector_state->crtc != crtc_state->base.crtc)
463 continue;
464
465 num_connectors++;
d0737e1d 466
a93e255f
ACO		 467 encoder = to_intel_encoder(connector_state->best_encoder);
468 if (encoder->type == type)
d0737e1d 469 return true;
a93e255f
ACO		 470 }
471
472 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 473
474 return false;
475}
476
a93e255f
ACO		 477static const intel_limit_t *
478intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 479{
a93e255f 480 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 481 const intel_limit_t *limit;
b91ad0ec 482
a93e255f 483 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 484 if (intel_is_dual_link_lvds(dev)) {
1b894b59 485 if (refclk == 100000)
b91ad0ec
ZW		 486 limit = &intel_limits_ironlake_dual_lvds_100m;
487 else
488 limit = &intel_limits_ironlake_dual_lvds;
489 } else {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_single_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_single_lvds;
494 }
c6bb3538 495 } else
b91ad0ec 496 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 497
498 return limit;
499}
500
a93e255f
ACO		 501static const intel_limit_t *
502intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 503{
a93e255f 504 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 505 const intel_limit_t *limit;
506
a93e255f 507 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 508 if (intel_is_dual_link_lvds(dev))
e4b36699 509 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 510 else
e4b36699 511 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 512 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
513 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 514 limit = &intel_limits_g4x_hdmi;
a93e255f 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 516 limit = &intel_limits_g4x_sdvo;
044c7c41 517 } else /* The option is for other outputs */
e4b36699 518 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 519
520 return limit;
521}
522
a93e255f
ACO		 523static const intel_limit_t *
524intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 525{
a93e255f 526 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 527 const intel_limit_t *limit;
528
5ab7b0b7
ID		 529 if (IS_BROXTON(dev))
530 limit = &intel_limits_bxt;
531 else if (HAS_PCH_SPLIT(dev))
a93e255f 532 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 533 else if (IS_G4X(dev)) {
a93e255f 534 limit = intel_g4x_limit(crtc_state);
f2b115e6 535 } else if (IS_PINEVIEW(dev)) {
a93e255f 536 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 537 limit = &intel_limits_pineview_lvds;
2177832f 538 else
f2b115e6 539 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 540 } else if (IS_CHERRYVIEW(dev)) {
541 limit = &intel_limits_chv;
a0c4da24 542 } else if (IS_VALLEYVIEW(dev)) {
dc730512 543 limit = &intel_limits_vlv;
a6c45cf0 544 } else if (!IS_GEN2(dev)) {
a93e255f 545 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 546 limit = &intel_limits_i9xx_lvds;
547 else
548 limit = &intel_limits_i9xx_sdvo;
79e53945 549 } else {
a93e255f 550 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 551 limit = &intel_limits_i8xx_lvds;
a93e255f 552 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 553 limit = &intel_limits_i8xx_dvo;
5d536e28
SV		 554 else
555 limit = &intel_limits_i8xx_dac;
79e53945
JB		 556 }
557 return limit;
558}
559
f2b115e6
AJ		 560/* m1 is reserved as 0 in Pineview, n is a ring counter */
561static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 562{
2177832f
SL		 563 clock->m = clock->m2 + 2;
564 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 565 if (WARN_ON(clock->n == 0 || clock->p == 0))
566 return;
fb03ac01
VS		 567 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
568 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 569}
570
7429e9d4
SV		 571static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
572{
573 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
574}
575
ac58c3f0 576static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 577{
7429e9d4 578 clock->m = i9xx_dpll_compute_m(clock);
79e53945 579 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 580 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
581 return;
fb03ac01
VS		 582 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
583 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 584}
585
ef9348c8
CML		 586static void chv_clock(int refclk, intel_clock_t *clock)
587{
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
591 return;
592 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
593 clock->n << 22);
594 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
595}
596
7c04d1d9 597#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 598/**
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
601 */
602
1b894b59
CW		 603static bool intel_PLL_is_valid(struct drm_device *dev,
604 const intel_limit_t *limit,
605 const intel_clock_t *clock)
79e53945 606{
f01b7962
VS		 607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
79e53945 609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 610 INTELPllInvalid("p1 out of range\n");
79e53945 611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 612 INTELPllInvalid("m2 out of range\n");
79e53945 613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 614 INTELPllInvalid("m1 out of range\n");
f01b7962 615
5ab7b0b7 616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 617 if (clock->m1 <= clock->m2)
618 INTELPllInvalid("m1 <= m2\n");
619
5ab7b0b7 620 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 621 if (clock->p < limit->p.min || limit->p.max < clock->p)
622 INTELPllInvalid("p out of range\n");
623 if (clock->m < limit->m.min || limit->m.max < clock->m)
624 INTELPllInvalid("m out of range\n");
625 }
626
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093 638static bool
a93e255f
ACO		 639i9xx_find_best_dpll(const intel_limit_t *limit,
640 struct intel_crtc_state *crtc_state,
cec2f356
SP		 641 int target, int refclk, intel_clock_t *match_clock,
642 intel_clock_t *best_clock)
79e53945 643{
a93e255f 644 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 645 struct drm_device *dev = crtc->base.dev;
79e53945 646 intel_clock_t clock;
79e53945
JB		 647 int err = target;
648
a93e255f 649 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 650 /*
a210b028
SV		 651 * For LVDS just rely on its current settings for dual-channel.
652 * We haven't figured out how to reliably set up different
653 * single/dual channel state, if we even can.
79e53945 654 */
1974cad0 655 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 656 clock.p2 = limit->p2.p2_fast;
657 else
658 clock.p2 = limit->p2.p2_slow;
659 } else {
660 if (target < limit->p2.dot_limit)
661 clock.p2 = limit->p2.p2_slow;
662 else
663 clock.p2 = limit->p2.p2_fast;
664 }
665
0206e353 666 memset(best_clock, 0, sizeof(*best_clock));
79e53945 667
42158660
ZY		 668 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
669 clock.m1++) {
670 for (clock.m2 = limit->m2.min;
671 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 672 if (clock.m2 >= clock.m1)
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
ac58c3f0
SV		 680 i9xx_clock(refclk, &clock);
681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
683 continue;
684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
701static bool
a93e255f
ACO		 702pnv_find_best_dpll(const intel_limit_t *limit,
703 struct intel_crtc_state *crtc_state,
ee9300bb
SV		 704 int target, int refclk, intel_clock_t *match_clock,
705 intel_clock_t *best_clock)
79e53945 706{
a93e255f 707 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 708 struct drm_device *dev = crtc->base.dev;
79e53945 709 intel_clock_t clock;
79e53945
JB		 710 int err = target;
711
a93e255f 712 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 713 /*
a210b028
SV		 714 * For LVDS just rely on its current settings for dual-channel.
715 * We haven't figured out how to reliably set up different
716 * single/dual channel state, if we even can.
79e53945 717 */
1974cad0 718 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 719 clock.p2 = limit->p2.p2_fast;
720 else
721 clock.p2 = limit->p2.p2_slow;
722 } else {
723 if (target < limit->p2.dot_limit)
724 clock.p2 = limit->p2.p2_slow;
725 else
726 clock.p2 = limit->p2.p2_fast;
727 }
728
0206e353 729 memset(best_clock, 0, sizeof(*best_clock));
79e53945 730
42158660
ZY		 731 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
732 clock.m1++) {
733 for (clock.m2 = limit->m2.min;
734 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 735 for (clock.n = limit->n.min;
736 clock.n <= limit->n.max; clock.n++) {
737 for (clock.p1 = limit->p1.min;
738 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 739 int this_err;
740
ac58c3f0 741 pineview_clock(refclk, &clock);
1b894b59
CW		 742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
79e53945 744 continue;
cec2f356
SP		 745 if (match_clock &&
746 clock.p != match_clock->p)
747 continue;
79e53945
JB		 748
749 this_err = abs(clock.dot - target);
750 if (this_err < err) {
751 *best_clock = clock;
752 err = this_err;
753 }
754 }
755 }
756 }
757 }
758
759 return (err != target);
760}
761
d4906093 762static bool
a93e255f
ACO		 763g4x_find_best_dpll(const intel_limit_t *limit,
764 struct intel_crtc_state *crtc_state,
ee9300bb
SV		 765 int target, int refclk, intel_clock_t *match_clock,
766 intel_clock_t *best_clock)
d4906093 767{
a93e255f 768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 769 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 770 intel_clock_t clock;
771 int max_n;
772 bool found;
6ba770dc
AJ		 773 /* approximately equals target * 0.00585 */
774 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 775 found = false;
776
a93e255f 777 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 778 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 779 clock.p2 = limit->p2.p2_fast;
780 else
781 clock.p2 = limit->p2.p2_slow;
782 } else {
783 if (target < limit->p2.dot_limit)
784 clock.p2 = limit->p2.p2_slow;
785 else
786 clock.p2 = limit->p2.p2_fast;
787 }
788
789 memset(best_clock, 0, sizeof(*best_clock));
790 max_n = limit->n.max;
f77f13e2 791 /* based on hardware requirement, prefer smaller n to precision */
d4906093 792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 793 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 794 for (clock.m1 = limit->m1.max;
795 clock.m1 >= limit->m1.min; clock.m1--) {
796 for (clock.m2 = limit->m2.max;
797 clock.m2 >= limit->m2.min; clock.m2--) {
798 for (clock.p1 = limit->p1.max;
799 clock.p1 >= limit->p1.min; clock.p1--) {
800 int this_err;
801
ac58c3f0 802 i9xx_clock(refclk, &clock);
1b894b59
CW		 803 if (!intel_PLL_is_valid(dev, limit,
804 &clock))
d4906093 805 continue;
1b894b59
CW		 806
807 this_err = abs(clock.dot - target);
d4906093
ML		 808 if (this_err < err_most) {
809 *best_clock = clock;
810 err_most = this_err;
811 max_n = clock.n;
812 found = true;
813 }
814 }
815 }
816 }
817 }
2c07245f
ZW		 818 return found;
819}
820
d5dd62bd
ID		 821/*
822 * Check if the calculated PLL configuration is more optimal compared to the
823 * best configuration and error found so far. Return the calculated error.
824 */
825static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
826 const intel_clock_t *calculated_clock,
827 const intel_clock_t *best_clock,
828 unsigned int best_error_ppm,
829 unsigned int *error_ppm)
830{
9ca3ba01
ID		 831 /*
832 * For CHV ignore the error and consider only the P value.
833 * Prefer a bigger P value based on HW requirements.
834 */
835 if (IS_CHERRYVIEW(dev)) {
836 *error_ppm = 0;
837
838 return calculated_clock->p > best_clock->p;
839 }
840
24be4e46
ID		 841 if (WARN_ON_ONCE(!target_freq))
842 return false;
843
d5dd62bd
ID		 844 *error_ppm = div_u64(1000000ULL *
845 abs(target_freq - calculated_clock->dot),
846 target_freq);
847 /*
848 * Prefer a better P value over a better (smaller) error if the error
849 * is small. Ensure this preference for future configurations too by
850 * setting the error to 0.
851 */
852 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
853 *error_ppm = 0;
854
855 return true;
856 }
857
858 return *error_ppm + 10 < best_error_ppm;
859}
860
a0c4da24 861static bool
a93e255f
ACO		 862vlv_find_best_dpll(const intel_limit_t *limit,
863 struct intel_crtc_state *crtc_state,
ee9300bb
SV		 864 int target, int refclk, intel_clock_t *match_clock,
865 intel_clock_t *best_clock)
a0c4da24 866{
a93e255f 867 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 868 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 869 intel_clock_t clock;
69e4f900 870 unsigned int bestppm = 1000000;
27e639bf
VS		 871 /* min update 19.2 MHz */
872 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 873 bool found = false;
a0c4da24 874
6b4bf1c4
VS		 875 target *= 5; /* fast clock */
876
877 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 878
879 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 880 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 881 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 882 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 883 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 884 clock.p = clock.p1 * clock.p2;
a0c4da24 885 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 886 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 887 unsigned int ppm;
69e4f900 888
6b4bf1c4
VS		 889 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
890 refclk * clock.m1);
891
892 vlv_clock(refclk, &clock);
43b0ac53 893
f01b7962
VS		 894 if (!intel_PLL_is_valid(dev, limit,
895 &clock))
43b0ac53
VS		 896 continue;
897
d5dd62bd
ID		 898 if (!vlv_PLL_is_optimal(dev, target,
899 &clock,
900 best_clock,
901 bestppm, &ppm))
902 continue;
6b4bf1c4 903
d5dd62bd
ID		 904 *best_clock = clock;
905 bestppm = ppm;
906 found = true;
a0c4da24
JB		 907 }
908 }
909 }
910 }
a0c4da24 911
49e497ef 912 return found;
a0c4da24 913}
a4fc5ed6 914
ef9348c8 915static bool
a93e255f
ACO		 916chv_find_best_dpll(const intel_limit_t *limit,
917 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 918 int target, int refclk, intel_clock_t *match_clock,
919 intel_clock_t *best_clock)
920{
a93e255f 921 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 922 struct drm_device *dev = crtc->base.dev;
9ca3ba01 923 unsigned int best_error_ppm;
ef9348c8
CML		 924 intel_clock_t clock;
925 uint64_t m2;
926 int found = false;
927
928 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 929 best_error_ppm = 1000000;
ef9348c8
CML		 930
931 /*
932 * Based on hardware doc, the n always set to 1, and m1 always
933 * set to 2. If requires to support 200Mhz refclk, we need to
934 * revisit this because n may not 1 anymore.
935 */
936 clock.n = 1, clock.m1 = 2;
937 target *= 5; /* fast clock */
938
939 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
940 for (clock.p2 = limit->p2.p2_fast;
941 clock.p2 >= limit->p2.p2_slow;
942 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 943 unsigned int error_ppm;
ef9348c8
CML		 944
945 clock.p = clock.p1 * clock.p2;
946
947 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
948 clock.n) << 22, refclk * clock.m1);
949
950 if (m2 > INT_MAX/clock.m1)
951 continue;
952
953 clock.m2 = m2;
954
955 chv_clock(refclk, &clock);
956
957 if (!intel_PLL_is_valid(dev, limit, &clock))
958 continue;
959
9ca3ba01
ID		 960 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
961 best_error_ppm, &error_ppm))
962 continue;
963
964 *best_clock = clock;
965 best_error_ppm = error_ppm;
966 found = true;
ef9348c8
CML		 967 }
968 }
969
970 return found;
971}
972
5ab7b0b7
ID		 973bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
974 intel_clock_t *best_clock)
975{
976 int refclk = i9xx_get_refclk(crtc_state, 0);
977
978 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
979 target_clock, refclk, NULL, best_clock);
980}
981
20ddf665
VS		 982bool intel_crtc_active(struct drm_crtc *crtc)
983{
984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
985
986 /* Be paranoid as we can arrive here with only partial
987 * state retrieved from the hardware during setup.
988 *
241bfc38 989 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 990 * as Haswell has gained clock readout/fastboot support.
991 *
66e514c1 992 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 993 * properly reconstruct framebuffers.
c3d1f436
MR		 994 *
995 * FIXME: The intel_crtc->active here should be switched to
996 * crtc->state->active once we have proper CRTC states wired up
997 * for atomic.
20ddf665 998 */
c3d1f436 999 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1000 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1001}
1002
a5c961d1
PZ		 1003enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1004 enum pipe pipe)
1005{
1006 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1008
6e3c9717 1009 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1010}
1011
fbf49ea2
VS		 1012static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1013{
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 u32 reg = PIPEDSL(pipe);
1016 u32 line1, line2;
1017 u32 line_mask;
1018
1019 if (IS_GEN2(dev))
1020 line_mask = DSL_LINEMASK_GEN2;
1021 else
1022 line_mask = DSL_LINEMASK_GEN3;
1023
1024 line1 = I915_READ(reg) & line_mask;
1025 mdelay(5);
1026 line2 = I915_READ(reg) & line_mask;
1027
1028 return line1 == line2;
1029}
1030
ab7ad7f6
KP		 1031/*
1032 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1033 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1034 *
1035 * After disabling a pipe, we can't wait for vblank in the usual way,
1036 * spinning on the vblank interrupt status bit, since we won't actually
1037 * see an interrupt when the pipe is disabled.
1038 *
ab7ad7f6
KP		 1039 * On Gen4 and above:
1040 * wait for the pipe register state bit to turn off
1041 *
1042 * Otherwise:
1043 * wait for the display line value to settle (it usually
1044 * ends up stopping at the start of the next frame).
58e10eb9 1045 *
9d0498a2 1046 */
575f7ab7 1047static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1048{
575f7ab7 1049 struct drm_device *dev = crtc->base.dev;
9d0498a2 1050 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1051 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1052 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1053
1054 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1055 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1056
1057 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1058 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1059 100))
284637d9 1060 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1061 } else {
ab7ad7f6 1062 /* Wait for the display line to settle */
fbf49ea2 1063 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1064 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1065 }
79e53945
JB		 1066}
1067
b0ea7d37
DL		 1068/*
1069 * ibx_digital_port_connected - is the specified port connected?
1070 * @dev_priv: i915 private structure
1071 * @port: the port to test
1072 *
1073 * Returns true if @port is connected, false otherwise.
1074 */
1075bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1076 struct intel_digital_port *port)
1077{
1078 u32 bit;
1079
c36346e3 1080 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1081 switch (port->port) {
c36346e3
DL		 1082 case PORT_B:
1083 bit = SDE_PORTB_HOTPLUG;
1084 break;
1085 case PORT_C:
1086 bit = SDE_PORTC_HOTPLUG;
1087 break;
1088 case PORT_D:
1089 bit = SDE_PORTD_HOTPLUG;
1090 break;
1091 default:
1092 return true;
1093 }
1094 } else {
eba905b2 1095 switch (port->port) {
c36346e3
DL		 1096 case PORT_B:
1097 bit = SDE_PORTB_HOTPLUG_CPT;
1098 break;
1099 case PORT_C:
1100 bit = SDE_PORTC_HOTPLUG_CPT;
1101 break;
1102 case PORT_D:
1103 bit = SDE_PORTD_HOTPLUG_CPT;
1104 break;
1105 default:
1106 return true;
1107 }
b0ea7d37
DL		 1108 }
1109
1110 return I915_READ(SDEISR) & bit;
1111}
1112
b24e7179
JB		 1113static const char *state_string(bool enabled)
1114{
1115 return enabled ? "on" : "off";
1116}
1117
1118/* Only for pre-ILK configs */
55607e8a
SV		 1119void assert_pll(struct drm_i915_private *dev_priv,
1120 enum pipe pipe, bool state)
b24e7179
JB		 1121{
1122 int reg;
1123 u32 val;
1124 bool cur_state;
1125
1126 reg = DPLL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1129 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1130 "PLL state assertion failure (expected %s, current %s)\n",
1131 state_string(state), state_string(cur_state));
1132}
b24e7179 1133
23538ef1
JN		 1134/* XXX: the dsi pll is shared between MIPI DSI ports */
1135static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1136{
1137 u32 val;
1138 bool cur_state;
1139
1140 mutex_lock(&dev_priv->dpio_lock);
1141 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1142 mutex_unlock(&dev_priv->dpio_lock);
1143
1144 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1145 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1146 "DSI PLL state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1148}
1149#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1150#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1151
55607e8a 1152struct intel_shared_dpll *
e2b78267
SV		 1153intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1154{
1155 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1156
6e3c9717 1157 if (crtc->config->shared_dpll < 0)
e2b78267
SV		 1158 return NULL;
1159
6e3c9717 1160 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
SV		 1161}
1162
040484af 1163/* For ILK+ */
55607e8a
SV		 1164void assert_shared_dpll(struct drm_i915_private *dev_priv,
1165 struct intel_shared_dpll *pll,
1166 bool state)
040484af 1167{
040484af 1168 bool cur_state;
5358901f 1169 struct intel_dpll_hw_state hw_state;
040484af 1170
92b27b08 1171 if (WARN (!pll,
46edb027 1172 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1173 return;
ee7b9f93 1174
5358901f 1175 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1176 I915_STATE_WARN(cur_state != state,
5358901f
SV		 1177 "%s assertion failure (expected %s, current %s)\n",
1178 pll->name, state_string(state), state_string(cur_state));
040484af 1179}
040484af
JB		 1180
1181static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1183{
1184 int reg;
1185 u32 val;
1186 bool cur_state;
ad80a810
PZ		 1187 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1188 pipe);
040484af 1189
affa9354
PZ		 1190 if (HAS_DDI(dev_priv->dev)) {
1191 /* DDI does not have a specific FDI_TX register */
ad80a810 1192 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1193 val = I915_READ(reg);
ad80a810 1194 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1195 } else {
1196 reg = FDI_TX_CTL(pipe);
1197 val = I915_READ(reg);
1198 cur_state = !!(val & FDI_TX_ENABLE);
1199 }
e2c719b7 1200 I915_STATE_WARN(cur_state != state,
040484af
JB		 1201 "FDI TX state assertion failure (expected %s, current %s)\n",
1202 state_string(state), state_string(cur_state));
1203}
1204#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1205#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1206
1207static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1208 enum pipe pipe, bool state)
1209{
1210 int reg;
1211 u32 val;
1212 bool cur_state;
1213
d63fa0dc
PZ		 1214 reg = FDI_RX_CTL(pipe);
1215 val = I915_READ(reg);
1216 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1217 I915_STATE_WARN(cur_state != state,
040484af
JB		 1218 "FDI RX state assertion failure (expected %s, current %s)\n",
1219 state_string(state), state_string(cur_state));
1220}
1221#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1222#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1223
1224static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe)
1226{
1227 int reg;
1228 u32 val;
1229
1230 /* ILK FDI PLL is always enabled */
3d13ef2e 1231 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1232 return;
1233
bf507ef7 1234 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1235 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1236 return;
1237
040484af
JB		 1238 reg = FDI_TX_CTL(pipe);
1239 val = I915_READ(reg);
e2c719b7 1240 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1241}
1242
55607e8a
SV		 1243void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1244 enum pipe pipe, bool state)
040484af
JB		 1245{
1246 int reg;
1247 u32 val;
55607e8a 1248 bool cur_state;
040484af
JB		 1249
1250 reg = FDI_RX_CTL(pipe);
1251 val = I915_READ(reg);
55607e8a 1252 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1253 I915_STATE_WARN(cur_state != state,
55607e8a
SV		 1254 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1255 state_string(state), state_string(cur_state));
040484af
JB		 1256}
1257
b680c37a
SV		 1258void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1259 enum pipe pipe)
ea0760cf 1260{
bedd4dba
JN		 1261 struct drm_device *dev = dev_priv->dev;
1262 int pp_reg;
ea0760cf
JB		 1263 u32 val;
1264 enum pipe panel_pipe = PIPE_A;
0de3b485 1265 bool locked = true;
ea0760cf 1266
bedd4dba
JN		 1267 if (WARN_ON(HAS_DDI(dev)))
1268 return;
1269
1270 if (HAS_PCH_SPLIT(dev)) {
1271 u32 port_sel;
1272
ea0760cf 1273 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1274 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1275
1276 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1277 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1278 panel_pipe = PIPE_B;
1279 /* XXX: else fix for eDP */
1280 } else if (IS_VALLEYVIEW(dev)) {
1281 /* presumably write lock depends on pipe, not port select */
1282 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1283 panel_pipe = pipe;
ea0760cf
JB		 1284 } else {
1285 pp_reg = PP_CONTROL;
bedd4dba
JN		 1286 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1287 panel_pipe = PIPE_B;
ea0760cf
JB		 1288 }
1289
1290 val = I915_READ(pp_reg);
1291 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1292 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1293 locked = false;
1294
e2c719b7 1295 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1296 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1297 pipe_name(pipe));
ea0760cf
JB		 1298}
1299
93ce0ba6
JN		 1300static void assert_cursor(struct drm_i915_private *dev_priv,
1301 enum pipe pipe, bool state)
1302{
1303 struct drm_device *dev = dev_priv->dev;
1304 bool cur_state;
1305
d9d82081 1306 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1307 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1308 else
5efb3e28 1309 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1310
e2c719b7 1311 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1312 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1313 pipe_name(pipe), state_string(state), state_string(cur_state));
1314}
1315#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1316#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1317
b840d907
JB		 1318void assert_pipe(struct drm_i915_private *dev_priv,
1319 enum pipe pipe, bool state)
b24e7179
JB		 1320{
1321 int reg;
1322 u32 val;
63d7bbe9 1323 bool cur_state;
702e7a56
PZ		 1324 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1325 pipe);
b24e7179 1326
b6b5d049
VS		 1327 /* if we need the pipe quirk it must be always on */
1328 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1329 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
SV		 1330 state = true;
1331
f458ebbc 1332 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1333 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1334 cur_state = false;
1335 } else {
1336 reg = PIPECONF(cpu_transcoder);
1337 val = I915_READ(reg);
1338 cur_state = !!(val & PIPECONF_ENABLE);
1339 }
1340
e2c719b7 1341 I915_STATE_WARN(cur_state != state,
63d7bbe9 1342 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1343 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1344}
1345
931872fc
CW		 1346static void assert_plane(struct drm_i915_private *dev_priv,
1347 enum plane plane, bool state)
b24e7179
JB		 1348{
1349 int reg;
1350 u32 val;
931872fc 1351 bool cur_state;
b24e7179
JB		 1352
1353 reg = DSPCNTR(plane);
1354 val = I915_READ(reg);
931872fc 1355 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1356 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1357 "plane %c assertion failure (expected %s, current %s)\n",
1358 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1359}
1360
931872fc
CW		 1361#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1362#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1363
b24e7179
JB		 1364static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe)
1366{
653e1026 1367 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1368 int reg, i;
1369 u32 val;
1370 int cur_pipe;
1371
653e1026
VS		 1372 /* Primary planes are fixed to pipes on gen4+ */
1373 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1374 reg = DSPCNTR(pipe);
1375 val = I915_READ(reg);
e2c719b7 1376 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1377 "plane %c assertion failure, should be disabled but not\n",
1378 plane_name(pipe));
19ec1358 1379 return;
28c05794 1380 }
19ec1358 1381
b24e7179 1382 /* Need to check both planes against the pipe */
055e393f 1383 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1384 reg = DSPCNTR(i);
1385 val = I915_READ(reg);
1386 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1387 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1388 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1389 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1390 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1391 }
1392}
1393
19332d7a
JB		 1394static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
20674eef 1397 struct drm_device *dev = dev_priv->dev;
1fe47785 1398 int reg, sprite;
19332d7a
JB		 1399 u32 val;
1400
7feb8b88 1401 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1402 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1403 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1404 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1405 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1406 sprite, pipe_name(pipe));
1407 }
1408 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1409 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1410 reg = SPCNTR(pipe, sprite);
20674eef 1411 val = I915_READ(reg);
e2c719b7 1412 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1413 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1414 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1415 }
1416 } else if (INTEL_INFO(dev)->gen >= 7) {
1417 reg = SPRCTL(pipe);
19332d7a 1418 val = I915_READ(reg);
e2c719b7 1419 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1420 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1421 plane_name(pipe), pipe_name(pipe));
1422 } else if (INTEL_INFO(dev)->gen >= 5) {
1423 reg = DVSCNTR(pipe);
19332d7a 1424 val = I915_READ(reg);
e2c719b7 1425 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1426 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1427 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1428 }
1429}
1430
08c71e5e
VS		 1431static void assert_vblank_disabled(struct drm_crtc *crtc)
1432{
e2c719b7 1433 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1434 drm_crtc_vblank_put(crtc);
1435}
1436
89eff4be 1437static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1438{
1439 u32 val;
1440 bool enabled;
1441
e2c719b7 1442 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1443
92f2584a
JB		 1444 val = I915_READ(PCH_DREF_CONTROL);
1445 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1446 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1447 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1448}
1449
ab9412ba
SV		 1450static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe)
92f2584a
JB		 1452{
1453 int reg;
1454 u32 val;
1455 bool enabled;
1456
ab9412ba 1457 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1458 val = I915_READ(reg);
1459 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1460 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1461 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1462 pipe_name(pipe));
92f2584a
JB		 1463}
1464
4e634389
KP		 1465static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1466 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1467{
1468 if ((val & DP_PORT_EN) == 0)
1469 return false;
1470
1471 if (HAS_PCH_CPT(dev_priv->dev)) {
1472 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1473 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1474 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1475 return false;
44f37d1f
CML		 1476 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1477 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1478 return false;
f0575e92
KP		 1479 } else {
1480 if ((val & DP_PIPE_MASK) != (pipe << 30))
1481 return false;
1482 }
1483 return true;
1484}
1485
1519b995
KP		 1486static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, u32 val)
1488{
dc0fa718 1489 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1490 return false;
1491
1492 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1493 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1494 return false;
44f37d1f
CML		 1495 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1496 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1497 return false;
1519b995 1498 } else {
dc0fa718 1499 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1500 return false;
1501 }
1502 return true;
1503}
1504
1505static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1506 enum pipe pipe, u32 val)
1507{
1508 if ((val & LVDS_PORT_EN) == 0)
1509 return false;
1510
1511 if (HAS_PCH_CPT(dev_priv->dev)) {
1512 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1513 return false;
1514 } else {
1515 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1516 return false;
1517 }
1518 return true;
1519}
1520
1521static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1522 enum pipe pipe, u32 val)
1523{
1524 if ((val & ADPA_DAC_ENABLE) == 0)
1525 return false;
1526 if (HAS_PCH_CPT(dev_priv->dev)) {
1527 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1528 return false;
1529 } else {
1530 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1531 return false;
1532 }
1533 return true;
1534}
1535
291906f1 1536static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1537 enum pipe pipe, int reg, u32 port_sel)
291906f1 1538{
47a05eca 1539 u32 val = I915_READ(reg);
e2c719b7 1540 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1541 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1542 reg, pipe_name(pipe));
de9a35ab 1543
e2c719b7 1544 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1545 && (val & DP_PIPEB_SELECT),
de9a35ab 1546 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1547}
1548
1549static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1550 enum pipe pipe, int reg)
1551{
47a05eca 1552 u32 val = I915_READ(reg);
e2c719b7 1553 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1554 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1555 reg, pipe_name(pipe));
de9a35ab 1556
e2c719b7 1557 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1558 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1559 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1560}
1561
1562static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1563 enum pipe pipe)
1564{
1565 int reg;
1566 u32 val;
291906f1 1567
f0575e92
KP		 1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1570 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1571
1572 reg = PCH_ADPA;
1573 val = I915_READ(reg);
e2c719b7 1574 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1575 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1576 pipe_name(pipe));
291906f1
JB		 1577
1578 reg = PCH_LVDS;
1579 val = I915_READ(reg);
e2c719b7 1580 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1581 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1582 pipe_name(pipe));
291906f1 1583
e2debe91
PZ		 1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1586 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1587}
1588
40e9cf64
JB		 1589static void intel_init_dpio(struct drm_device *dev)
1590{
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592
1593 if (!IS_VALLEYVIEW(dev))
1594 return;
1595
a09caddd
CML		 1596 /*
1597 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1598 * CHV x1 PHY (DP/HDMI D)
1599 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1600 */
1601 if (IS_CHERRYVIEW(dev)) {
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1604 } else {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1606 }
5382f5f3
JB		 1607}
1608
d288f65f 1609static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1610 const struct intel_crtc_state *pipe_config)
87442f73 1611{
426115cf
SV		 1612 struct drm_device *dev = crtc->base.dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 int reg = DPLL(crtc->pipe);
d288f65f 1615 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1616
426115cf 1617 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
SV		 1618
1619 /* No really, not for ILK+ */
1620 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1621
1622 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1623 if (IS_MOBILE(dev_priv->dev))
426115cf 1624 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1625
426115cf
SV		 1626 I915_WRITE(reg, dpll);
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1631 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1632
d288f65f 1633 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1634 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
SV		 1635
1636 /* We do this three times for luck */
426115cf 1637 I915_WRITE(reg, dpll);
87442f73
SV		 1638 POSTING_READ(reg);
1639 udelay(150); /* wait for warmup */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
SV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
SV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646}
1647
d288f65f 1648static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1649 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1650{
1651 struct drm_device *dev = crtc->base.dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 int pipe = crtc->pipe;
1654 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1655 u32 tmp;
1656
1657 assert_pipe_disabled(dev_priv, crtc->pipe);
1658
1659 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1660
1661 mutex_lock(&dev_priv->dpio_lock);
1662
1663 /* Enable back the 10bit clock to display controller */
1664 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1665 tmp |= DPIO_DCLKP_EN;
1666 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1667
1668 /*
1669 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1670 */
1671 udelay(1);
1672
1673 /* Enable PLL */
d288f65f 1674 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1675
1676 /* Check PLL is locked */
a11b0703 1677 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1678 DRM_ERROR("PLL %d failed to lock\n", pipe);
1679
a11b0703 1680 /* not sure when this should be written */
d288f65f 1681 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1682 POSTING_READ(DPLL_MD(pipe));
1683
9d556c99
CML		 1684 mutex_unlock(&dev_priv->dpio_lock);
1685}
1686
1c4e0274
VS		 1687static int intel_num_dvo_pipes(struct drm_device *dev)
1688{
1689 struct intel_crtc *crtc;
1690 int count = 0;
1691
1692 for_each_intel_crtc(dev, crtc)
1693 count += crtc->active &&
409ee761 1694 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1695
1696 return count;
1697}
1698
66e3d5c0 1699static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1700{
66e3d5c0
SV		 1701 struct drm_device *dev = crtc->base.dev;
1702 struct drm_i915_private *dev_priv = dev->dev_private;
1703 int reg = DPLL(crtc->pipe);
6e3c9717 1704 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1705
66e3d5c0 1706 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1707
63d7bbe9 1708 /* No really, not for ILK+ */
3d13ef2e 1709 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1710
1711 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
SV		 1712 if (IS_MOBILE(dev) && !IS_I830(dev))
1713 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1714
1c4e0274
VS		 1715 /* Enable DVO 2x clock on both PLLs if necessary */
1716 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1717 /*
1718 * It appears to be important that we don't enable this
1719 * for the current pipe before otherwise configuring the
1720 * PLL. No idea how this should be handled if multiple
1721 * DVO outputs are enabled simultaneosly.
1722 */
1723 dpll |= DPLL_DVO_2X_MODE;
1724 I915_WRITE(DPLL(!crtc->pipe),
1725 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1726 }
66e3d5c0
SV		 1727
1728 /* Wait for the clocks to stabilize. */
1729 POSTING_READ(reg);
1730 udelay(150);
1731
1732 if (INTEL_INFO(dev)->gen >= 4) {
1733 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1734 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
SV		 1735 } else {
1736 /* The pixel multiplier can only be updated once the
1737 * DPLL is enabled and the clocks are stable.
1738 *
1739 * So write it again.
1740 */
1741 I915_WRITE(reg, dpll);
1742 }
63d7bbe9
JB		 1743
1744 /* We do this three times for luck */
66e3d5c0 1745 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1746 POSTING_READ(reg);
1747 udelay(150); /* wait for warmup */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
1754}
1755
1756/**
50b44a44 1757 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1758 * @dev_priv: i915 private structure
1759 * @pipe: pipe PLL to disable
1760 *
1761 * Disable the PLL for @pipe, making sure the pipe is off first.
1762 *
1763 * Note! This is for pre-ILK only.
1764 */
1c4e0274 1765static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1766{
1c4e0274
VS		 1767 struct drm_device *dev = crtc->base.dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 enum pipe pipe = crtc->pipe;
1770
1771 /* Disable DVO 2x clock on both PLLs if necessary */
1772 if (IS_I830(dev) &&
409ee761 1773 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1774 intel_num_dvo_pipes(dev) == 1) {
1775 I915_WRITE(DPLL(PIPE_B),
1776 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1777 I915_WRITE(DPLL(PIPE_A),
1778 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1779 }
1780
b6b5d049
VS		 1781 /* Don't disable pipe or pipe PLLs if needed */
1782 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1783 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1784 return;
1785
1786 /* Make sure the pipe isn't still relying on us */
1787 assert_pipe_disabled(dev_priv, pipe);
1788
50b44a44
SV		 1789 I915_WRITE(DPLL(pipe), 0);
1790 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1791}
1792
f6071166
JB		 1793static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1794{
1795 u32 val = 0;
1796
1797 /* Make sure the pipe isn't still relying on us */
1798 assert_pipe_disabled(dev_priv, pipe);
1799
e5cbfbfb
ID		 1800 /*
1801 * Leave integrated clock source and reference clock enabled for pipe B.
1802 * The latter is needed for VGA hotplug / manual detection.
1803 */
f6071166 1804 if (pipe == PIPE_B)
e5cbfbfb 1805 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1806 I915_WRITE(DPLL(pipe), val);
1807 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1808
1809}
1810
1811static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1812{
d752048d 1813 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1814 u32 val;
1815
a11b0703
VS		 1816 /* Make sure the pipe isn't still relying on us */
1817 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1818
a11b0703 1819 /* Set PLL en = 0 */
d17ec4ce 1820 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1821 if (pipe != PIPE_A)
1822 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1823 I915_WRITE(DPLL(pipe), val);
1824 POSTING_READ(DPLL(pipe));
d752048d
VS		 1825
1826 mutex_lock(&dev_priv->dpio_lock);
1827
1828 /* Disable 10bit clock to display controller */
1829 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1830 val &= ~DPIO_DCLKP_EN;
1831 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1832
61407f6d
VS		 1833 /* disable left/right clock distribution */
1834 if (pipe != PIPE_B) {
1835 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1836 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1837 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1838 } else {
1839 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1840 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1841 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1842 }
1843
d752048d 1844 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1845}
1846
e4607fcf
CML		 1847void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1848 struct intel_digital_port *dport)
89b667f8
JB		 1849{
1850 u32 port_mask;
00fc31b7 1851 int dpll_reg;
89b667f8 1852
e4607fcf
CML		 1853 switch (dport->port) {
1854 case PORT_B:
89b667f8 1855 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1856 dpll_reg = DPLL(0);
e4607fcf
CML		 1857 break;
1858 case PORT_C:
89b667f8 1859 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1860 dpll_reg = DPLL(0);
1861 break;
1862 case PORT_D:
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1865 break;
1866 default:
1867 BUG();
1868 }
89b667f8 1869
00fc31b7 1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1871 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1872 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1873}
1874
b14b1055
SV		 1875static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876{
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
be19f0ff
CW		 1881 if (WARN_ON(pll == NULL))
1882 return;
1883
3e369b76 1884 WARN_ON(!pll->config.crtc_mask);
b14b1055
SV		 1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887 WARN_ON(pll->on);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890 pll->mode_set(dev_priv, pll);
1891 }
1892}
1893
92f2584a 1894/**
85b3894f 1895 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1898 *
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1901 */
85b3894f 1902static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1903{
3d13ef2e
DL		 1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1907
87a875bb 1908 if (WARN_ON(pll == NULL))
48da64a8
CW		 1909 return;
1910
3e369b76 1911 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1912 return;
ee7b9f93 1913
74dd6928 1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1915 pll->name, pll->active, pll->on,
e2b78267 1916 crtc->base.base.id);
92f2584a 1917
cdbd2316
SV		 1918 if (pll->active++) {
1919 WARN_ON(!pll->on);
e9d6944e 1920 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1921 return;
1922 }
f4a091c7 1923 WARN_ON(pll->on);
ee7b9f93 1924
bd2bb1b9
PZ		 1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
46edb027 1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1928 pll->enable(dev_priv, pll);
ee7b9f93 1929 pll->on = true;
92f2584a
JB		 1930}
1931
f6daaec2 1932static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1933{
3d13ef2e
DL		 1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1937
92f2584a 1938 /* PCH only available on ILK+ */
3d13ef2e 1939 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1940 if (WARN_ON(pll == NULL))
ee7b9f93 1941 return;
92f2584a 1942
3e369b76 1943 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1944 return;
7a419866 1945
46edb027
SV		 1946 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947 pll->name, pll->active, pll->on,
e2b78267 1948 crtc->base.base.id);
7a419866 1949
48da64a8 1950 if (WARN_ON(pll->active == 0)) {
e9d6944e 1951 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1952 return;
1953 }
1954
e9d6944e 1955 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1956 WARN_ON(!pll->on);
cdbd2316 1957 if (--pll->active)
7a419866 1958 return;
ee7b9f93 1959
46edb027 1960 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1961 pll->disable(dev_priv, pll);
ee7b9f93 1962 pll->on = false;
bd2bb1b9
PZ		 1963
1964 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1965}
1966
b8a4f404
PZ		 1967static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1968 enum pipe pipe)
040484af 1969{
23670b32 1970 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1971 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1973 uint32_t reg, val, pipeconf_val;
040484af
JB		 1974
1975 /* PCH only available on ILK+ */
55522f37 1976 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1977
1978 /* Make sure PCH DPLL is enabled */
e72f9fbf 1979 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1980 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1981
1982 /* FDI must be feeding us bits for PCH ports */
1983 assert_fdi_tx_enabled(dev_priv, pipe);
1984 assert_fdi_rx_enabled(dev_priv, pipe);
1985
23670b32
SV		 1986 if (HAS_PCH_CPT(dev)) {
1987 /* Workaround: Set the timing override bit before enabling the
1988 * pch transcoder. */
1989 reg = TRANS_CHICKEN2(pipe);
1990 val = I915_READ(reg);
1991 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1992 I915_WRITE(reg, val);
59c859d6 1993 }
23670b32 1994
ab9412ba 1995 reg = PCH_TRANSCONF(pipe);
040484af 1996 val = I915_READ(reg);
5f7f726d 1997 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1998
1999 if (HAS_PCH_IBX(dev_priv->dev)) {
2000 /*
2001 * make the BPC in transcoder be consistent with
2002 * that in pipeconf reg.
2003 */
dfd07d72
SV		 2004 val &= ~PIPECONF_BPC_MASK;
2005 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2006 }
5f7f726d
PZ		 2007
2008 val &= ~TRANS_INTERLACE_MASK;
2009 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2010 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2011 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2012 val |= TRANS_LEGACY_INTERLACED_ILK;
2013 else
2014 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2015 else
2016 val |= TRANS_PROGRESSIVE;
2017
040484af
JB		 2018 I915_WRITE(reg, val | TRANS_ENABLE);
2019 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2020 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2021}
2022
8fb033d7 2023static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2024 enum transcoder cpu_transcoder)
040484af 2025{
8fb033d7 2026 u32 val, pipeconf_val;
8fb033d7
PZ		 2027
2028 /* PCH only available on ILK+ */
55522f37 2029 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2030
8fb033d7 2031 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2032 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2033 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2034
223a6fdf
PZ		 2035 /* Workaround: set timing override bit. */
2036 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2037 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2038 I915_WRITE(_TRANSA_CHICKEN2, val);
2039
25f3ef11 2040 val = TRANS_ENABLE;
937bb610 2041 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2042
9a76b1c6
PZ		 2043 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2044 PIPECONF_INTERLACED_ILK)
a35f2679 2045 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2046 else
2047 val |= TRANS_PROGRESSIVE;
2048
ab9412ba
SV		 2049 I915_WRITE(LPT_TRANSCONF, val);
2050 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2051 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2052}
2053
b8a4f404
PZ		 2054static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2055 enum pipe pipe)
040484af 2056{
23670b32
SV		 2057 struct drm_device *dev = dev_priv->dev;
2058 uint32_t reg, val;
040484af
JB		 2059
2060 /* FDI relies on the transcoder */
2061 assert_fdi_tx_disabled(dev_priv, pipe);
2062 assert_fdi_rx_disabled(dev_priv, pipe);
2063
291906f1
JB		 2064 /* Ports must be off as well */
2065 assert_pch_ports_disabled(dev_priv, pipe);
2066
ab9412ba 2067 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2068 val = I915_READ(reg);
2069 val &= ~TRANS_ENABLE;
2070 I915_WRITE(reg, val);
2071 /* wait for PCH transcoder off, transcoder state */
2072 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2073 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
SV		 2074
2075 if (!HAS_PCH_IBX(dev)) {
2076 /* Workaround: Clear the timing override chicken bit again. */
2077 reg = TRANS_CHICKEN2(pipe);
2078 val = I915_READ(reg);
2079 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2080 I915_WRITE(reg, val);
2081 }
040484af
JB		 2082}
2083
ab4d966c 2084static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2085{
8fb033d7
PZ		 2086 u32 val;
2087
ab9412ba 2088 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2089 val &= ~TRANS_ENABLE;
ab9412ba 2090 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2091 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2092 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2093 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2094
2095 /* Workaround: clear timing override bit. */
2096 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2097 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2098 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2099}
2100
b24e7179 2101/**
309cfea8 2102 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2103 * @crtc: crtc responsible for the pipe
b24e7179 2104 *
0372264a 2105 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2106 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2107 */
e1fdc473 2108static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2109{
0372264a
PZ		 2110 struct drm_device *dev = crtc->base.dev;
2111 struct drm_i915_private *dev_priv = dev->dev_private;
2112 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2113 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2114 pipe);
1a240d4d 2115 enum pipe pch_transcoder;
b24e7179
JB		 2116 int reg;
2117 u32 val;
2118
58c6eaa2 2119 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2120 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
SV		 2121 assert_sprites_disabled(dev_priv, pipe);
2122
681e5811 2123 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2124 pch_transcoder = TRANSCODER_A;
2125 else
2126 pch_transcoder = pipe;
2127
b24e7179
JB		 2128 /*
2129 * A pipe without a PLL won't actually be able to drive bits from
2130 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2131 * need the check.
2132 */
50360403 2133 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2134 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2135 assert_dsi_pll_enabled(dev_priv);
2136 else
2137 assert_pll_enabled(dev_priv, pipe);
040484af 2138 else {
6e3c9717 2139 if (crtc->config->has_pch_encoder) {
040484af 2140 /* if driving the PCH, we need FDI enabled */
cc391bbb 2141 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
SV		 2142 assert_fdi_tx_pll_enabled(dev_priv,
2143 (enum pipe) cpu_transcoder);
040484af
JB		 2144 }
2145 /* FIXME: assert CPU port conditions for SNB+ */
2146 }
b24e7179 2147
702e7a56 2148 reg = PIPECONF(cpu_transcoder);
b24e7179 2149 val = I915_READ(reg);
7ad25d48 2150 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2151 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2152 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2153 return;
7ad25d48 2154 }
00d70b15
CW		 2155
2156 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2157 POSTING_READ(reg);
b24e7179
JB		 2158}
2159
2160/**
309cfea8 2161 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2162 * @crtc: crtc whose pipes is to be disabled
b24e7179 2163 *
575f7ab7
VS		 2164 * Disable the pipe of @crtc, making sure that various hardware
2165 * specific requirements are met, if applicable, e.g. plane
2166 * disabled, panel fitter off, etc.
b24e7179
JB		 2167 *
2168 * Will wait until the pipe has shut down before returning.
2169 */
575f7ab7 2170static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2171{
575f7ab7 2172 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2173 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2174 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2175 int reg;
2176 u32 val;
2177
2178 /*
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2181 */
2182 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2183 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2184 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2185
702e7a56 2186 reg = PIPECONF(cpu_transcoder);
b24e7179 2187 val = I915_READ(reg);
00d70b15
CW		 2188 if ((val & PIPECONF_ENABLE) == 0)
2189 return;
2190
67adc644
VS		 2191 /*
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2194 */
6e3c9717 2195 if (crtc->config->double_wide)
67adc644
VS		 2196 val &= ~PIPECONF_DOUBLE_WIDE;
2197
2198 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2199 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2200 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2201 val &= ~PIPECONF_ENABLE;
2202
2203 I915_WRITE(reg, val);
2204 if ((val & PIPECONF_ENABLE) == 0)
2205 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2206}
2207
d74362c9
KP		 2208/*
2209 * Plane regs are double buffered, going from enabled->disabled needs a
2210 * trigger in order to latch. The display address reg provides this.
2211 */
1dba99f4
VS		 2212void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2213 enum plane plane)
d74362c9 2214{
3d13ef2e
DL		 2215 struct drm_device *dev = dev_priv->dev;
2216 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2217
2218 I915_WRITE(reg, I915_READ(reg));
2219 POSTING_READ(reg);
d74362c9
KP		 2220}
2221
b24e7179 2222/**
262ca2b0 2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
b24e7179 2226 *
fdd508a6 2227 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2228 */
fdd508a6
VS		 2229static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230 struct drm_crtc *crtc)
b24e7179 2231{
fdd508a6
VS		 2232 struct drm_device *dev = plane->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2235
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2237 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2238 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2239
fdd508a6
VS		 2240 dev_priv->display.update_primary_plane(crtc, plane->fb,
2241 crtc->x, crtc->y);
b24e7179
JB		 2242}
2243
693db184
CW		 2244static bool need_vtd_wa(struct drm_device *dev)
2245{
2246#ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2248 return true;
2249#endif
2250 return false;
2251}
2252
50470bb0 2253unsigned int
6761dd31
TU		 2254intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255 uint64_t fb_format_modifier)
a57ce0b2 2256{
6761dd31
TU		 2257 unsigned int tile_height;
2258 uint32_t pixel_bytes;
a57ce0b2 2259
b5d0e9bf
DL		 2260 switch (fb_format_modifier) {
2261 case DRM_FORMAT_MOD_NONE:
2262 tile_height = 1;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 tile_height = IS_GEN2(dev) ? 16 : 8;
2266 break;
2267 case I915_FORMAT_MOD_Y_TILED:
2268 tile_height = 32;
2269 break;
2270 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2271 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272 switch (pixel_bytes) {
b5d0e9bf 2273 default:
6761dd31 2274 case 1:
b5d0e9bf
DL		 2275 tile_height = 64;
2276 break;
6761dd31
TU		 2277 case 2:
2278 case 4:
b5d0e9bf
DL		 2279 tile_height = 32;
2280 break;
6761dd31 2281 case 8:
b5d0e9bf
DL		 2282 tile_height = 16;
2283 break;
6761dd31 2284 case 16:
b5d0e9bf
DL		 2285 WARN_ONCE(1,
2286 "128-bit pixels are not supported for display!");
2287 tile_height = 16;
2288 break;
2289 }
2290 break;
2291 default:
2292 MISSING_CASE(fb_format_modifier);
2293 tile_height = 1;
2294 break;
2295 }
091df6cb 2296
6761dd31
TU		 2297 return tile_height;
2298}
2299
2300unsigned int
2301intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302 uint32_t pixel_format, uint64_t fb_format_modifier)
2303{
2304 return ALIGN(height, intel_tile_height(dev, pixel_format,
2305 fb_format_modifier));
a57ce0b2
JB		 2306}
2307
f64b98cd
TU		 2308static int
2309intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310 const struct drm_plane_state *plane_state)
2311{
50470bb0 2312 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2313
f64b98cd
TU		 2314 *view = i915_ggtt_view_normal;
2315
50470bb0
TU		 2316 if (!plane_state)
2317 return 0;
2318
121920fa 2319 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2320 return 0;
2321
9abc4648 2322 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2323
2324 info->height = fb->height;
2325 info->pixel_format = fb->pixel_format;
2326 info->pitch = fb->pitches[0];
2327 info->fb_modifier = fb->modifier[0];
2328
f64b98cd
TU		 2329 return 0;
2330}
2331
127bd2ac 2332int
850c4cdc
TU		 2333intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2334 struct drm_framebuffer *fb,
82bc3b2d 2335 const struct drm_plane_state *plane_state,
a4872ba6 2336 struct intel_engine_cs *pipelined)
6b95a207 2337{
850c4cdc 2338 struct drm_device *dev = fb->dev;
ce453d81 2339 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2340 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2341 struct i915_ggtt_view view;
6b95a207
KH		 2342 u32 alignment;
2343 int ret;
2344
ebcdd39e
MR		 2345 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2346
7b911adc
TU		 2347 switch (fb->modifier[0]) {
2348 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2349 if (INTEL_INFO(dev)->gen >= 9)
2350 alignment = 256 * 1024;
2351 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2352 alignment = 128 * 1024;
a6c45cf0 2353 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2354 alignment = 4 * 1024;
2355 else
2356 alignment = 64 * 1024;
6b95a207 2357 break;
7b911adc 2358 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2359 if (INTEL_INFO(dev)->gen >= 9)
2360 alignment = 256 * 1024;
2361 else {
2362 /* pin() will align the object as required by fence */
2363 alignment = 0;
2364 }
6b95a207 2365 break;
7b911adc 2366 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2367 case I915_FORMAT_MOD_Yf_TILED:
2368 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2369 "Y tiling bo slipped through, driver bug!\n"))
2370 return -EINVAL;
2371 alignment = 1 * 1024 * 1024;
2372 break;
6b95a207 2373 default:
7b911adc
TU		 2374 MISSING_CASE(fb->modifier[0]);
2375 return -EINVAL;
6b95a207
KH		 2376 }
2377
f64b98cd
TU		 2378 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2379 if (ret)
2380 return ret;
2381
693db184
CW		 2382 /* Note that the w/a also requires 64 PTE of padding following the
2383 * bo. We currently fill all unused PTE with the shadow page and so
2384 * we should always have valid PTE following the scanout preventing
2385 * the VT-d warning.
2386 */
2387 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2388 alignment = 256 * 1024;
2389
d6dd6843
PZ		 2390 /*
2391 * Global gtt pte registers are special registers which actually forward
2392 * writes to a chunk of system memory. Which means that there is no risk
2393 * that the register values disappear as soon as we call
2394 * intel_runtime_pm_put(), so it is correct to wrap only the
2395 * pin/unpin/fence and not more.
2396 */
2397 intel_runtime_pm_get(dev_priv);
2398
ce453d81 2399 dev_priv->mm.interruptible = false;
e6617330 2400 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2401 &view);
48b956c5 2402 if (ret)
ce453d81 2403 goto err_interruptible;
6b95a207
KH		 2404
2405 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2406 * fence, whereas 965+ only requires a fence if using
2407 * framebuffer compression. For simplicity, we always install
2408 * a fence as the cost is not that onerous.
2409 */
06d98131 2410 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2411 if (ret)
2412 goto err_unpin;
1690e1eb 2413
9a5a53b3 2414 i915_gem_object_pin_fence(obj);
6b95a207 2415
ce453d81 2416 dev_priv->mm.interruptible = true;
d6dd6843 2417 intel_runtime_pm_put(dev_priv);
6b95a207 2418 return 0;
48b956c5
CW		 2419
2420err_unpin:
f64b98cd 2421 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2422err_interruptible:
2423 dev_priv->mm.interruptible = true;
d6dd6843 2424 intel_runtime_pm_put(dev_priv);
48b956c5 2425 return ret;
6b95a207
KH		 2426}
2427
82bc3b2d
TU		 2428static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2429 const struct drm_plane_state *plane_state)
1690e1eb 2430{
82bc3b2d 2431 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2432 struct i915_ggtt_view view;
2433 int ret;
82bc3b2d 2434
ebcdd39e
MR		 2435 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2436
f64b98cd
TU		 2437 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2438 WARN_ONCE(ret, "Couldn't get view from plane state!");
2439
1690e1eb 2440 i915_gem_object_unpin_fence(obj);
f64b98cd 2441 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2442}
2443
c2c75131
SV		 2444/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445 * is assumed to be a power-of-two. */
bc752862
CW		 2446unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2447 unsigned int tiling_mode,
2448 unsigned int cpp,
2449 unsigned int pitch)
c2c75131 2450{
bc752862
CW		 2451 if (tiling_mode != I915_TILING_NONE) {
2452 unsigned int tile_rows, tiles;
c2c75131 2453
bc752862
CW		 2454 tile_rows = *y / 8;
2455 *y %= 8;
c2c75131 2456
bc752862
CW		 2457 tiles = *x / (512/cpp);
2458 *x %= 512/cpp;
2459
2460 return tile_rows * pitch * 8 + tiles * 4096;
2461 } else {
2462 unsigned int offset;
2463
2464 offset = *y * pitch + *x * cpp;
2465 *y = 0;
2466 *x = (offset & 4095) / cpp;
2467 return offset & -4096;
2468 }
c2c75131
SV		 2469}
2470
b35d63fa 2471static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2472{
2473 switch (format) {
2474 case DISPPLANE_8BPP:
2475 return DRM_FORMAT_C8;
2476 case DISPPLANE_BGRX555:
2477 return DRM_FORMAT_XRGB1555;
2478 case DISPPLANE_BGRX565:
2479 return DRM_FORMAT_RGB565;
2480 default:
2481 case DISPPLANE_BGRX888:
2482 return DRM_FORMAT_XRGB8888;
2483 case DISPPLANE_RGBX888:
2484 return DRM_FORMAT_XBGR8888;
2485 case DISPPLANE_BGRX101010:
2486 return DRM_FORMAT_XRGB2101010;
2487 case DISPPLANE_RGBX101010:
2488 return DRM_FORMAT_XBGR2101010;
2489 }
2490}
2491
bc8d7dff
DL		 2492static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2493{
2494 switch (format) {
2495 case PLANE_CTL_FORMAT_RGB_565:
2496 return DRM_FORMAT_RGB565;
2497 default:
2498 case PLANE_CTL_FORMAT_XRGB_8888:
2499 if (rgb_order) {
2500 if (alpha)
2501 return DRM_FORMAT_ABGR8888;
2502 else
2503 return DRM_FORMAT_XBGR8888;
2504 } else {
2505 if (alpha)
2506 return DRM_FORMAT_ARGB8888;
2507 else
2508 return DRM_FORMAT_XRGB8888;
2509 }
2510 case PLANE_CTL_FORMAT_XRGB_2101010:
2511 if (rgb_order)
2512 return DRM_FORMAT_XBGR2101010;
2513 else
2514 return DRM_FORMAT_XRGB2101010;
2515 }
2516}
2517
5724dbd1 2518static bool
f6936e29
SV		 2519intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2520 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2521{
2522 struct drm_device *dev = crtc->base.dev;
2523 struct drm_i915_gem_object *obj = NULL;
2524 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2525 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
SV		 2526 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2527 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2528 PAGE_SIZE);
2529
2530 size_aligned -= base_aligned;
46f297fb 2531
ff2652ea
CW		 2532 if (plane_config->size == 0)
2533 return false;
2534
f37b5c2b
SV		 2535 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2536 base_aligned,
2537 base_aligned,
2538 size_aligned);
46f297fb 2539 if (!obj)
484b41dd 2540 return false;
46f297fb 2541
49af449b
DL		 2542 obj->tiling_mode = plane_config->tiling;
2543 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2544 obj->stride = fb->pitches[0];
46f297fb 2545
6bf129df
DL		 2546 mode_cmd.pixel_format = fb->pixel_format;
2547 mode_cmd.width = fb->width;
2548 mode_cmd.height = fb->height;
2549 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
SV		 2550 mode_cmd.modifier[0] = fb->modifier[0];
2551 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2552
2553 mutex_lock(&dev->struct_mutex);
6bf129df 2554 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2555 &mode_cmd, obj)) {
46f297fb
JB		 2556 DRM_DEBUG_KMS("intel fb init failed\n");
2557 goto out_unref_obj;
2558 }
46f297fb 2559 mutex_unlock(&dev->struct_mutex);
484b41dd 2560
f6936e29 2561 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2562 return true;
46f297fb
JB		 2563
2564out_unref_obj:
2565 drm_gem_object_unreference(&obj->base);
2566 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2567 return false;
2568}
2569
afd65eb4
MR		 2570/* Update plane->state->fb to match plane->fb after driver-internal updates */
2571static void
2572update_state_fb(struct drm_plane *plane)
2573{
2574 if (plane->fb == plane->state->fb)
2575 return;
2576
2577 if (plane->state->fb)
2578 drm_framebuffer_unreference(plane->state->fb);
2579 plane->state->fb = plane->fb;
2580 if (plane->state->fb)
2581 drm_framebuffer_reference(plane->state->fb);
2582}
2583
5724dbd1 2584static void
f6936e29
SV		 2585intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2586 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2587{
2588 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2589 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2590 struct drm_crtc *c;
2591 struct intel_crtc *i;
2ff8fde1 2592 struct drm_i915_gem_object *obj;
88595ac9
SV		 2593 struct drm_plane *primary = intel_crtc->base.primary;
2594 struct drm_framebuffer *fb;
484b41dd 2595
2d14030b 2596 if (!plane_config->fb)
484b41dd
JB		 2597 return;
2598
f6936e29 2599 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
SV		 2600 fb = &plane_config->fb->base;
2601 goto valid_fb;
f55548b5 2602 }
484b41dd 2603
2d14030b 2604 kfree(plane_config->fb);
484b41dd
JB		 2605
2606 /*
2607 * Failed to alloc the obj, check to see if we should share
2608 * an fb with another CRTC instead
2609 */
70e1e0ec 2610 for_each_crtc(dev, c) {
484b41dd
JB		 2611 i = to_intel_crtc(c);
2612
2613 if (c == &intel_crtc->base)
2614 continue;
2615
2ff8fde1
MR		 2616 if (!i->active)
2617 continue;
2618
88595ac9
SV		 2619 fb = c->primary->fb;
2620 if (!fb)
484b41dd
JB		 2621 continue;
2622
88595ac9 2623 obj = intel_fb_obj(fb);
2ff8fde1 2624 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
SV		 2625 drm_framebuffer_reference(fb);
2626 goto valid_fb;
484b41dd
JB		 2627 }
2628 }
88595ac9
SV		 2629
2630 return;
2631
2632valid_fb:
2633 obj = intel_fb_obj(fb);
2634 if (obj->tiling_mode != I915_TILING_NONE)
2635 dev_priv->preserve_bios_swizzle = true;
2636
2637 primary->fb = fb;
2638 primary->state->crtc = &intel_crtc->base;
2639 primary->crtc = &intel_crtc->base;
2640 update_state_fb(primary);
2641 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2642}
2643
29b9bde6
SV		 2644static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2645 struct drm_framebuffer *fb,
2646 int x, int y)
81255565
JB		 2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2651 struct drm_plane *primary = crtc->primary;
2652 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2653 struct drm_i915_gem_object *obj;
81255565 2654 int plane = intel_crtc->plane;
e506a0c6 2655 unsigned long linear_offset;
81255565 2656 u32 dspcntr;
f45651ba 2657 u32 reg = DSPCNTR(plane);
48404c1e 2658 int pixel_size;
f45651ba 2659
b70709a6 2660 if (!visible || !fb) {
fdd508a6
VS		 2661 I915_WRITE(reg, 0);
2662 if (INTEL_INFO(dev)->gen >= 4)
2663 I915_WRITE(DSPSURF(plane), 0);
2664 else
2665 I915_WRITE(DSPADDR(plane), 0);
2666 POSTING_READ(reg);
2667 return;
2668 }
2669
c9ba6fad
VS		 2670 obj = intel_fb_obj(fb);
2671 if (WARN_ON(obj == NULL))
2672 return;
2673
2674 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2675
f45651ba
VS		 2676 dspcntr = DISPPLANE_GAMMA_ENABLE;
2677
fdd508a6 2678 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2679
2680 if (INTEL_INFO(dev)->gen < 4) {
2681 if (intel_crtc->pipe == PIPE_B)
2682 dspcntr |= DISPPLANE_SEL_PIPE_B;
2683
2684 /* pipesrc and dspsize control the size that is scaled from,
2685 * which should always be the user's requested size.
2686 */
2687 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2688 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2689 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2690 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2691 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2692 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2695 I915_WRITE(PRIMPOS(plane), 0);
2696 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2697 }
81255565 2698
57779d06
VS		 2699 switch (fb->pixel_format) {
2700 case DRM_FORMAT_C8:
81255565
JB		 2701 dspcntr |= DISPPLANE_8BPP;
2702 break;
57779d06
VS		 2703 case DRM_FORMAT_XRGB1555:
2704 case DRM_FORMAT_ARGB1555:
2705 dspcntr |= DISPPLANE_BGRX555;
81255565 2706 break;
57779d06
VS		 2707 case DRM_FORMAT_RGB565:
2708 dspcntr |= DISPPLANE_BGRX565;
2709 break;
2710 case DRM_FORMAT_XRGB8888:
2711 case DRM_FORMAT_ARGB8888:
2712 dspcntr |= DISPPLANE_BGRX888;
2713 break;
2714 case DRM_FORMAT_XBGR8888:
2715 case DRM_FORMAT_ABGR8888:
2716 dspcntr |= DISPPLANE_RGBX888;
2717 break;
2718 case DRM_FORMAT_XRGB2101010:
2719 case DRM_FORMAT_ARGB2101010:
2720 dspcntr |= DISPPLANE_BGRX101010;
2721 break;
2722 case DRM_FORMAT_XBGR2101010:
2723 case DRM_FORMAT_ABGR2101010:
2724 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2725 break;
2726 default:
baba133a 2727 BUG();
81255565 2728 }
57779d06 2729
f45651ba
VS		 2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
81255565 2733
de1aa629
VS		 2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
b9897127 2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2738
c2c75131
SV		 2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
bc752862 2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2742 pixel_size,
bc752862 2743 fb->pitches[0]);
c2c75131
SV		 2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 } else {
e506a0c6 2746 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2747 }
e506a0c6 2748
8e7d688b 2749 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2750 dspcntr |= DISPPLANE_ROTATE_180;
2751
6e3c9717
ACO		 2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
6e3c9717
ACO		 2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2760 }
2761
2762 I915_WRITE(reg, dspcntr);
2763
01f2c773 2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2765 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
SV		 2766 I915_WRITE(DSPSURF(plane),
2767 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2770 } else
f343c5f6 2771 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2772 POSTING_READ(reg);
17638cd6
JB		 2773}
2774
29b9bde6
SV		 2775static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776 struct drm_framebuffer *fb,
2777 int x, int y)
17638cd6
JB		 2778{
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2782 struct drm_plane *primary = crtc->primary;
2783 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2784 struct drm_i915_gem_object *obj;
17638cd6 2785 int plane = intel_crtc->plane;
e506a0c6 2786 unsigned long linear_offset;
17638cd6 2787 u32 dspcntr;
f45651ba 2788 u32 reg = DSPCNTR(plane);
48404c1e 2789 int pixel_size;
f45651ba 2790
b70709a6 2791 if (!visible || !fb) {
fdd508a6
VS		 2792 I915_WRITE(reg, 0);
2793 I915_WRITE(DSPSURF(plane), 0);
2794 POSTING_READ(reg);
2795 return;
2796 }
2797
c9ba6fad
VS		 2798 obj = intel_fb_obj(fb);
2799 if (WARN_ON(obj == NULL))
2800 return;
2801
2802 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
f45651ba
VS		 2804 dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
fdd508a6 2806 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2807
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2810
57779d06
VS		 2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
17638cd6
JB		 2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
57779d06
VS		 2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2817 break;
57779d06
VS		 2818 case DRM_FORMAT_XRGB8888:
2819 case DRM_FORMAT_ARGB8888:
2820 dspcntr |= DISPPLANE_BGRX888;
2821 break;
2822 case DRM_FORMAT_XBGR8888:
2823 case DRM_FORMAT_ABGR8888:
2824 dspcntr |= DISPPLANE_RGBX888;
2825 break;
2826 case DRM_FORMAT_XRGB2101010:
2827 case DRM_FORMAT_ARGB2101010:
2828 dspcntr |= DISPPLANE_BGRX101010;
2829 break;
2830 case DRM_FORMAT_XBGR2101010:
2831 case DRM_FORMAT_ABGR2101010:
2832 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2833 break;
2834 default:
baba133a 2835 BUG();
17638cd6
JB		 2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
17638cd6 2840
f45651ba 2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2843
b9897127 2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2845 intel_crtc->dspaddr_offset =
bc752862 2846 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2847 pixel_size,
bc752862 2848 fb->pitches[0]);
c2c75131 2849 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2850 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2851 dspcntr |= DISPPLANE_ROTATE_180;
2852
2853 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2854 x += (intel_crtc->config->pipe_src_w - 1);
2855 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2856
2857 /* Finding the last pixel of the last line of the display
2858 data and adding to linear_offset*/
2859 linear_offset +=
6e3c9717
ACO		 2860 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2861 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2862 }
2863 }
2864
2865 I915_WRITE(reg, dspcntr);
17638cd6 2866
01f2c773 2867 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
SV		 2868 I915_WRITE(DSPSURF(plane),
2869 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2870 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2871 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2872 } else {
2873 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2874 I915_WRITE(DSPLINOFF(plane), linear_offset);
2875 }
17638cd6 2876 POSTING_READ(reg);
17638cd6
JB		 2877}
2878
b321803d
DL		 2879u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2880 uint32_t pixel_format)
2881{
2882 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2883
2884 /*
2885 * The stride is either expressed as a multiple of 64 bytes
2886 * chunks for linear buffers or in number of tiles for tiled
2887 * buffers.
2888 */
2889 switch (fb_modifier) {
2890 case DRM_FORMAT_MOD_NONE:
2891 return 64;
2892 case I915_FORMAT_MOD_X_TILED:
2893 if (INTEL_INFO(dev)->gen == 2)
2894 return 128;
2895 return 512;
2896 case I915_FORMAT_MOD_Y_TILED:
2897 /* No need to check for old gens and Y tiling since this is
2898 * about the display engine and those will be blocked before
2899 * we get here.
2900 */
2901 return 128;
2902 case I915_FORMAT_MOD_Yf_TILED:
2903 if (bits_per_pixel == 8)
2904 return 64;
2905 else
2906 return 128;
2907 default:
2908 MISSING_CASE(fb_modifier);
2909 return 64;
2910 }
2911}
2912
121920fa
TU		 2913unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2914 struct drm_i915_gem_object *obj)
2915{
9abc4648 2916 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2917
2918 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2919 view = &i915_ggtt_view_rotated;
121920fa
TU		 2920
2921 return i915_gem_obj_ggtt_offset_view(obj, view);
2922}
2923
a1b2278e
CK		 2924/*
2925 * This function detaches (aka. unbinds) unused scalers in hardware
2926 */
2927void skl_detach_scalers(struct intel_crtc *intel_crtc)
2928{
2929 struct drm_device *dev;
2930 struct drm_i915_private *dev_priv;
2931 struct intel_crtc_scaler_state *scaler_state;
2932 int i;
2933
2934 if (!intel_crtc || !intel_crtc->config)
2935 return;
2936
2937 dev = intel_crtc->base.dev;
2938 dev_priv = dev->dev_private;
2939 scaler_state = &intel_crtc->config->scaler_state;
2940
2941 /* loop through and disable scalers that aren't in use */
2942 for (i = 0; i < intel_crtc->num_scalers; i++) {
2943 if (!scaler_state->scalers[i].in_use) {
2944 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2945 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2947 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2948 intel_crtc->base.base.id, intel_crtc->pipe, i);
2949 }
2950 }
2951}
2952
6156a456 2953u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2954{
6156a456
CK		 2955 u32 plane_ctl_format = 0;
2956 switch (pixel_format) {
70d21f0e 2957 case DRM_FORMAT_RGB565:
6156a456 2958 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
f75fb42a 2959 break;
70d21f0e 2960 case DRM_FORMAT_XBGR8888:
6156a456
CK		 2961 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2962 break;
2963 case DRM_FORMAT_XRGB8888:
2964 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
70d21f0e 2965 break;
6156a456
CK		 2966 /*
2967 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2968 * to be already pre-multiplied. We need to add a knob (or a different
2969 * DRM_FORMAT) for user-space to configure that.
2970 */
f75fb42a 2971 case DRM_FORMAT_ABGR8888:
6156a456
CK		 2972 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2973 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2974 break;
2975 case DRM_FORMAT_ARGB8888:
2976 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2977 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
f75fb42a 2978 break;
70d21f0e 2979 case DRM_FORMAT_XRGB2101010:
6156a456 2980 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e
DL		 2981 break;
2982 case DRM_FORMAT_XBGR2101010:
6156a456
CK		 2983 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2984 break;
2985 case DRM_FORMAT_YUYV:
2986 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2987 break;
2988 case DRM_FORMAT_YVYU:
2989 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2990 break;
2991 case DRM_FORMAT_UYVY:
2992 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2993 break;
2994 case DRM_FORMAT_VYUY:
2995 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e
DL		 2996 break;
2997 default:
2998 BUG();
2999 }
6156a456
CK		 3000 return plane_ctl_format;
3001}
70d21f0e 3002
6156a456
CK		 3003u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3004{
3005 u32 plane_ctl_tiling = 0;
3006 switch (fb_modifier) {
30af77c4 3007 case DRM_FORMAT_MOD_NONE:
70d21f0e 3008 break;
30af77c4 3009 case I915_FORMAT_MOD_X_TILED:
6156a456 3010 plane_ctl_tiling = PLANE_CTL_TILED_X;
b321803d
DL		 3011 break;
3012 case I915_FORMAT_MOD_Y_TILED:
6156a456 3013 plane_ctl_tiling = PLANE_CTL_TILED_Y;
b321803d
DL		 3014 break;
3015 case I915_FORMAT_MOD_Yf_TILED:
6156a456 3016 plane_ctl_tiling = PLANE_CTL_TILED_YF;
70d21f0e
DL		 3017 break;
3018 default:
6156a456 3019 MISSING_CASE(fb_modifier);
70d21f0e 3020 }
6156a456
CK		 3021 return plane_ctl_tiling;
3022}
70d21f0e 3023
6156a456
CK		 3024u32 skl_plane_ctl_rotation(unsigned int rotation)
3025{
3026 u32 plane_ctl_rotation = 0;
3b7a5119 3027 switch (rotation) {
6156a456
CK		 3028 case BIT(DRM_ROTATE_0):
3029 break;
3b7a5119 3030 case BIT(DRM_ROTATE_90):
6156a456 3031 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3b7a5119 3032 break;
3b7a5119 3033 case BIT(DRM_ROTATE_180):
6156a456 3034 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3b7a5119 3035 break;
3b7a5119 3036 case BIT(DRM_ROTATE_270):
6156a456 3037 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3b7a5119 3038 break;
6156a456
CK		 3039 default:
3040 MISSING_CASE(rotation);
3041 }
3042
3043 return plane_ctl_rotation;
3044}
3045
3046static void skylake_update_primary_plane(struct drm_crtc *crtc,
3047 struct drm_framebuffer *fb,
3048 int x, int y)
3049{
3050 struct drm_device *dev = crtc->dev;
3051 struct drm_i915_private *dev_priv = dev->dev_private;
3052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3053 struct drm_plane *plane = crtc->primary;
3054 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3055 struct drm_i915_gem_object *obj;
3056 int pipe = intel_crtc->pipe;
3057 u32 plane_ctl, stride_div, stride;
3058 u32 tile_height, plane_offset, plane_size;
3059 unsigned int rotation;
3060 int x_offset, y_offset;
3061 unsigned long surf_addr;
6156a456
CK		 3062 struct intel_crtc_state *crtc_state = intel_crtc->config;
3063 struct intel_plane_state *plane_state;
3064 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3065 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3066 int scaler_id = -1;
3067
6156a456
CK		 3068 plane_state = to_intel_plane_state(plane->state);
3069
b70709a6 3070 if (!visible || !fb) {
6156a456
CK		 3071 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3072 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3073 POSTING_READ(PLANE_CTL(pipe, 0));
3074 return;
3b7a5119 3075 }
70d21f0e 3076
6156a456
CK		 3077 plane_ctl = PLANE_CTL_ENABLE |
3078 PLANE_CTL_PIPE_GAMMA_ENABLE |
3079 PLANE_CTL_PIPE_CSC_ENABLE;
3080
3081 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3082 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3083 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3084
3085 rotation = plane->state->rotation;
3086 plane_ctl |= skl_plane_ctl_rotation(rotation);
3087
b321803d
DL		 3088 obj = intel_fb_obj(fb);
3089 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3090 fb->pixel_format);
3b7a5119
SJ		 3091 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3092
6156a456
CK		 3093 /*
3094 * FIXME: intel_plane_state->src, dst aren't set when transitional
3095 * update_plane helpers are called from legacy paths.
3096 * Once full atomic crtc is available, below check can be avoided.
3097 */
3098 if (drm_rect_width(&plane_state->src)) {
3099 scaler_id = plane_state->scaler_id;
3100 src_x = plane_state->src.x1 >> 16;
3101 src_y = plane_state->src.y1 >> 16;
3102 src_w = drm_rect_width(&plane_state->src) >> 16;
3103 src_h = drm_rect_height(&plane_state->src) >> 16;
3104 dst_x = plane_state->dst.x1;
3105 dst_y = plane_state->dst.y1;
3106 dst_w = drm_rect_width(&plane_state->dst);
3107 dst_h = drm_rect_height(&plane_state->dst);
3108
3109 WARN_ON(x != src_x || y != src_y);
3110 } else {
3111 src_w = intel_crtc->config->pipe_src_w;
3112 src_h = intel_crtc->config->pipe_src_h;
3113 }
3114
3b7a5119
SJ		 3115 if (intel_rotation_90_or_270(rotation)) {
3116 /* stride = Surface height in tiles */
3117 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3118 fb->modifier[0]);
3119 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3120 x_offset = stride * tile_height - y - src_h;
3b7a5119 3121 y_offset = x;
6156a456 3122 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3123 } else {
3124 stride = fb->pitches[0] / stride_div;
3125 x_offset = x;
3126 y_offset = y;
6156a456 3127 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3128 }
3129 plane_offset = y_offset << 16 | x_offset;
b321803d 3130
70d21f0e 3131 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3132 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3133 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3134 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3135
3136 if (scaler_id >= 0) {
3137 uint32_t ps_ctrl = 0;
3138
3139 WARN_ON(!dst_w || !dst_h);
3140 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3141 crtc_state->scaler_state.scalers[scaler_id].mode;
3142 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3143 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3144 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3145 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3146 I915_WRITE(PLANE_POS(pipe, 0), 0);
3147 } else {
3148 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3149 }
3150
121920fa 3151 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3152
3153 POSTING_READ(PLANE_SURF(pipe, 0));
3154}
3155
17638cd6
JB		 3156/* Assume fb object is pinned & idle & fenced and just update base pointers */
3157static int
3158intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3159 int x, int y, enum mode_set_atomic state)
3160{
3161 struct drm_device *dev = crtc->dev;
3162 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3163
6b8e6ed0
CW		 3164 if (dev_priv->display.disable_fbc)
3165 dev_priv->display.disable_fbc(dev);
81255565 3166
29b9bde6
SV		 3167 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3168
3169 return 0;
81255565
JB		 3170}
3171
7514747d 3172static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3173{
96a02917
VS		 3174 struct drm_crtc *crtc;
3175
70e1e0ec 3176 for_each_crtc(dev, crtc) {
96a02917
VS		 3177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3178 enum plane plane = intel_crtc->plane;
3179
3180 intel_prepare_page_flip(dev, plane);
3181 intel_finish_page_flip_plane(dev, plane);
3182 }
7514747d
VS		 3183}
3184
3185static void intel_update_primary_planes(struct drm_device *dev)
3186{
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct drm_crtc *crtc;
96a02917 3189
70e1e0ec 3190 for_each_crtc(dev, crtc) {
96a02917
VS		 3191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3192
51fd371b 3193 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3194 /*
3195 * FIXME: Once we have proper support for primary planes (and
3196 * disabling them without disabling the entire crtc) allow again
66e514c1 3197 * a NULL crtc->primary->fb.
947fdaad 3198 */
f4510a27 3199 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3200 dev_priv->display.update_primary_plane(crtc,
66e514c1 3201 crtc->primary->fb,
262ca2b0
MR		 3202 crtc->x,
3203 crtc->y);
51fd371b 3204 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3205 }
3206}
3207
ce22dba9
ML		 3208void intel_crtc_reset(struct intel_crtc *crtc)
3209{
3210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3211
3212 if (!crtc->active)
3213 return;
3214
3215 intel_crtc_disable_planes(&crtc->base);
3216 dev_priv->display.crtc_disable(&crtc->base);
3217 dev_priv->display.crtc_enable(&crtc->base);
3218 intel_crtc_enable_planes(&crtc->base);
3219}
3220
7514747d
VS		 3221void intel_prepare_reset(struct drm_device *dev)
3222{
f98ce92f
VS		 3223 struct drm_i915_private *dev_priv = to_i915(dev);
3224 struct intel_crtc *crtc;
3225
7514747d
VS		 3226 /* no reset support for gen2 */
3227 if (IS_GEN2(dev))
3228 return;
3229
3230 /* reset doesn't touch the display */
3231 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3232 return;
3233
3234 drm_modeset_lock_all(dev);
f98ce92f
VS		 3235
3236 /*
3237 * Disabling the crtcs gracefully seems nicer. Also the
3238 * g33 docs say we should at least disable all the planes.
3239 */
3240 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3241 if (!crtc->active)
3242 continue;
3243
3244 intel_crtc_disable_planes(&crtc->base);
3245 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3246 }
7514747d
VS		 3247}
3248
3249void intel_finish_reset(struct drm_device *dev)
3250{
3251 struct drm_i915_private *dev_priv = to_i915(dev);
3252
3253 /*
3254 * Flips in the rings will be nuked by the reset,
3255 * so complete all pending flips so that user space
3256 * will get its events and not get stuck.
3257 */
3258 intel_complete_page_flips(dev);
3259
3260 /* no reset support for gen2 */
3261 if (IS_GEN2(dev))
3262 return;
3263
3264 /* reset doesn't touch the display */
3265 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3266 /*
3267 * Flips in the rings have been nuked by the reset,
3268 * so update the base address of all primary
3269 * planes to the the last fb to make sure we're
3270 * showing the correct fb after a reset.
3271 */
3272 intel_update_primary_planes(dev);
3273 return;
3274 }
3275
3276 /*
3277 * The display has been reset as well,
3278 * so need a full re-initialization.
3279 */
3280 intel_runtime_pm_disable_interrupts(dev_priv);
3281 intel_runtime_pm_enable_interrupts(dev_priv);
3282
3283 intel_modeset_init_hw(dev);
3284
3285 spin_lock_irq(&dev_priv->irq_lock);
3286 if (dev_priv->display.hpd_irq_setup)
3287 dev_priv->display.hpd_irq_setup(dev);
3288 spin_unlock_irq(&dev_priv->irq_lock);
3289
3290 intel_modeset_setup_hw_state(dev, true);
3291
3292 intel_hpd_init(dev_priv);
3293
3294 drm_modeset_unlock_all(dev);
3295}
3296
14667a4b
CW		 3297static int
3298intel_finish_fb(struct drm_framebuffer *old_fb)
3299{
2ff8fde1 3300 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3301 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3302 bool was_interruptible = dev_priv->mm.interruptible;
3303 int ret;
3304
14667a4b
CW		 3305 /* Big Hammer, we also need to ensure that any pending
3306 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3307 * current scanout is retired before unpinning the old
3308 * framebuffer.
3309 *
3310 * This should only fail upon a hung GPU, in which case we
3311 * can safely continue.
3312 */
3313 dev_priv->mm.interruptible = false;
3314 ret = i915_gem_object_finish_gpu(obj);
3315 dev_priv->mm.interruptible = was_interruptible;
3316
3317 return ret;
3318}
3319
7d5e3799
CW		 3320static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3321{
3322 struct drm_device *dev = crtc->dev;
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3325 bool pending;
3326
3327 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3328 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3329 return false;
3330
5e2d7afc 3331 spin_lock_irq(&dev->event_lock);
7d5e3799 3332 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3333 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3334
3335 return pending;
3336}
3337
e30e8f75
GP		 3338static void intel_update_pipe_size(struct intel_crtc *crtc)
3339{
3340 struct drm_device *dev = crtc->base.dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 const struct drm_display_mode *adjusted_mode;
3343
3344 if (!i915.fastboot)
3345 return;
3346
3347 /*
3348 * Update pipe size and adjust fitter if needed: the reason for this is
3349 * that in compute_mode_changes we check the native mode (not the pfit
3350 * mode) to see if we can flip rather than do a full mode set. In the
3351 * fastboot case, we'll flip, but if we don't update the pipesrc and
3352 * pfit state, we'll end up with a big fb scanned out into the wrong
3353 * sized surface.
3354 *
3355 * To fix this properly, we need to hoist the checks up into
3356 * compute_mode_changes (or above), check the actual pfit state and
3357 * whether the platform allows pfit disable with pipe active, and only
3358 * then update the pipesrc and pfit state, even on the flip path.
3359 */
3360
6e3c9717 3361 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3362
3363 I915_WRITE(PIPESRC(crtc->pipe),
3364 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3365 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3366 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3367 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3368 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3369 I915_WRITE(PF_CTL(crtc->pipe), 0);
3370 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3371 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3372 }
6e3c9717
ACO		 3373 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3374 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3375}
3376
5e84e1a4
ZW		 3377static void intel_fdi_normal_train(struct drm_crtc *crtc)
3378{
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
3383 u32 reg, temp;
3384
3385 /* enable normal train */
3386 reg = FDI_TX_CTL(pipe);
3387 temp = I915_READ(reg);
61e499bf 3388 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3389 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3390 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3391 } else {
3392 temp &= ~FDI_LINK_TRAIN_NONE;
3393 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3394 }
5e84e1a4
ZW		 3395 I915_WRITE(reg, temp);
3396
3397 reg = FDI_RX_CTL(pipe);
3398 temp = I915_READ(reg);
3399 if (HAS_PCH_CPT(dev)) {
3400 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3401 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3402 } else {
3403 temp &= ~FDI_LINK_TRAIN_NONE;
3404 temp |= FDI_LINK_TRAIN_NONE;
3405 }
3406 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3407
3408 /* wait one idle pattern time */
3409 POSTING_READ(reg);
3410 udelay(1000);
357555c0
JB		 3411
3412 /* IVB wants error correction enabled */
3413 if (IS_IVYBRIDGE(dev))
3414 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3415 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3416}
3417
8db9d77b
ZW		 3418/* The FDI link training functions for ILK/Ibexpeak. */
3419static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3420{
3421 struct drm_device *dev = crtc->dev;
3422 struct drm_i915_private *dev_priv = dev->dev_private;
3423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3424 int pipe = intel_crtc->pipe;
5eddb70b 3425 u32 reg, temp, tries;
8db9d77b 3426
1c8562f6 3427 /* FDI needs bits from pipe first */
0fc932b8 3428 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3429
e1a44743
AJ		 3430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3431 for train result */
5eddb70b
CW		 3432 reg = FDI_RX_IMR(pipe);
3433 temp = I915_READ(reg);
e1a44743
AJ		 3434 temp &= ~FDI_RX_SYMBOL_LOCK;
3435 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3436 I915_WRITE(reg, temp);
3437 I915_READ(reg);
e1a44743
AJ		 3438 udelay(150);
3439
8db9d77b 3440 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3441 reg = FDI_TX_CTL(pipe);
3442 temp = I915_READ(reg);
627eb5a3 3443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3447 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3448
5eddb70b
CW		 3449 reg = FDI_RX_CTL(pipe);
3450 temp = I915_READ(reg);
8db9d77b
ZW		 3451 temp &= ~FDI_LINK_TRAIN_NONE;
3452 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3453 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3454
3455 POSTING_READ(reg);
8db9d77b
ZW		 3456 udelay(150);
3457
5b2adf89 3458 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
SV		 3459 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3461 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3462
5eddb70b 3463 reg = FDI_RX_IIR(pipe);
e1a44743 3464 for (tries = 0; tries < 5; tries++) {
5eddb70b 3465 temp = I915_READ(reg);
8db9d77b
ZW		 3466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3467
3468 if ((temp & FDI_RX_BIT_LOCK)) {
3469 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3470 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3471 break;
3472 }
8db9d77b 3473 }
e1a44743 3474 if (tries == 5)
5eddb70b 3475 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3476
3477 /* Train 2 */
5eddb70b
CW		 3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
8db9d77b
ZW		 3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3482 I915_WRITE(reg, temp);
8db9d77b 3483
5eddb70b
CW		 3484 reg = FDI_RX_CTL(pipe);
3485 temp = I915_READ(reg);
8db9d77b
ZW		 3486 temp &= ~FDI_LINK_TRAIN_NONE;
3487 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3488 I915_WRITE(reg, temp);
8db9d77b 3489
5eddb70b
CW		 3490 POSTING_READ(reg);
3491 udelay(150);
8db9d77b 3492
5eddb70b 3493 reg = FDI_RX_IIR(pipe);
e1a44743 3494 for (tries = 0; tries < 5; tries++) {
5eddb70b 3495 temp = I915_READ(reg);
8db9d77b
ZW		 3496 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3497
3498 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3499 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3500 DRM_DEBUG_KMS("FDI train 2 done.\n");
3501 break;
3502 }
8db9d77b 3503 }
e1a44743 3504 if (tries == 5)
5eddb70b 3505 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3506
3507 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3508
8db9d77b
ZW		 3509}
3510
0206e353 3511static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3512 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3513 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3514 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3515 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3516};
3517
3518/* The FDI link training functions for SNB/Cougarpoint. */
3519static void gen6_fdi_link_train(struct drm_crtc *crtc)
3520{
3521 struct drm_device *dev = crtc->dev;
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3524 int pipe = intel_crtc->pipe;
fa37d39e 3525 u32 reg, temp, i, retry;
8db9d77b 3526
e1a44743
AJ		 3527 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3528 for train result */
5eddb70b
CW		 3529 reg = FDI_RX_IMR(pipe);
3530 temp = I915_READ(reg);
e1a44743
AJ		 3531 temp &= ~FDI_RX_SYMBOL_LOCK;
3532 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3533 I915_WRITE(reg, temp);
3534
3535 POSTING_READ(reg);
e1a44743
AJ		 3536 udelay(150);
3537
8db9d77b 3538 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3539 reg = FDI_TX_CTL(pipe);
3540 temp = I915_READ(reg);
627eb5a3 3541 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3542 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3543 temp &= ~FDI_LINK_TRAIN_NONE;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1;
3545 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3546 /* SNB-B */
3547 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3548 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3549
d74cf324
SV		 3550 I915_WRITE(FDI_RX_MISC(pipe),
3551 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3552
5eddb70b
CW		 3553 reg = FDI_RX_CTL(pipe);
3554 temp = I915_READ(reg);
8db9d77b
ZW		 3555 if (HAS_PCH_CPT(dev)) {
3556 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3557 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3558 } else {
3559 temp &= ~FDI_LINK_TRAIN_NONE;
3560 temp |= FDI_LINK_TRAIN_PATTERN_1;
3561 }
5eddb70b
CW		 3562 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3563
3564 POSTING_READ(reg);
8db9d77b
ZW		 3565 udelay(150);
3566
0206e353 3567 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
8db9d77b
ZW		 3570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3571 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3572 I915_WRITE(reg, temp);
3573
3574 POSTING_READ(reg);
8db9d77b
ZW		 3575 udelay(500);
3576
fa37d39e
SP		 3577 for (retry = 0; retry < 5; retry++) {
3578 reg = FDI_RX_IIR(pipe);
3579 temp = I915_READ(reg);
3580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3581 if (temp & FDI_RX_BIT_LOCK) {
3582 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3583 DRM_DEBUG_KMS("FDI train 1 done.\n");
3584 break;
3585 }
3586 udelay(50);
8db9d77b 3587 }
fa37d39e
SP		 3588 if (retry < 5)
3589 break;
8db9d77b
ZW		 3590 }
3591 if (i == 4)
5eddb70b 3592 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3593
3594 /* Train 2 */
5eddb70b
CW		 3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
8db9d77b
ZW		 3597 temp &= ~FDI_LINK_TRAIN_NONE;
3598 temp |= FDI_LINK_TRAIN_PATTERN_2;
3599 if (IS_GEN6(dev)) {
3600 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3601 /* SNB-B */
3602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3603 }
5eddb70b 3604 I915_WRITE(reg, temp);
8db9d77b 3605
5eddb70b
CW		 3606 reg = FDI_RX_CTL(pipe);
3607 temp = I915_READ(reg);
8db9d77b
ZW		 3608 if (HAS_PCH_CPT(dev)) {
3609 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3610 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3611 } else {
3612 temp &= ~FDI_LINK_TRAIN_NONE;
3613 temp |= FDI_LINK_TRAIN_PATTERN_2;
3614 }
5eddb70b
CW		 3615 I915_WRITE(reg, temp);
3616
3617 POSTING_READ(reg);
8db9d77b
ZW		 3618 udelay(150);
3619
0206e353 3620 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3621 reg = FDI_TX_CTL(pipe);
3622 temp = I915_READ(reg);
8db9d77b
ZW		 3623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3624 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3625 I915_WRITE(reg, temp);
3626
3627 POSTING_READ(reg);
8db9d77b
ZW		 3628 udelay(500);
3629
fa37d39e
SP		 3630 for (retry = 0; retry < 5; retry++) {
3631 reg = FDI_RX_IIR(pipe);
3632 temp = I915_READ(reg);
3633 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3634 if (temp & FDI_RX_SYMBOL_LOCK) {
3635 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3636 DRM_DEBUG_KMS("FDI train 2 done.\n");
3637 break;
3638 }
3639 udelay(50);
8db9d77b 3640 }
fa37d39e
SP		 3641 if (retry < 5)
3642 break;
8db9d77b
ZW		 3643 }
3644 if (i == 4)
5eddb70b 3645 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3646
3647 DRM_DEBUG_KMS("FDI train done.\n");
3648}
3649
357555c0
JB		 3650/* Manual link training for Ivy Bridge A0 parts */
3651static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3652{
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 int pipe = intel_crtc->pipe;
139ccd3f 3657 u32 reg, temp, i, j;
357555c0
JB		 3658
3659 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3660 for train result */
3661 reg = FDI_RX_IMR(pipe);
3662 temp = I915_READ(reg);
3663 temp &= ~FDI_RX_SYMBOL_LOCK;
3664 temp &= ~FDI_RX_BIT_LOCK;
3665 I915_WRITE(reg, temp);
3666
3667 POSTING_READ(reg);
3668 udelay(150);
3669
01a415fd
SV		 3670 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3671 I915_READ(FDI_RX_IIR(pipe)));
3672
139ccd3f
JB		 3673 /* Try each vswing and preemphasis setting twice before moving on */
3674 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3675 /* disable first in case we need to retry */
3676 reg = FDI_TX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3679 temp &= ~FDI_TX_ENABLE;
3680 I915_WRITE(reg, temp);
357555c0 3681
139ccd3f
JB		 3682 reg = FDI_RX_CTL(pipe);
3683 temp = I915_READ(reg);
3684 temp &= ~FDI_LINK_TRAIN_AUTO;
3685 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3686 temp &= ~FDI_RX_ENABLE;
3687 I915_WRITE(reg, temp);
357555c0 3688
139ccd3f 3689 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3690 reg = FDI_TX_CTL(pipe);
3691 temp = I915_READ(reg);
139ccd3f 3692 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3693 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3694 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3695 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3696 temp |= snb_b_fdi_train_param[j/2];
3697 temp |= FDI_COMPOSITE_SYNC;
3698 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3699
139ccd3f
JB		 3700 I915_WRITE(FDI_RX_MISC(pipe),
3701 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3702
139ccd3f 3703 reg = FDI_RX_CTL(pipe);
357555c0 3704 temp = I915_READ(reg);
139ccd3f
JB		 3705 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3706 temp |= FDI_COMPOSITE_SYNC;
3707 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3708
139ccd3f
JB		 3709 POSTING_READ(reg);
3710 udelay(1); /* should be 0.5us */
357555c0 3711
139ccd3f
JB		 3712 for (i = 0; i < 4; i++) {
3713 reg = FDI_RX_IIR(pipe);
3714 temp = I915_READ(reg);
3715 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3716
139ccd3f
JB		 3717 if (temp & FDI_RX_BIT_LOCK ||
3718 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3719 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3720 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3721 i);
3722 break;
3723 }
3724 udelay(1); /* should be 0.5us */
3725 }
3726 if (i == 4) {
3727 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3728 continue;
3729 }
357555c0 3730
139ccd3f 3731 /* Train 2 */
357555c0
JB		 3732 reg = FDI_TX_CTL(pipe);
3733 temp = I915_READ(reg);
139ccd3f
JB		 3734 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3735 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3736 I915_WRITE(reg, temp);
3737
3738 reg = FDI_RX_CTL(pipe);
3739 temp = I915_READ(reg);
3740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3741 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3742 I915_WRITE(reg, temp);
3743
3744 POSTING_READ(reg);
139ccd3f 3745 udelay(2); /* should be 1.5us */
357555c0 3746
139ccd3f
JB		 3747 for (i = 0; i < 4; i++) {
3748 reg = FDI_RX_IIR(pipe);
3749 temp = I915_READ(reg);
3750 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3751
139ccd3f
JB		 3752 if (temp & FDI_RX_SYMBOL_LOCK ||
3753 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3754 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3755 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3756 i);
3757 goto train_done;
3758 }
3759 udelay(2); /* should be 1.5us */
357555c0 3760 }
139ccd3f
JB		 3761 if (i == 4)
3762 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3763 }
357555c0 3764
139ccd3f 3765train_done:
357555c0
JB		 3766 DRM_DEBUG_KMS("FDI train done.\n");
3767}
3768
88cefb6c 3769static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3770{
88cefb6c 3771 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3772 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3773 int pipe = intel_crtc->pipe;
5eddb70b 3774 u32 reg, temp;
79e53945 3775
c64e311e 3776
c98e9dcf 3777 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3778 reg = FDI_RX_CTL(pipe);
3779 temp = I915_READ(reg);
627eb5a3 3780 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3781 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3782 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3783 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3784
3785 POSTING_READ(reg);
c98e9dcf
JB		 3786 udelay(200);
3787
3788 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3789 temp = I915_READ(reg);
3790 I915_WRITE(reg, temp | FDI_PCDCLK);
3791
3792 POSTING_READ(reg);
c98e9dcf
JB		 3793 udelay(200);
3794
20749730
PZ		 3795 /* Enable CPU FDI TX PLL, always on for Ironlake */
3796 reg = FDI_TX_CTL(pipe);
3797 temp = I915_READ(reg);
3798 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3799 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3800
20749730
PZ		 3801 POSTING_READ(reg);
3802 udelay(100);
6be4a607 3803 }
0e23b99d
JB		 3804}
3805
88cefb6c
SV		 3806static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3807{
3808 struct drm_device *dev = intel_crtc->base.dev;
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 int pipe = intel_crtc->pipe;
3811 u32 reg, temp;
3812
3813 /* Switch from PCDclk to Rawclk */
3814 reg = FDI_RX_CTL(pipe);
3815 temp = I915_READ(reg);
3816 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3817
3818 /* Disable CPU FDI TX PLL */
3819 reg = FDI_TX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3822
3823 POSTING_READ(reg);
3824 udelay(100);
3825
3826 reg = FDI_RX_CTL(pipe);
3827 temp = I915_READ(reg);
3828 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3829
3830 /* Wait for the clocks to turn off. */
3831 POSTING_READ(reg);
3832 udelay(100);
3833}
3834
0fc932b8
JB		 3835static void ironlake_fdi_disable(struct drm_crtc *crtc)
3836{
3837 struct drm_device *dev = crtc->dev;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
3839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3840 int pipe = intel_crtc->pipe;
3841 u32 reg, temp;
3842
3843 /* disable CPU FDI tx and PCH FDI rx */
3844 reg = FDI_TX_CTL(pipe);
3845 temp = I915_READ(reg);
3846 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3847 POSTING_READ(reg);
3848
3849 reg = FDI_RX_CTL(pipe);
3850 temp = I915_READ(reg);
3851 temp &= ~(0x7 << 16);
dfd07d72 3852 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3853 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3854
3855 POSTING_READ(reg);
3856 udelay(100);
3857
3858 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3859 if (HAS_PCH_IBX(dev))
6f06ce18 3860 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3861
3862 /* still set train pattern 1 */
3863 reg = FDI_TX_CTL(pipe);
3864 temp = I915_READ(reg);
3865 temp &= ~FDI_LINK_TRAIN_NONE;
3866 temp |= FDI_LINK_TRAIN_PATTERN_1;
3867 I915_WRITE(reg, temp);
3868
3869 reg = FDI_RX_CTL(pipe);
3870 temp = I915_READ(reg);
3871 if (HAS_PCH_CPT(dev)) {
3872 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3873 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3874 } else {
3875 temp &= ~FDI_LINK_TRAIN_NONE;
3876 temp |= FDI_LINK_TRAIN_PATTERN_1;
3877 }
3878 /* BPC in FDI rx is consistent with that in PIPECONF */
3879 temp &= ~(0x07 << 16);
dfd07d72 3880 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3881 I915_WRITE(reg, temp);
3882
3883 POSTING_READ(reg);
3884 udelay(100);
3885}
3886
5dce5b93
CW		 3887bool intel_has_pending_fb_unpin(struct drm_device *dev)
3888{
3889 struct intel_crtc *crtc;
3890
3891 /* Note that we don't need to be called with mode_config.lock here
3892 * as our list of CRTC objects is static for the lifetime of the
3893 * device and so cannot disappear as we iterate. Similarly, we can
3894 * happily treat the predicates as racy, atomic checks as userspace
3895 * cannot claim and pin a new fb without at least acquring the
3896 * struct_mutex and so serialising with us.
3897 */
d3fcc808 3898 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3899 if (atomic_read(&crtc->unpin_work_count) == 0)
3900 continue;
3901
3902 if (crtc->unpin_work)
3903 intel_wait_for_vblank(dev, crtc->pipe);
3904
3905 return true;
3906 }
3907
3908 return false;
3909}
3910
d6bbafa1
CW		 3911static void page_flip_completed(struct intel_crtc *intel_crtc)
3912{
3913 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3914 struct intel_unpin_work *work = intel_crtc->unpin_work;
3915
3916 /* ensure that the unpin work is consistent wrt ->pending. */
3917 smp_rmb();
3918 intel_crtc->unpin_work = NULL;
3919
3920 if (work->event)
3921 drm_send_vblank_event(intel_crtc->base.dev,
3922 intel_crtc->pipe,
3923 work->event);
3924
3925 drm_crtc_vblank_put(&intel_crtc->base);
3926
3927 wake_up_all(&dev_priv->pending_flip_queue);
3928 queue_work(dev_priv->wq, &work->work);
3929
3930 trace_i915_flip_complete(intel_crtc->plane,
3931 work->pending_flip_obj);
3932}
3933
46a55d30 3934void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3935{
0f91128d 3936 struct drm_device *dev = crtc->dev;
5bb61643 3937 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3938
2c10d571 3939 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3940 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3941 !intel_crtc_has_pending_flip(crtc),
3942 60*HZ) == 0)) {
3943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3944
5e2d7afc 3945 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3946 if (intel_crtc->unpin_work) {
3947 WARN_ONCE(1, "Removing stuck page flip\n");
3948 page_flip_completed(intel_crtc);
3949 }
5e2d7afc 3950 spin_unlock_irq(&dev->event_lock);
9c787942 3951 }
5bb61643 3952
975d568a
CW		 3953 if (crtc->primary->fb) {
3954 mutex_lock(&dev->struct_mutex);
3955 intel_finish_fb(crtc->primary->fb);
3956 mutex_unlock(&dev->struct_mutex);
3957 }
e6c3a2a6
CW		 3958}
3959
e615efe4
ED		 3960/* Program iCLKIP clock to the desired frequency */
3961static void lpt_program_iclkip(struct drm_crtc *crtc)
3962{
3963 struct drm_device *dev = crtc->dev;
3964 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3965 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3966 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3967 u32 temp;
3968
09153000
SV		 3969 mutex_lock(&dev_priv->dpio_lock);
3970
e615efe4
ED		 3971 /* It is necessary to ungate the pixclk gate prior to programming
3972 * the divisors, and gate it back when it is done.
3973 */
3974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3975
3976 /* Disable SSCCTL */
3977 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3978 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3979 SBI_SSCCTL_DISABLE,
3980 SBI_ICLK);
e615efe4
ED		 3981
3982 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3983 if (clock == 20000) {
e615efe4
ED		 3984 auxdiv = 1;
3985 divsel = 0x41;
3986 phaseinc = 0x20;
3987 } else {
3988 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3989 * but the adjusted_mode->crtc_clock in in KHz. To get the
3990 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3991 * convert the virtual clock precision to KHz here for higher
3992 * precision.
3993 */
3994 u32 iclk_virtual_root_freq = 172800 * 1000;
3995 u32 iclk_pi_range = 64;
3996 u32 desired_divisor, msb_divisor_value, pi_value;
3997
12d7ceed 3998 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3999 msb_divisor_value = desired_divisor / iclk_pi_range;
4000 pi_value = desired_divisor % iclk_pi_range;
4001
4002 auxdiv = 0;
4003 divsel = msb_divisor_value - 2;
4004 phaseinc = pi_value;
4005 }
4006
4007 /* This should not happen with any sane values */
4008 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4009 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4010 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4011 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4012
4013 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4014 clock,
e615efe4
ED		 4015 auxdiv,
4016 divsel,
4017 phasedir,
4018 phaseinc);
4019
4020 /* Program SSCDIVINTPHASE6 */
988d6ee8 4021 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4022 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4023 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4024 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4025 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4026 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4027 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4028 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4029
4030 /* Program SSCAUXDIV */
988d6ee8 4031 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4032 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4033 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4034 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4035
4036 /* Enable modulator and associated divider */
988d6ee8 4037 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4038 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4039 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4040
4041 /* Wait for initialization time */
4042 udelay(24);
4043
4044 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
SV		 4045
4046 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4047}
4048
275f01b2
SV		 4049static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4050 enum pipe pch_transcoder)
4051{
4052 struct drm_device *dev = crtc->base.dev;
4053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
SV		 4055
4056 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4057 I915_READ(HTOTAL(cpu_transcoder)));
4058 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4059 I915_READ(HBLANK(cpu_transcoder)));
4060 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4061 I915_READ(HSYNC(cpu_transcoder)));
4062
4063 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4064 I915_READ(VTOTAL(cpu_transcoder)));
4065 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4066 I915_READ(VBLANK(cpu_transcoder)));
4067 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4068 I915_READ(VSYNC(cpu_transcoder)));
4069 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4070 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4071}
4072
003632d9 4073static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
SV		 4074{
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076 uint32_t temp;
4077
4078 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4079 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
SV		 4080 return;
4081
4082 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4083 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4084
003632d9
ACO		 4085 temp &= ~FDI_BC_BIFURCATION_SELECT;
4086 if (enable)
4087 temp |= FDI_BC_BIFURCATION_SELECT;
4088
4089 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
SV		 4090 I915_WRITE(SOUTH_CHICKEN1, temp);
4091 POSTING_READ(SOUTH_CHICKEN1);
4092}
4093
4094static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4095{
4096 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
SV		 4097
4098 switch (intel_crtc->pipe) {
4099 case PIPE_A:
4100 break;
4101 case PIPE_B:
6e3c9717 4102 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4103 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4104 else
003632d9 4105 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
SV		 4106
4107 break;
4108 case PIPE_C:
003632d9 4109 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
SV		 4110
4111 break;
4112 default:
4113 BUG();
4114 }
4115}
4116
f67a559d
JB		 4117/*
4118 * Enable PCH resources required for PCH ports:
4119 * - PCH PLLs
4120 * - FDI training & RX/TX
4121 * - update transcoder timings
4122 * - DP transcoding bits
4123 * - transcoder
4124 */
4125static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4126{
4127 struct drm_device *dev = crtc->dev;
4128 struct drm_i915_private *dev_priv = dev->dev_private;
4129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4130 int pipe = intel_crtc->pipe;
ee7b9f93 4131 u32 reg, temp;
2c07245f 4132
ab9412ba 4133 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4134
1fbc0d78
SV		 4135 if (IS_IVYBRIDGE(dev))
4136 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4137
cd986abb
SV		 4138 /* Write the TU size bits before fdi link training, so that error
4139 * detection works. */
4140 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4141 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4142
c98e9dcf 4143 /* For PCH output, training FDI link */
674cf967 4144 dev_priv->display.fdi_link_train(crtc);
2c07245f 4145
3ad8a208
SV		 4146 /* We need to program the right clock selection before writing the pixel
4147 * mutliplier into the DPLL. */
303b81e0 4148 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4149 u32 sel;
4b645f14 4150
c98e9dcf 4151 temp = I915_READ(PCH_DPLL_SEL);
11887397
SV		 4152 temp |= TRANS_DPLL_ENABLE(pipe);
4153 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4154 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4155 temp |= sel;
4156 else
4157 temp &= ~sel;
c98e9dcf 4158 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4159 }
5eddb70b 4160
3ad8a208
SV		 4161 /* XXX: pch pll's can be enabled any time before we enable the PCH
4162 * transcoder, and we actually should do this to not upset any PCH
4163 * transcoder that already use the clock when we share it.
4164 *
4165 * Note that enable_shared_dpll tries to do the right thing, but
4166 * get_shared_dpll unconditionally resets the pll - we need that to have
4167 * the right LVDS enable sequence. */
85b3894f 4168 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4169
d9b6cb56
JB		 4170 /* set transcoder timing, panel must allow it */
4171 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4172 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4173
303b81e0 4174 intel_fdi_normal_train(crtc);
5e84e1a4 4175
c98e9dcf 4176 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4177 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4178 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4179 reg = TRANS_DP_CTL(pipe);
4180 temp = I915_READ(reg);
4181 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4182 TRANS_DP_SYNC_MASK |
4183 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4184 temp |= (TRANS_DP_OUTPUT_ENABLE |
4185 TRANS_DP_ENH_FRAMING);
9325c9f0 4186 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4187
4188 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4189 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4190 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4191 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4192
4193 switch (intel_trans_dp_port_sel(crtc)) {
4194 case PCH_DP_B:
5eddb70b 4195 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4196 break;
4197 case PCH_DP_C:
5eddb70b 4198 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4199 break;
4200 case PCH_DP_D:
5eddb70b 4201 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4202 break;
4203 default:
e95d41e1 4204 BUG();
32f9d658 4205 }
2c07245f 4206
5eddb70b 4207 I915_WRITE(reg, temp);
6be4a607 4208 }
b52eb4dc 4209
b8a4f404 4210 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4211}
4212
1507e5bd
PZ		 4213static void lpt_pch_enable(struct drm_crtc *crtc)
4214{
4215 struct drm_device *dev = crtc->dev;
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4218 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4219
ab9412ba 4220 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4221
8c52b5e8 4222 lpt_program_iclkip(crtc);
1507e5bd 4223
0540e488 4224 /* Set transcoder timing. */
275f01b2 4225 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4226
937bb610 4227 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4228}
4229
716c2e55 4230void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4231{
e2b78267 4232 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4233
4234 if (pll == NULL)
4235 return;
4236
3e369b76 4237 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4238 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4239 return;
4240 }
4241
3e369b76
ACO		 4242 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4243 if (pll->config.crtc_mask == 0) {
f4a091c7
SV		 4244 WARN_ON(pll->on);
4245 WARN_ON(pll->active);
4246 }
4247
6e3c9717 4248 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4249}
4250
190f68c5
ACO		 4251struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4252 struct intel_crtc_state *crtc_state)
ee7b9f93 4253{
e2b78267 4254 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4255 struct intel_shared_dpll *pll;
e2b78267 4256 enum intel_dpll_id i;
ee7b9f93 4257
98b6bd99
SV		 4258 if (HAS_PCH_IBX(dev_priv->dev)) {
4259 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4260 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4261 pll = &dev_priv->shared_dplls[i];
98b6bd99 4262
46edb027
SV		 4263 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4264 crtc->base.base.id, pll->name);
98b6bd99 4265
8bd31e67 4266 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4267
98b6bd99
SV		 4268 goto found;
4269 }
4270
bcddf610
S		 4271 if (IS_BROXTON(dev_priv->dev)) {
4272 /* PLL is attached to port in bxt */
4273 struct intel_encoder *encoder;
4274 struct intel_digital_port *intel_dig_port;
4275
4276 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4277 if (WARN_ON(!encoder))
4278 return NULL;
4279
4280 intel_dig_port = enc_to_dig_port(&encoder->base);
4281 /* 1:1 mapping between ports and PLLs */
4282 i = (enum intel_dpll_id)intel_dig_port->port;
4283 pll = &dev_priv->shared_dplls[i];
4284 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4285 crtc->base.base.id, pll->name);
4286 WARN_ON(pll->new_config->crtc_mask);
4287
4288 goto found;
4289 }
4290
e72f9fbf
SV		 4291 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4292 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4293
4294 /* Only want to check enabled timings first */
8bd31e67 4295 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4296 continue;
4297
190f68c5 4298 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4299 &pll->new_config->hw_state,
4300 sizeof(pll->new_config->hw_state)) == 0) {
4301 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4302 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4303 pll->new_config->crtc_mask,
4304 pll->active);
ee7b9f93
JB		 4305 goto found;
4306 }
4307 }
4308
4309 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
SV		 4310 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4311 pll = &dev_priv->shared_dplls[i];
8bd31e67 4312 if (pll->new_config->crtc_mask == 0) {
46edb027
SV		 4313 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4314 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4315 goto found;
4316 }
4317 }
4318
4319 return NULL;
4320
4321found:
8bd31e67 4322 if (pll->new_config->crtc_mask == 0)
190f68c5 4323 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4324
190f68c5 4325 crtc_state->shared_dpll = i;
46edb027
SV		 4326 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4327 pipe_name(crtc->pipe));
ee7b9f93 4328
8bd31e67 4329 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4330
ee7b9f93
JB		 4331 return pll;
4332}
4333
8bd31e67
ACO		 4334/**
4335 * intel_shared_dpll_start_config - start a new PLL staged config
4336 * @dev_priv: DRM device
4337 * @clear_pipes: mask of pipes that will have their PLLs freed
4338 *
4339 * Starts a new PLL staged config, copying the current config but
4340 * releasing the references of pipes specified in clear_pipes.
4341 */
4342static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4343 unsigned clear_pipes)
4344{
4345 struct intel_shared_dpll *pll;
4346 enum intel_dpll_id i;
4347
4348 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4349 pll = &dev_priv->shared_dplls[i];
4350
4351 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4352 GFP_KERNEL);
4353 if (!pll->new_config)
4354 goto cleanup;
4355
4356 pll->new_config->crtc_mask &= ~clear_pipes;
4357 }
4358
4359 return 0;
4360
4361cleanup:
4362 while (--i >= 0) {
4363 pll = &dev_priv->shared_dplls[i];
f354d733 4364 kfree(pll->new_config);
8bd31e67
ACO		 4365 pll->new_config = NULL;
4366 }
4367
4368 return -ENOMEM;
4369}
4370
4371static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4372{
4373 struct intel_shared_dpll *pll;
4374 enum intel_dpll_id i;
4375
4376 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4377 pll = &dev_priv->shared_dplls[i];
4378
4379 WARN_ON(pll->new_config == &pll->config);
4380
4381 pll->config = *pll->new_config;
4382 kfree(pll->new_config);
4383 pll->new_config = NULL;
4384 }
4385}
4386
4387static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4388{
4389 struct intel_shared_dpll *pll;
4390 enum intel_dpll_id i;
4391
4392 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4393 pll = &dev_priv->shared_dplls[i];
4394
4395 WARN_ON(pll->new_config == &pll->config);
4396
4397 kfree(pll->new_config);
4398 pll->new_config = NULL;
4399 }
4400}
4401
a1520318 4402static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4403{
4404 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4405 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4406 u32 temp;
4407
4408 temp = I915_READ(dslreg);
4409 udelay(500);
4410 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4411 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4412 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4413 }
4414}
4415
a1b2278e
CK		 4416/**
4417 * skl_update_scaler_users - Stages update to crtc's scaler state
4418 * @intel_crtc: crtc
4419 * @crtc_state: crtc_state
4420 * @plane: plane (NULL indicates crtc is requesting update)
4421 * @plane_state: plane's state
4422 * @force_detach: request unconditional detachment of scaler
4423 *
4424 * This function updates scaler state for requested plane or crtc.
4425 * To request scaler usage update for a plane, caller shall pass plane pointer.
4426 * To request scaler usage update for crtc, caller shall pass plane pointer
4427 * as NULL.
4428 *
4429 * Return
4430 * 0 - scaler_usage updated successfully
4431 * error - requested scaling cannot be supported or other error condition
4432 */
4433int
4434skl_update_scaler_users(
4435 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4436 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4437 int force_detach)
4438{
4439 int need_scaling;
4440 int idx;
4441 int src_w, src_h, dst_w, dst_h;
4442 int *scaler_id;
4443 struct drm_framebuffer *fb;
4444 struct intel_crtc_scaler_state *scaler_state;
6156a456 4445 unsigned int rotation;
a1b2278e
CK		 4446
4447 if (!intel_crtc || !crtc_state)
4448 return 0;
4449
4450 scaler_state = &crtc_state->scaler_state;
4451
4452 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4453 fb = intel_plane ? plane_state->base.fb : NULL;
4454
4455 if (intel_plane) {
4456 src_w = drm_rect_width(&plane_state->src) >> 16;
4457 src_h = drm_rect_height(&plane_state->src) >> 16;
4458 dst_w = drm_rect_width(&plane_state->dst);
4459 dst_h = drm_rect_height(&plane_state->dst);
4460 scaler_id = &plane_state->scaler_id;
6156a456 4461 rotation = plane_state->base.rotation;
a1b2278e
CK		 4462 } else {
4463 struct drm_display_mode *adjusted_mode =
4464 &crtc_state->base.adjusted_mode;
4465 src_w = crtc_state->pipe_src_w;
4466 src_h = crtc_state->pipe_src_h;
4467 dst_w = adjusted_mode->hdisplay;
4468 dst_h = adjusted_mode->vdisplay;
4469 scaler_id = &scaler_state->scaler_id;
6156a456 4470 rotation = DRM_ROTATE_0;
a1b2278e 4471 }
6156a456
CK		 4472
4473 need_scaling = intel_rotation_90_or_270(rotation) ?
4474 (src_h != dst_w || src_w != dst_h):
4475 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4476
4477 /*
4478 * if plane is being disabled or scaler is no more required or force detach
4479 * - free scaler binded to this plane/crtc
4480 * - in order to do this, update crtc->scaler_usage
4481 *
4482 * Here scaler state in crtc_state is set free so that
4483 * scaler can be assigned to other user. Actual register
4484 * update to free the scaler is done in plane/panel-fit programming.
4485 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4486 */
4487 if (force_detach || !need_scaling || (intel_plane &&
4488 (!fb || !plane_state->visible))) {
4489 if (*scaler_id >= 0) {
4490 scaler_state->scaler_users &= ~(1 << idx);
4491 scaler_state->scalers[*scaler_id].in_use = 0;
4492
4493 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4494 "crtc_state = %p scaler_users = 0x%x\n",
4495 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4496 intel_plane ? intel_plane->base.base.id :
4497 intel_crtc->base.base.id, crtc_state,
4498 scaler_state->scaler_users);
4499 *scaler_id = -1;
4500 }
4501 return 0;
4502 }
4503
4504 /* range checks */
4505 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4506 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4507
4508 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4509 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4510 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4511 "size is out of scaler range\n",
4512 intel_plane ? "PLANE" : "CRTC",
4513 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4514 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4515 return -EINVAL;
4516 }
4517
4518 /* check colorkey */
4519 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4520 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4521 intel_plane->base.base.id);
4522 return -EINVAL;
4523 }
4524
4525 /* Check src format */
4526 if (intel_plane) {
4527 switch (fb->pixel_format) {
4528 case DRM_FORMAT_RGB565:
4529 case DRM_FORMAT_XBGR8888:
4530 case DRM_FORMAT_XRGB8888:
4531 case DRM_FORMAT_ABGR8888:
4532 case DRM_FORMAT_ARGB8888:
4533 case DRM_FORMAT_XRGB2101010:
4534 case DRM_FORMAT_ARGB2101010:
4535 case DRM_FORMAT_XBGR2101010:
4536 case DRM_FORMAT_ABGR2101010:
4537 case DRM_FORMAT_YUYV:
4538 case DRM_FORMAT_YVYU:
4539 case DRM_FORMAT_UYVY:
4540 case DRM_FORMAT_VYUY:
4541 break;
4542 default:
4543 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4544 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4545 return -EINVAL;
4546 }
4547 }
4548
4549 /* mark this plane as a scaler user in crtc_state */
4550 scaler_state->scaler_users |= (1 << idx);
4551 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4552 "crtc_state = %p scaler_users = 0x%x\n",
4553 intel_plane ? "PLANE" : "CRTC",
4554 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4555 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4556 return 0;
4557}
4558
4559static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4560{
4561 struct drm_device *dev = crtc->base.dev;
4562 struct drm_i915_private *dev_priv = dev->dev_private;
4563 int pipe = crtc->pipe;
a1b2278e
CK		 4564 struct intel_crtc_scaler_state *scaler_state =
4565 &crtc->config->scaler_state;
4566
4567 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4568
4569 /* To update pfit, first update scaler state */
4570 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4571 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4572 skl_detach_scalers(crtc);
4573 if (!enable)
4574 return;
bd2e244f 4575
6e3c9717 4576 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4577 int id;
4578
4579 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4580 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4581 return;
4582 }
4583
4584 id = scaler_state->scaler_id;
4585 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4586 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4587 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4588 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4589
4590 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4591 }
4592}
4593
b074cec8
JB		 4594static void ironlake_pfit_enable(struct intel_crtc *crtc)
4595{
4596 struct drm_device *dev = crtc->base.dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 int pipe = crtc->pipe;
4599
6e3c9717 4600 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4601 /* Force use of hard-coded filter coefficients
4602 * as some pre-programmed values are broken,
4603 * e.g. x201.
4604 */
4605 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4606 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4607 PF_PIPE_SEL_IVB(pipe));
4608 else
4609 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4610 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4611 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4612 }
4613}
4614
4a3b8769 4615static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4616{
4617 struct drm_device *dev = crtc->dev;
4618 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4619 struct drm_plane *plane;
bb53d4ae
VS		 4620 struct intel_plane *intel_plane;
4621
af2b653b
MR		 4622 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4623 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4624 if (intel_plane->pipe == pipe)
4625 intel_plane_restore(&intel_plane->base);
af2b653b 4626 }
bb53d4ae
VS		 4627}
4628
20bc8673 4629void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4630{
cea165c3
VS		 4631 struct drm_device *dev = crtc->base.dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4633
6e3c9717 4634 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4635 return;
4636
cea165c3
VS		 4637 /* We can only enable IPS after we enable a plane and wait for a vblank */
4638 intel_wait_for_vblank(dev, crtc->pipe);
4639
d77e4531 4640 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4641 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4642 mutex_lock(&dev_priv->rps.hw_lock);
4643 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4644 mutex_unlock(&dev_priv->rps.hw_lock);
4645 /* Quoting Art Runyan: "its not safe to expect any particular
4646 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4647 * mailbox." Moreover, the mailbox may return a bogus state,
4648 * so we need to just enable it and continue on.
2a114cc1
BW		 4649 */
4650 } else {
4651 I915_WRITE(IPS_CTL, IPS_ENABLE);
4652 /* The bit only becomes 1 in the next vblank, so this wait here
4653 * is essentially intel_wait_for_vblank. If we don't have this
4654 * and don't wait for vblanks until the end of crtc_enable, then
4655 * the HW state readout code will complain that the expected
4656 * IPS_CTL value is not the one we read. */
4657 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4658 DRM_ERROR("Timed out waiting for IPS enable\n");
4659 }
d77e4531
PZ		 4660}
4661
20bc8673 4662void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4663{
4664 struct drm_device *dev = crtc->base.dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
4666
6e3c9717 4667 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4668 return;
4669
4670 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4671 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4672 mutex_lock(&dev_priv->rps.hw_lock);
4673 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4674 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4675 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4676 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4677 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4678 } else {
2a114cc1 4679 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4680 POSTING_READ(IPS_CTL);
4681 }
d77e4531
PZ		 4682
4683 /* We need to wait for a vblank before we can disable the plane. */
4684 intel_wait_for_vblank(dev, crtc->pipe);
4685}
4686
4687/** Loads the palette/gamma unit for the CRTC with the prepared values */
4688static void intel_crtc_load_lut(struct drm_crtc *crtc)
4689{
4690 struct drm_device *dev = crtc->dev;
4691 struct drm_i915_private *dev_priv = dev->dev_private;
4692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4693 enum pipe pipe = intel_crtc->pipe;
4694 int palreg = PALETTE(pipe);
4695 int i;
4696 bool reenable_ips = false;
4697
4698 /* The clocks have to be on to load the palette. */
83d65738 4699 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4700 return;
4701
50360403 4702 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4703 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4704 assert_dsi_pll_enabled(dev_priv);
4705 else
4706 assert_pll_enabled(dev_priv, pipe);
4707 }
4708
4709 /* use legacy palette for Ironlake */
7a1db49a 4710 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4711 palreg = LGC_PALETTE(pipe);
4712
4713 /* Workaround : Do not read or write the pipe palette/gamma data while
4714 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4715 */
6e3c9717 4716 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4717 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4718 GAMMA_MODE_MODE_SPLIT)) {
4719 hsw_disable_ips(intel_crtc);
4720 reenable_ips = true;
4721 }
4722
4723 for (i = 0; i < 256; i++) {
4724 I915_WRITE(palreg + 4 * i,
4725 (intel_crtc->lut_r[i] << 16) |
4726 (intel_crtc->lut_g[i] << 8) |
4727 intel_crtc->lut_b[i]);
4728 }
4729
4730 if (reenable_ips)
4731 hsw_enable_ips(intel_crtc);
4732}
4733
7cac945f 4734static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4735{
7cac945f 4736 if (intel_crtc->overlay) {
d3eedb1a
VS		 4737 struct drm_device *dev = intel_crtc->base.dev;
4738 struct drm_i915_private *dev_priv = dev->dev_private;
4739
4740 mutex_lock(&dev->struct_mutex);
4741 dev_priv->mm.interruptible = false;
4742 (void) intel_overlay_switch_off(intel_crtc->overlay);
4743 dev_priv->mm.interruptible = true;
4744 mutex_unlock(&dev->struct_mutex);
4745 }
4746
4747 /* Let userspace switch the overlay on again. In most cases userspace
4748 * has to recompute where to put it anyway.
4749 */
4750}
4751
87d4300a
ML		 4752/**
4753 * intel_post_enable_primary - Perform operations after enabling primary plane
4754 * @crtc: the CRTC whose primary plane was just enabled
4755 *
4756 * Performs potentially sleeping operations that must be done after the primary
4757 * plane is enabled, such as updating FBC and IPS. Note that this may be
4758 * called due to an explicit primary plane update, or due to an implicit
4759 * re-enable that is caused when a sprite plane is updated to no longer
4760 * completely hide the primary plane.
4761 */
4762static void
4763intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4764{
4765 struct drm_device *dev = crtc->dev;
87d4300a 4766 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4768 int pipe = intel_crtc->pipe;
a5c4d7bc 4769
87d4300a
ML		 4770 /*
4771 * BDW signals flip done immediately if the plane
4772 * is disabled, even if the plane enable is already
4773 * armed to occur at the next vblank :(
4774 */
4775 if (IS_BROADWELL(dev))
4776 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4777
87d4300a
ML		 4778 /*
4779 * FIXME IPS should be fine as long as one plane is
4780 * enabled, but in practice it seems to have problems
4781 * when going from primary only to sprite only and vice
4782 * versa.
4783 */
a5c4d7bc
VS		 4784 hsw_enable_ips(intel_crtc);
4785
4786 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4787 intel_fbc_update(dev);
a5c4d7bc 4788 mutex_unlock(&dev->struct_mutex);
f99d7069
SV		 4789
4790 /*
87d4300a
ML		 4791 * Gen2 reports pipe underruns whenever all planes are disabled.
4792 * So don't enable underrun reporting before at least some planes
4793 * are enabled.
4794 * FIXME: Need to fix the logic to work when we turn off all planes
4795 * but leave the pipe running.
f99d7069 4796 */
87d4300a
ML		 4797 if (IS_GEN2(dev))
4798 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4799
4800 /* Underruns don't raise interrupts, so check manually. */
4801 if (HAS_GMCH_DISPLAY(dev))
4802 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4803}
4804
87d4300a
ML		 4805/**
4806 * intel_pre_disable_primary - Perform operations before disabling primary plane
4807 * @crtc: the CRTC whose primary plane is to be disabled
4808 *
4809 * Performs potentially sleeping operations that must be done before the
4810 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4811 * be called due to an explicit primary plane update, or due to an implicit
4812 * disable that is caused when a sprite plane completely hides the primary
4813 * plane.
4814 */
4815static void
4816intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4817{
4818 struct drm_device *dev = crtc->dev;
4819 struct drm_i915_private *dev_priv = dev->dev_private;
4820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4821 int pipe = intel_crtc->pipe;
a5c4d7bc 4822
87d4300a
ML		 4823 /*
4824 * Gen2 reports pipe underruns whenever all planes are disabled.
4825 * So diasble underrun reporting before all the planes get disabled.
4826 * FIXME: Need to fix the logic to work when we turn off all planes
4827 * but leave the pipe running.
4828 */
4829 if (IS_GEN2(dev))
4830 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4831
87d4300a
ML		 4832 /*
4833 * Vblank time updates from the shadow to live plane control register
4834 * are blocked if the memory self-refresh mode is active at that
4835 * moment. So to make sure the plane gets truly disabled, disable
4836 * first the self-refresh mode. The self-refresh enable bit in turn
4837 * will be checked/applied by the HW only at the next frame start
4838 * event which is after the vblank start event, so we need to have a
4839 * wait-for-vblank between disabling the plane and the pipe.
4840 */
4841 if (HAS_GMCH_DISPLAY(dev))
4842 intel_set_memory_cxsr(dev_priv, false);
4843
4844 mutex_lock(&dev->struct_mutex);
e35fef21 4845 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4846 intel_fbc_disable(dev);
87d4300a 4847 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4848
87d4300a
ML		 4849 /*
4850 * FIXME IPS should be fine as long as one plane is
4851 * enabled, but in practice it seems to have problems
4852 * when going from primary only to sprite only and vice
4853 * versa.
4854 */
a5c4d7bc 4855 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4856}
4857
4858static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4859{
87d4300a
ML		 4860 intel_enable_primary_hw_plane(crtc->primary, crtc);
4861 intel_enable_sprite_planes(crtc);
4862 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4863
4864 intel_post_enable_primary(crtc);
4865}
4866
4867static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4868{
4869 struct drm_device *dev = crtc->dev;
4870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4871 struct intel_plane *intel_plane;
4872 int pipe = intel_crtc->pipe;
4873
4874 intel_crtc_wait_for_pending_flips(crtc);
4875
4876 intel_pre_disable_primary(crtc);
a5c4d7bc 4877
7cac945f 4878 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4879 for_each_intel_plane(dev, intel_plane) {
4880 if (intel_plane->pipe == pipe) {
4881 struct drm_crtc *from = intel_plane->base.crtc;
4882
4883 intel_plane->disable_plane(&intel_plane->base,
4884 from ?: crtc, true);
4885 }
4886 }
f98551ae 4887
f99d7069
SV		 4888 /*
4889 * FIXME: Once we grow proper nuclear flip support out of this we need
4890 * to compute the mask of flip planes precisely. For the time being
4891 * consider this a flip to a NULL plane.
4892 */
4893 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4894}
4895
f67a559d
JB		 4896static void ironlake_crtc_enable(struct drm_crtc *crtc)
4897{
4898 struct drm_device *dev = crtc->dev;
4899 struct drm_i915_private *dev_priv = dev->dev_private;
4900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4901 struct intel_encoder *encoder;
f67a559d 4902 int pipe = intel_crtc->pipe;
f67a559d 4903
83d65738 4904 WARN_ON(!crtc->state->enable);
08a48469 4905
f67a559d
JB		 4906 if (intel_crtc->active)
4907 return;
4908
6e3c9717 4909 if (intel_crtc->config->has_pch_encoder)
b14b1055
SV		 4910 intel_prepare_shared_dpll(intel_crtc);
4911
6e3c9717 4912 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4913 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
SV		 4914
4915 intel_set_pipe_timings(intel_crtc);
4916
6e3c9717 4917 if (intel_crtc->config->has_pch_encoder) {
29407aab 4918 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4919 &intel_crtc->config->fdi_m_n, NULL);
29407aab
SV		 4920 }
4921
4922 ironlake_set_pipeconf(crtc);
4923
f67a559d 4924 intel_crtc->active = true;
8664281b 4925
a72e4c9f
SV		 4926 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4927 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4928
f6736a1a 4929 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
SV		 4930 if (encoder->pre_enable)
4931 encoder->pre_enable(encoder);
f67a559d 4932
6e3c9717 4933 if (intel_crtc->config->has_pch_encoder) {
fff367c7
SV		 4934 /* Note: FDI PLL enabling _must_ be done before we enable the
4935 * cpu pipes, hence this is separate from all the other fdi/pch
4936 * enabling. */
88cefb6c 4937 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
SV		 4938 } else {
4939 assert_fdi_tx_disabled(dev_priv, pipe);
4940 assert_fdi_rx_disabled(dev_priv, pipe);
4941 }
f67a559d 4942
b074cec8 4943 ironlake_pfit_enable(intel_crtc);
f67a559d 4944
9c54c0dd
JB		 4945 /*
4946 * On ILK+ LUT must be loaded before the pipe is running but with
4947 * clocks enabled
4948 */
4949 intel_crtc_load_lut(crtc);
4950
f37fcc2a 4951 intel_update_watermarks(crtc);
e1fdc473 4952 intel_enable_pipe(intel_crtc);
f67a559d 4953
6e3c9717 4954 if (intel_crtc->config->has_pch_encoder)
f67a559d 4955 ironlake_pch_enable(crtc);
c98e9dcf 4956
f9b61ff6
SV		 4957 assert_vblank_disabled(crtc);
4958 drm_crtc_vblank_on(crtc);
4959
fa5c73b1
SV		 4960 for_each_encoder_on_crtc(dev, crtc, encoder)
4961 encoder->enable(encoder);
61b77ddd
SV		 4962
4963 if (HAS_PCH_CPT(dev))
a1520318 4964 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4965}
4966
42db64ef
PZ		 4967/* IPS only exists on ULT machines and is tied to pipe A. */
4968static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4969{
f5adf94e 4970 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4971}
4972
e4916946
PZ		 4973/*
4974 * This implements the workaround described in the "notes" section of the mode
4975 * set sequence documentation. When going from no pipes or single pipe to
4976 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4977 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4978 */
4979static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4980{
4981 struct drm_device *dev = crtc->base.dev;
4982 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4983
4984 /* We want to get the other_active_crtc only if there's only 1 other
4985 * active crtc. */
d3fcc808 4986 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4987 if (!crtc_it->active || crtc_it == crtc)
4988 continue;
4989
4990 if (other_active_crtc)
4991 return;
4992
4993 other_active_crtc = crtc_it;
4994 }
4995 if (!other_active_crtc)
4996 return;
4997
4998 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4999 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5000}
5001
4f771f10
PZ		 5002static void haswell_crtc_enable(struct drm_crtc *crtc)
5003{
5004 struct drm_device *dev = crtc->dev;
5005 struct drm_i915_private *dev_priv = dev->dev_private;
5006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5007 struct intel_encoder *encoder;
5008 int pipe = intel_crtc->pipe;
4f771f10 5009
83d65738 5010 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 5011
5012 if (intel_crtc->active)
5013 return;
5014
df8ad70c
SV		 5015 if (intel_crtc_to_shared_dpll(intel_crtc))
5016 intel_enable_shared_dpll(intel_crtc);
5017
6e3c9717 5018 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5019 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
SV		 5020
5021 intel_set_pipe_timings(intel_crtc);
5022
6e3c9717
ACO		 5023 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5024 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5025 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5026 }
5027
6e3c9717 5028 if (intel_crtc->config->has_pch_encoder) {
229fca97 5029 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5030 &intel_crtc->config->fdi_m_n, NULL);
229fca97
SV		 5031 }
5032
5033 haswell_set_pipeconf(crtc);
5034
5035 intel_set_pipe_csc(crtc);
5036
4f771f10 5037 intel_crtc->active = true;
8664281b 5038
a72e4c9f 5039 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5040 for_each_encoder_on_crtc(dev, crtc, encoder)
5041 if (encoder->pre_enable)
5042 encoder->pre_enable(encoder);
5043
6e3c9717 5044 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
SV		 5045 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5046 true);
4fe9467d
ID		 5047 dev_priv->display.fdi_link_train(crtc);
5048 }
5049
1f544388 5050 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5051
ff6d9f55 5052 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5053 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5054 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5055 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5056 else
5057 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5058
5059 /*
5060 * On ILK+ LUT must be loaded before the pipe is running but with
5061 * clocks enabled
5062 */
5063 intel_crtc_load_lut(crtc);
5064
1f544388 5065 intel_ddi_set_pipe_settings(crtc);
8228c251 5066 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5067
f37fcc2a 5068 intel_update_watermarks(crtc);
e1fdc473 5069 intel_enable_pipe(intel_crtc);
42db64ef 5070
6e3c9717 5071 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5072 lpt_pch_enable(crtc);
4f771f10 5073
6e3c9717 5074 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5075 intel_ddi_set_vc_payload_alloc(crtc, true);
5076
f9b61ff6
SV		 5077 assert_vblank_disabled(crtc);
5078 drm_crtc_vblank_on(crtc);
5079
8807e55b 5080 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5081 encoder->enable(encoder);
8807e55b
JN		 5082 intel_opregion_notify_encoder(encoder, true);
5083 }
4f771f10 5084
e4916946
PZ		 5085 /* If we change the relative order between pipe/planes enabling, we need
5086 * to change the workaround. */
5087 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5088}
5089
3f8dce3a
SV		 5090static void ironlake_pfit_disable(struct intel_crtc *crtc)
5091{
5092 struct drm_device *dev = crtc->base.dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 int pipe = crtc->pipe;
5095
5096 /* To avoid upsetting the power well on haswell only disable the pfit if
5097 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5098 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
SV		 5099 I915_WRITE(PF_CTL(pipe), 0);
5100 I915_WRITE(PF_WIN_POS(pipe), 0);
5101 I915_WRITE(PF_WIN_SZ(pipe), 0);
5102 }
5103}
5104
6be4a607
JB		 5105static void ironlake_crtc_disable(struct drm_crtc *crtc)
5106{
5107 struct drm_device *dev = crtc->dev;
5108 struct drm_i915_private *dev_priv = dev->dev_private;
5109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5110 struct intel_encoder *encoder;
6be4a607 5111 int pipe = intel_crtc->pipe;
5eddb70b 5112 u32 reg, temp;
b52eb4dc 5113
f7abfe8b
CW		 5114 if (!intel_crtc->active)
5115 return;
5116
ea9d758d
SV		 5117 for_each_encoder_on_crtc(dev, crtc, encoder)
5118 encoder->disable(encoder);
5119
f9b61ff6
SV		 5120 drm_crtc_vblank_off(crtc);
5121 assert_vblank_disabled(crtc);
5122
6e3c9717 5123 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5124 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5125
575f7ab7 5126 intel_disable_pipe(intel_crtc);
32f9d658 5127
3f8dce3a 5128 ironlake_pfit_disable(intel_crtc);
2c07245f 5129
bf49ec8c
SV		 5130 for_each_encoder_on_crtc(dev, crtc, encoder)
5131 if (encoder->post_disable)
5132 encoder->post_disable(encoder);
2c07245f 5133
6e3c9717 5134 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5135 ironlake_fdi_disable(crtc);
913d8d11 5136
d925c59a 5137 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5138
d925c59a
SV		 5139 if (HAS_PCH_CPT(dev)) {
5140 /* disable TRANS_DP_CTL */
5141 reg = TRANS_DP_CTL(pipe);
5142 temp = I915_READ(reg);
5143 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5144 TRANS_DP_PORT_SEL_MASK);
5145 temp |= TRANS_DP_PORT_SEL_NONE;
5146 I915_WRITE(reg, temp);
5147
5148 /* disable DPLL_SEL */
5149 temp = I915_READ(PCH_DPLL_SEL);
11887397 5150 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5151 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5152 }
e3421a18 5153
d925c59a 5154 /* disable PCH DPLL */
e72f9fbf 5155 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5156
d925c59a
SV		 5157 ironlake_fdi_pll_disable(intel_crtc);
5158 }
6b383a7f 5159
f7abfe8b 5160 intel_crtc->active = false;
46ba614c 5161 intel_update_watermarks(crtc);
d1ebd816
BW		 5162
5163 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5164 intel_fbc_update(dev);
d1ebd816 5165 mutex_unlock(&dev->struct_mutex);
6be4a607 5166}
1b3c7a47 5167
4f771f10 5168static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5169{
4f771f10
PZ		 5170 struct drm_device *dev = crtc->dev;
5171 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5173 struct intel_encoder *encoder;
6e3c9717 5174 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5175
4f771f10
PZ		 5176 if (!intel_crtc->active)
5177 return;
5178
8807e55b
JN		 5179 for_each_encoder_on_crtc(dev, crtc, encoder) {
5180 intel_opregion_notify_encoder(encoder, false);
4f771f10 5181 encoder->disable(encoder);
8807e55b 5182 }
4f771f10 5183
f9b61ff6
SV		 5184 drm_crtc_vblank_off(crtc);
5185 assert_vblank_disabled(crtc);
5186
6e3c9717 5187 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
SV		 5188 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5189 false);
575f7ab7 5190 intel_disable_pipe(intel_crtc);
4f771f10 5191
6e3c9717 5192 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5193 intel_ddi_set_vc_payload_alloc(crtc, false);
5194
ad80a810 5195 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5196
ff6d9f55 5197 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5198 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5199 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5200 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5201 else
5202 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5203
1f544388 5204 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5205
6e3c9717 5206 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5207 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5208 intel_ddi_fdi_disable(crtc);
83616634 5209 }
4f771f10 5210
97b040aa
ID		 5211 for_each_encoder_on_crtc(dev, crtc, encoder)
5212 if (encoder->post_disable)
5213 encoder->post_disable(encoder);
5214
4f771f10 5215 intel_crtc->active = false;
46ba614c 5216 intel_update_watermarks(crtc);
4f771f10
PZ		 5217
5218 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5219 intel_fbc_update(dev);
4f771f10 5220 mutex_unlock(&dev->struct_mutex);
df8ad70c
SV		 5221
5222 if (intel_crtc_to_shared_dpll(intel_crtc))
5223 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5224}
5225
ee7b9f93
JB		 5226static void ironlake_crtc_off(struct drm_crtc *crtc)
5227{
5228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5229 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5230}
5231
6441ab5f 5232
2dd24552
JB		 5233static void i9xx_pfit_enable(struct intel_crtc *crtc)
5234{
5235 struct drm_device *dev = crtc->base.dev;
5236 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5237 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5238
681a8504 5239 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5240 return;
5241
2dd24552 5242 /*
c0b03411
SV		 5243 * The panel fitter should only be adjusted whilst the pipe is disabled,
5244 * according to register description and PRM.
2dd24552 5245 */
c0b03411
SV		 5246 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5247 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5248
b074cec8
JB		 5249 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5250 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
SV		 5251
5252 /* Border color in case we don't scale up to the full screen. Black by
5253 * default, change to something else for debugging. */
5254 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5255}
5256
d05410f9
DA		 5257static enum intel_display_power_domain port_to_power_domain(enum port port)
5258{
5259 switch (port) {
5260 case PORT_A:
5261 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5262 case PORT_B:
5263 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5264 case PORT_C:
5265 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5266 case PORT_D:
5267 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5268 default:
5269 WARN_ON_ONCE(1);
5270 return POWER_DOMAIN_PORT_OTHER;
5271 }
5272}
5273
77d22dca
ID		 5274#define for_each_power_domain(domain, mask) \
5275 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5276 if ((1 << (domain)) & (mask))
5277
319be8ae
ID		 5278enum intel_display_power_domain
5279intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5280{
5281 struct drm_device *dev = intel_encoder->base.dev;
5282 struct intel_digital_port *intel_dig_port;
5283
5284 switch (intel_encoder->type) {
5285 case INTEL_OUTPUT_UNKNOWN:
5286 /* Only DDI platforms should ever use this output type */
5287 WARN_ON_ONCE(!HAS_DDI(dev));
5288 case INTEL_OUTPUT_DISPLAYPORT:
5289 case INTEL_OUTPUT_HDMI:
5290 case INTEL_OUTPUT_EDP:
5291 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5292 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5293 case INTEL_OUTPUT_DP_MST:
5294 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5295 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5296 case INTEL_OUTPUT_ANALOG:
5297 return POWER_DOMAIN_PORT_CRT;
5298 case INTEL_OUTPUT_DSI:
5299 return POWER_DOMAIN_PORT_DSI;
5300 default:
5301 return POWER_DOMAIN_PORT_OTHER;
5302 }
5303}
5304
5305static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5306{
319be8ae
ID		 5307 struct drm_device *dev = crtc->dev;
5308 struct intel_encoder *intel_encoder;
5309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5310 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5311 unsigned long mask;
5312 enum transcoder transcoder;
5313
5314 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5315
5316 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5317 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5318 if (intel_crtc->config->pch_pfit.enabled ||
5319 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5320 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5321
319be8ae
ID		 5322 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5323 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5324
77d22dca
ID		 5325 return mask;
5326}
5327
679dacd4 5328static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5329{
679dacd4 5330 struct drm_device *dev = state->dev;
77d22dca
ID		 5331 struct drm_i915_private *dev_priv = dev->dev_private;
5332 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5333 struct intel_crtc *crtc;
5334
5335 /*
5336 * First get all needed power domains, then put all unneeded, to avoid
5337 * any unnecessary toggling of the power wells.
5338 */
d3fcc808 5339 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5340 enum intel_display_power_domain domain;
5341
83d65738 5342 if (!crtc->base.state->enable)
77d22dca
ID		 5343 continue;
5344
319be8ae 5345 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5346
5347 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5348 intel_display_power_get(dev_priv, domain);
5349 }
5350
50f6e502 5351 if (dev_priv->display.modeset_global_resources)
679dacd4 5352 dev_priv->display.modeset_global_resources(state);
50f6e502 5353
d3fcc808 5354 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5355 enum intel_display_power_domain domain;
5356
5357 for_each_power_domain(domain, crtc->enabled_power_domains)
5358 intel_display_power_put(dev_priv, domain);
5359
5360 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5361 }
5362
5363 intel_display_set_init_power(dev_priv, false);
5364}
5365
f8437dd1
VK		 5366void broxton_set_cdclk(struct drm_device *dev, int frequency)
5367{
5368 struct drm_i915_private *dev_priv = dev->dev_private;
5369 uint32_t divider;
5370 uint32_t ratio;
5371 uint32_t current_freq;
5372 int ret;
5373
5374 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5375 switch (frequency) {
5376 case 144000:
5377 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5378 ratio = BXT_DE_PLL_RATIO(60);
5379 break;
5380 case 288000:
5381 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5382 ratio = BXT_DE_PLL_RATIO(60);
5383 break;
5384 case 384000:
5385 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5386 ratio = BXT_DE_PLL_RATIO(60);
5387 break;
5388 case 576000:
5389 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5390 ratio = BXT_DE_PLL_RATIO(60);
5391 break;
5392 case 624000:
5393 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5394 ratio = BXT_DE_PLL_RATIO(65);
5395 break;
5396 case 19200:
5397 /*
5398 * Bypass frequency with DE PLL disabled. Init ratio, divider
5399 * to suppress GCC warning.
5400 */
5401 ratio = 0;
5402 divider = 0;
5403 break;
5404 default:
5405 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5406
5407 return;
5408 }
5409
5410 mutex_lock(&dev_priv->rps.hw_lock);
5411 /* Inform power controller of upcoming frequency change */
5412 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5413 0x80000000);
5414 mutex_unlock(&dev_priv->rps.hw_lock);
5415
5416 if (ret) {
5417 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5418 ret, frequency);
5419 return;
5420 }
5421
5422 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5423 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5424 current_freq = current_freq * 500 + 1000;
5425
5426 /*
5427 * DE PLL has to be disabled when
5428 * - setting to 19.2MHz (bypass, PLL isn't used)
5429 * - before setting to 624MHz (PLL needs toggling)
5430 * - before setting to any frequency from 624MHz (PLL needs toggling)
5431 */
5432 if (frequency == 19200 || frequency == 624000 ||
5433 current_freq == 624000) {
5434 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5435 /* Timeout 200us */
5436 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5437 1))
5438 DRM_ERROR("timout waiting for DE PLL unlock\n");
5439 }
5440
5441 if (frequency != 19200) {
5442 uint32_t val;
5443
5444 val = I915_READ(BXT_DE_PLL_CTL);
5445 val &= ~BXT_DE_PLL_RATIO_MASK;
5446 val |= ratio;
5447 I915_WRITE(BXT_DE_PLL_CTL, val);
5448
5449 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5450 /* Timeout 200us */
5451 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5452 DRM_ERROR("timeout waiting for DE PLL lock\n");
5453
5454 val = I915_READ(CDCLK_CTL);
5455 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5456 val |= divider;
5457 /*
5458 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5459 * enable otherwise.
5460 */
5461 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5462 if (frequency >= 500000)
5463 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5464
5465 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5466 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5467 val |= (frequency - 1000) / 500;
5468 I915_WRITE(CDCLK_CTL, val);
5469 }
5470
5471 mutex_lock(&dev_priv->rps.hw_lock);
5472 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5473 DIV_ROUND_UP(frequency, 25000));
5474 mutex_unlock(&dev_priv->rps.hw_lock);
5475
5476 if (ret) {
5477 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5478 ret, frequency);
5479 return;
5480 }
5481
5482 dev_priv->cdclk_freq = frequency;
5483}
5484
5485void broxton_init_cdclk(struct drm_device *dev)
5486{
5487 struct drm_i915_private *dev_priv = dev->dev_private;
5488 uint32_t val;
5489
5490 /*
5491 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5492 * or else the reset will hang because there is no PCH to respond.
5493 * Move the handshake programming to initialization sequence.
5494 * Previously was left up to BIOS.
5495 */
5496 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5497 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5498 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5499
5500 /* Enable PG1 for cdclk */
5501 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5502
5503 /* check if cd clock is enabled */
5504 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5505 DRM_DEBUG_KMS("Display already initialized\n");
5506 return;
5507 }
5508
5509 /*
5510 * FIXME:
5511 * - The initial CDCLK needs to be read from VBT.
5512 * Need to make this change after VBT has changes for BXT.
5513 * - check if setting the max (or any) cdclk freq is really necessary
5514 * here, it belongs to modeset time
5515 */
5516 broxton_set_cdclk(dev, 624000);
5517
5518 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5519 POSTING_READ(DBUF_CTL);
5520
f8437dd1
VK		 5521 udelay(10);
5522
5523 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5524 DRM_ERROR("DBuf power enable timeout!\n");
5525}
5526
5527void broxton_uninit_cdclk(struct drm_device *dev)
5528{
5529 struct drm_i915_private *dev_priv = dev->dev_private;
5530
5531 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5532 POSTING_READ(DBUF_CTL);
5533
f8437dd1
VK		 5534 udelay(10);
5535
5536 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5537 DRM_ERROR("DBuf power disable timeout!\n");
5538
5539 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5540 broxton_set_cdclk(dev, 19200);
5541
5542 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5543}
5544
dfcab17e 5545/* returns HPLL frequency in kHz */
f8bf63fd 5546static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5547{
586f49dc 5548 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5549
586f49dc
JB		 5550 /* Obtain SKU information */
5551 mutex_lock(&dev_priv->dpio_lock);
5552 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5553 CCK_FUSE_HPLL_FREQ_MASK;
5554 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5555
dfcab17e 5556 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5557}
5558
f8bf63fd
VS		 5559static void vlv_update_cdclk(struct drm_device *dev)
5560{
5561 struct drm_i915_private *dev_priv = dev->dev_private;
5562
164dfd28 5563 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5564 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5565 dev_priv->cdclk_freq);
f8bf63fd
VS		 5566
5567 /*
5568 * Program the gmbus_freq based on the cdclk frequency.
5569 * BSpec erroneously claims we should aim for 4MHz, but
5570 * in fact 1MHz is the correct frequency.
5571 */
164dfd28 5572 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5573}
5574
30a970c6
JB		 5575/* Adjust CDclk dividers to allow high res or save power if possible */
5576static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5577{
5578 struct drm_i915_private *dev_priv = dev->dev_private;
5579 u32 val, cmd;
5580
164dfd28
VK		 5581 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5582 != dev_priv->cdclk_freq);
d60c4473 5583
dfcab17e 5584 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5585 cmd = 2;
dfcab17e 5586 else if (cdclk == 266667)
30a970c6
JB		 5587 cmd = 1;
5588 else
5589 cmd = 0;
5590
5591 mutex_lock(&dev_priv->rps.hw_lock);
5592 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5593 val &= ~DSPFREQGUAR_MASK;
5594 val |= (cmd << DSPFREQGUAR_SHIFT);
5595 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5596 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5597 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5598 50)) {
5599 DRM_ERROR("timed out waiting for CDclk change\n");
5600 }
5601 mutex_unlock(&dev_priv->rps.hw_lock);
5602
dfcab17e 5603 if (cdclk == 400000) {
6bcda4f0 5604 u32 divider;
30a970c6 5605
6bcda4f0 5606 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5607
5608 mutex_lock(&dev_priv->dpio_lock);
5609 /* adjust cdclk divider */
5610 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5611 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5612 val |= divider;
5613 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5614
5615 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5616 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5617 50))
5618 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5619 mutex_unlock(&dev_priv->dpio_lock);
5620 }
5621
5622 mutex_lock(&dev_priv->dpio_lock);
5623 /* adjust self-refresh exit latency value */
5624 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5625 val &= ~0x7f;
5626
5627 /*
5628 * For high bandwidth configs, we set a higher latency in the bunit
5629 * so that the core display fetch happens in time to avoid underruns.
5630 */
dfcab17e 5631 if (cdclk == 400000)
30a970c6
JB		 5632 val |= 4500 / 250; /* 4.5 usec */
5633 else
5634 val |= 3000 / 250; /* 3.0 usec */
5635 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5636 mutex_unlock(&dev_priv->dpio_lock);
5637
f8bf63fd 5638 vlv_update_cdclk(dev);
30a970c6
JB		 5639}
5640
383c5a6a
VS		 5641static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5642{
5643 struct drm_i915_private *dev_priv = dev->dev_private;
5644 u32 val, cmd;
5645
164dfd28
VK		 5646 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5647 != dev_priv->cdclk_freq);
383c5a6a
VS		 5648
5649 switch (cdclk) {
383c5a6a
VS		 5650 case 333333:
5651 case 320000:
383c5a6a 5652 case 266667:
383c5a6a 5653 case 200000:
383c5a6a
VS		 5654 break;
5655 default:
5f77eeb0 5656 MISSING_CASE(cdclk);
383c5a6a
VS		 5657 return;
5658 }
5659
9d0d3fda
VS		 5660 /*
5661 * Specs are full of misinformation, but testing on actual
5662 * hardware has shown that we just need to write the desired
5663 * CCK divider into the Punit register.
5664 */
5665 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5666
383c5a6a
VS		 5667 mutex_lock(&dev_priv->rps.hw_lock);
5668 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5669 val &= ~DSPFREQGUAR_MASK_CHV;
5670 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5671 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5672 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5673 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5674 50)) {
5675 DRM_ERROR("timed out waiting for CDclk change\n");
5676 }
5677 mutex_unlock(&dev_priv->rps.hw_lock);
5678
5679 vlv_update_cdclk(dev);
5680}
5681
30a970c6
JB		 5682static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5683 int max_pixclk)
5684{
6bcda4f0 5685 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5686 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5687
30a970c6
JB		 5688 /*
5689 * Really only a few cases to deal with, as only 4 CDclks are supported:
5690 * 200MHz
5691 * 267MHz
29dc7ef3 5692 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5693 * 400MHz (VLV only)
5694 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5695 * of the lower bin and adjust if needed.
e37c67a1
VS		 5696 *
5697 * We seem to get an unstable or solid color picture at 200MHz.
5698 * Not sure what's wrong. For now use 200MHz only when all pipes
5699 * are off.
30a970c6 5700 */
6cca3195
VS		 5701 if (!IS_CHERRYVIEW(dev_priv) &&
5702 max_pixclk > freq_320*limit/100)
dfcab17e 5703 return 400000;
6cca3195 5704 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5705 return freq_320;
e37c67a1 5706 else if (max_pixclk > 0)
dfcab17e 5707 return 266667;
e37c67a1
VS		 5708 else
5709 return 200000;
30a970c6
JB		 5710}
5711
f8437dd1
VK		 5712static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5713 int max_pixclk)
5714{
5715 /*
5716 * FIXME:
5717 * - remove the guardband, it's not needed on BXT
5718 * - set 19.2MHz bypass frequency if there are no active pipes
5719 */
5720 if (max_pixclk > 576000*9/10)
5721 return 624000;
5722 else if (max_pixclk > 384000*9/10)
5723 return 576000;
5724 else if (max_pixclk > 288000*9/10)
5725 return 384000;
5726 else if (max_pixclk > 144000*9/10)
5727 return 288000;
5728 else
5729 return 144000;
5730}
5731
2f2d7aa1 5732/* compute the max pixel clock for new configuration */
304603f4 5733static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5734{
304603f4 5735 struct drm_device *dev = state->dev;
30a970c6 5736 struct intel_crtc *intel_crtc;
304603f4 5737 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5738 int max_pixclk = 0;
5739
d3fcc808 5740 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5741 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5742 if (IS_ERR(crtc_state))
5743 return PTR_ERR(crtc_state);
5744
5745 if (!crtc_state->base.enable)
5746 continue;
5747
5748 max_pixclk = max(max_pixclk,
5749 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5750 }
5751
5752 return max_pixclk;
5753}
5754
0a9ab303 5755static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5756{
304603f4 5757 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5758 struct drm_crtc *crtc;
5759 struct drm_crtc_state *crtc_state;
304603f4 5760 int max_pixclk = intel_mode_max_pixclk(state);
0a9ab303 5761 int cdclk, i;
30a970c6 5762
304603f4
ACO		 5763 if (max_pixclk < 0)
5764 return max_pixclk;
30a970c6 5765
f8437dd1
VK		 5766 if (IS_VALLEYVIEW(dev_priv))
5767 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5768 else
5769 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5770
5771 if (cdclk == dev_priv->cdclk_freq)
304603f4 5772 return 0;
30a970c6 5773
0a9ab303
ACO		 5774 /* add all active pipes to the state */
5775 for_each_crtc(state->dev, crtc) {
5776 if (!crtc->state->enable)
5777 continue;
5778
5779 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5780 if (IS_ERR(crtc_state))
5781 return PTR_ERR(crtc_state);
5782 }
5783
2f2d7aa1 5784 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5785 for_each_crtc_in_state(state, crtc, crtc_state, i)
5786 if (crtc_state->enable)
5787 crtc_state->mode_changed = true;
304603f4
ACO		 5788
5789 return 0;
30a970c6
JB		 5790}
5791
1e69cd74
VS		 5792static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5793{
5794 unsigned int credits, default_credits;
5795
5796 if (IS_CHERRYVIEW(dev_priv))
5797 default_credits = PFI_CREDIT(12);
5798 else
5799 default_credits = PFI_CREDIT(8);
5800
164dfd28 5801 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5802 /* CHV suggested value is 31 or 63 */
5803 if (IS_CHERRYVIEW(dev_priv))
5804 credits = PFI_CREDIT_31;
5805 else
5806 credits = PFI_CREDIT(15);
5807 } else {
5808 credits = default_credits;
5809 }
5810
5811 /*
5812 * WA - write default credits before re-programming
5813 * FIXME: should we also set the resend bit here?
5814 */
5815 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5816 default_credits);
5817
5818 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5819 credits | PFI_CREDIT_RESEND);
5820
5821 /*
5822 * FIXME is this guaranteed to clear
5823 * immediately or should we poll for it?
5824 */
5825 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5826}
5827
679dacd4 5828static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5829{
679dacd4 5830 struct drm_device *dev = state->dev;
30a970c6 5831 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5832 int max_pixclk = intel_mode_max_pixclk(state);
5833 int req_cdclk;
5834
5835 /* The only reason this can fail is if we fail to add the crtc_state
5836 * to the atomic state. But that can't happen since the call to
5837 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5838 * can't have failed otherwise the mode set would be aborted) added all
5839 * the states already. */
5840 if (WARN_ON(max_pixclk < 0))
5841 return;
30a970c6 5842
304603f4 5843 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5844
164dfd28 5845 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5846 /*
5847 * FIXME: We can end up here with all power domains off, yet
5848 * with a CDCLK frequency other than the minimum. To account
5849 * for this take the PIPE-A power domain, which covers the HW
5850 * blocks needed for the following programming. This can be
5851 * removed once it's guaranteed that we get here either with
5852 * the minimum CDCLK set, or the required power domains
5853 * enabled.
5854 */
5855 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5856
383c5a6a
VS		 5857 if (IS_CHERRYVIEW(dev))
5858 cherryview_set_cdclk(dev, req_cdclk);
5859 else
5860 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5861
1e69cd74
VS		 5862 vlv_program_pfi_credits(dev_priv);
5863
738c05c0 5864 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5865 }
30a970c6
JB		 5866}
5867
89b667f8
JB		 5868static void valleyview_crtc_enable(struct drm_crtc *crtc)
5869{
5870 struct drm_device *dev = crtc->dev;
a72e4c9f 5871 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5873 struct intel_encoder *encoder;
5874 int pipe = intel_crtc->pipe;
23538ef1 5875 bool is_dsi;
89b667f8 5876
83d65738 5877 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5878
5879 if (intel_crtc->active)
5880 return;
5881
409ee761 5882 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5883
1ae0d137
VS		 5884 if (!is_dsi) {
5885 if (IS_CHERRYVIEW(dev))
6e3c9717 5886 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5887 else
6e3c9717 5888 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5889 }
5b18e57c 5890
6e3c9717 5891 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5892 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
SV		 5893
5894 intel_set_pipe_timings(intel_crtc);
5895
c14b0485
VS		 5896 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898
5899 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5900 I915_WRITE(CHV_CANVAS(pipe), 0);
5901 }
5902
5b18e57c
SV		 5903 i9xx_set_pipeconf(intel_crtc);
5904
89b667f8 5905 intel_crtc->active = true;
89b667f8 5906
a72e4c9f 5907 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5908
89b667f8
JB		 5909 for_each_encoder_on_crtc(dev, crtc, encoder)
5910 if (encoder->pre_pll_enable)
5911 encoder->pre_pll_enable(encoder);
5912
9d556c99
CML		 5913 if (!is_dsi) {
5914 if (IS_CHERRYVIEW(dev))
6e3c9717 5915 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5916 else
6e3c9717 5917 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5918 }
89b667f8
JB		 5919
5920 for_each_encoder_on_crtc(dev, crtc, encoder)
5921 if (encoder->pre_enable)
5922 encoder->pre_enable(encoder);
5923
2dd24552
JB		 5924 i9xx_pfit_enable(intel_crtc);
5925
63cbb074
VS		 5926 intel_crtc_load_lut(crtc);
5927
f37fcc2a 5928 intel_update_watermarks(crtc);
e1fdc473 5929 intel_enable_pipe(intel_crtc);
be6a6f8e 5930
4b3a9526
VS		 5931 assert_vblank_disabled(crtc);
5932 drm_crtc_vblank_on(crtc);
5933
f9b61ff6
SV		 5934 for_each_encoder_on_crtc(dev, crtc, encoder)
5935 encoder->enable(encoder);
89b667f8
JB		 5936}
5937
f13c2ef3
SV		 5938static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5939{
5940 struct drm_device *dev = crtc->base.dev;
5941 struct drm_i915_private *dev_priv = dev->dev_private;
5942
6e3c9717
ACO		 5943 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5944 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
SV		 5945}
5946
0b8765c6 5947static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5948{
5949 struct drm_device *dev = crtc->dev;
a72e4c9f 5950 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5952 struct intel_encoder *encoder;
79e53945 5953 int pipe = intel_crtc->pipe;
79e53945 5954
83d65738 5955 WARN_ON(!crtc->state->enable);
08a48469 5956
f7abfe8b
CW		 5957 if (intel_crtc->active)
5958 return;
5959
f13c2ef3
SV		 5960 i9xx_set_pll_dividers(intel_crtc);
5961
6e3c9717 5962 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5963 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
SV		 5964
5965 intel_set_pipe_timings(intel_crtc);
5966
5b18e57c
SV		 5967 i9xx_set_pipeconf(intel_crtc);
5968
f7abfe8b 5969 intel_crtc->active = true;
6b383a7f 5970
4a3436e8 5971 if (!IS_GEN2(dev))
a72e4c9f 5972 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5973
9d6d9f19
MK		 5974 for_each_encoder_on_crtc(dev, crtc, encoder)
5975 if (encoder->pre_enable)
5976 encoder->pre_enable(encoder);
5977
f6736a1a
SV		 5978 i9xx_enable_pll(intel_crtc);
5979
2dd24552
JB		 5980 i9xx_pfit_enable(intel_crtc);
5981
63cbb074
VS		 5982 intel_crtc_load_lut(crtc);
5983
f37fcc2a 5984 intel_update_watermarks(crtc);
e1fdc473 5985 intel_enable_pipe(intel_crtc);
be6a6f8e 5986
4b3a9526
VS		 5987 assert_vblank_disabled(crtc);
5988 drm_crtc_vblank_on(crtc);
5989
f9b61ff6
SV		 5990 for_each_encoder_on_crtc(dev, crtc, encoder)
5991 encoder->enable(encoder);
0b8765c6 5992}
79e53945 5993
87476d63
SV		 5994static void i9xx_pfit_disable(struct intel_crtc *crtc)
5995{
5996 struct drm_device *dev = crtc->base.dev;
5997 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5998
6e3c9717 5999 if (!crtc->config->gmch_pfit.control)
328d8e82 6000 return;
87476d63 6001
328d8e82 6002 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6003
328d8e82
SV		 6004 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6005 I915_READ(PFIT_CONTROL));
6006 I915_WRITE(PFIT_CONTROL, 0);
87476d63
SV		 6007}
6008
0b8765c6
JB		 6009static void i9xx_crtc_disable(struct drm_crtc *crtc)
6010{
6011 struct drm_device *dev = crtc->dev;
6012 struct drm_i915_private *dev_priv = dev->dev_private;
6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6014 struct intel_encoder *encoder;
0b8765c6 6015 int pipe = intel_crtc->pipe;
ef9c3aee 6016
f7abfe8b
CW		 6017 if (!intel_crtc->active)
6018 return;
6019
6304cd91
VS		 6020 /*
6021 * On gen2 planes are double buffered but the pipe isn't, so we must
6022 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6023 * We also need to wait on all gmch platforms because of the
6024 * self-refresh mode constraint explained above.
6304cd91 6025 */
564ed191 6026 intel_wait_for_vblank(dev, pipe);
6304cd91 6027
4b3a9526
VS		 6028 for_each_encoder_on_crtc(dev, crtc, encoder)
6029 encoder->disable(encoder);
6030
f9b61ff6
SV		 6031 drm_crtc_vblank_off(crtc);
6032 assert_vblank_disabled(crtc);
6033
575f7ab7 6034 intel_disable_pipe(intel_crtc);
24a1f16d 6035
87476d63 6036 i9xx_pfit_disable(intel_crtc);
24a1f16d 6037
89b667f8
JB		 6038 for_each_encoder_on_crtc(dev, crtc, encoder)
6039 if (encoder->post_disable)
6040 encoder->post_disable(encoder);
6041
409ee761 6042 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6043 if (IS_CHERRYVIEW(dev))
6044 chv_disable_pll(dev_priv, pipe);
6045 else if (IS_VALLEYVIEW(dev))
6046 vlv_disable_pll(dev_priv, pipe);
6047 else
1c4e0274 6048 i9xx_disable_pll(intel_crtc);
076ed3b2 6049 }
0b8765c6 6050
4a3436e8 6051 if (!IS_GEN2(dev))
a72e4c9f 6052 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6053
f7abfe8b 6054 intel_crtc->active = false;
46ba614c 6055 intel_update_watermarks(crtc);
f37fcc2a 6056
efa9624e 6057 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6058 intel_fbc_update(dev);
efa9624e 6059 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6060}
6061
ee7b9f93
JB		 6062static void i9xx_crtc_off(struct drm_crtc *crtc)
6063{
6064}
6065
b04c5bd6
BF		 6066/* Master function to enable/disable CRTC and corresponding power wells */
6067void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
SV		 6068{
6069 struct drm_device *dev = crtc->dev;
6070 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
SV		 6072 enum intel_display_power_domain domain;
6073 unsigned long domains;
976f8a20 6074
0e572fe7
SV		 6075 if (enable) {
6076 if (!intel_crtc->active) {
e1e9fb84
SV		 6077 domains = get_crtc_power_domains(crtc);
6078 for_each_power_domain(domain, domains)
6079 intel_display_power_get(dev_priv, domain);
6080 intel_crtc->enabled_power_domains = domains;
0e572fe7
SV		 6081
6082 dev_priv->display.crtc_enable(crtc);
ce22dba9 6083 intel_crtc_enable_planes(crtc);
0e572fe7
SV		 6084 }
6085 } else {
6086 if (intel_crtc->active) {
ce22dba9 6087 intel_crtc_disable_planes(crtc);
0e572fe7
SV		 6088 dev_priv->display.crtc_disable(crtc);
6089
e1e9fb84
SV		 6090 domains = intel_crtc->enabled_power_domains;
6091 for_each_power_domain(domain, domains)
6092 intel_display_power_put(dev_priv, domain);
6093 intel_crtc->enabled_power_domains = 0;
0e572fe7
SV		 6094 }
6095 }
b04c5bd6
BF		 6096}
6097
6098/**
6099 * Sets the power management mode of the pipe and plane.
6100 */
6101void intel_crtc_update_dpms(struct drm_crtc *crtc)
6102{
6103 struct drm_device *dev = crtc->dev;
6104 struct intel_encoder *intel_encoder;
6105 bool enable = false;
6106
6107 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6108 enable |= intel_encoder->connectors_active;
6109
6110 intel_crtc_control(crtc, enable);
976f8a20
SV		 6111}
6112
cdd59983
CW		 6113static void intel_crtc_disable(struct drm_crtc *crtc)
6114{
cdd59983 6115 struct drm_device *dev = crtc->dev;
976f8a20 6116 struct drm_connector *connector;
ee7b9f93 6117 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6118
976f8a20 6119 /* crtc should still be enabled when we disable it. */
83d65738 6120 WARN_ON(!crtc->state->enable);
976f8a20 6121
ce22dba9 6122 intel_crtc_disable_planes(crtc);
976f8a20 6123 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6124 dev_priv->display.off(crtc);
6125
70a101f8 6126 drm_plane_helper_disable(crtc->primary);
976f8a20
SV		 6127
6128 /* Update computed state. */
6129 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6130 if (!connector->encoder || !connector->encoder->crtc)
6131 continue;
6132
6133 if (connector->encoder->crtc != crtc)
6134 continue;
6135
6136 connector->dpms = DRM_MODE_DPMS_OFF;
6137 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6138 }
6139}
6140
ea5b213a 6141void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6142{
4ef69c7a 6143 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6144
ea5b213a
CW		 6145 drm_encoder_cleanup(encoder);
6146 kfree(intel_encoder);
7e7d76c3
JB		 6147}
6148
9237329d 6149/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
SV		 6150 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6151 * state of the entire output pipe. */
9237329d 6152static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6153{
5ab432ef
SV		 6154 if (mode == DRM_MODE_DPMS_ON) {
6155 encoder->connectors_active = true;
6156
b2cabb0e 6157 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
SV		 6158 } else {
6159 encoder->connectors_active = false;
6160
b2cabb0e 6161 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6162 }
79e53945
JB		 6163}
6164
0a91ca29
SV		 6165/* Cross check the actual hw state with our own modeset state tracking (and it's
6166 * internal consistency). */
b980514c 6167static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6168{
0a91ca29
SV		 6169 if (connector->get_hw_state(connector)) {
6170 struct intel_encoder *encoder = connector->encoder;
6171 struct drm_crtc *crtc;
6172 bool encoder_enabled;
6173 enum pipe pipe;
6174
6175 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6176 connector->base.base.id,
c23cc417 6177 connector->base.name);
0a91ca29 6178
0e32b39c
DA		 6179 /* there is no real hw state for MST connectors */
6180 if (connector->mst_port)
6181 return;
6182
e2c719b7 6183 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6184 "wrong connector dpms state\n");
e2c719b7 6185 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6186 "active connector not linked to encoder\n");
0a91ca29 6187
36cd7444 6188 if (encoder) {
e2c719b7 6189 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6190 "encoder->connectors_active not set\n");
6191
6192 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6193 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6194 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6195 return;
0a91ca29 6196
36cd7444 6197 crtc = encoder->base.crtc;
0a91ca29 6198
83d65738
MR		 6199 I915_STATE_WARN(!crtc->state->enable,
6200 "crtc not enabled\n");
e2c719b7
RC		 6201 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6202 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6203 "encoder active on the wrong pipe\n");
6204 }
0a91ca29 6205 }
79e53945
JB		 6206}
6207
08d9bc92
ACO		 6208int intel_connector_init(struct intel_connector *connector)
6209{
6210 struct drm_connector_state *connector_state;
6211
6212 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6213 if (!connector_state)
6214 return -ENOMEM;
6215
6216 connector->base.state = connector_state;
6217 return 0;
6218}
6219
6220struct intel_connector *intel_connector_alloc(void)
6221{
6222 struct intel_connector *connector;
6223
6224 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6225 if (!connector)
6226 return NULL;
6227
6228 if (intel_connector_init(connector) < 0) {
6229 kfree(connector);
6230 return NULL;
6231 }
6232
6233 return connector;
6234}
6235
5ab432ef
SV		 6236/* Even simpler default implementation, if there's really no special case to
6237 * consider. */
6238void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6239{
5ab432ef
SV		 6240 /* All the simple cases only support two dpms states. */
6241 if (mode != DRM_MODE_DPMS_ON)
6242 mode = DRM_MODE_DPMS_OFF;
d4270e57 6243
5ab432ef
SV		 6244 if (mode == connector->dpms)
6245 return;
6246
6247 connector->dpms = mode;
6248
6249 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6250 if (connector->encoder)
6251 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6252
b980514c 6253 intel_modeset_check_state(connector->dev);
79e53945
JB		 6254}
6255
f0947c37
SV		 6256/* Simple connector->get_hw_state implementation for encoders that support only
6257 * one connector and no cloning and hence the encoder state determines the state
6258 * of the connector. */
6259bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6260{
24929352 6261 enum pipe pipe = 0;
f0947c37 6262 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6263
f0947c37 6264 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6265}
6266
6d293983 6267static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6268{
6d293983
ACO		 6269 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6270 return crtc_state->fdi_lanes;
d272ddfa
VS		 6271
6272 return 0;
6273}
6274
6d293983 6275static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6276 struct intel_crtc_state *pipe_config)
1857e1da 6277{
6d293983
ACO		 6278 struct drm_atomic_state *state = pipe_config->base.state;
6279 struct intel_crtc *other_crtc;
6280 struct intel_crtc_state *other_crtc_state;
6281
1857e1da
SV		 6282 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6283 pipe_name(pipe), pipe_config->fdi_lanes);
6284 if (pipe_config->fdi_lanes > 4) {
6285 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6286 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6287 return -EINVAL;
1857e1da
SV		 6288 }
6289
bafb6553 6290 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
SV		 6291 if (pipe_config->fdi_lanes > 2) {
6292 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6293 pipe_config->fdi_lanes);
6d293983 6294 return -EINVAL;
1857e1da 6295 } else {
6d293983 6296 return 0;
1857e1da
SV		 6297 }
6298 }
6299
6300 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6301 return 0;
1857e1da
SV		 6302
6303 /* Ivybridge 3 pipe is really complicated */
6304 switch (pipe) {
6305 case PIPE_A:
6d293983 6306 return 0;
1857e1da 6307 case PIPE_B:
6d293983
ACO		 6308 if (pipe_config->fdi_lanes <= 2)
6309 return 0;
6310
6311 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6312 other_crtc_state =
6313 intel_atomic_get_crtc_state(state, other_crtc);
6314 if (IS_ERR(other_crtc_state))
6315 return PTR_ERR(other_crtc_state);
6316
6317 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
SV		 6318 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6319 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6320 return -EINVAL;
1857e1da 6321 }
6d293983 6322 return 0;
1857e1da 6323 case PIPE_C:
251cc67c
VS		 6324 if (pipe_config->fdi_lanes > 2) {
6325 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6326 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6327 return -EINVAL;
251cc67c 6328 }
6d293983
ACO		 6329
6330 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6331 other_crtc_state =
6332 intel_atomic_get_crtc_state(state, other_crtc);
6333 if (IS_ERR(other_crtc_state))
6334 return PTR_ERR(other_crtc_state);
6335
6336 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6337 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6338 return -EINVAL;
1857e1da 6339 }
6d293983 6340 return 0;
1857e1da
SV		 6341 default:
6342 BUG();
6343 }
6344}
6345
e29c22c0
SV		 6346#define RETRY 1
6347static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6348 struct intel_crtc_state *pipe_config)
877d48d5 6349{
1857e1da 6350 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6351 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6352 int lane, link_bw, fdi_dotclock, ret;
6353 bool needs_recompute = false;
877d48d5 6354
e29c22c0 6355retry:
877d48d5
SV		 6356 /* FDI is a binary signal running at ~2.7GHz, encoding
6357 * each output octet as 10 bits. The actual frequency
6358 * is stored as a divider into a 100MHz clock, and the
6359 * mode pixel clock is stored in units of 1KHz.
6360 * Hence the bw of each lane in terms of the mode signal
6361 * is:
6362 */
6363 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6364
241bfc38 6365 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6366
2bd89a07 6367 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
SV		 6368 pipe_config->pipe_bpp);
6369
6370 pipe_config->fdi_lanes = lane;
6371
2bd89a07 6372 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6373 link_bw, &pipe_config->fdi_m_n);
1857e1da 6374
6d293983
ACO		 6375 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6376 intel_crtc->pipe, pipe_config);
6377 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
SV		 6378 pipe_config->pipe_bpp -= 2*3;
6379 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6380 pipe_config->pipe_bpp);
6381 needs_recompute = true;
6382 pipe_config->bw_constrained = true;
6383
6384 goto retry;
6385 }
6386
6387 if (needs_recompute)
6388 return RETRY;
6389
6d293983 6390 return ret;
877d48d5
SV		 6391}
6392
42db64ef 6393static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6394 struct intel_crtc_state *pipe_config)
42db64ef 6395{
d330a953 6396 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6397 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6398 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6399}
6400
a43f6e0f 6401static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6402 struct intel_crtc_state *pipe_config)
79e53945 6403{
a43f6e0f 6404 struct drm_device *dev = crtc->base.dev;
8bd31e67 6405 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6406 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6407 int ret;
89749350 6408
ad3a4479 6409 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6410 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6411 int clock_limit =
6412 dev_priv->display.get_display_clock_speed(dev);
6413
6414 /*
6415 * Enable pixel doubling when the dot clock
6416 * is > 90% of the (display) core speed.
6417 *
b397c96b
VS		 6418 * GDG double wide on either pipe,
6419 * otherwise pipe A only.
cf532bb2 6420 */
b397c96b 6421 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6422 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6423 clock_limit *= 2;
cf532bb2 6424 pipe_config->double_wide = true;
ad3a4479
VS		 6425 }
6426
241bfc38 6427 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6428 return -EINVAL;
2c07245f 6429 }
89749350 6430
1d1d0e27
VS		 6431 /*
6432 * Pipe horizontal size must be even in:
6433 * - DVO ganged mode
6434 * - LVDS dual channel mode
6435 * - Double wide pipe
6436 */
a93e255f 6437 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6438 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6439 pipe_config->pipe_src_w &= ~1;
6440
8693a824
DL		 6441 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6442 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6443 */
6444 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6445 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6446 return -EINVAL;
44f46b42 6447
f5adf94e 6448 if (HAS_IPS(dev))
a43f6e0f
SV		 6449 hsw_compute_ips_config(crtc, pipe_config);
6450
877d48d5 6451 if (pipe_config->has_pch_encoder)
a43f6e0f 6452 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6453
d03c93d4
CK		 6454 /* FIXME: remove below call once atomic mode set is place and all crtc
6455 * related checks called from atomic_crtc_check function */
6456 ret = 0;
6457 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6458 crtc, pipe_config->base.state);
6459 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6460
6461 return ret;
79e53945
JB		 6462}
6463
1652d19e
VS		 6464static int skylake_get_display_clock_speed(struct drm_device *dev)
6465{
6466 struct drm_i915_private *dev_priv = to_i915(dev);
6467 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6468 uint32_t cdctl = I915_READ(CDCLK_CTL);
6469 uint32_t linkrate;
6470
6471 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6472 WARN(1, "LCPLL1 not enabled\n");
6473 return 24000; /* 24MHz is the cd freq with NSSC ref */
6474 }
6475
6476 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6477 return 540000;
6478
6479 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6480 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6481
71cd8423
DL		 6482 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6483 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6484 /* vco 8640 */
6485 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6486 case CDCLK_FREQ_450_432:
6487 return 432000;
6488 case CDCLK_FREQ_337_308:
6489 return 308570;
6490 case CDCLK_FREQ_675_617:
6491 return 617140;
6492 default:
6493 WARN(1, "Unknown cd freq selection\n");
6494 }
6495 } else {
6496 /* vco 8100 */
6497 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6498 case CDCLK_FREQ_450_432:
6499 return 450000;
6500 case CDCLK_FREQ_337_308:
6501 return 337500;
6502 case CDCLK_FREQ_675_617:
6503 return 675000;
6504 default:
6505 WARN(1, "Unknown cd freq selection\n");
6506 }
6507 }
6508
6509 /* error case, do as if DPLL0 isn't enabled */
6510 return 24000;
6511}
6512
6513static int broadwell_get_display_clock_speed(struct drm_device *dev)
6514{
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516 uint32_t lcpll = I915_READ(LCPLL_CTL);
6517 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6518
6519 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6520 return 800000;
6521 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6522 return 450000;
6523 else if (freq == LCPLL_CLK_FREQ_450)
6524 return 450000;
6525 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6526 return 540000;
6527 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6528 return 337500;
6529 else
6530 return 675000;
6531}
6532
6533static int haswell_get_display_clock_speed(struct drm_device *dev)
6534{
6535 struct drm_i915_private *dev_priv = dev->dev_private;
6536 uint32_t lcpll = I915_READ(LCPLL_CTL);
6537 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6538
6539 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6540 return 800000;
6541 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6542 return 450000;
6543 else if (freq == LCPLL_CLK_FREQ_450)
6544 return 450000;
6545 else if (IS_HSW_ULT(dev))
6546 return 337500;
6547 else
6548 return 540000;
79e53945
JB		 6549}
6550
25eb05fc
JB		 6551static int valleyview_get_display_clock_speed(struct drm_device *dev)
6552{
d197b7d3 6553 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6554 u32 val;
6555 int divider;
6556
6bcda4f0
VS		 6557 if (dev_priv->hpll_freq == 0)
6558 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6559
d197b7d3
VS		 6560 mutex_lock(&dev_priv->dpio_lock);
6561 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6562 mutex_unlock(&dev_priv->dpio_lock);
6563
6564 divider = val & DISPLAY_FREQUENCY_VALUES;
6565
7d007f40
VS		 6566 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6567 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6568 "cdclk change in progress\n");
6569
6bcda4f0 6570 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6571}
6572
b37a6434
VS		 6573static int ilk_get_display_clock_speed(struct drm_device *dev)
6574{
6575 return 450000;
6576}
6577
e70236a8
JB		 6578static int i945_get_display_clock_speed(struct drm_device *dev)
6579{
6580 return 400000;
6581}
79e53945 6582
e70236a8 6583static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6584{
e907f170 6585 return 333333;
e70236a8 6586}
79e53945 6587
e70236a8
JB		 6588static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6589{
6590 return 200000;
6591}
79e53945 6592
257a7ffc
SV		 6593static int pnv_get_display_clock_speed(struct drm_device *dev)
6594{
6595 u16 gcfgc = 0;
6596
6597 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6598
6599 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6600 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6601 return 266667;
257a7ffc 6602 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6603 return 333333;
257a7ffc 6604 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6605 return 444444;
257a7ffc
SV		 6606 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6607 return 200000;
6608 default:
6609 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6610 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6611 return 133333;
257a7ffc 6612 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6613 return 166667;
257a7ffc
SV		 6614 }
6615}
6616
e70236a8
JB		 6617static int i915gm_get_display_clock_speed(struct drm_device *dev)
6618{
6619 u16 gcfgc = 0;
79e53945 6620
e70236a8
JB		 6621 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6622
6623 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6624 return 133333;
e70236a8
JB		 6625 else {
6626 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6627 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6628 return 333333;
e70236a8
JB		 6629 default:
6630 case GC_DISPLAY_CLOCK_190_200_MHZ:
6631 return 190000;
79e53945 6632 }
e70236a8
JB		 6633 }
6634}
6635
6636static int i865_get_display_clock_speed(struct drm_device *dev)
6637{
e907f170 6638 return 266667;
e70236a8
JB		 6639}
6640
6641static int i855_get_display_clock_speed(struct drm_device *dev)
6642{
6643 u16 hpllcc = 0;
6644 /* Assume that the hardware is in the high speed state. This
6645 * should be the default.
6646 */
6647 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6648 case GC_CLOCK_133_200:
6649 case GC_CLOCK_100_200:
6650 return 200000;
6651 case GC_CLOCK_166_250:
6652 return 250000;
6653 case GC_CLOCK_100_133:
e907f170 6654 return 133333;
e70236a8 6655 }
79e53945 6656
e70236a8
JB		 6657 /* Shouldn't happen */
6658 return 0;
6659}
79e53945 6660
e70236a8
JB		 6661static int i830_get_display_clock_speed(struct drm_device *dev)
6662{
e907f170 6663 return 133333;
79e53945
JB		 6664}
6665
2c07245f 6666static void
a65851af 6667intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6668{
a65851af
VS		 6669 while (*num > DATA_LINK_M_N_MASK ||
6670 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6671 *num >>= 1;
6672 *den >>= 1;
6673 }
6674}
6675
a65851af
VS		 6676static void compute_m_n(unsigned int m, unsigned int n,
6677 uint32_t *ret_m, uint32_t *ret_n)
6678{
6679 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6680 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6681 intel_reduce_m_n_ratio(ret_m, ret_n);
6682}
6683
e69d0bc1
SV		 6684void
6685intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6686 int pixel_clock, int link_clock,
6687 struct intel_link_m_n *m_n)
2c07245f 6688{
e69d0bc1 6689 m_n->tu = 64;
a65851af
VS		 6690
6691 compute_m_n(bits_per_pixel * pixel_clock,
6692 link_clock * nlanes * 8,
6693 &m_n->gmch_m, &m_n->gmch_n);
6694
6695 compute_m_n(pixel_clock, link_clock,
6696 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6697}
6698
a7615030
CW		 6699static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6700{
d330a953
JN		 6701 if (i915.panel_use_ssc >= 0)
6702 return i915.panel_use_ssc != 0;
41aa3448 6703 return dev_priv->vbt.lvds_use_ssc
435793df 6704 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6705}
6706
a93e255f
ACO		 6707static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6708 int num_connectors)
c65d77d8 6709{
a93e255f 6710 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6711 struct drm_i915_private *dev_priv = dev->dev_private;
6712 int refclk;
6713
a93e255f
ACO		 6714 WARN_ON(!crtc_state->base.state);
6715
5ab7b0b7 6716 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6717 refclk = 100000;
a93e255f 6718 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6719 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6720 refclk = dev_priv->vbt.lvds_ssc_freq;
6721 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6722 } else if (!IS_GEN2(dev)) {
6723 refclk = 96000;
6724 } else {
6725 refclk = 48000;
6726 }
6727
6728 return refclk;
6729}
6730
7429e9d4 6731static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6732{
7df00d7a 6733 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6734}
f47709a9 6735
7429e9d4
SV		 6736static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6737{
6738 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6739}
6740
f47709a9 6741static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6742 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6743 intel_clock_t *reduced_clock)
6744{
f47709a9 6745 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6746 u32 fp, fp2 = 0;
6747
6748 if (IS_PINEVIEW(dev)) {
190f68c5 6749 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6750 if (reduced_clock)
7429e9d4 6751 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6752 } else {
190f68c5 6753 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6754 if (reduced_clock)
7429e9d4 6755 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6756 }
6757
190f68c5 6758 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6759
f47709a9 6760 crtc->lowfreq_avail = false;
a93e255f 6761 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6762 reduced_clock) {
190f68c5 6763 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6764 crtc->lowfreq_avail = true;
a7516a05 6765 } else {
190f68c5 6766 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6767 }
6768}
6769
5e69f97f
CML		 6770static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6771 pipe)
89b667f8
JB		 6772{
6773 u32 reg_val;
6774
6775 /*
6776 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6777 * and set it to a reasonable value instead.
6778 */
ab3c759a 6779 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6780 reg_val &= 0xffffff00;
6781 reg_val |= 0x00000030;
ab3c759a 6782 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6783
ab3c759a 6784 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6785 reg_val &= 0x8cffffff;
6786 reg_val = 0x8c000000;
ab3c759a 6787 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6788
ab3c759a 6789 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6790 reg_val &= 0xffffff00;
ab3c759a 6791 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6792
ab3c759a 6793 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6794 reg_val &= 0x00ffffff;
6795 reg_val |= 0xb0000000;
ab3c759a 6796 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6797}
6798
b551842d
SV		 6799static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6800 struct intel_link_m_n *m_n)
6801{
6802 struct drm_device *dev = crtc->base.dev;
6803 struct drm_i915_private *dev_priv = dev->dev_private;
6804 int pipe = crtc->pipe;
6805
e3b95f1e
SV		 6806 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6807 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6808 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6809 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
SV		 6810}
6811
6812static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6813 struct intel_link_m_n *m_n,
6814 struct intel_link_m_n *m2_n2)
b551842d
SV		 6815{
6816 struct drm_device *dev = crtc->base.dev;
6817 struct drm_i915_private *dev_priv = dev->dev_private;
6818 int pipe = crtc->pipe;
6e3c9717 6819 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
SV		 6820
6821 if (INTEL_INFO(dev)->gen >= 5) {
6822 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6823 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6824 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6825 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6826 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6827 * for gen < 8) and if DRRS is supported (to make sure the
6828 * registers are not unnecessarily accessed).
6829 */
44395bfe 6830 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6831 crtc->config->has_drrs) {
f769cd24
VK		 6832 I915_WRITE(PIPE_DATA_M2(transcoder),
6833 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6834 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6835 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6836 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6837 }
b551842d 6838 } else {
e3b95f1e
SV		 6839 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6840 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6841 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6842 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
SV		 6843 }
6844}
6845
fe3cd48d 6846void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6847{
fe3cd48d
R		 6848 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6849
6850 if (m_n == M1_N1) {
6851 dp_m_n = &crtc->config->dp_m_n;
6852 dp_m2_n2 = &crtc->config->dp_m2_n2;
6853 } else if (m_n == M2_N2) {
6854
6855 /*
6856 * M2_N2 registers are not supported. Hence m2_n2 divider value
6857 * needs to be programmed into M1_N1.
6858 */
6859 dp_m_n = &crtc->config->dp_m2_n2;
6860 } else {
6861 DRM_ERROR("Unsupported divider value\n");
6862 return;
6863 }
6864
6e3c9717
ACO		 6865 if (crtc->config->has_pch_encoder)
6866 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6867 else
fe3cd48d 6868 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
SV		 6869}
6870
d288f65f 6871static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6872 struct intel_crtc_state *pipe_config)
bdd4b6a6
SV		 6873{
6874 u32 dpll, dpll_md;
6875
6876 /*
6877 * Enable DPIO clock input. We should never disable the reference
6878 * clock for pipe B, since VGA hotplug / manual detection depends
6879 * on it.
6880 */
6881 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6882 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6883 /* We should never disable this, set it here for state tracking */
6884 if (crtc->pipe == PIPE_B)
6885 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6886 dpll |= DPLL_VCO_ENABLE;
d288f65f 6887 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6888
d288f65f 6889 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6890 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6891 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
SV		 6892}
6893
d288f65f 6894static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6895 const struct intel_crtc_state *pipe_config)
a0c4da24 6896{
f47709a9 6897 struct drm_device *dev = crtc->base.dev;
a0c4da24 6898 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6899 int pipe = crtc->pipe;
bdd4b6a6 6900 u32 mdiv;
a0c4da24 6901 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6902 u32 coreclk, reg_val;
a0c4da24 6903
09153000
SV		 6904 mutex_lock(&dev_priv->dpio_lock);
6905
d288f65f
VS		 6906 bestn = pipe_config->dpll.n;
6907 bestm1 = pipe_config->dpll.m1;
6908 bestm2 = pipe_config->dpll.m2;
6909 bestp1 = pipe_config->dpll.p1;
6910 bestp2 = pipe_config->dpll.p2;
a0c4da24 6911
89b667f8
JB		 6912 /* See eDP HDMI DPIO driver vbios notes doc */
6913
6914 /* PLL B needs special handling */
bdd4b6a6 6915 if (pipe == PIPE_B)
5e69f97f 6916 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6917
6918 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6919 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6920
6921 /* Disable target IRef on PLL */
ab3c759a 6922 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6923 reg_val &= 0x00ffffff;
ab3c759a 6924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6925
6926 /* Disable fast lock */
ab3c759a 6927 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6928
6929 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6930 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6931 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6932 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6933 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6934
6935 /*
6936 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6937 * but we don't support that).
6938 * Note: don't use the DAC post divider as it seems unstable.
6939 */
6940 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6942
a0c4da24 6943 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6945
89b667f8 6946 /* Set HBR and RBR LPF coefficients */
d288f65f 6947 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6948 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6949 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6951 0x009f0003);
89b667f8 6952 else
ab3c759a 6953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6954 0x00d0000f);
6955
681a8504 6956 if (pipe_config->has_dp_encoder) {
89b667f8 6957 /* Use SSC source */
bdd4b6a6 6958 if (pipe == PIPE_A)
ab3c759a 6959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6960 0x0df40000);
6961 else
ab3c759a 6962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6963 0x0df70000);
6964 } else { /* HDMI or VGA */
6965 /* Use bend source */
bdd4b6a6 6966 if (pipe == PIPE_A)
ab3c759a 6967 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6968 0x0df70000);
6969 else
ab3c759a 6970 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6971 0x0df40000);
6972 }
a0c4da24 6973
ab3c759a 6974 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6975 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6976 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6977 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6978 coreclk |= 0x01000000;
ab3c759a 6979 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6980
ab3c759a 6981 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6982 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6983}
6984
d288f65f 6985static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6986 struct intel_crtc_state *pipe_config)
1ae0d137 6987{
d288f65f 6988 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6989 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6990 DPLL_VCO_ENABLE;
6991 if (crtc->pipe != PIPE_A)
d288f65f 6992 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6993
d288f65f
VS		 6994 pipe_config->dpll_hw_state.dpll_md =
6995 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6996}
6997
d288f65f 6998static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6999 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7000{
7001 struct drm_device *dev = crtc->base.dev;
7002 struct drm_i915_private *dev_priv = dev->dev_private;
7003 int pipe = crtc->pipe;
7004 int dpll_reg = DPLL(crtc->pipe);
7005 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7006 u32 loopfilter, tribuf_calcntr;
9d556c99 7007 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7008 u32 dpio_val;
9cbe40c1 7009 int vco;
9d556c99 7010
d288f65f
VS		 7011 bestn = pipe_config->dpll.n;
7012 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7013 bestm1 = pipe_config->dpll.m1;
7014 bestm2 = pipe_config->dpll.m2 >> 22;
7015 bestp1 = pipe_config->dpll.p1;
7016 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7017 vco = pipe_config->dpll.vco;
a945ce7e 7018 dpio_val = 0;
9cbe40c1 7019 loopfilter = 0;
9d556c99
CML		 7020
7021 /*
7022 * Enable Refclk and SSC
7023 */
a11b0703 7024 I915_WRITE(dpll_reg,
d288f65f 7025 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 7026
7027 mutex_lock(&dev_priv->dpio_lock);
9d556c99 7028
9d556c99
CML		 7029 /* p1 and p2 divider */
7030 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7031 5 << DPIO_CHV_S1_DIV_SHIFT |
7032 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7033 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7034 1 << DPIO_CHV_K_DIV_SHIFT);
7035
7036 /* Feedback post-divider - m2 */
7037 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7038
7039 /* Feedback refclk divider - n and m1 */
7040 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7041 DPIO_CHV_M1_DIV_BY_2 |
7042 1 << DPIO_CHV_N_DIV_SHIFT);
7043
7044 /* M2 fraction division */
a945ce7e
VP		 7045 if (bestm2_frac)
7046 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7047
7048 /* M2 fraction division enable */
a945ce7e
VP		 7049 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7050 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7051 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7052 if (bestm2_frac)
7053 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7054 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7055
de3a0fde
VP		 7056 /* Program digital lock detect threshold */
7057 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7058 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7059 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7060 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7061 if (!bestm2_frac)
7062 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7063 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7064
9d556c99 7065 /* Loop filter */
9cbe40c1
VP		 7066 if (vco == 5400000) {
7067 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7068 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7069 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7070 tribuf_calcntr = 0x9;
7071 } else if (vco <= 6200000) {
7072 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7073 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7074 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7075 tribuf_calcntr = 0x9;
7076 } else if (vco <= 6480000) {
7077 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7078 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7079 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7080 tribuf_calcntr = 0x8;
7081 } else {
7082 /* Not supported. Apply the same limits as in the max case */
7083 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7084 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7085 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7086 tribuf_calcntr = 0;
7087 }
9d556c99
CML		 7088 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7089
968040b2 7090 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7091 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7092 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7093 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7094
9d556c99
CML		 7095 /* AFC Recal */
7096 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7097 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7098 DPIO_AFC_RECAL);
7099
7100 mutex_unlock(&dev_priv->dpio_lock);
7101}
7102
d288f65f
VS		 7103/**
7104 * vlv_force_pll_on - forcibly enable just the PLL
7105 * @dev_priv: i915 private structure
7106 * @pipe: pipe PLL to enable
7107 * @dpll: PLL configuration
7108 *
7109 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7110 * in cases where we need the PLL enabled even when @pipe is not going to
7111 * be enabled.
7112 */
7113void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7114 const struct dpll *dpll)
7115{
7116 struct intel_crtc *crtc =
7117 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7118 struct intel_crtc_state pipe_config = {
a93e255f 7119 .base.crtc = &crtc->base,
d288f65f
VS		 7120 .pixel_multiplier = 1,
7121 .dpll = *dpll,
7122 };
7123
7124 if (IS_CHERRYVIEW(dev)) {
7125 chv_update_pll(crtc, &pipe_config);
7126 chv_prepare_pll(crtc, &pipe_config);
7127 chv_enable_pll(crtc, &pipe_config);
7128 } else {
7129 vlv_update_pll(crtc, &pipe_config);
7130 vlv_prepare_pll(crtc, &pipe_config);
7131 vlv_enable_pll(crtc, &pipe_config);
7132 }
7133}
7134
7135/**
7136 * vlv_force_pll_off - forcibly disable just the PLL
7137 * @dev_priv: i915 private structure
7138 * @pipe: pipe PLL to disable
7139 *
7140 * Disable the PLL for @pipe. To be used in cases where we need
7141 * the PLL enabled even when @pipe is not going to be enabled.
7142 */
7143void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7144{
7145 if (IS_CHERRYVIEW(dev))
7146 chv_disable_pll(to_i915(dev), pipe);
7147 else
7148 vlv_disable_pll(to_i915(dev), pipe);
7149}
7150
f47709a9 7151static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7152 struct intel_crtc_state *crtc_state,
f47709a9 7153 intel_clock_t *reduced_clock,
eb1cbe48
SV		 7154 int num_connectors)
7155{
f47709a9 7156 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7157 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
SV		 7158 u32 dpll;
7159 bool is_sdvo;
190f68c5 7160 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7161
190f68c5 7162 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7163
a93e255f
ACO		 7164 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7165 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
SV		 7166
7167 dpll = DPLL_VGA_MODE_DIS;
7168
a93e255f 7169 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
SV		 7170 dpll |= DPLLB_MODE_LVDS;
7171 else
7172 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7173
ef1b460d 7174 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7175 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7176 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7177 }
198a037f
SV		 7178
7179 if (is_sdvo)
4a33e48d 7180 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7181
190f68c5 7182 if (crtc_state->has_dp_encoder)
4a33e48d 7183 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
SV		 7184
7185 /* compute bitmask from p1 value */
7186 if (IS_PINEVIEW(dev))
7187 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7188 else {
7189 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7190 if (IS_G4X(dev) && reduced_clock)
7191 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7192 }
7193 switch (clock->p2) {
7194 case 5:
7195 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7196 break;
7197 case 7:
7198 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7199 break;
7200 case 10:
7201 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7202 break;
7203 case 14:
7204 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7205 break;
7206 }
7207 if (INTEL_INFO(dev)->gen >= 4)
7208 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7209
190f68c5 7210 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7211 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7212 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
SV		 7213 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7214 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7215 else
7216 dpll |= PLL_REF_INPUT_DREFCLK;
7217
7218 dpll |= DPLL_VCO_ENABLE;
190f68c5 7219 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7220
eb1cbe48 7221 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7222 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7223 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7224 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
SV		 7225 }
7226}
7227
f47709a9 7228static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7229 struct intel_crtc_state *crtc_state,
f47709a9 7230 intel_clock_t *reduced_clock,
eb1cbe48
SV		 7231 int num_connectors)
7232{
f47709a9 7233 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7234 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7235 u32 dpll;
190f68c5 7236 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7237
190f68c5 7238 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7239
eb1cbe48
SV		 7240 dpll = DPLL_VGA_MODE_DIS;
7241
a93e255f 7242 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
SV		 7243 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7244 } else {
7245 if (clock->p1 == 2)
7246 dpll |= PLL_P1_DIVIDE_BY_TWO;
7247 else
7248 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7249 if (clock->p2 == 4)
7250 dpll |= PLL_P2_DIVIDE_BY_4;
7251 }
7252
a93e255f 7253 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
SV		 7254 dpll |= DPLL_DVO_2X_MODE;
7255
a93e255f 7256 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
SV		 7257 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7258 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7259 else
7260 dpll |= PLL_REF_INPUT_DREFCLK;
7261
7262 dpll |= DPLL_VCO_ENABLE;
190f68c5 7263 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
SV		 7264}
7265
8a654f3b 7266static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7267{
7268 struct drm_device *dev = intel_crtc->base.dev;
7269 struct drm_i915_private *dev_priv = dev->dev_private;
7270 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7271 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7272 struct drm_display_mode *adjusted_mode =
6e3c9717 7273 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7274 uint32_t crtc_vtotal, crtc_vblank_end;
7275 int vsyncshift = 0;
4d8a62ea
SV		 7276
7277 /* We need to be careful not to changed the adjusted mode, for otherwise
7278 * the hw state checker will get angry at the mismatch. */
7279 crtc_vtotal = adjusted_mode->crtc_vtotal;
7280 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7281
609aeaca 7282 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7283 /* the chip adds 2 halflines automatically */
4d8a62ea
SV		 7284 crtc_vtotal -= 1;
7285 crtc_vblank_end -= 1;
609aeaca 7286
409ee761 7287 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7288 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7289 else
7290 vsyncshift = adjusted_mode->crtc_hsync_start -
7291 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7292 if (vsyncshift < 0)
7293 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7294 }
7295
7296 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7297 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7298
fe2b8f9d 7299 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7300 (adjusted_mode->crtc_hdisplay - 1) |
7301 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7302 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7303 (adjusted_mode->crtc_hblank_start - 1) |
7304 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7305 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7306 (adjusted_mode->crtc_hsync_start - 1) |
7307 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7308
fe2b8f9d 7309 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7310 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7311 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7312 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7313 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7314 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7315 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7316 (adjusted_mode->crtc_vsync_start - 1) |
7317 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7318
b5e508d4
PZ		 7319 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7320 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7321 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7322 * bits. */
7323 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7324 (pipe == PIPE_B || pipe == PIPE_C))
7325 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7326
b0e77b9c
PZ		 7327 /* pipesrc controls the size that is scaled from, which should
7328 * always be the user's requested size.
7329 */
7330 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7331 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7332 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7333}
7334
1bd1bd80 7335static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7336 struct intel_crtc_state *pipe_config)
1bd1bd80
SV		 7337{
7338 struct drm_device *dev = crtc->base.dev;
7339 struct drm_i915_private *dev_priv = dev->dev_private;
7340 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7341 uint32_t tmp;
7342
7343 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7344 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7345 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7346 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7347 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7348 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7349 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7350 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7351 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
SV		 7352
7353 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7354 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7355 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7356 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7357 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7358 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7359 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7360 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7361 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
SV		 7362
7363 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7364 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7365 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7366 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
SV		 7367 }
7368
7369 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7370 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7371 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7372
2d112de7
ACO		 7373 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7374 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
SV		 7375}
7376
f6a83288 7377void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7378 struct intel_crtc_state *pipe_config)
babea61d 7379{
2d112de7
ACO		 7380 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7381 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7382 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7383 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7384
2d112de7
ACO		 7385 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7386 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7387 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7388 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7389
2d112de7 7390 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7391
2d112de7
ACO		 7392 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7393 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7394}
7395
84b046f3
SV		 7396static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7397{
7398 struct drm_device *dev = intel_crtc->base.dev;
7399 struct drm_i915_private *dev_priv = dev->dev_private;
7400 uint32_t pipeconf;
7401
9f11a9e4 7402 pipeconf = 0;
84b046f3 7403
b6b5d049
VS		 7404 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7405 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7406 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7407
6e3c9717 7408 if (intel_crtc->config->double_wide)
cf532bb2 7409 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7410
ff9ce46e
SV		 7411 /* only g4x and later have fancy bpc/dither controls */
7412 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7413 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7414 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7415 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7416 PIPECONF_DITHER_TYPE_SP;
84b046f3 7417
6e3c9717 7418 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
SV		 7419 case 18:
7420 pipeconf |= PIPECONF_6BPC;
7421 break;
7422 case 24:
7423 pipeconf |= PIPECONF_8BPC;
7424 break;
7425 case 30:
7426 pipeconf |= PIPECONF_10BPC;
7427 break;
7428 default:
7429 /* Case prevented by intel_choose_pipe_bpp_dither. */
7430 BUG();
84b046f3
SV		 7431 }
7432 }
7433
7434 if (HAS_PIPE_CXSR(dev)) {
7435 if (intel_crtc->lowfreq_avail) {
7436 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7437 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7438 } else {
7439 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
SV		 7440 }
7441 }
7442
6e3c9717 7443 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7444 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7445 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7446 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7447 else
7448 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7449 } else
84b046f3
SV		 7450 pipeconf |= PIPECONF_PROGRESSIVE;
7451
6e3c9717 7452 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7453 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7454
84b046f3
SV		 7455 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7456 POSTING_READ(PIPECONF(intel_crtc->pipe));
7457}
7458
190f68c5
ACO		 7459static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7460 struct intel_crtc_state *crtc_state)
79e53945 7461{
c7653199 7462 struct drm_device *dev = crtc->base.dev;
79e53945 7463 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7464 int refclk, num_connectors = 0;
652c393a 7465 intel_clock_t clock, reduced_clock;
a16af721 7466 bool ok, has_reduced_clock = false;
e9fd1c02 7467 bool is_lvds = false, is_dsi = false;
5eddb70b 7468 struct intel_encoder *encoder;
d4906093 7469 const intel_limit_t *limit;
55bb9992 7470 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7471 struct drm_connector *connector;
55bb9992
ACO		 7472 struct drm_connector_state *connector_state;
7473 int i;
79e53945 7474
da3ced29 7475 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7476 if (connector_state->crtc != &crtc->base)
7477 continue;
7478
7479 encoder = to_intel_encoder(connector_state->best_encoder);
7480
5eddb70b 7481 switch (encoder->type) {
79e53945
JB		 7482 case INTEL_OUTPUT_LVDS:
7483 is_lvds = true;
7484 break;
e9fd1c02
JN		 7485 case INTEL_OUTPUT_DSI:
7486 is_dsi = true;
7487 break;
6847d71b
PZ		 7488 default:
7489 break;
79e53945 7490 }
43565a06 7491
c751ce4f 7492 num_connectors++;
79e53945
JB		 7493 }
7494
f2335330 7495 if (is_dsi)
5b18e57c 7496 return 0;
f2335330 7497
190f68c5 7498 if (!crtc_state->clock_set) {
a93e255f 7499 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7500
e9fd1c02
JN		 7501 /*
7502 * Returns a set of divisors for the desired target clock with
7503 * the given refclk, or FALSE. The returned values represent
7504 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7505 * 2) / p1 / p2.
7506 */
a93e255f
ACO		 7507 limit = intel_limit(crtc_state, refclk);
7508 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7509 crtc_state->port_clock,
e9fd1c02 7510 refclk, NULL, &clock);
f2335330 7511 if (!ok) {
e9fd1c02
JN		 7512 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7513 return -EINVAL;
7514 }
79e53945 7515
f2335330
JN		 7516 if (is_lvds && dev_priv->lvds_downclock_avail) {
7517 /*
7518 * Ensure we match the reduced clock's P to the target
7519 * clock. If the clocks don't match, we can't switch
7520 * the display clock by using the FP0/FP1. In such case
7521 * we will disable the LVDS downclock feature.
7522 */
7523 has_reduced_clock =
a93e255f 7524 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7525 dev_priv->lvds_downclock,
7526 refclk, &clock,
7527 &reduced_clock);
7528 }
7529 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7530 crtc_state->dpll.n = clock.n;
7531 crtc_state->dpll.m1 = clock.m1;
7532 crtc_state->dpll.m2 = clock.m2;
7533 crtc_state->dpll.p1 = clock.p1;
7534 crtc_state->dpll.p2 = clock.p2;
f47709a9 7535 }
7026d4ac 7536
e9fd1c02 7537 if (IS_GEN2(dev)) {
190f68c5 7538 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7539 has_reduced_clock ? &reduced_clock : NULL,
7540 num_connectors);
9d556c99 7541 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7542 chv_update_pll(crtc, crtc_state);
e9fd1c02 7543 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7544 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7545 } else {
190f68c5 7546 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7547 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7548 num_connectors);
e9fd1c02 7549 }
79e53945 7550
c8f7a0db 7551 return 0;
f564048e
EA		 7552}
7553
2fa2fe9a 7554static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7555 struct intel_crtc_state *pipe_config)
2fa2fe9a
SV		 7556{
7557 struct drm_device *dev = crtc->base.dev;
7558 struct drm_i915_private *dev_priv = dev->dev_private;
7559 uint32_t tmp;
7560
dc9e7dec
VS		 7561 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7562 return;
7563
2fa2fe9a 7564 tmp = I915_READ(PFIT_CONTROL);
06922821
SV		 7565 if (!(tmp & PFIT_ENABLE))
7566 return;
2fa2fe9a 7567
06922821 7568 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
SV		 7569 if (INTEL_INFO(dev)->gen < 4) {
7570 if (crtc->pipe != PIPE_B)
7571 return;
2fa2fe9a
SV		 7572 } else {
7573 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7574 return;
7575 }
7576
06922821 7577 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
SV		 7578 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7579 if (INTEL_INFO(dev)->gen < 5)
7580 pipe_config->gmch_pfit.lvds_border_bits =
7581 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7582}
7583
acbec814 7584static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7585 struct intel_crtc_state *pipe_config)
acbec814
JB		 7586{
7587 struct drm_device *dev = crtc->base.dev;
7588 struct drm_i915_private *dev_priv = dev->dev_private;
7589 int pipe = pipe_config->cpu_transcoder;
7590 intel_clock_t clock;
7591 u32 mdiv;
662c6ecb 7592 int refclk = 100000;
acbec814 7593
f573de5a
SK		 7594 /* In case of MIPI DPLL will not even be used */
7595 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7596 return;
7597
acbec814 7598 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7599 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7600 mutex_unlock(&dev_priv->dpio_lock);
7601
7602 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7603 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7604 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7605 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7606 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7607
f646628b 7608 vlv_clock(refclk, &clock);
acbec814 7609
f646628b
VS		 7610 /* clock.dot is the fast clock */
7611 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7612}
7613
5724dbd1
DL		 7614static void
7615i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7616 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7617{
7618 struct drm_device *dev = crtc->base.dev;
7619 struct drm_i915_private *dev_priv = dev->dev_private;
7620 u32 val, base, offset;
7621 int pipe = crtc->pipe, plane = crtc->plane;
7622 int fourcc, pixel_format;
6761dd31 7623 unsigned int aligned_height;
b113d5ee 7624 struct drm_framebuffer *fb;
1b842c89 7625 struct intel_framebuffer *intel_fb;
1ad292b5 7626
42a7b088
DL		 7627 val = I915_READ(DSPCNTR(plane));
7628 if (!(val & DISPLAY_PLANE_ENABLE))
7629 return;
7630
d9806c9f 7631 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7632 if (!intel_fb) {
1ad292b5
JB		 7633 DRM_DEBUG_KMS("failed to alloc fb\n");
7634 return;
7635 }
7636
1b842c89
DL		 7637 fb = &intel_fb->base;
7638
18c5247e
SV		 7639 if (INTEL_INFO(dev)->gen >= 4) {
7640 if (val & DISPPLANE_TILED) {
49af449b 7641 plane_config->tiling = I915_TILING_X;
18c5247e
SV		 7642 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7643 }
7644 }
1ad292b5
JB		 7645
7646 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7647 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7648 fb->pixel_format = fourcc;
7649 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7650
7651 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7652 if (plane_config->tiling)
1ad292b5
JB		 7653 offset = I915_READ(DSPTILEOFF(plane));
7654 else
7655 offset = I915_READ(DSPLINOFF(plane));
7656 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7657 } else {
7658 base = I915_READ(DSPADDR(plane));
7659 }
7660 plane_config->base = base;
7661
7662 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7663 fb->width = ((val >> 16) & 0xfff) + 1;
7664 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7665
7666 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7667 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7668
b113d5ee 7669 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
SV		 7670 fb->pixel_format,
7671 fb->modifier[0]);
1ad292b5 7672
f37b5c2b 7673 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7674
2844a921
DL		 7675 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7676 pipe_name(pipe), plane, fb->width, fb->height,
7677 fb->bits_per_pixel, base, fb->pitches[0],
7678 plane_config->size);
1ad292b5 7679
2d14030b 7680 plane_config->fb = intel_fb;
1ad292b5
JB		 7681}
7682
70b23a98 7683static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7684 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7685{
7686 struct drm_device *dev = crtc->base.dev;
7687 struct drm_i915_private *dev_priv = dev->dev_private;
7688 int pipe = pipe_config->cpu_transcoder;
7689 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7690 intel_clock_t clock;
7691 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7692 int refclk = 100000;
7693
7694 mutex_lock(&dev_priv->dpio_lock);
7695 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7696 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7697 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7698 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7699 mutex_unlock(&dev_priv->dpio_lock);
7700
7701 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7702 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7703 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7704 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7705 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7706
7707 chv_clock(refclk, &clock);
7708
7709 /* clock.dot is the fast clock */
7710 pipe_config->port_clock = clock.dot / 5;
7711}
7712
0e8ffe1b 7713static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7714 struct intel_crtc_state *pipe_config)
0e8ffe1b
SV		 7715{
7716 struct drm_device *dev = crtc->base.dev;
7717 struct drm_i915_private *dev_priv = dev->dev_private;
7718 uint32_t tmp;
7719
f458ebbc
SV		 7720 if (!intel_display_power_is_enabled(dev_priv,
7721 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7722 return false;
7723
e143a21c 7724 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7725 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7726
0e8ffe1b
SV		 7727 tmp = I915_READ(PIPECONF(crtc->pipe));
7728 if (!(tmp & PIPECONF_ENABLE))
7729 return false;
7730
42571aef
VS		 7731 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7732 switch (tmp & PIPECONF_BPC_MASK) {
7733 case PIPECONF_6BPC:
7734 pipe_config->pipe_bpp = 18;
7735 break;
7736 case PIPECONF_8BPC:
7737 pipe_config->pipe_bpp = 24;
7738 break;
7739 case PIPECONF_10BPC:
7740 pipe_config->pipe_bpp = 30;
7741 break;
7742 default:
7743 break;
7744 }
7745 }
7746
b5a9fa09
SV		 7747 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7748 pipe_config->limited_color_range = true;
7749
282740f7
VS		 7750 if (INTEL_INFO(dev)->gen < 4)
7751 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7752
1bd1bd80
SV		 7753 intel_get_pipe_timings(crtc, pipe_config);
7754
2fa2fe9a
SV		 7755 i9xx_get_pfit_config(crtc, pipe_config);
7756
6c49f241
SV		 7757 if (INTEL_INFO(dev)->gen >= 4) {
7758 tmp = I915_READ(DPLL_MD(crtc->pipe));
7759 pipe_config->pixel_multiplier =
7760 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7761 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7762 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
SV		 7763 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7764 tmp = I915_READ(DPLL(crtc->pipe));
7765 pipe_config->pixel_multiplier =
7766 ((tmp & SDVO_MULTIPLIER_MASK)
7767 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7768 } else {
7769 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7770 * port and will be fixed up in the encoder->get_config
7771 * function. */
7772 pipe_config->pixel_multiplier = 1;
7773 }
8bcc2795
SV		 7774 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7775 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7776 /*
7777 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7778 * on 830. Filter it out here so that we don't
7779 * report errors due to that.
7780 */
7781 if (IS_I830(dev))
7782 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7783
8bcc2795
SV		 7784 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7785 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7786 } else {
7787 /* Mask out read-only status bits. */
7788 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7789 DPLL_PORTC_READY_MASK |
7790 DPLL_PORTB_READY_MASK);
8bcc2795 7791 }
6c49f241 7792
70b23a98
VS		 7793 if (IS_CHERRYVIEW(dev))
7794 chv_crtc_clock_get(crtc, pipe_config);
7795 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7796 vlv_crtc_clock_get(crtc, pipe_config);
7797 else
7798 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7799
0e8ffe1b
SV		 7800 return true;
7801}
7802
dde86e2d 7803static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7804{
7805 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7806 struct intel_encoder *encoder;
74cfd7ac 7807 u32 val, final;
13d83a67 7808 bool has_lvds = false;
199e5d79 7809 bool has_cpu_edp = false;
199e5d79 7810 bool has_panel = false;
99eb6a01
KP		 7811 bool has_ck505 = false;
7812 bool can_ssc = false;
13d83a67
JB		 7813
7814 /* We need to take the global config into account */
b2784e15 7815 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7816 switch (encoder->type) {
7817 case INTEL_OUTPUT_LVDS:
7818 has_panel = true;
7819 has_lvds = true;
7820 break;
7821 case INTEL_OUTPUT_EDP:
7822 has_panel = true;
2de6905f 7823 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7824 has_cpu_edp = true;
7825 break;
6847d71b
PZ		 7826 default:
7827 break;
13d83a67
JB		 7828 }
7829 }
7830
99eb6a01 7831 if (HAS_PCH_IBX(dev)) {
41aa3448 7832 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7833 can_ssc = has_ck505;
7834 } else {
7835 has_ck505 = false;
7836 can_ssc = true;
7837 }
7838
2de6905f
ID		 7839 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7840 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7841
7842 /* Ironlake: try to setup display ref clock before DPLL
7843 * enabling. This is only under driver's control after
7844 * PCH B stepping, previous chipset stepping should be
7845 * ignoring this setting.
7846 */
74cfd7ac
CW		 7847 val = I915_READ(PCH_DREF_CONTROL);
7848
7849 /* As we must carefully and slowly disable/enable each source in turn,
7850 * compute the final state we want first and check if we need to
7851 * make any changes at all.
7852 */
7853 final = val;
7854 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7855 if (has_ck505)
7856 final |= DREF_NONSPREAD_CK505_ENABLE;
7857 else
7858 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7859
7860 final &= ~DREF_SSC_SOURCE_MASK;
7861 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7862 final &= ~DREF_SSC1_ENABLE;
7863
7864 if (has_panel) {
7865 final |= DREF_SSC_SOURCE_ENABLE;
7866
7867 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7868 final |= DREF_SSC1_ENABLE;
7869
7870 if (has_cpu_edp) {
7871 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7872 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7873 else
7874 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7875 } else
7876 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7877 } else {
7878 final |= DREF_SSC_SOURCE_DISABLE;
7879 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7880 }
7881
7882 if (final == val)
7883 return;
7884
13d83a67 7885 /* Always enable nonspread source */
74cfd7ac 7886 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7887
99eb6a01 7888 if (has_ck505)
74cfd7ac 7889 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7890 else
74cfd7ac 7891 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7892
199e5d79 7893 if (has_panel) {
74cfd7ac
CW		 7894 val &= ~DREF_SSC_SOURCE_MASK;
7895 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7896
199e5d79 7897 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7898 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7899 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7900 val |= DREF_SSC1_ENABLE;
e77166b5 7901 } else
74cfd7ac 7902 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7903
7904 /* Get SSC going before enabling the outputs */
74cfd7ac 7905 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7906 POSTING_READ(PCH_DREF_CONTROL);
7907 udelay(200);
7908
74cfd7ac 7909 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7910
7911 /* Enable CPU source on CPU attached eDP */
199e5d79 7912 if (has_cpu_edp) {
99eb6a01 7913 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7914 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7915 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7916 } else
74cfd7ac 7917 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7918 } else
74cfd7ac 7919 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7920
74cfd7ac 7921 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7922 POSTING_READ(PCH_DREF_CONTROL);
7923 udelay(200);
7924 } else {
7925 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7926
74cfd7ac 7927 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7928
7929 /* Turn off CPU output */
74cfd7ac 7930 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7931
74cfd7ac 7932 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7933 POSTING_READ(PCH_DREF_CONTROL);
7934 udelay(200);
7935
7936 /* Turn off the SSC source */
74cfd7ac
CW		 7937 val &= ~DREF_SSC_SOURCE_MASK;
7938 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7939
7940 /* Turn off SSC1 */
74cfd7ac 7941 val &= ~DREF_SSC1_ENABLE;
199e5d79 7942
74cfd7ac 7943 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7944 POSTING_READ(PCH_DREF_CONTROL);
7945 udelay(200);
7946 }
74cfd7ac
CW		 7947
7948 BUG_ON(val != final);
13d83a67
JB		 7949}
7950
f31f2d55 7951static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7952{
f31f2d55 7953 uint32_t tmp;
dde86e2d 7954
0ff066a9
PZ		 7955 tmp = I915_READ(SOUTH_CHICKEN2);
7956 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7957 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7958
0ff066a9
PZ		 7959 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7960 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7961 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7962
0ff066a9
PZ		 7963 tmp = I915_READ(SOUTH_CHICKEN2);
7964 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7965 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7966
0ff066a9
PZ		 7967 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7968 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7969 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7970}
7971
7972/* WaMPhyProgramming:hsw */
7973static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7974{
7975 uint32_t tmp;
dde86e2d
PZ		 7976
7977 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7978 tmp &= ~(0xFF << 24);
7979 tmp |= (0x12 << 24);
7980 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7981
dde86e2d
PZ		 7982 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7983 tmp |= (1 << 11);
7984 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7985
7986 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7987 tmp |= (1 << 11);
7988 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7989
dde86e2d
PZ		 7990 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7991 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7992 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7993
7994 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7995 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7996 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7997
0ff066a9
PZ		 7998 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7999 tmp &= ~(7 << 13);
8000 tmp |= (5 << 13);
8001 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8002
0ff066a9
PZ		 8003 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8004 tmp &= ~(7 << 13);
8005 tmp |= (5 << 13);
8006 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8007
8008 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8009 tmp &= ~0xFF;
8010 tmp |= 0x1C;
8011 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8012
8013 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8014 tmp &= ~0xFF;
8015 tmp |= 0x1C;
8016 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8017
8018 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8019 tmp &= ~(0xFF << 16);
8020 tmp |= (0x1C << 16);
8021 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8022
8023 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8024 tmp &= ~(0xFF << 16);
8025 tmp |= (0x1C << 16);
8026 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8027
0ff066a9
PZ		 8028 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8029 tmp |= (1 << 27);
8030 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8031
0ff066a9
PZ		 8032 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8033 tmp |= (1 << 27);
8034 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8035
0ff066a9
PZ		 8036 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8037 tmp &= ~(0xF << 28);
8038 tmp |= (4 << 28);
8039 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8040
0ff066a9
PZ		 8041 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8042 tmp &= ~(0xF << 28);
8043 tmp |= (4 << 28);
8044 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8045}
8046
2fa86a1f
PZ		 8047/* Implements 3 different sequences from BSpec chapter "Display iCLK
8048 * Programming" based on the parameters passed:
8049 * - Sequence to enable CLKOUT_DP
8050 * - Sequence to enable CLKOUT_DP without spread
8051 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8052 */
8053static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8054 bool with_fdi)
f31f2d55
PZ		 8055{
8056 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8057 uint32_t reg, tmp;
8058
8059 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8060 with_spread = true;
8061 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8062 with_fdi, "LP PCH doesn't have FDI\n"))
8063 with_fdi = false;
f31f2d55
PZ		 8064
8065 mutex_lock(&dev_priv->dpio_lock);
8066
8067 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8068 tmp &= ~SBI_SSCCTL_DISABLE;
8069 tmp |= SBI_SSCCTL_PATHALT;
8070 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8071
8072 udelay(24);
8073
2fa86a1f
PZ		 8074 if (with_spread) {
8075 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8076 tmp &= ~SBI_SSCCTL_PATHALT;
8077 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8078
2fa86a1f
PZ		 8079 if (with_fdi) {
8080 lpt_reset_fdi_mphy(dev_priv);
8081 lpt_program_fdi_mphy(dev_priv);
8082 }
8083 }
dde86e2d 8084
2fa86a1f
PZ		 8085 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8086 SBI_GEN0 : SBI_DBUFF0;
8087 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8088 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8089 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
SV		 8090
8091 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8092}
8093
47701c3b
PZ		 8094/* Sequence to disable CLKOUT_DP */
8095static void lpt_disable_clkout_dp(struct drm_device *dev)
8096{
8097 struct drm_i915_private *dev_priv = dev->dev_private;
8098 uint32_t reg, tmp;
8099
8100 mutex_lock(&dev_priv->dpio_lock);
8101
8102 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8103 SBI_GEN0 : SBI_DBUFF0;
8104 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8105 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8106 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8107
8108 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8109 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8110 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8111 tmp |= SBI_SSCCTL_PATHALT;
8112 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8113 udelay(32);
8114 }
8115 tmp |= SBI_SSCCTL_DISABLE;
8116 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8117 }
8118
8119 mutex_unlock(&dev_priv->dpio_lock);
8120}
8121
bf8fa3d3
PZ		 8122static void lpt_init_pch_refclk(struct drm_device *dev)
8123{
bf8fa3d3
PZ		 8124 struct intel_encoder *encoder;
8125 bool has_vga = false;
8126
b2784e15 8127 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8128 switch (encoder->type) {
8129 case INTEL_OUTPUT_ANALOG:
8130 has_vga = true;
8131 break;
6847d71b
PZ		 8132 default:
8133 break;
bf8fa3d3
PZ		 8134 }
8135 }
8136
47701c3b
PZ		 8137 if (has_vga)
8138 lpt_enable_clkout_dp(dev, true, true);
8139 else
8140 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8141}
8142
dde86e2d
PZ		 8143/*
8144 * Initialize reference clocks when the driver loads
8145 */
8146void intel_init_pch_refclk(struct drm_device *dev)
8147{
8148 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8149 ironlake_init_pch_refclk(dev);
8150 else if (HAS_PCH_LPT(dev))
8151 lpt_init_pch_refclk(dev);
8152}
8153
55bb9992 8154static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8155{
55bb9992 8156 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8157 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8158 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8159 struct drm_connector *connector;
55bb9992 8160 struct drm_connector_state *connector_state;
d9d444cb 8161 struct intel_encoder *encoder;
55bb9992 8162 int num_connectors = 0, i;
d9d444cb
JB		 8163 bool is_lvds = false;
8164
da3ced29 8165 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8166 if (connector_state->crtc != crtc_state->base.crtc)
8167 continue;
8168
8169 encoder = to_intel_encoder(connector_state->best_encoder);
8170
d9d444cb
JB		 8171 switch (encoder->type) {
8172 case INTEL_OUTPUT_LVDS:
8173 is_lvds = true;
8174 break;
6847d71b
PZ		 8175 default:
8176 break;
d9d444cb
JB		 8177 }
8178 num_connectors++;
8179 }
8180
8181 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8182 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8183 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8184 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8185 }
8186
8187 return 120000;
8188}
8189
6ff93609 8190static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8191{
c8203565 8192 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8194 int pipe = intel_crtc->pipe;
c8203565
PZ		 8195 uint32_t val;
8196
78114071 8197 val = 0;
c8203565 8198
6e3c9717 8199 switch (intel_crtc->config->pipe_bpp) {
c8203565 8200 case 18:
dfd07d72 8201 val |= PIPECONF_6BPC;
c8203565
PZ		 8202 break;
8203 case 24:
dfd07d72 8204 val |= PIPECONF_8BPC;
c8203565
PZ		 8205 break;
8206 case 30:
dfd07d72 8207 val |= PIPECONF_10BPC;
c8203565
PZ		 8208 break;
8209 case 36:
dfd07d72 8210 val |= PIPECONF_12BPC;
c8203565
PZ		 8211 break;
8212 default:
cc769b62
PZ		 8213 /* Case prevented by intel_choose_pipe_bpp_dither. */
8214 BUG();
c8203565
PZ		 8215 }
8216
6e3c9717 8217 if (intel_crtc->config->dither)
c8203565
PZ		 8218 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8219
6e3c9717 8220 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8221 val |= PIPECONF_INTERLACED_ILK;
8222 else
8223 val |= PIPECONF_PROGRESSIVE;
8224
6e3c9717 8225 if (intel_crtc->config->limited_color_range)
3685a8f3 8226 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8227
c8203565
PZ		 8228 I915_WRITE(PIPECONF(pipe), val);
8229 POSTING_READ(PIPECONF(pipe));
8230}
8231
86d3efce
VS		 8232/*
8233 * Set up the pipe CSC unit.
8234 *
8235 * Currently only full range RGB to limited range RGB conversion
8236 * is supported, but eventually this should handle various
8237 * RGB<->YCbCr scenarios as well.
8238 */
50f3b016 8239static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8240{
8241 struct drm_device *dev = crtc->dev;
8242 struct drm_i915_private *dev_priv = dev->dev_private;
8243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8244 int pipe = intel_crtc->pipe;
8245 uint16_t coeff = 0x7800; /* 1.0 */
8246
8247 /*
8248 * TODO: Check what kind of values actually come out of the pipe
8249 * with these coeff/postoff values and adjust to get the best
8250 * accuracy. Perhaps we even need to take the bpc value into
8251 * consideration.
8252 */
8253
6e3c9717 8254 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8255 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8256
8257 /*
8258 * GY/GU and RY/RU should be the other way around according
8259 * to BSpec, but reality doesn't agree. Just set them up in
8260 * a way that results in the correct picture.
8261 */
8262 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8263 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8264
8265 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8266 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8267
8268 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8269 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8270
8271 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8272 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8273 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8274
8275 if (INTEL_INFO(dev)->gen > 6) {
8276 uint16_t postoff = 0;
8277
6e3c9717 8278 if (intel_crtc->config->limited_color_range)
32cf0cb0 8279 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8280
8281 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8282 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8283 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8284
8285 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8286 } else {
8287 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8288
6e3c9717 8289 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8290 mode |= CSC_BLACK_SCREEN_OFFSET;
8291
8292 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8293 }
8294}
8295
6ff93609 8296static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8297{
756f85cf
PZ		 8298 struct drm_device *dev = crtc->dev;
8299 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8301 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8302 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8303 uint32_t val;
8304
3eff4faa 8305 val = 0;
ee2b0b38 8306
6e3c9717 8307 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8308 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8309
6e3c9717 8310 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8311 val |= PIPECONF_INTERLACED_ILK;
8312 else
8313 val |= PIPECONF_PROGRESSIVE;
8314
702e7a56
PZ		 8315 I915_WRITE(PIPECONF(cpu_transcoder), val);
8316 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
SV		 8317
8318 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8319 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8320
3cdf122c 8321 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8322 val = 0;
8323
6e3c9717 8324 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8325 case 18:
8326 val |= PIPEMISC_DITHER_6_BPC;
8327 break;
8328 case 24:
8329 val |= PIPEMISC_DITHER_8_BPC;
8330 break;
8331 case 30:
8332 val |= PIPEMISC_DITHER_10_BPC;
8333 break;
8334 case 36:
8335 val |= PIPEMISC_DITHER_12_BPC;
8336 break;
8337 default:
8338 /* Case prevented by pipe_config_set_bpp. */
8339 BUG();
8340 }
8341
6e3c9717 8342 if (intel_crtc->config->dither)
756f85cf
PZ		 8343 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8344
8345 I915_WRITE(PIPEMISC(pipe), val);
8346 }
ee2b0b38
PZ		 8347}
8348
6591c6e4 8349static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8350 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8351 intel_clock_t *clock,
8352 bool *has_reduced_clock,
8353 intel_clock_t *reduced_clock)
8354{
8355 struct drm_device *dev = crtc->dev;
8356 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8357 int refclk;
d4906093 8358 const intel_limit_t *limit;
a16af721 8359 bool ret, is_lvds = false;
79e53945 8360
a93e255f 8361 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8362
55bb9992 8363 refclk = ironlake_get_refclk(crtc_state);
79e53945 8364
d4906093
ML		 8365 /*
8366 * Returns a set of divisors for the desired target clock with the given
8367 * refclk, or FALSE. The returned values represent the clock equation:
8368 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8369 */
a93e255f
ACO		 8370 limit = intel_limit(crtc_state, refclk);
8371 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8372 crtc_state->port_clock,
ee9300bb 8373 refclk, NULL, clock);
6591c6e4
PZ		 8374 if (!ret)
8375 return false;
cda4b7d3 8376
ddc9003c 8377 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8378 /*
8379 * Ensure we match the reduced clock's P to the target clock.
8380 * If the clocks don't match, we can't switch the display clock
8381 * by using the FP0/FP1. In such case we will disable the LVDS
8382 * downclock feature.
8383 */
ee9300bb 8384 *has_reduced_clock =
a93e255f 8385 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
SV		 8386 dev_priv->lvds_downclock,
8387 refclk, clock,
8388 reduced_clock);
652c393a 8389 }
61e9653f 8390
6591c6e4
PZ		 8391 return true;
8392}
8393
d4b1931c
PZ		 8394int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8395{
8396 /*
8397 * Account for spread spectrum to avoid
8398 * oversubscribing the link. Max center spread
8399 * is 2.5%; use 5% for safety's sake.
8400 */
8401 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8402 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8403}
8404
7429e9d4 8405static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8406{
7429e9d4 8407 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8408}
8409
de13a2e3 8410static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8411 struct intel_crtc_state *crtc_state,
7429e9d4 8412 u32 *fp,
9a7c7890 8413 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8414{
de13a2e3 8415 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8416 struct drm_device *dev = crtc->dev;
8417 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8418 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8419 struct drm_connector *connector;
55bb9992
ACO		 8420 struct drm_connector_state *connector_state;
8421 struct intel_encoder *encoder;
de13a2e3 8422 uint32_t dpll;
55bb9992 8423 int factor, num_connectors = 0, i;
09ede541 8424 bool is_lvds = false, is_sdvo = false;
79e53945 8425
da3ced29 8426 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8427 if (connector_state->crtc != crtc_state->base.crtc)
8428 continue;
8429
8430 encoder = to_intel_encoder(connector_state->best_encoder);
8431
8432 switch (encoder->type) {
79e53945
JB		 8433 case INTEL_OUTPUT_LVDS:
8434 is_lvds = true;
8435 break;
8436 case INTEL_OUTPUT_SDVO:
7d57382e 8437 case INTEL_OUTPUT_HDMI:
79e53945 8438 is_sdvo = true;
79e53945 8439 break;
6847d71b
PZ		 8440 default:
8441 break;
79e53945 8442 }
43565a06 8443
c751ce4f 8444 num_connectors++;
79e53945 8445 }
79e53945 8446
c1858123 8447 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8448 factor = 21;
8449 if (is_lvds) {
8450 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8451 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8452 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8453 factor = 25;
190f68c5 8454 } else if (crtc_state->sdvo_tv_clock)
8febb297 8455 factor = 20;
c1858123 8456
190f68c5 8457 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8458 *fp |= FP_CB_TUNE;
2c07245f 8459
9a7c7890
SV		 8460 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8461 *fp2 |= FP_CB_TUNE;
8462
5eddb70b 8463 dpll = 0;
2c07245f 8464
a07d6787
EA		 8465 if (is_lvds)
8466 dpll |= DPLLB_MODE_LVDS;
8467 else
8468 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8469
190f68c5 8470 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8471 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
SV		 8472
8473 if (is_sdvo)
4a33e48d 8474 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8475 if (crtc_state->has_dp_encoder)
4a33e48d 8476 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8477
a07d6787 8478 /* compute bitmask from p1 value */
190f68c5 8479 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8480 /* also FPA1 */
190f68c5 8481 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8482
190f68c5 8483 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8484 case 5:
8485 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8486 break;
8487 case 7:
8488 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8489 break;
8490 case 10:
8491 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8492 break;
8493 case 14:
8494 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8495 break;
79e53945
JB		 8496 }
8497
b4c09f3b 8498 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8499 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8500 else
8501 dpll |= PLL_REF_INPUT_DREFCLK;
8502
959e16d6 8503 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8504}
8505
190f68c5
ACO		 8506static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8507 struct intel_crtc_state *crtc_state)
de13a2e3 8508{
c7653199 8509 struct drm_device *dev = crtc->base.dev;
de13a2e3 8510 intel_clock_t clock, reduced_clock;
cbbab5bd 8511 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8512 bool ok, has_reduced_clock = false;
8b47047b 8513 bool is_lvds = false;
e2b78267 8514 struct intel_shared_dpll *pll;
de13a2e3 8515
409ee761 8516 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8517
5dc5298b
PZ		 8518 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8519 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8520
190f68c5 8521 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8522 &has_reduced_clock, &reduced_clock);
190f68c5 8523 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8524 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8525 return -EINVAL;
79e53945 8526 }
f47709a9 8527 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8528 if (!crtc_state->clock_set) {
8529 crtc_state->dpll.n = clock.n;
8530 crtc_state->dpll.m1 = clock.m1;
8531 crtc_state->dpll.m2 = clock.m2;
8532 crtc_state->dpll.p1 = clock.p1;
8533 crtc_state->dpll.p2 = clock.p2;
f47709a9 8534 }
79e53945 8535
5dc5298b 8536 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8537 if (crtc_state->has_pch_encoder) {
8538 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8539 if (has_reduced_clock)
7429e9d4 8540 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8541
190f68c5 8542 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
SV		 8543 &fp, &reduced_clock,
8544 has_reduced_clock ? &fp2 : NULL);
8545
190f68c5
ACO		 8546 crtc_state->dpll_hw_state.dpll = dpll;
8547 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8548 if (has_reduced_clock)
190f68c5 8549 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8550 else
190f68c5 8551 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8552
190f68c5 8553 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8554 if (pll == NULL) {
84f44ce7 8555 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8556 pipe_name(crtc->pipe));
4b645f14
JB		 8557 return -EINVAL;
8558 }
3fb37703 8559 }
79e53945 8560
ab585dea 8561 if (is_lvds && has_reduced_clock)
c7653199 8562 crtc->lowfreq_avail = true;
bcd644e0 8563 else
c7653199 8564 crtc->lowfreq_avail = false;
e2b78267 8565
c8f7a0db 8566 return 0;
79e53945
JB		 8567}
8568
eb14cb74
VS		 8569static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8570 struct intel_link_m_n *m_n)
8571{
8572 struct drm_device *dev = crtc->base.dev;
8573 struct drm_i915_private *dev_priv = dev->dev_private;
8574 enum pipe pipe = crtc->pipe;
8575
8576 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8577 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8578 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8579 & ~TU_SIZE_MASK;
8580 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8581 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8582 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8583}
8584
8585static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8586 enum transcoder transcoder,
b95af8be
VK		 8587 struct intel_link_m_n *m_n,
8588 struct intel_link_m_n *m2_n2)
72419203
SV		 8589{
8590 struct drm_device *dev = crtc->base.dev;
8591 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8592 enum pipe pipe = crtc->pipe;
72419203 8593
eb14cb74
VS		 8594 if (INTEL_INFO(dev)->gen >= 5) {
8595 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8596 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8597 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8598 & ~TU_SIZE_MASK;
8599 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8600 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8601 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8602 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8603 * gen < 8) and if DRRS is supported (to make sure the
8604 * registers are not unnecessarily read).
8605 */
8606 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8607 crtc->config->has_drrs) {
b95af8be
VK		 8608 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8609 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8610 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8611 & ~TU_SIZE_MASK;
8612 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8613 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8614 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8615 }
eb14cb74
VS		 8616 } else {
8617 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8618 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8619 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8620 & ~TU_SIZE_MASK;
8621 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8622 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8623 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8624 }
8625}
8626
8627void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8628 struct intel_crtc_state *pipe_config)
eb14cb74 8629{
681a8504 8630 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8631 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8632 else
8633 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8634 &pipe_config->dp_m_n,
8635 &pipe_config->dp_m2_n2);
eb14cb74 8636}
72419203 8637
eb14cb74 8638static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8639 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8640{
8641 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8642 &pipe_config->fdi_m_n, NULL);
72419203
SV		 8643}
8644
bd2e244f 8645static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8646 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8647{
8648 struct drm_device *dev = crtc->base.dev;
8649 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8650 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8651 uint32_t ps_ctrl = 0;
8652 int id = -1;
8653 int i;
bd2e244f 8654
a1b2278e
CK		 8655 /* find scaler attached to this pipe */
8656 for (i = 0; i < crtc->num_scalers; i++) {
8657 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8658 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8659 id = i;
8660 pipe_config->pch_pfit.enabled = true;
8661 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8662 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8663 break;
8664 }
8665 }
bd2e244f 8666
a1b2278e
CK		 8667 scaler_state->scaler_id = id;
8668 if (id >= 0) {
8669 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8670 } else {
8671 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8672 }
8673}
8674
5724dbd1
DL		 8675static void
8676skylake_get_initial_plane_config(struct intel_crtc *crtc,
8677 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8678{
8679 struct drm_device *dev = crtc->base.dev;
8680 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8681 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8682 int pipe = crtc->pipe;
8683 int fourcc, pixel_format;
6761dd31 8684 unsigned int aligned_height;
bc8d7dff 8685 struct drm_framebuffer *fb;
1b842c89 8686 struct intel_framebuffer *intel_fb;
bc8d7dff 8687
d9806c9f 8688 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8689 if (!intel_fb) {
bc8d7dff
DL		 8690 DRM_DEBUG_KMS("failed to alloc fb\n");
8691 return;
8692 }
8693
1b842c89
DL		 8694 fb = &intel_fb->base;
8695
bc8d7dff 8696 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8697 if (!(val & PLANE_CTL_ENABLE))
8698 goto error;
8699
bc8d7dff
DL		 8700 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8701 fourcc = skl_format_to_fourcc(pixel_format,
8702 val & PLANE_CTL_ORDER_RGBX,
8703 val & PLANE_CTL_ALPHA_MASK);
8704 fb->pixel_format = fourcc;
8705 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8706
40f46283
DL		 8707 tiling = val & PLANE_CTL_TILED_MASK;
8708 switch (tiling) {
8709 case PLANE_CTL_TILED_LINEAR:
8710 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8711 break;
8712 case PLANE_CTL_TILED_X:
8713 plane_config->tiling = I915_TILING_X;
8714 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8715 break;
8716 case PLANE_CTL_TILED_Y:
8717 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8718 break;
8719 case PLANE_CTL_TILED_YF:
8720 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8721 break;
8722 default:
8723 MISSING_CASE(tiling);
8724 goto error;
8725 }
8726
bc8d7dff
DL		 8727 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8728 plane_config->base = base;
8729
8730 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8731
8732 val = I915_READ(PLANE_SIZE(pipe, 0));
8733 fb->height = ((val >> 16) & 0xfff) + 1;
8734 fb->width = ((val >> 0) & 0x1fff) + 1;
8735
8736 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8737 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8738 fb->pixel_format);
bc8d7dff
DL		 8739 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8740
8741 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
SV		 8742 fb->pixel_format,
8743 fb->modifier[0]);
bc8d7dff 8744
f37b5c2b 8745 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8746
8747 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8748 pipe_name(pipe), fb->width, fb->height,
8749 fb->bits_per_pixel, base, fb->pitches[0],
8750 plane_config->size);
8751
2d14030b 8752 plane_config->fb = intel_fb;
bc8d7dff
DL		 8753 return;
8754
8755error:
8756 kfree(fb);
8757}
8758
2fa2fe9a 8759static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8760 struct intel_crtc_state *pipe_config)
2fa2fe9a
SV		 8761{
8762 struct drm_device *dev = crtc->base.dev;
8763 struct drm_i915_private *dev_priv = dev->dev_private;
8764 uint32_t tmp;
8765
8766 tmp = I915_READ(PF_CTL(crtc->pipe));
8767
8768 if (tmp & PF_ENABLE) {
fd4daa9c 8769 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
SV		 8770 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8771 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
SV		 8772
8773 /* We currently do not free assignements of panel fitters on
8774 * ivb/hsw (since we don't use the higher upscaling modes which
8775 * differentiates them) so just WARN about this case for now. */
8776 if (IS_GEN7(dev)) {
8777 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8778 PF_PIPE_SEL_IVB(crtc->pipe));
8779 }
2fa2fe9a 8780 }
79e53945
JB		 8781}
8782
5724dbd1
DL		 8783static void
8784ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8785 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8786{
8787 struct drm_device *dev = crtc->base.dev;
8788 struct drm_i915_private *dev_priv = dev->dev_private;
8789 u32 val, base, offset;
aeee5a49 8790 int pipe = crtc->pipe;
4c6baa59 8791 int fourcc, pixel_format;
6761dd31 8792 unsigned int aligned_height;
b113d5ee 8793 struct drm_framebuffer *fb;
1b842c89 8794 struct intel_framebuffer *intel_fb;
4c6baa59 8795
42a7b088
DL		 8796 val = I915_READ(DSPCNTR(pipe));
8797 if (!(val & DISPLAY_PLANE_ENABLE))
8798 return;
8799
d9806c9f 8800 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8801 if (!intel_fb) {
4c6baa59
JB		 8802 DRM_DEBUG_KMS("failed to alloc fb\n");
8803 return;
8804 }
8805
1b842c89
DL		 8806 fb = &intel_fb->base;
8807
18c5247e
SV		 8808 if (INTEL_INFO(dev)->gen >= 4) {
8809 if (val & DISPPLANE_TILED) {
49af449b 8810 plane_config->tiling = I915_TILING_X;
18c5247e
SV		 8811 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8812 }
8813 }
4c6baa59
JB		 8814
8815 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8816 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8817 fb->pixel_format = fourcc;
8818 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8819
aeee5a49 8820 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8821 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8822 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8823 } else {
49af449b 8824 if (plane_config->tiling)
aeee5a49 8825 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8826 else
aeee5a49 8827 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8828 }
8829 plane_config->base = base;
8830
8831 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8832 fb->width = ((val >> 16) & 0xfff) + 1;
8833 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8834
8835 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8836 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8837
b113d5ee 8838 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
SV		 8839 fb->pixel_format,
8840 fb->modifier[0]);
4c6baa59 8841
f37b5c2b 8842 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8843
2844a921
DL		 8844 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8845 pipe_name(pipe), fb->width, fb->height,
8846 fb->bits_per_pixel, base, fb->pitches[0],
8847 plane_config->size);
b113d5ee 8848
2d14030b 8849 plane_config->fb = intel_fb;
4c6baa59
JB		 8850}
8851
0e8ffe1b 8852static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8853 struct intel_crtc_state *pipe_config)
0e8ffe1b
SV		 8854{
8855 struct drm_device *dev = crtc->base.dev;
8856 struct drm_i915_private *dev_priv = dev->dev_private;
8857 uint32_t tmp;
8858
f458ebbc
SV		 8859 if (!intel_display_power_is_enabled(dev_priv,
8860 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8861 return false;
8862
e143a21c 8863 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8864 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8865
0e8ffe1b
SV		 8866 tmp = I915_READ(PIPECONF(crtc->pipe));
8867 if (!(tmp & PIPECONF_ENABLE))
8868 return false;
8869
42571aef
VS		 8870 switch (tmp & PIPECONF_BPC_MASK) {
8871 case PIPECONF_6BPC:
8872 pipe_config->pipe_bpp = 18;
8873 break;
8874 case PIPECONF_8BPC:
8875 pipe_config->pipe_bpp = 24;
8876 break;
8877 case PIPECONF_10BPC:
8878 pipe_config->pipe_bpp = 30;
8879 break;
8880 case PIPECONF_12BPC:
8881 pipe_config->pipe_bpp = 36;
8882 break;
8883 default:
8884 break;
8885 }
8886
b5a9fa09
SV		 8887 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8888 pipe_config->limited_color_range = true;
8889
ab9412ba 8890 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
SV		 8891 struct intel_shared_dpll *pll;
8892
88adfff1
SV		 8893 pipe_config->has_pch_encoder = true;
8894
627eb5a3
SV		 8895 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8896 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8897 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
SV		 8898
8899 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8900
c0d43d62 8901 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
SV		 8902 pipe_config->shared_dpll =
8903 (enum intel_dpll_id) crtc->pipe;
c0d43d62
SV		 8904 } else {
8905 tmp = I915_READ(PCH_DPLL_SEL);
8906 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8907 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8908 else
8909 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8910 }
66e985c0
SV		 8911
8912 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8913
8914 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8915 &pipe_config->dpll_hw_state));
c93f54cf
SV		 8916
8917 tmp = pipe_config->dpll_hw_state.dpll;
8918 pipe_config->pixel_multiplier =
8919 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8920 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8921
8922 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
SV		 8923 } else {
8924 pipe_config->pixel_multiplier = 1;
627eb5a3
SV		 8925 }
8926
1bd1bd80
SV		 8927 intel_get_pipe_timings(crtc, pipe_config);
8928
2fa2fe9a
SV		 8929 ironlake_get_pfit_config(crtc, pipe_config);
8930
0e8ffe1b
SV		 8931 return true;
8932}
8933
be256dc7
PZ		 8934static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8935{
8936 struct drm_device *dev = dev_priv->dev;
be256dc7 8937 struct intel_crtc *crtc;
be256dc7 8938
d3fcc808 8939 for_each_intel_crtc(dev, crtc)
e2c719b7 8940 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8941 pipe_name(crtc->pipe));
8942
e2c719b7
RC		 8943 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8944 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8945 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8946 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8947 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8948 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8949 "CPU PWM1 enabled\n");
c5107b87 8950 if (IS_HASWELL(dev))
e2c719b7 8951 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8952 "CPU PWM2 enabled\n");
e2c719b7 8953 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8954 "PCH PWM1 enabled\n");
e2c719b7 8955 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8956 "Utility pin enabled\n");
e2c719b7 8957 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8958
9926ada1
PZ		 8959 /*
8960 * In theory we can still leave IRQs enabled, as long as only the HPD
8961 * interrupts remain enabled. We used to check for that, but since it's
8962 * gen-specific and since we only disable LCPLL after we fully disable
8963 * the interrupts, the check below should be enough.
8964 */
e2c719b7 8965 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8966}
8967
9ccd5aeb
PZ		 8968static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8969{
8970 struct drm_device *dev = dev_priv->dev;
8971
8972 if (IS_HASWELL(dev))
8973 return I915_READ(D_COMP_HSW);
8974 else
8975 return I915_READ(D_COMP_BDW);
8976}
8977
3c4c9b81
PZ		 8978static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8979{
8980 struct drm_device *dev = dev_priv->dev;
8981
8982 if (IS_HASWELL(dev)) {
8983 mutex_lock(&dev_priv->rps.hw_lock);
8984 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8985 val))
f475dadf 8986 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8987 mutex_unlock(&dev_priv->rps.hw_lock);
8988 } else {
9ccd5aeb
PZ		 8989 I915_WRITE(D_COMP_BDW, val);
8990 POSTING_READ(D_COMP_BDW);
3c4c9b81 8991 }
be256dc7
PZ		 8992}
8993
8994/*
8995 * This function implements pieces of two sequences from BSpec:
8996 * - Sequence for display software to disable LCPLL
8997 * - Sequence for display software to allow package C8+
8998 * The steps implemented here are just the steps that actually touch the LCPLL
8999 * register. Callers should take care of disabling all the display engine
9000 * functions, doing the mode unset, fixing interrupts, etc.
9001 */
6ff58d53
PZ		 9002static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9003 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9004{
9005 uint32_t val;
9006
9007 assert_can_disable_lcpll(dev_priv);
9008
9009 val = I915_READ(LCPLL_CTL);
9010
9011 if (switch_to_fclk) {
9012 val |= LCPLL_CD_SOURCE_FCLK;
9013 I915_WRITE(LCPLL_CTL, val);
9014
9015 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9016 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9017 DRM_ERROR("Switching to FCLK failed\n");
9018
9019 val = I915_READ(LCPLL_CTL);
9020 }
9021
9022 val |= LCPLL_PLL_DISABLE;
9023 I915_WRITE(LCPLL_CTL, val);
9024 POSTING_READ(LCPLL_CTL);
9025
9026 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9027 DRM_ERROR("LCPLL still locked\n");
9028
9ccd5aeb 9029 val = hsw_read_dcomp(dev_priv);
be256dc7 9030 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9031 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9032 ndelay(100);
9033
9ccd5aeb
PZ		 9034 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9035 1))
be256dc7
PZ		 9036 DRM_ERROR("D_COMP RCOMP still in progress\n");
9037
9038 if (allow_power_down) {
9039 val = I915_READ(LCPLL_CTL);
9040 val |= LCPLL_POWER_DOWN_ALLOW;
9041 I915_WRITE(LCPLL_CTL, val);
9042 POSTING_READ(LCPLL_CTL);
9043 }
9044}
9045
9046/*
9047 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9048 * source.
9049 */
6ff58d53 9050static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9051{
9052 uint32_t val;
9053
9054 val = I915_READ(LCPLL_CTL);
9055
9056 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9057 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9058 return;
9059
a8a8bd54
PZ		 9060 /*
9061 * Make sure we're not on PC8 state before disabling PC8, otherwise
9062 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9063 */
59bad947 9064 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9065
be256dc7
PZ		 9066 if (val & LCPLL_POWER_DOWN_ALLOW) {
9067 val &= ~LCPLL_POWER_DOWN_ALLOW;
9068 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9069 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9070 }
9071
9ccd5aeb 9072 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9073 val |= D_COMP_COMP_FORCE;
9074 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9075 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9076
9077 val = I915_READ(LCPLL_CTL);
9078 val &= ~LCPLL_PLL_DISABLE;
9079 I915_WRITE(LCPLL_CTL, val);
9080
9081 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9082 DRM_ERROR("LCPLL not locked yet\n");
9083
9084 if (val & LCPLL_CD_SOURCE_FCLK) {
9085 val = I915_READ(LCPLL_CTL);
9086 val &= ~LCPLL_CD_SOURCE_FCLK;
9087 I915_WRITE(LCPLL_CTL, val);
9088
9089 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9090 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9091 DRM_ERROR("Switching back to LCPLL failed\n");
9092 }
215733fa 9093
59bad947 9094 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9095}
9096
765dab67
PZ		 9097/*
9098 * Package states C8 and deeper are really deep PC states that can only be
9099 * reached when all the devices on the system allow it, so even if the graphics
9100 * device allows PC8+, it doesn't mean the system will actually get to these
9101 * states. Our driver only allows PC8+ when going into runtime PM.
9102 *
9103 * The requirements for PC8+ are that all the outputs are disabled, the power
9104 * well is disabled and most interrupts are disabled, and these are also
9105 * requirements for runtime PM. When these conditions are met, we manually do
9106 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9107 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9108 * hang the machine.
9109 *
9110 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9111 * the state of some registers, so when we come back from PC8+ we need to
9112 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9113 * need to take care of the registers kept by RC6. Notice that this happens even
9114 * if we don't put the device in PCI D3 state (which is what currently happens
9115 * because of the runtime PM support).
9116 *
9117 * For more, read "Display Sequences for Package C8" on the hardware
9118 * documentation.
9119 */
a14cb6fc 9120void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9121{
c67a470b
PZ		 9122 struct drm_device *dev = dev_priv->dev;
9123 uint32_t val;
9124
c67a470b
PZ		 9125 DRM_DEBUG_KMS("Enabling package C8+\n");
9126
c67a470b
PZ		 9127 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9128 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9129 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9130 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9131 }
9132
9133 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9134 hsw_disable_lcpll(dev_priv, true, true);
9135}
9136
a14cb6fc 9137void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9138{
9139 struct drm_device *dev = dev_priv->dev;
9140 uint32_t val;
9141
c67a470b
PZ		 9142 DRM_DEBUG_KMS("Disabling package C8+\n");
9143
9144 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9145 lpt_init_pch_refclk(dev);
9146
9147 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9148 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9149 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9150 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9151 }
9152
9153 intel_prepare_ddi(dev);
c67a470b
PZ		 9154}
9155
f8437dd1
VK		 9156static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9157{
9158 struct drm_device *dev = state->dev;
9159 struct drm_i915_private *dev_priv = dev->dev_private;
9160 int max_pixclk = intel_mode_max_pixclk(state);
9161 int req_cdclk;
9162
9163 /* see the comment in valleyview_modeset_global_resources */
9164 if (WARN_ON(max_pixclk < 0))
9165 return;
9166
9167 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9168
9169 if (req_cdclk != dev_priv->cdclk_freq)
9170 broxton_set_cdclk(dev, req_cdclk);
9171}
9172
190f68c5
ACO		 9173static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9174 struct intel_crtc_state *crtc_state)
09b4ddf9 9175{
190f68c5 9176 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9177 return -EINVAL;
716c2e55 9178
c7653199 9179 crtc->lowfreq_avail = false;
644cef34 9180
c8f7a0db 9181 return 0;
79e53945
JB		 9182}
9183
3760b59c
S		 9184static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9185 enum port port,
9186 struct intel_crtc_state *pipe_config)
9187{
9188 switch (port) {
9189 case PORT_A:
9190 pipe_config->ddi_pll_sel = SKL_DPLL0;
9191 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9192 break;
9193 case PORT_B:
9194 pipe_config->ddi_pll_sel = SKL_DPLL1;
9195 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9196 break;
9197 case PORT_C:
9198 pipe_config->ddi_pll_sel = SKL_DPLL2;
9199 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9200 break;
9201 default:
9202 DRM_ERROR("Incorrect port type\n");
9203 }
9204}
9205
96b7dfb7
S		 9206static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9207 enum port port,
5cec258b 9208 struct intel_crtc_state *pipe_config)
96b7dfb7 9209{
3148ade7 9210 u32 temp, dpll_ctl1;
96b7dfb7
S		 9211
9212 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9213 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9214
9215 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9216 case SKL_DPLL0:
9217 /*
9218 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9219 * of the shared DPLL framework and thus needs to be read out
9220 * separately
9221 */
9222 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9223 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9224 break;
96b7dfb7
S		 9225 case SKL_DPLL1:
9226 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9227 break;
9228 case SKL_DPLL2:
9229 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9230 break;
9231 case SKL_DPLL3:
9232 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9233 break;
96b7dfb7
S		 9234 }
9235}
9236
7d2c8175
DL		 9237static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9238 enum port port,
5cec258b 9239 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9240{
9241 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9242
9243 switch (pipe_config->ddi_pll_sel) {
9244 case PORT_CLK_SEL_WRPLL1:
9245 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9246 break;
9247 case PORT_CLK_SEL_WRPLL2:
9248 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9249 break;
9250 }
9251}
9252
26804afd 9253static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9254 struct intel_crtc_state *pipe_config)
26804afd
SV		 9255{
9256 struct drm_device *dev = crtc->base.dev;
9257 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9258 struct intel_shared_dpll *pll;
26804afd
SV		 9259 enum port port;
9260 uint32_t tmp;
9261
9262 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9263
9264 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9265
96b7dfb7
S		 9266 if (IS_SKYLAKE(dev))
9267 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9268 else if (IS_BROXTON(dev))
9269 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9270 else
9271 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9272
d452c5b6
SV		 9273 if (pipe_config->shared_dpll >= 0) {
9274 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9275
9276 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9277 &pipe_config->dpll_hw_state));
9278 }
9279
26804afd
SV		 9280 /*
9281 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9282 * DDI E. So just check whether this pipe is wired to DDI E and whether
9283 * the PCH transcoder is on.
9284 */
ca370455
DL		 9285 if (INTEL_INFO(dev)->gen < 9 &&
9286 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
SV		 9287 pipe_config->has_pch_encoder = true;
9288
9289 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9290 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9291 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9292
9293 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9294 }
9295}
9296
0e8ffe1b 9297static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9298 struct intel_crtc_state *pipe_config)
0e8ffe1b
SV		 9299{
9300 struct drm_device *dev = crtc->base.dev;
9301 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9302 enum intel_display_power_domain pfit_domain;
0e8ffe1b
SV		 9303 uint32_t tmp;
9304
f458ebbc 9305 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9306 POWER_DOMAIN_PIPE(crtc->pipe)))
9307 return false;
9308
e143a21c 9309 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
SV		 9310 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9311
eccb140b
SV		 9312 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9313 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9314 enum pipe trans_edp_pipe;
9315 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9316 default:
9317 WARN(1, "unknown pipe linked to edp transcoder\n");
9318 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9319 case TRANS_DDI_EDP_INPUT_A_ON:
9320 trans_edp_pipe = PIPE_A;
9321 break;
9322 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9323 trans_edp_pipe = PIPE_B;
9324 break;
9325 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9326 trans_edp_pipe = PIPE_C;
9327 break;
9328 }
9329
9330 if (trans_edp_pipe == crtc->pipe)
9331 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9332 }
9333
f458ebbc 9334 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9335 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9336 return false;
9337
eccb140b 9338 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
SV		 9339 if (!(tmp & PIPECONF_ENABLE))
9340 return false;
9341
26804afd 9342 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9343
1bd1bd80
SV		 9344 intel_get_pipe_timings(crtc, pipe_config);
9345
a1b2278e
CK		 9346 if (INTEL_INFO(dev)->gen >= 9) {
9347 skl_init_scalers(dev, crtc, pipe_config);
9348 }
9349
2fa2fe9a 9350 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f 9351 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9352 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9353 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9354 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9355 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9356 else
9357 MISSING_CASE(INTEL_INFO(dev)->gen);
9358
a1b2278e
CK		 9359 } else {
9360 pipe_config->scaler_state.scaler_id = -1;
9361 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f 9362 }
88adfff1 9363
e59150dc
JB		 9364 if (IS_HASWELL(dev))
9365 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9366 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9367
ebb69c95
CT		 9368 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9369 pipe_config->pixel_multiplier =
9370 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9371 } else {
9372 pipe_config->pixel_multiplier = 1;
9373 }
6c49f241 9374
0e8ffe1b
SV		 9375 return true;
9376}
9377
560b85bb
CW		 9378static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9379{
9380 struct drm_device *dev = crtc->dev;
9381 struct drm_i915_private *dev_priv = dev->dev_private;
9382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9383 uint32_t cntl = 0, size = 0;
560b85bb 9384
dc41c154 9385 if (base) {
3dd512fb
MR		 9386 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9387 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9388 unsigned int stride = roundup_pow_of_two(width) * 4;
9389
9390 switch (stride) {
9391 default:
9392 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9393 width, stride);
9394 stride = 256;
9395 /* fallthrough */
9396 case 256:
9397 case 512:
9398 case 1024:
9399 case 2048:
9400 break;
4b0e333e
CW		 9401 }
9402
dc41c154
VS		 9403 cntl |= CURSOR_ENABLE |
9404 CURSOR_GAMMA_ENABLE |
9405 CURSOR_FORMAT_ARGB |
9406 CURSOR_STRIDE(stride);
9407
9408 size = (height << 12) | width;
4b0e333e 9409 }
560b85bb 9410
dc41c154
VS		 9411 if (intel_crtc->cursor_cntl != 0 &&
9412 (intel_crtc->cursor_base != base ||
9413 intel_crtc->cursor_size != size ||
9414 intel_crtc->cursor_cntl != cntl)) {
9415 /* On these chipsets we can only modify the base/size/stride
9416 * whilst the cursor is disabled.
9417 */
9418 I915_WRITE(_CURACNTR, 0);
4b0e333e 9419 POSTING_READ(_CURACNTR);
dc41c154 9420 intel_crtc->cursor_cntl = 0;
4b0e333e 9421 }
560b85bb 9422
99d1f387 9423 if (intel_crtc->cursor_base != base) {
9db4a9c7 9424 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9425 intel_crtc->cursor_base = base;
9426 }
4726e0b0 9427
dc41c154
VS		 9428 if (intel_crtc->cursor_size != size) {
9429 I915_WRITE(CURSIZE, size);
9430 intel_crtc->cursor_size = size;
4b0e333e 9431 }
560b85bb 9432
4b0e333e 9433 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9434 I915_WRITE(_CURACNTR, cntl);
9435 POSTING_READ(_CURACNTR);
4b0e333e 9436 intel_crtc->cursor_cntl = cntl;
560b85bb 9437 }
560b85bb
CW		 9438}
9439
560b85bb 9440static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9441{
9442 struct drm_device *dev = crtc->dev;
9443 struct drm_i915_private *dev_priv = dev->dev_private;
9444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9445 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9446 uint32_t cntl;
9447
9448 cntl = 0;
9449 if (base) {
9450 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9451 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9452 case 64:
9453 cntl |= CURSOR_MODE_64_ARGB_AX;
9454 break;
9455 case 128:
9456 cntl |= CURSOR_MODE_128_ARGB_AX;
9457 break;
9458 case 256:
9459 cntl |= CURSOR_MODE_256_ARGB_AX;
9460 break;
9461 default:
3dd512fb 9462 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9463 return;
65a21cd6 9464 }
4b0e333e 9465 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9466
9467 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9468 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9469 }
65a21cd6 9470
8e7d688b 9471 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9472 cntl |= CURSOR_ROTATE_180;
9473
4b0e333e
CW		 9474 if (intel_crtc->cursor_cntl != cntl) {
9475 I915_WRITE(CURCNTR(pipe), cntl);
9476 POSTING_READ(CURCNTR(pipe));
9477 intel_crtc->cursor_cntl = cntl;
65a21cd6 9478 }
4b0e333e 9479
65a21cd6 9480 /* and commit changes on next vblank */
5efb3e28
VS		 9481 I915_WRITE(CURBASE(pipe), base);
9482 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9483
9484 intel_crtc->cursor_base = base;
65a21cd6
JB		 9485}
9486
cda4b7d3 9487/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9488static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9489 bool on)
cda4b7d3
CW		 9490{
9491 struct drm_device *dev = crtc->dev;
9492 struct drm_i915_private *dev_priv = dev->dev_private;
9493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9494 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9495 int x = crtc->cursor_x;
9496 int y = crtc->cursor_y;
d6e4db15 9497 u32 base = 0, pos = 0;
cda4b7d3 9498
d6e4db15 9499 if (on)
cda4b7d3 9500 base = intel_crtc->cursor_addr;
cda4b7d3 9501
6e3c9717 9502 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9503 base = 0;
9504
6e3c9717 9505 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9506 base = 0;
9507
9508 if (x < 0) {
3dd512fb 9509 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9510 base = 0;
9511
9512 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9513 x = -x;
9514 }
9515 pos |= x << CURSOR_X_SHIFT;
9516
9517 if (y < 0) {
3dd512fb 9518 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9519 base = 0;
9520
9521 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9522 y = -y;
9523 }
9524 pos |= y << CURSOR_Y_SHIFT;
9525
4b0e333e 9526 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9527 return;
9528
5efb3e28
VS		 9529 I915_WRITE(CURPOS(pipe), pos);
9530
4398ad45
VS		 9531 /* ILK+ do this automagically */
9532 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9533 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9534 base += (intel_crtc->base.cursor->state->crtc_h *
9535 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9536 }
9537
8ac54669 9538 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9539 i845_update_cursor(crtc, base);
9540 else
9541 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9542}
9543
dc41c154
VS		 9544static bool cursor_size_ok(struct drm_device *dev,
9545 uint32_t width, uint32_t height)
9546{
9547 if (width == 0 || height == 0)
9548 return false;
9549
9550 /*
9551 * 845g/865g are special in that they are only limited by
9552 * the width of their cursors, the height is arbitrary up to
9553 * the precision of the register. Everything else requires
9554 * square cursors, limited to a few power-of-two sizes.
9555 */
9556 if (IS_845G(dev) || IS_I865G(dev)) {
9557 if ((width & 63) != 0)
9558 return false;
9559
9560 if (width > (IS_845G(dev) ? 64 : 512))
9561 return false;
9562
9563 if (height > 1023)
9564 return false;
9565 } else {
9566 switch (width | height) {
9567 case 256:
9568 case 128:
9569 if (IS_GEN2(dev))
9570 return false;
9571 case 64:
9572 break;
9573 default:
9574 return false;
9575 }
9576 }
9577
9578 return true;
9579}
9580
79e53945 9581static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9582 u16 *blue, uint32_t start, uint32_t size)
79e53945 9583{
7203425a 9584 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9586
7203425a 9587 for (i = start; i < end; i++) {
79e53945
JB		 9588 intel_crtc->lut_r[i] = red[i] >> 8;
9589 intel_crtc->lut_g[i] = green[i] >> 8;
9590 intel_crtc->lut_b[i] = blue[i] >> 8;
9591 }
9592
9593 intel_crtc_load_lut(crtc);
9594}
9595
79e53945
JB		 9596/* VESA 640x480x72Hz mode to set on the pipe */
9597static struct drm_display_mode load_detect_mode = {
9598 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9599 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9600};
9601
a8bb6818
SV		 9602struct drm_framebuffer *
9603__intel_framebuffer_create(struct drm_device *dev,
9604 struct drm_mode_fb_cmd2 *mode_cmd,
9605 struct drm_i915_gem_object *obj)
d2dff872
CW		 9606{
9607 struct intel_framebuffer *intel_fb;
9608 int ret;
9609
9610 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9611 if (!intel_fb) {
6ccb81f2 9612 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9613 return ERR_PTR(-ENOMEM);
9614 }
9615
9616 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
SV		 9617 if (ret)
9618 goto err;
d2dff872
CW		 9619
9620 return &intel_fb->base;
dd4916c5 9621err:
6ccb81f2 9622 drm_gem_object_unreference(&obj->base);
dd4916c5
SV		 9623 kfree(intel_fb);
9624
9625 return ERR_PTR(ret);
d2dff872
CW		 9626}
9627
b5ea642a 9628static struct drm_framebuffer *
a8bb6818
SV		 9629intel_framebuffer_create(struct drm_device *dev,
9630 struct drm_mode_fb_cmd2 *mode_cmd,
9631 struct drm_i915_gem_object *obj)
9632{
9633 struct drm_framebuffer *fb;
9634 int ret;
9635
9636 ret = i915_mutex_lock_interruptible(dev);
9637 if (ret)
9638 return ERR_PTR(ret);
9639 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9640 mutex_unlock(&dev->struct_mutex);
9641
9642 return fb;
9643}
9644
d2dff872
CW		 9645static u32
9646intel_framebuffer_pitch_for_width(int width, int bpp)
9647{
9648 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9649 return ALIGN(pitch, 64);
9650}
9651
9652static u32
9653intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9654{
9655 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9656 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9657}
9658
9659static struct drm_framebuffer *
9660intel_framebuffer_create_for_mode(struct drm_device *dev,
9661 struct drm_display_mode *mode,
9662 int depth, int bpp)
9663{
9664 struct drm_i915_gem_object *obj;
0fed39bd 9665 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9666
9667 obj = i915_gem_alloc_object(dev,
9668 intel_framebuffer_size_for_mode(mode, bpp));
9669 if (obj == NULL)
9670 return ERR_PTR(-ENOMEM);
9671
9672 mode_cmd.width = mode->hdisplay;
9673 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9674 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9675 bpp);
5ca0c34a 9676 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9677
9678 return intel_framebuffer_create(dev, &mode_cmd, obj);
9679}
9680
9681static struct drm_framebuffer *
9682mode_fits_in_fbdev(struct drm_device *dev,
9683 struct drm_display_mode *mode)
9684{
4520f53a 9685#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9686 struct drm_i915_private *dev_priv = dev->dev_private;
9687 struct drm_i915_gem_object *obj;
9688 struct drm_framebuffer *fb;
9689
4c0e5528 9690 if (!dev_priv->fbdev)
d2dff872
CW		 9691 return NULL;
9692
4c0e5528 9693 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9694 return NULL;
9695
4c0e5528
SV		 9696 obj = dev_priv->fbdev->fb->obj;
9697 BUG_ON(!obj);
9698
8bcd4553 9699 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9700 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9701 fb->bits_per_pixel))
d2dff872
CW		 9702 return NULL;
9703
01f2c773 9704 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9705 return NULL;
9706
9707 return fb;
4520f53a
SV		 9708#else
9709 return NULL;
9710#endif
d2dff872
CW		 9711}
9712
d2434ab7 9713bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9714 struct drm_display_mode *mode,
51fd371b
RC		 9715 struct intel_load_detect_pipe *old,
9716 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9717{
9718 struct intel_crtc *intel_crtc;
d2434ab7
SV		 9719 struct intel_encoder *intel_encoder =
9720 intel_attached_encoder(connector);
79e53945 9721 struct drm_crtc *possible_crtc;
4ef69c7a 9722 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9723 struct drm_crtc *crtc = NULL;
9724 struct drm_device *dev = encoder->dev;
94352cf9 9725 struct drm_framebuffer *fb;
51fd371b 9726 struct drm_mode_config *config = &dev->mode_config;
83a57153 9727 struct drm_atomic_state *state = NULL;
944b0c76 9728 struct drm_connector_state *connector_state;
4be07317 9729 struct intel_crtc_state *crtc_state;
51fd371b 9730 int ret, i = -1;
79e53945 9731
d2dff872 9732 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9733 connector->base.id, connector->name,
8e329a03 9734 encoder->base.id, encoder->name);
d2dff872 9735
51fd371b
RC		 9736retry:
9737 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9738 if (ret)
9739 goto fail_unlock;
6e9f798d 9740
79e53945
JB		 9741 /*
9742 * Algorithm gets a little messy:
7a5e4805 9743 *
79e53945
JB		 9744 * - if the connector already has an assigned crtc, use it (but make
9745 * sure it's on first)
7a5e4805 9746 *
79e53945
JB		 9747 * - try to find the first unused crtc that can drive this connector,
9748 * and use that if we find one
79e53945
JB		 9749 */
9750
9751 /* See if we already have a CRTC for this connector */
9752 if (encoder->crtc) {
9753 crtc = encoder->crtc;
8261b191 9754
51fd371b 9755 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
SV		 9756 if (ret)
9757 goto fail_unlock;
9758 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9759 if (ret)
9760 goto fail_unlock;
7b24056b 9761
24218aac 9762 old->dpms_mode = connector->dpms;
8261b191
CW		 9763 old->load_detect_temp = false;
9764
9765 /* Make sure the crtc and connector are running */
24218aac
SV		 9766 if (connector->dpms != DRM_MODE_DPMS_ON)
9767 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9768
7173188d 9769 return true;
79e53945
JB		 9770 }
9771
9772 /* Find an unused one (if possible) */
70e1e0ec 9773 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9774 i++;
9775 if (!(encoder->possible_crtcs & (1 << i)))
9776 continue;
83d65738 9777 if (possible_crtc->state->enable)
a459249c
VS		 9778 continue;
9779 /* This can occur when applying the pipe A quirk on resume. */
9780 if (to_intel_crtc(possible_crtc)->new_enabled)
9781 continue;
9782
9783 crtc = possible_crtc;
9784 break;
79e53945
JB		 9785 }
9786
9787 /*
9788 * If we didn't find an unused CRTC, don't use any.
9789 */
9790 if (!crtc) {
7173188d 9791 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9792 goto fail_unlock;
79e53945
JB		 9793 }
9794
51fd371b
RC		 9795 ret = drm_modeset_lock(&crtc->mutex, ctx);
9796 if (ret)
4d02e2de
SV		 9797 goto fail_unlock;
9798 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9799 if (ret)
51fd371b 9800 goto fail_unlock;
fc303101
SV		 9801 intel_encoder->new_crtc = to_intel_crtc(crtc);
9802 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9803
9804 intel_crtc = to_intel_crtc(crtc);
412b61d8 9805 intel_crtc->new_enabled = true;
24218aac 9806 old->dpms_mode = connector->dpms;
8261b191 9807 old->load_detect_temp = true;
d2dff872 9808 old->release_fb = NULL;
79e53945 9809
83a57153
ACO		 9810 state = drm_atomic_state_alloc(dev);
9811 if (!state)
9812 return false;
9813
9814 state->acquire_ctx = ctx;
9815
944b0c76
ACO		 9816 connector_state = drm_atomic_get_connector_state(state, connector);
9817 if (IS_ERR(connector_state)) {
9818 ret = PTR_ERR(connector_state);
9819 goto fail;
9820 }
9821
9822 connector_state->crtc = crtc;
9823 connector_state->best_encoder = &intel_encoder->base;
9824
4be07317
ACO		 9825 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9826 if (IS_ERR(crtc_state)) {
9827 ret = PTR_ERR(crtc_state);
9828 goto fail;
9829 }
9830
9831 crtc_state->base.enable = true;
9832
6492711d
CW		 9833 if (!mode)
9834 mode = &load_detect_mode;
79e53945 9835
d2dff872
CW		 9836 /* We need a framebuffer large enough to accommodate all accesses
9837 * that the plane may generate whilst we perform load detection.
9838 * We can not rely on the fbcon either being present (we get called
9839 * during its initialisation to detect all boot displays, or it may
9840 * not even exist) or that it is large enough to satisfy the
9841 * requested mode.
9842 */
94352cf9
SV		 9843 fb = mode_fits_in_fbdev(dev, mode);
9844 if (fb == NULL) {
d2dff872 9845 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
SV		 9846 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9847 old->release_fb = fb;
d2dff872
CW		 9848 } else
9849 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9850 if (IS_ERR(fb)) {
d2dff872 9851 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9852 goto fail;
79e53945 9853 }
79e53945 9854
83a57153 9855 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9856 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9857 if (old->release_fb)
9858 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9859 goto fail;
79e53945 9860 }
9128b040 9861 crtc->primary->crtc = crtc;
7173188d 9862
79e53945 9863 /* let the connector get through one full cycle before testing */
9d0498a2 9864 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9865 return true;
412b61d8
VS		 9866
9867 fail:
83d65738 9868 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9869fail_unlock:
e5d958ef
ACO		 9870 drm_atomic_state_free(state);
9871 state = NULL;
83a57153 9872
51fd371b
RC		 9873 if (ret == -EDEADLK) {
9874 drm_modeset_backoff(ctx);
9875 goto retry;
9876 }
9877
412b61d8 9878 return false;
79e53945
JB		 9879}
9880
d2434ab7 9881void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9882 struct intel_load_detect_pipe *old,
9883 struct drm_modeset_acquire_ctx *ctx)
79e53945 9884{
83a57153 9885 struct drm_device *dev = connector->dev;
d2434ab7
SV		 9886 struct intel_encoder *intel_encoder =
9887 intel_attached_encoder(connector);
4ef69c7a 9888 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9889 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9891 struct drm_atomic_state *state;
944b0c76 9892 struct drm_connector_state *connector_state;
4be07317 9893 struct intel_crtc_state *crtc_state;
79e53945 9894
d2dff872 9895 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9896 connector->base.id, connector->name,
8e329a03 9897 encoder->base.id, encoder->name);
d2dff872 9898
8261b191 9899 if (old->load_detect_temp) {
83a57153 9900 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9901 if (!state)
9902 goto fail;
83a57153
ACO		 9903
9904 state->acquire_ctx = ctx;
9905
944b0c76
ACO		 9906 connector_state = drm_atomic_get_connector_state(state, connector);
9907 if (IS_ERR(connector_state))
9908 goto fail;
9909
4be07317
ACO		 9910 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9911 if (IS_ERR(crtc_state))
9912 goto fail;
9913
fc303101
SV		 9914 to_intel_connector(connector)->new_encoder = NULL;
9915 intel_encoder->new_crtc = NULL;
412b61d8 9916 intel_crtc->new_enabled = false;
944b0c76
ACO		 9917
9918 connector_state->best_encoder = NULL;
9919 connector_state->crtc = NULL;
9920
4be07317
ACO		 9921 crtc_state->base.enable = false;
9922
83a57153
ACO		 9923 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9924
9925 drm_atomic_state_free(state);
d2dff872 9926
36206361
SV		 9927 if (old->release_fb) {
9928 drm_framebuffer_unregister_private(old->release_fb);
9929 drm_framebuffer_unreference(old->release_fb);
9930 }
d2dff872 9931
0622a53c 9932 return;
79e53945
JB		 9933 }
9934
c751ce4f 9935 /* Switch crtc and encoder back off if necessary */
24218aac
SV		 9936 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9937 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9938
9939 return;
9940fail:
9941 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9942 drm_atomic_state_free(state);
79e53945
JB		 9943}
9944
da4a1efa 9945static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9946 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9947{
9948 struct drm_i915_private *dev_priv = dev->dev_private;
9949 u32 dpll = pipe_config->dpll_hw_state.dpll;
9950
9951 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9952 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9953 else if (HAS_PCH_SPLIT(dev))
9954 return 120000;
9955 else if (!IS_GEN2(dev))
9956 return 96000;
9957 else
9958 return 48000;
9959}
9960
79e53945 9961/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9962static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9963 struct intel_crtc_state *pipe_config)
79e53945 9964{
f1f644dc 9965 struct drm_device *dev = crtc->base.dev;
79e53945 9966 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9967 int pipe = pipe_config->cpu_transcoder;
293623f7 9968 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9969 u32 fp;
9970 intel_clock_t clock;
da4a1efa 9971 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9972
9973 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9974 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9975 else
293623f7 9976 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9977
9978 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9979 if (IS_PINEVIEW(dev)) {
9980 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9981 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9982 } else {
9983 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9984 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9985 }
9986
a6c45cf0 9987 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9988 if (IS_PINEVIEW(dev))
9989 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9990 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9991 else
9992 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9993 DPLL_FPA01_P1_POST_DIV_SHIFT);
9994
9995 switch (dpll & DPLL_MODE_MASK) {
9996 case DPLLB_MODE_DAC_SERIAL:
9997 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9998 5 : 10;
9999 break;
10000 case DPLLB_MODE_LVDS:
10001 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10002 7 : 14;
10003 break;
10004 default:
28c97730 10005 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10006 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10007 return;
79e53945
JB		 10008 }
10009
ac58c3f0 10010 if (IS_PINEVIEW(dev))
da4a1efa 10011 pineview_clock(refclk, &clock);
ac58c3f0 10012 else
da4a1efa 10013 i9xx_clock(refclk, &clock);
79e53945 10014 } else {
0fb58223 10015 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10016 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10017
10018 if (is_lvds) {
10019 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10020 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10021
10022 if (lvds & LVDS_CLKB_POWER_UP)
10023 clock.p2 = 7;
10024 else
10025 clock.p2 = 14;
79e53945
JB		 10026 } else {
10027 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10028 clock.p1 = 2;
10029 else {
10030 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10031 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10032 }
10033 if (dpll & PLL_P2_DIVIDE_BY_4)
10034 clock.p2 = 4;
10035 else
10036 clock.p2 = 2;
79e53945 10037 }
da4a1efa
VS		 10038
10039 i9xx_clock(refclk, &clock);
79e53945
JB		 10040 }
10041
18442d08
VS		 10042 /*
10043 * This value includes pixel_multiplier. We will use
241bfc38 10044 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10045 * encoder's get_config() function.
10046 */
10047 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10048}
10049
6878da05
VS		 10050int intel_dotclock_calculate(int link_freq,
10051 const struct intel_link_m_n *m_n)
f1f644dc 10052{
f1f644dc
JB		 10053 /*
10054 * The calculation for the data clock is:
1041a02f 10055 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10056 * But we want to avoid losing precison if possible, so:
1041a02f 10057 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10058 *
10059 * and the link clock is simpler:
1041a02f 10060 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10061 */
10062
6878da05
VS		 10063 if (!m_n->link_n)
10064 return 0;
f1f644dc 10065
6878da05
VS		 10066 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10067}
f1f644dc 10068
18442d08 10069static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10070 struct intel_crtc_state *pipe_config)
6878da05
VS		 10071{
10072 struct drm_device *dev = crtc->base.dev;
79e53945 10073
18442d08
VS		 10074 /* read out port_clock from the DPLL */
10075 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10076
f1f644dc 10077 /*
18442d08 10078 * This value does not include pixel_multiplier.
241bfc38 10079 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10080 * agree once we know their relationship in the encoder's
10081 * get_config() function.
79e53945 10082 */
2d112de7 10083 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10084 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10085 &pipe_config->fdi_m_n);
79e53945
JB		 10086}
10087
10088/** Returns the currently programmed mode of the given pipe. */
10089struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10090 struct drm_crtc *crtc)
10091{
548f245b 10092 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10094 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10095 struct drm_display_mode *mode;
5cec258b 10096 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10097 int htot = I915_READ(HTOTAL(cpu_transcoder));
10098 int hsync = I915_READ(HSYNC(cpu_transcoder));
10099 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10100 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10101 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10102
10103 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10104 if (!mode)
10105 return NULL;
10106
f1f644dc
JB		 10107 /*
10108 * Construct a pipe_config sufficient for getting the clock info
10109 * back out of crtc_clock_get.
10110 *
10111 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10112 * to use a real value here instead.
10113 */
293623f7 10114 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10115 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10116 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10117 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10118 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10119 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10120
773ae034 10121 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10122 mode->hdisplay = (htot & 0xffff) + 1;
10123 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10124 mode->hsync_start = (hsync & 0xffff) + 1;
10125 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10126 mode->vdisplay = (vtot & 0xffff) + 1;
10127 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10128 mode->vsync_start = (vsync & 0xffff) + 1;
10129 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10130
10131 drm_mode_set_name(mode);
79e53945
JB		 10132
10133 return mode;
10134}
10135
652c393a
JB		 10136static void intel_decrease_pllclock(struct drm_crtc *crtc)
10137{
10138 struct drm_device *dev = crtc->dev;
fbee40df 10139 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10141
baff296c 10142 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10143 return;
10144
10145 if (!dev_priv->lvds_downclock_avail)
10146 return;
10147
10148 /*
10149 * Since this is called by a timer, we should never get here in
10150 * the manual case.
10151 */
10152 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
SV		 10153 int pipe = intel_crtc->pipe;
10154 int dpll_reg = DPLL(pipe);
10155 int dpll;
f6e5b160 10156
44d98a61 10157 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10158
8ac5a6d5 10159 assert_panel_unlocked(dev_priv, pipe);
652c393a 10160
dc257cf1 10161 dpll = I915_READ(dpll_reg);
652c393a
JB		 10162 dpll |= DISPLAY_RATE_SELECT_FPA1;
10163 I915_WRITE(dpll_reg, dpll);
9d0498a2 10164 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10165 dpll = I915_READ(dpll_reg);
10166 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10167 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10168 }
10169
10170}
10171
f047e395
CW		 10172void intel_mark_busy(struct drm_device *dev)
10173{
c67a470b
PZ		 10174 struct drm_i915_private *dev_priv = dev->dev_private;
10175
f62a0076
CW		 10176 if (dev_priv->mm.busy)
10177 return;
10178
43694d69 10179 intel_runtime_pm_get(dev_priv);
c67a470b 10180 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10181 if (INTEL_INFO(dev)->gen >= 6)
10182 gen6_rps_busy(dev_priv);
f62a0076 10183 dev_priv->mm.busy = true;
f047e395
CW		 10184}
10185
10186void intel_mark_idle(struct drm_device *dev)
652c393a 10187{
c67a470b 10188 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10189 struct drm_crtc *crtc;
652c393a 10190
f62a0076
CW		 10191 if (!dev_priv->mm.busy)
10192 return;
10193
10194 dev_priv->mm.busy = false;
10195
70e1e0ec 10196 for_each_crtc(dev, crtc) {
f4510a27 10197 if (!crtc->primary->fb)
652c393a
JB		 10198 continue;
10199
725a5b54 10200 intel_decrease_pllclock(crtc);
652c393a 10201 }
b29c19b6 10202
3d13ef2e 10203 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10204 gen6_rps_idle(dev->dev_private);
bb4cdd53 10205
43694d69 10206 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10207}
10208
f5de6e07
ACO		 10209static void intel_crtc_set_state(struct intel_crtc *crtc,
10210 struct intel_crtc_state *crtc_state)
10211{
10212 kfree(crtc->config);
10213 crtc->config = crtc_state;
16f3f658 10214 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 10215}
10216
79e53945
JB		 10217static void intel_crtc_destroy(struct drm_crtc *crtc)
10218{
10219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
SV		 10220 struct drm_device *dev = crtc->dev;
10221 struct intel_unpin_work *work;
67e77c5a 10222
5e2d7afc 10223 spin_lock_irq(&dev->event_lock);
67e77c5a
SV		 10224 work = intel_crtc->unpin_work;
10225 intel_crtc->unpin_work = NULL;
5e2d7afc 10226 spin_unlock_irq(&dev->event_lock);
67e77c5a
SV		 10227
10228 if (work) {
10229 cancel_work_sync(&work->work);
10230 kfree(work);
10231 }
79e53945 10232
f5de6e07 10233 intel_crtc_set_state(intel_crtc, NULL);
79e53945 10234 drm_crtc_cleanup(crtc);
67e77c5a 10235
79e53945
JB		 10236 kfree(intel_crtc);
10237}
10238
6b95a207
KH		 10239static void intel_unpin_work_fn(struct work_struct *__work)
10240{
10241 struct intel_unpin_work *work =
10242 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10243 struct drm_device *dev = work->crtc->dev;
f99d7069 10244 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10245
b4a98e57 10246 mutex_lock(&dev->struct_mutex);
82bc3b2d 10247 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10248 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10249
7ff0ebcc 10250 intel_fbc_update(dev);
f06cc1b9
JH		 10251
10252 if (work->flip_queued_req)
146d84f0 10253 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10254 mutex_unlock(&dev->struct_mutex);
10255
f99d7069 10256 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10257 drm_framebuffer_unreference(work->old_fb);
f99d7069 10258
b4a98e57
CW		 10259 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10260 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10261
6b95a207
KH		 10262 kfree(work);
10263}
10264
1afe3e9d 10265static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10266 struct drm_crtc *crtc)
6b95a207 10267{
6b95a207
KH		 10268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10269 struct intel_unpin_work *work;
6b95a207
KH		 10270 unsigned long flags;
10271
10272 /* Ignore early vblank irqs */
10273 if (intel_crtc == NULL)
10274 return;
10275
f326038a
SV		 10276 /*
10277 * This is called both by irq handlers and the reset code (to complete
10278 * lost pageflips) so needs the full irqsave spinlocks.
10279 */
6b95a207
KH		 10280 spin_lock_irqsave(&dev->event_lock, flags);
10281 work = intel_crtc->unpin_work;
e7d841ca
CW		 10282
10283 /* Ensure we don't miss a work->pending update ... */
10284 smp_rmb();
10285
10286 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10287 spin_unlock_irqrestore(&dev->event_lock, flags);
10288 return;
10289 }
10290
d6bbafa1 10291 page_flip_completed(intel_crtc);
0af7e4df 10292
6b95a207 10293 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10294}
10295
1afe3e9d
JB		 10296void intel_finish_page_flip(struct drm_device *dev, int pipe)
10297{
fbee40df 10298 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10299 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10300
49b14a5c 10301 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10302}
10303
10304void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10305{
fbee40df 10306 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10307 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10308
49b14a5c 10309 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10310}
10311
75f7f3ec
VS		 10312/* Is 'a' after or equal to 'b'? */
10313static bool g4x_flip_count_after_eq(u32 a, u32 b)
10314{
10315 return !((a - b) & 0x80000000);
10316}
10317
10318static bool page_flip_finished(struct intel_crtc *crtc)
10319{
10320 struct drm_device *dev = crtc->base.dev;
10321 struct drm_i915_private *dev_priv = dev->dev_private;
10322
bdfa7542
VS		 10323 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10324 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10325 return true;
10326
75f7f3ec
VS		 10327 /*
10328 * The relevant registers doen't exist on pre-ctg.
10329 * As the flip done interrupt doesn't trigger for mmio
10330 * flips on gmch platforms, a flip count check isn't
10331 * really needed there. But since ctg has the registers,
10332 * include it in the check anyway.
10333 */
10334 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10335 return true;
10336
10337 /*
10338 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10339 * used the same base address. In that case the mmio flip might
10340 * have completed, but the CS hasn't even executed the flip yet.
10341 *
10342 * A flip count check isn't enough as the CS might have updated
10343 * the base address just after start of vblank, but before we
10344 * managed to process the interrupt. This means we'd complete the
10345 * CS flip too soon.
10346 *
10347 * Combining both checks should get us a good enough result. It may
10348 * still happen that the CS flip has been executed, but has not
10349 * yet actually completed. But in case the base address is the same
10350 * anyway, we don't really care.
10351 */
10352 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10353 crtc->unpin_work->gtt_offset &&
10354 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10355 crtc->unpin_work->flip_count);
10356}
10357
6b95a207
KH		 10358void intel_prepare_page_flip(struct drm_device *dev, int plane)
10359{
fbee40df 10360 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10361 struct intel_crtc *intel_crtc =
10362 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10363 unsigned long flags;
10364
f326038a
SV		 10365
10366 /*
10367 * This is called both by irq handlers and the reset code (to complete
10368 * lost pageflips) so needs the full irqsave spinlocks.
10369 *
10370 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10371 * generate a page-flip completion irq, i.e. every modeset
10372 * is also accompanied by a spurious intel_prepare_page_flip().
10373 */
6b95a207 10374 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10375 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10376 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10377 spin_unlock_irqrestore(&dev->event_lock, flags);
10378}
10379
eba905b2 10380static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10381{
10382 /* Ensure that the work item is consistent when activating it ... */
10383 smp_wmb();
10384 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10385 /* and that it is marked active as soon as the irq could fire. */
10386 smp_wmb();
10387}
10388
8c9f3aaf
JB		 10389static int intel_gen2_queue_flip(struct drm_device *dev,
10390 struct drm_crtc *crtc,
10391 struct drm_framebuffer *fb,
ed8d1975 10392 struct drm_i915_gem_object *obj,
a4872ba6 10393 struct intel_engine_cs *ring,
ed8d1975 10394 uint32_t flags)
8c9f3aaf 10395{
8c9f3aaf 10396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10397 u32 flip_mask;
10398 int ret;
10399
6d90c952 10400 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10401 if (ret)
4fa62c89 10402 return ret;
8c9f3aaf
JB		 10403
10404 /* Can't queue multiple flips, so wait for the previous
10405 * one to finish before executing the next.
10406 */
10407 if (intel_crtc->plane)
10408 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10409 else
10410 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
SV		 10411 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10412 intel_ring_emit(ring, MI_NOOP);
10413 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10414 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10415 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10416 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10417 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10418
10419 intel_mark_page_flip_active(intel_crtc);
09246732 10420 __intel_ring_advance(ring);
83d4092b 10421 return 0;
8c9f3aaf
JB		 10422}
10423
10424static int intel_gen3_queue_flip(struct drm_device *dev,
10425 struct drm_crtc *crtc,
10426 struct drm_framebuffer *fb,
ed8d1975 10427 struct drm_i915_gem_object *obj,
a4872ba6 10428 struct intel_engine_cs *ring,
ed8d1975 10429 uint32_t flags)
8c9f3aaf 10430{
8c9f3aaf 10431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10432 u32 flip_mask;
10433 int ret;
10434
6d90c952 10435 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10436 if (ret)
4fa62c89 10437 return ret;
8c9f3aaf
JB		 10438
10439 if (intel_crtc->plane)
10440 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10441 else
10442 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
SV		 10443 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10444 intel_ring_emit(ring, MI_NOOP);
10445 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10446 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10447 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10448 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
SV		 10449 intel_ring_emit(ring, MI_NOOP);
10450
e7d841ca 10451 intel_mark_page_flip_active(intel_crtc);
09246732 10452 __intel_ring_advance(ring);
83d4092b 10453 return 0;
8c9f3aaf
JB		 10454}
10455
10456static int intel_gen4_queue_flip(struct drm_device *dev,
10457 struct drm_crtc *crtc,
10458 struct drm_framebuffer *fb,
ed8d1975 10459 struct drm_i915_gem_object *obj,
a4872ba6 10460 struct intel_engine_cs *ring,
ed8d1975 10461 uint32_t flags)
8c9f3aaf
JB		 10462{
10463 struct drm_i915_private *dev_priv = dev->dev_private;
10464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10465 uint32_t pf, pipesrc;
10466 int ret;
10467
6d90c952 10468 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10469 if (ret)
4fa62c89 10470 return ret;
8c9f3aaf
JB		 10471
10472 /* i965+ uses the linear or tiled offsets from the
10473 * Display Registers (which do not change across a page-flip)
10474 * so we need only reprogram the base address.
10475 */
6d90c952
SV		 10476 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10477 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10478 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10479 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10480 obj->tiling_mode);
8c9f3aaf
JB		 10481
10482 /* XXX Enabling the panel-fitter across page-flip is so far
10483 * untested on non-native modes, so ignore it for now.
10484 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10485 */
10486 pf = 0;
10487 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10488 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10489
10490 intel_mark_page_flip_active(intel_crtc);
09246732 10491 __intel_ring_advance(ring);
83d4092b 10492 return 0;
8c9f3aaf
JB		 10493}
10494
10495static int intel_gen6_queue_flip(struct drm_device *dev,
10496 struct drm_crtc *crtc,
10497 struct drm_framebuffer *fb,
ed8d1975 10498 struct drm_i915_gem_object *obj,
a4872ba6 10499 struct intel_engine_cs *ring,
ed8d1975 10500 uint32_t flags)
8c9f3aaf
JB		 10501{
10502 struct drm_i915_private *dev_priv = dev->dev_private;
10503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10504 uint32_t pf, pipesrc;
10505 int ret;
10506
6d90c952 10507 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10508 if (ret)
4fa62c89 10509 return ret;
8c9f3aaf 10510
6d90c952
SV		 10511 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10512 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10513 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10514 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10515
dc257cf1
SV		 10516 /* Contrary to the suggestions in the documentation,
10517 * "Enable Panel Fitter" does not seem to be required when page
10518 * flipping with a non-native mode, and worse causes a normal
10519 * modeset to fail.
10520 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10521 */
10522 pf = 0;
8c9f3aaf 10523 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10524 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10525
10526 intel_mark_page_flip_active(intel_crtc);
09246732 10527 __intel_ring_advance(ring);
83d4092b 10528 return 0;
8c9f3aaf
JB		 10529}
10530
7c9017e5
JB		 10531static int intel_gen7_queue_flip(struct drm_device *dev,
10532 struct drm_crtc *crtc,
10533 struct drm_framebuffer *fb,
ed8d1975 10534 struct drm_i915_gem_object *obj,
a4872ba6 10535 struct intel_engine_cs *ring,
ed8d1975 10536 uint32_t flags)
7c9017e5 10537{
7c9017e5 10538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10539 uint32_t plane_bit = 0;
ffe74d75
CW		 10540 int len, ret;
10541
eba905b2 10542 switch (intel_crtc->plane) {
cb05d8de
SV		 10543 case PLANE_A:
10544 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10545 break;
10546 case PLANE_B:
10547 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10548 break;
10549 case PLANE_C:
10550 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10551 break;
10552 default:
10553 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10554 return -ENODEV;
cb05d8de
SV		 10555 }
10556
ffe74d75 10557 len = 4;
f476828a 10558 if (ring->id == RCS) {
ffe74d75 10559 len += 6;
f476828a
DL		 10560 /*
10561 * On Gen 8, SRM is now taking an extra dword to accommodate
10562 * 48bits addresses, and we need a NOOP for the batch size to
10563 * stay even.
10564 */
10565 if (IS_GEN8(dev))
10566 len += 2;
10567 }
ffe74d75 10568
f66fab8e
VS		 10569 /*
10570 * BSpec MI_DISPLAY_FLIP for IVB:
10571 * "The full packet must be contained within the same cache line."
10572 *
10573 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10574 * cacheline, if we ever start emitting more commands before
10575 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10576 * then do the cacheline alignment, and finally emit the
10577 * MI_DISPLAY_FLIP.
10578 */
10579 ret = intel_ring_cacheline_align(ring);
10580 if (ret)
4fa62c89 10581 return ret;
f66fab8e 10582
ffe74d75 10583 ret = intel_ring_begin(ring, len);
7c9017e5 10584 if (ret)
4fa62c89 10585 return ret;
7c9017e5 10586
ffe74d75
CW		 10587 /* Unmask the flip-done completion message. Note that the bspec says that
10588 * we should do this for both the BCS and RCS, and that we must not unmask
10589 * more than one flip event at any time (or ensure that one flip message
10590 * can be sent by waiting for flip-done prior to queueing new flips).
10591 * Experimentation says that BCS works despite DERRMR masking all
10592 * flip-done completion events and that unmasking all planes at once
10593 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10594 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10595 */
10596 if (ring->id == RCS) {
10597 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10598 intel_ring_emit(ring, DERRMR);
10599 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10600 DERRMR_PIPEB_PRI_FLIP_DONE |
10601 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10602 if (IS_GEN8(dev))
10603 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10604 MI_SRM_LRM_GLOBAL_GTT);
10605 else
10606 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10607 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10608 intel_ring_emit(ring, DERRMR);
10609 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10610 if (IS_GEN8(dev)) {
10611 intel_ring_emit(ring, 0);
10612 intel_ring_emit(ring, MI_NOOP);
10613 }
ffe74d75
CW		 10614 }
10615
cb05d8de 10616 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10617 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10618 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10619 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10620
10621 intel_mark_page_flip_active(intel_crtc);
09246732 10622 __intel_ring_advance(ring);
83d4092b 10623 return 0;
7c9017e5
JB		 10624}
10625
84c33a64
SG		 10626static bool use_mmio_flip(struct intel_engine_cs *ring,
10627 struct drm_i915_gem_object *obj)
10628{
10629 /*
10630 * This is not being used for older platforms, because
10631 * non-availability of flip done interrupt forces us to use
10632 * CS flips. Older platforms derive flip done using some clever
10633 * tricks involving the flip_pending status bits and vblank irqs.
10634 * So using MMIO flips there would disrupt this mechanism.
10635 */
10636
8e09bf83
CW		 10637 if (ring == NULL)
10638 return true;
10639
84c33a64
SG		 10640 if (INTEL_INFO(ring->dev)->gen < 5)
10641 return false;
10642
10643 if (i915.use_mmio_flip < 0)
10644 return false;
10645 else if (i915.use_mmio_flip > 0)
10646 return true;
14bf993e
OM		 10647 else if (i915.enable_execlists)
10648 return true;
84c33a64 10649 else
41c52415 10650 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10651}
10652
ff944564
DL		 10653static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10654{
10655 struct drm_device *dev = intel_crtc->base.dev;
10656 struct drm_i915_private *dev_priv = dev->dev_private;
10657 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10658 const enum pipe pipe = intel_crtc->pipe;
10659 u32 ctl, stride;
10660
10661 ctl = I915_READ(PLANE_CTL(pipe, 0));
10662 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10663 switch (fb->modifier[0]) {
10664 case DRM_FORMAT_MOD_NONE:
10665 break;
10666 case I915_FORMAT_MOD_X_TILED:
ff944564 10667 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10668 break;
10669 case I915_FORMAT_MOD_Y_TILED:
10670 ctl |= PLANE_CTL_TILED_Y;
10671 break;
10672 case I915_FORMAT_MOD_Yf_TILED:
10673 ctl |= PLANE_CTL_TILED_YF;
10674 break;
10675 default:
10676 MISSING_CASE(fb->modifier[0]);
10677 }
ff944564
DL		 10678
10679 /*
10680 * The stride is either expressed as a multiple of 64 bytes chunks for
10681 * linear buffers or in number of tiles for tiled buffers.
10682 */
2ebef630
TU		 10683 stride = fb->pitches[0] /
10684 intel_fb_stride_alignment(dev, fb->modifier[0],
10685 fb->pixel_format);
ff944564
DL		 10686
10687 /*
10688 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10689 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10690 */
10691 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10692 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10693
10694 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10695 POSTING_READ(PLANE_SURF(pipe, 0));
10696}
10697
10698static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10699{
10700 struct drm_device *dev = intel_crtc->base.dev;
10701 struct drm_i915_private *dev_priv = dev->dev_private;
10702 struct intel_framebuffer *intel_fb =
10703 to_intel_framebuffer(intel_crtc->base.primary->fb);
10704 struct drm_i915_gem_object *obj = intel_fb->obj;
10705 u32 dspcntr;
10706 u32 reg;
10707
84c33a64
SG		 10708 reg = DSPCNTR(intel_crtc->plane);
10709 dspcntr = I915_READ(reg);
10710
c5d97472
DL		 10711 if (obj->tiling_mode != I915_TILING_NONE)
10712 dspcntr |= DISPPLANE_TILED;
10713 else
10714 dspcntr &= ~DISPPLANE_TILED;
10715
84c33a64
SG		 10716 I915_WRITE(reg, dspcntr);
10717
10718 I915_WRITE(DSPSURF(intel_crtc->plane),
10719 intel_crtc->unpin_work->gtt_offset);
10720 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10721
ff944564
DL		 10722}
10723
10724/*
10725 * XXX: This is the temporary way to update the plane registers until we get
10726 * around to using the usual plane update functions for MMIO flips
10727 */
10728static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10729{
10730 struct drm_device *dev = intel_crtc->base.dev;
10731 bool atomic_update;
10732 u32 start_vbl_count;
10733
10734 intel_mark_page_flip_active(intel_crtc);
10735
10736 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10737
10738 if (INTEL_INFO(dev)->gen >= 9)
10739 skl_do_mmio_flip(intel_crtc);
10740 else
10741 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10742 ilk_do_mmio_flip(intel_crtc);
10743
9362c7c5
ACO		 10744 if (atomic_update)
10745 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10746}
10747
9362c7c5 10748static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10749{
cc8c4cc2 10750 struct intel_crtc *crtc =
9362c7c5 10751 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10752 struct intel_mmio_flip *mmio_flip;
84c33a64 10753
cc8c4cc2
JH		 10754 mmio_flip = &crtc->mmio_flip;
10755 if (mmio_flip->req)
9c654818
JH		 10756 WARN_ON(__i915_wait_request(mmio_flip->req,
10757 crtc->reset_counter,
10758 false, NULL, NULL) != 0);
84c33a64 10759
cc8c4cc2
JH		 10760 intel_do_mmio_flip(crtc);
10761 if (mmio_flip->req) {
10762 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10763 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10764 mutex_unlock(&crtc->base.dev->struct_mutex);
10765 }
84c33a64
SG		 10766}
10767
10768static int intel_queue_mmio_flip(struct drm_device *dev,
10769 struct drm_crtc *crtc,
10770 struct drm_framebuffer *fb,
10771 struct drm_i915_gem_object *obj,
10772 struct intel_engine_cs *ring,
10773 uint32_t flags)
10774{
84c33a64 10775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10776
cc8c4cc2
JH		 10777 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10778 obj->last_write_req);
536f5b5e
ACO		 10779
10780 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10781
84c33a64
SG		 10782 return 0;
10783}
10784
8c9f3aaf
JB		 10785static int intel_default_queue_flip(struct drm_device *dev,
10786 struct drm_crtc *crtc,
10787 struct drm_framebuffer *fb,
ed8d1975 10788 struct drm_i915_gem_object *obj,
a4872ba6 10789 struct intel_engine_cs *ring,
ed8d1975 10790 uint32_t flags)
8c9f3aaf
JB		 10791{
10792 return -ENODEV;
10793}
10794
d6bbafa1
CW		 10795static bool __intel_pageflip_stall_check(struct drm_device *dev,
10796 struct drm_crtc *crtc)
10797{
10798 struct drm_i915_private *dev_priv = dev->dev_private;
10799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10800 struct intel_unpin_work *work = intel_crtc->unpin_work;
10801 u32 addr;
10802
10803 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10804 return true;
10805
10806 if (!work->enable_stall_check)
10807 return false;
10808
10809 if (work->flip_ready_vblank == 0) {
3a8a946e
SV		 10810 if (work->flip_queued_req &&
10811 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10812 return false;
10813
1e3feefd 10814 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10815 }
10816
1e3feefd 10817 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10818 return false;
10819
10820 /* Potential stall - if we see that the flip has happened,
10821 * assume a missed interrupt. */
10822 if (INTEL_INFO(dev)->gen >= 4)
10823 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10824 else
10825 addr = I915_READ(DSPADDR(intel_crtc->plane));
10826
10827 /* There is a potential issue here with a false positive after a flip
10828 * to the same address. We could address this by checking for a
10829 * non-incrementing frame counter.
10830 */
10831 return addr == work->gtt_offset;
10832}
10833
10834void intel_check_page_flip(struct drm_device *dev, int pipe)
10835{
10836 struct drm_i915_private *dev_priv = dev->dev_private;
10837 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10839 struct intel_unpin_work *work;
f326038a 10840
6c51d46f 10841 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10842
10843 if (crtc == NULL)
10844 return;
10845
f326038a 10846 spin_lock(&dev->event_lock);
6ad790c0
CW		 10847 work = intel_crtc->unpin_work;
10848 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10849 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10850 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10851 page_flip_completed(intel_crtc);
6ad790c0 10852 work = NULL;
d6bbafa1 10853 }
6ad790c0
CW		 10854 if (work != NULL &&
10855 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10856 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10857 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10858}
10859
6b95a207
KH		 10860static int intel_crtc_page_flip(struct drm_crtc *crtc,
10861 struct drm_framebuffer *fb,
ed8d1975
KP		 10862 struct drm_pending_vblank_event *event,
10863 uint32_t page_flip_flags)
6b95a207
KH		 10864{
10865 struct drm_device *dev = crtc->dev;
10866 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10867 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10868 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10870 struct drm_plane *primary = crtc->primary;
a071fa00 10871 enum pipe pipe = intel_crtc->pipe;
6b95a207 10872 struct intel_unpin_work *work;
a4872ba6 10873 struct intel_engine_cs *ring;
cf5d8a46 10874 bool mmio_flip;
52e68630 10875 int ret;
6b95a207 10876
2ff8fde1
MR		 10877 /*
10878 * drm_mode_page_flip_ioctl() should already catch this, but double
10879 * check to be safe. In the future we may enable pageflipping from
10880 * a disabled primary plane.
10881 */
10882 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10883 return -EBUSY;
10884
e6a595d2 10885 /* Can't change pixel format via MI display flips. */
f4510a27 10886 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10887 return -EINVAL;
10888
10889 /*
10890 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10891 * Note that pitch changes could also affect these register.
10892 */
10893 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10894 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10895 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10896 return -EINVAL;
10897
f900db47
CW		 10898 if (i915_terminally_wedged(&dev_priv->gpu_error))
10899 goto out_hang;
10900
b14c5679 10901 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10902 if (work == NULL)
10903 return -ENOMEM;
10904
6b95a207 10905 work->event = event;
b4a98e57 10906 work->crtc = crtc;
ab8d6675 10907 work->old_fb = old_fb;
6b95a207
KH		 10908 INIT_WORK(&work->work, intel_unpin_work_fn);
10909
87b6b101 10910 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10911 if (ret)
10912 goto free_work;
10913
6b95a207 10914 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10915 spin_lock_irq(&dev->event_lock);
6b95a207 10916 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10917 /* Before declaring the flip queue wedged, check if
10918 * the hardware completed the operation behind our backs.
10919 */
10920 if (__intel_pageflip_stall_check(dev, crtc)) {
10921 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10922 page_flip_completed(intel_crtc);
10923 } else {
10924 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10925 spin_unlock_irq(&dev->event_lock);
468f0b44 10926
d6bbafa1
CW		 10927 drm_crtc_vblank_put(crtc);
10928 kfree(work);
10929 return -EBUSY;
10930 }
6b95a207
KH		 10931 }
10932 intel_crtc->unpin_work = work;
5e2d7afc 10933 spin_unlock_irq(&dev->event_lock);
6b95a207 10934
b4a98e57
CW		 10935 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10936 flush_workqueue(dev_priv->wq);
10937
75dfca80 10938 /* Reference the objects for the scheduled work. */
ab8d6675 10939 drm_framebuffer_reference(work->old_fb);
05394f39 10940 drm_gem_object_reference(&obj->base);
6b95a207 10941
f4510a27 10942 crtc->primary->fb = fb;
afd65eb4 10943 update_state_fb(crtc->primary);
1ed1f968 10944
e1f99ce6 10945 work->pending_flip_obj = obj;
e1f99ce6 10946
89ed88ba
CW		 10947 ret = i915_mutex_lock_interruptible(dev);
10948 if (ret)
10949 goto cleanup;
10950
b4a98e57 10951 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10952 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10953
75f7f3ec 10954 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10955 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10956
4fa62c89
VS		 10957 if (IS_VALLEYVIEW(dev)) {
10958 ring = &dev_priv->ring[BCS];
ab8d6675 10959 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10960 /* vlv: DISPLAY_FLIP fails to change tiling */
10961 ring = NULL;
48bf5b2d 10962 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10963 ring = &dev_priv->ring[BCS];
4fa62c89 10964 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10965 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10966 if (ring == NULL || ring->id != RCS)
10967 ring = &dev_priv->ring[BCS];
10968 } else {
10969 ring = &dev_priv->ring[RCS];
10970 }
10971
cf5d8a46
CW		 10972 mmio_flip = use_mmio_flip(ring, obj);
10973
10974 /* When using CS flips, we want to emit semaphores between rings.
10975 * However, when using mmio flips we will create a task to do the
10976 * synchronisation, so all we want here is to pin the framebuffer
10977 * into the display plane and skip any waits.
10978 */
82bc3b2d 10979 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 10980 crtc->primary->state,
10981 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 10982 if (ret)
10983 goto cleanup_pending;
6b95a207 10984
121920fa
TU		 10985 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10986 + intel_crtc->dspaddr_offset;
4fa62c89 10987
cf5d8a46 10988 if (mmio_flip) {
84c33a64
SG		 10989 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10990 page_flip_flags);
d6bbafa1
CW		 10991 if (ret)
10992 goto cleanup_unpin;
10993
f06cc1b9
JH		 10994 i915_gem_request_assign(&work->flip_queued_req,
10995 obj->last_write_req);
d6bbafa1 10996 } else {
84c33a64 10997 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10998 page_flip_flags);
10999 if (ret)
11000 goto cleanup_unpin;
11001
f06cc1b9
JH		 11002 i915_gem_request_assign(&work->flip_queued_req,
11003 intel_ring_get_request(ring));
d6bbafa1
CW		 11004 }
11005
1e3feefd 11006 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11007 work->enable_stall_check = true;
4fa62c89 11008
ab8d6675 11009 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
SV		 11010 INTEL_FRONTBUFFER_PRIMARY(pipe));
11011
7ff0ebcc 11012 intel_fbc_disable(dev);
f99d7069 11013 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11014 mutex_unlock(&dev->struct_mutex);
11015
e5510fac
JB		 11016 trace_i915_flip_request(intel_crtc->plane, obj);
11017
6b95a207 11018 return 0;
96b099fd 11019
4fa62c89 11020cleanup_unpin:
82bc3b2d 11021 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11022cleanup_pending:
b4a98e57 11023 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11024 mutex_unlock(&dev->struct_mutex);
11025cleanup:
f4510a27 11026 crtc->primary->fb = old_fb;
afd65eb4 11027 update_state_fb(crtc->primary);
89ed88ba
CW		 11028
11029 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11030 drm_framebuffer_unreference(work->old_fb);
96b099fd 11031
5e2d7afc 11032 spin_lock_irq(&dev->event_lock);
96b099fd 11033 intel_crtc->unpin_work = NULL;
5e2d7afc 11034 spin_unlock_irq(&dev->event_lock);
96b099fd 11035
87b6b101 11036 drm_crtc_vblank_put(crtc);
7317c75e 11037free_work:
96b099fd
CW		 11038 kfree(work);
11039
f900db47
CW		 11040 if (ret == -EIO) {
11041out_hang:
53a366b9 11042 ret = intel_plane_restore(primary);
f0d3dad3 11043 if (ret == 0 && event) {
5e2d7afc 11044 spin_lock_irq(&dev->event_lock);
a071fa00 11045 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11046 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11047 }
f900db47 11048 }
96b099fd 11049 return ret;
6b95a207
KH		 11050}
11051
65b38e0d 11052static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11053 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11054 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11055 .atomic_begin = intel_begin_crtc_commit,
11056 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11057};
11058
9a935856
SV		 11059/**
11060 * intel_modeset_update_staged_output_state
11061 *
11062 * Updates the staged output configuration state, e.g. after we've read out the
11063 * current hw state.
11064 */
11065static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11066{
7668851f 11067 struct intel_crtc *crtc;
9a935856
SV		 11068 struct intel_encoder *encoder;
11069 struct intel_connector *connector;
f6e5b160 11070
3a3371ff 11071 for_each_intel_connector(dev, connector) {
9a935856
SV		 11072 connector->new_encoder =
11073 to_intel_encoder(connector->base.encoder);
11074 }
f6e5b160 11075
b2784e15 11076 for_each_intel_encoder(dev, encoder) {
9a935856
SV		 11077 encoder->new_crtc =
11078 to_intel_crtc(encoder->base.crtc);
11079 }
7668851f 11080
d3fcc808 11081 for_each_intel_crtc(dev, crtc) {
83d65738 11082 crtc->new_enabled = crtc->base.state->enable;
7668851f 11083 }
f6e5b160
CW		 11084}
11085
d29b2f9d
ACO		 11086/* Transitional helper to copy current connector/encoder state to
11087 * connector->state. This is needed so that code that is partially
11088 * converted to atomic does the right thing.
11089 */
11090static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11091{
11092 struct intel_connector *connector;
11093
11094 for_each_intel_connector(dev, connector) {
11095 if (connector->base.encoder) {
11096 connector->base.state->best_encoder =
11097 connector->base.encoder;
11098 connector->base.state->crtc =
11099 connector->base.encoder->crtc;
11100 } else {
11101 connector->base.state->best_encoder = NULL;
11102 connector->base.state->crtc = NULL;
11103 }
11104 }
11105}
11106
9a935856
SV		 11107/**
11108 * intel_modeset_commit_output_state
11109 *
11110 * This function copies the stage display pipe configuration to the real one.
11111 */
11112static void intel_modeset_commit_output_state(struct drm_device *dev)
11113{
7668851f 11114 struct intel_crtc *crtc;
9a935856
SV		 11115 struct intel_encoder *encoder;
11116 struct intel_connector *connector;
f6e5b160 11117
3a3371ff 11118 for_each_intel_connector(dev, connector) {
9a935856
SV		 11119 connector->base.encoder = &connector->new_encoder->base;
11120 }
f6e5b160 11121
b2784e15 11122 for_each_intel_encoder(dev, encoder) {
9a935856
SV		 11123 encoder->base.crtc = &encoder->new_crtc->base;
11124 }
7668851f 11125
d3fcc808 11126 for_each_intel_crtc(dev, crtc) {
83d65738 11127 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 11128 crtc->base.enabled = crtc->new_enabled;
11129 }
d29b2f9d
ACO		 11130
11131 intel_modeset_update_connector_atomic_state(dev);
9a935856
SV		 11132}
11133
050f7aeb 11134static void
eba905b2 11135connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11136 struct intel_crtc_state *pipe_config)
050f7aeb
SV		 11137{
11138 int bpp = pipe_config->pipe_bpp;
11139
11140 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11141 connector->base.base.id,
c23cc417 11142 connector->base.name);
050f7aeb
SV		 11143
11144 /* Don't use an invalid EDID bpc value */
11145 if (connector->base.display_info.bpc &&
11146 connector->base.display_info.bpc * 3 < bpp) {
11147 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11148 bpp, connector->base.display_info.bpc*3);
11149 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11150 }
11151
11152 /* Clamp bpp to 8 on screens without EDID 1.4 */
11153 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11154 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11155 bpp);
11156 pipe_config->pipe_bpp = 24;
11157 }
11158}
11159
4e53c2e0 11160static int
050f7aeb 11161compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11162 struct intel_crtc_state *pipe_config)
4e53c2e0 11163{
050f7aeb 11164 struct drm_device *dev = crtc->base.dev;
1486017f 11165 struct drm_atomic_state *state;
da3ced29
ACO		 11166 struct drm_connector *connector;
11167 struct drm_connector_state *connector_state;
1486017f 11168 int bpp, i;
4e53c2e0 11169
d328c9d7 11170 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11171 bpp = 10*3;
d328c9d7
SV		 11172 else if (INTEL_INFO(dev)->gen >= 5)
11173 bpp = 12*3;
11174 else
11175 bpp = 8*3;
11176
4e53c2e0 11177
4e53c2e0
SV		 11178 pipe_config->pipe_bpp = bpp;
11179
1486017f
ACO		 11180 state = pipe_config->base.state;
11181
4e53c2e0 11182 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11183 for_each_connector_in_state(state, connector, connector_state, i) {
11184 if (connector_state->crtc != &crtc->base)
4e53c2e0
SV		 11185 continue;
11186
da3ced29
ACO		 11187 connected_sink_compute_bpp(to_intel_connector(connector),
11188 pipe_config);
4e53c2e0
SV		 11189 }
11190
11191 return bpp;
11192}
11193
644db711
SV		 11194static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11195{
11196 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11197 "type: 0x%x flags: 0x%x\n",
1342830c 11198 mode->crtc_clock,
644db711
SV		 11199 mode->crtc_hdisplay, mode->crtc_hsync_start,
11200 mode->crtc_hsync_end, mode->crtc_htotal,
11201 mode->crtc_vdisplay, mode->crtc_vsync_start,
11202 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11203}
11204
c0b03411 11205static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11206 struct intel_crtc_state *pipe_config,
c0b03411
SV		 11207 const char *context)
11208{
6a60cd87
CK		 11209 struct drm_device *dev = crtc->base.dev;
11210 struct drm_plane *plane;
11211 struct intel_plane *intel_plane;
11212 struct intel_plane_state *state;
11213 struct drm_framebuffer *fb;
11214
11215 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11216 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
SV		 11217
11218 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11219 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11220 pipe_config->pipe_bpp, pipe_config->dither);
11221 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11222 pipe_config->has_pch_encoder,
11223 pipe_config->fdi_lanes,
11224 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11225 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11226 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11227 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11228 pipe_config->has_dp_encoder,
11229 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11230 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11231 pipe_config->dp_m_n.tu);
b95af8be
VK		 11232
11233 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11234 pipe_config->has_dp_encoder,
11235 pipe_config->dp_m2_n2.gmch_m,
11236 pipe_config->dp_m2_n2.gmch_n,
11237 pipe_config->dp_m2_n2.link_m,
11238 pipe_config->dp_m2_n2.link_n,
11239 pipe_config->dp_m2_n2.tu);
11240
55072d19
SV		 11241 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11242 pipe_config->has_audio,
11243 pipe_config->has_infoframe);
11244
c0b03411 11245 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11246 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11247 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11248 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11249 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11250 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11251 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11252 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6a60cd87
CK		 11253 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11254 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11255 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
c0b03411
SV		 11256 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11257 pipe_config->gmch_pfit.control,
11258 pipe_config->gmch_pfit.pgm_ratios,
11259 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11260 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11261 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11262 pipe_config->pch_pfit.size,
11263 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11264 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11265 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87
CK		 11266
11267 DRM_DEBUG_KMS("planes on this crtc\n");
11268 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11269 intel_plane = to_intel_plane(plane);
11270 if (intel_plane->pipe != crtc->pipe)
11271 continue;
11272
11273 state = to_intel_plane_state(plane->state);
11274 fb = state->base.fb;
11275 if (!fb) {
11276 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11277 "disabled, scaler_id = %d\n",
11278 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11279 plane->base.id, intel_plane->pipe,
11280 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11281 drm_plane_index(plane), state->scaler_id);
11282 continue;
11283 }
11284
11285 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11286 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11287 plane->base.id, intel_plane->pipe,
11288 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11289 drm_plane_index(plane));
11290 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11291 fb->base.id, fb->width, fb->height, fb->pixel_format);
11292 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11293 state->scaler_id,
11294 state->src.x1 >> 16, state->src.y1 >> 16,
11295 drm_rect_width(&state->src) >> 16,
11296 drm_rect_height(&state->src) >> 16,
11297 state->dst.x1, state->dst.y1,
11298 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11299 }
c0b03411
SV		 11300}
11301
bc079e8b
VS		 11302static bool encoders_cloneable(const struct intel_encoder *a,
11303 const struct intel_encoder *b)
accfc0c5 11304{
bc079e8b
VS		 11305 /* masks could be asymmetric, so check both ways */
11306 return a == b || (a->cloneable & (1 << b->type) &&
11307 b->cloneable & (1 << a->type));
11308}
11309
98a221da
ACO		 11310static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11311 struct intel_crtc *crtc,
bc079e8b
VS		 11312 struct intel_encoder *encoder)
11313{
bc079e8b 11314 struct intel_encoder *source_encoder;
da3ced29 11315 struct drm_connector *connector;
98a221da
ACO		 11316 struct drm_connector_state *connector_state;
11317 int i;
bc079e8b 11318
da3ced29 11319 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11320 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11321 continue;
11322
98a221da
ACO		 11323 source_encoder =
11324 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11325 if (!encoders_cloneable(encoder, source_encoder))
11326 return false;
11327 }
11328
11329 return true;
11330}
11331
98a221da
ACO		 11332static bool check_encoder_cloning(struct drm_atomic_state *state,
11333 struct intel_crtc *crtc)
bc079e8b 11334{
accfc0c5 11335 struct intel_encoder *encoder;
da3ced29 11336 struct drm_connector *connector;
98a221da
ACO		 11337 struct drm_connector_state *connector_state;
11338 int i;
accfc0c5 11339
da3ced29 11340 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11341 if (connector_state->crtc != &crtc->base)
11342 continue;
11343
11344 encoder = to_intel_encoder(connector_state->best_encoder);
11345 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11346 return false;
accfc0c5
SV		 11347 }
11348
bc079e8b 11349 return true;
accfc0c5
SV		 11350}
11351
5448a00d 11352static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11353{
5448a00d
ACO		 11354 struct drm_device *dev = state->dev;
11355 struct intel_encoder *encoder;
da3ced29 11356 struct drm_connector *connector;
5448a00d 11357 struct drm_connector_state *connector_state;
00f0b378 11358 unsigned int used_ports = 0;
5448a00d 11359 int i;
00f0b378
VS		 11360
11361 /*
11362 * Walk the connector list instead of the encoder
11363 * list to detect the problem on ddi platforms
11364 * where there's just one encoder per digital port.
11365 */
da3ced29 11366 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11367 if (!connector_state->best_encoder)
00f0b378
VS		 11368 continue;
11369
5448a00d
ACO		 11370 encoder = to_intel_encoder(connector_state->best_encoder);
11371
11372 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11373
11374 switch (encoder->type) {
11375 unsigned int port_mask;
11376 case INTEL_OUTPUT_UNKNOWN:
11377 if (WARN_ON(!HAS_DDI(dev)))
11378 break;
11379 case INTEL_OUTPUT_DISPLAYPORT:
11380 case INTEL_OUTPUT_HDMI:
11381 case INTEL_OUTPUT_EDP:
11382 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11383
11384 /* the same port mustn't appear more than once */
11385 if (used_ports & port_mask)
11386 return false;
11387
11388 used_ports |= port_mask;
11389 default:
11390 break;
11391 }
11392 }
11393
11394 return true;
11395}
11396
83a57153
ACO		 11397static void
11398clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11399{
11400 struct drm_crtc_state tmp_state;
663a3640 11401 struct intel_crtc_scaler_state scaler_state;
83a57153 11402
663a3640 11403 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11404 tmp_state = crtc_state->base;
663a3640 11405 scaler_state = crtc_state->scaler_state;
83a57153
ACO		 11406 memset(crtc_state, 0, sizeof *crtc_state);
11407 crtc_state->base = tmp_state;
663a3640 11408 crtc_state->scaler_state = scaler_state;
83a57153
ACO		 11409}
11410
548ee15b 11411static int
b8cecdf5 11412intel_modeset_pipe_config(struct drm_crtc *crtc,
83a57153 11413 struct drm_display_mode *mode,
548ee15b
ACO		 11414 struct drm_atomic_state *state,
11415 struct intel_crtc_state *pipe_config)
ee7b9f93 11416{
7758a113 11417 struct intel_encoder *encoder;
da3ced29 11418 struct drm_connector *connector;
0b901879 11419 struct drm_connector_state *connector_state;
d328c9d7 11420 int base_bpp, ret = -EINVAL;
0b901879 11421 int i;
e29c22c0 11422 bool retry = true;
ee7b9f93 11423
98a221da 11424 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11425 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11426 return -EINVAL;
accfc0c5
SV		 11427 }
11428
5448a00d 11429 if (!check_digital_port_conflicts(state)) {
00f0b378 11430 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11431 return -EINVAL;
00f0b378
VS		 11432 }
11433
83a57153 11434 clear_intel_crtc_state(pipe_config);
7758a113 11435
07878248 11436 pipe_config->base.crtc = crtc;
2d112de7
ACO		 11437 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11438 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 11439
e143a21c
SV		 11440 pipe_config->cpu_transcoder =
11441 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 11442 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 11443
2960bc9c
ID		 11444 /*
11445 * Sanitize sync polarity flags based on requested ones. If neither
11446 * positive or negative polarity is requested, treat this as meaning
11447 * negative polarity.
11448 */
2d112de7 11449 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11450 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11451 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11452
2d112de7 11453 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11454 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11455 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11456
050f7aeb
SV		 11457 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11458 * plane pixel format and any sink constraints into account. Returns the
11459 * source plane bpp so that dithering can be selected on mismatches
11460 * after encoders and crtc also have had their say. */
d328c9d7
SV		 11461 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11462 pipe_config);
11463 if (base_bpp < 0)
4e53c2e0
SV		 11464 goto fail;
11465
e41a56be
VS		 11466 /*
11467 * Determine the real pipe dimensions. Note that stereo modes can
11468 * increase the actual pipe size due to the frame doubling and
11469 * insertion of additional space for blanks between the frame. This
11470 * is stored in the crtc timings. We use the requested mode to do this
11471 * computation to clearly distinguish it from the adjusted mode, which
11472 * can be changed by the connectors in the below retry loop.
11473 */
2d112de7 11474 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11475 &pipe_config->pipe_src_w,
11476 &pipe_config->pipe_src_h);
e41a56be 11477
e29c22c0 11478encoder_retry:
ef1b460d 11479 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11480 pipe_config->port_clock = 0;
ef1b460d 11481 pipe_config->pixel_multiplier = 1;
ff9a6750 11482
135c81b8 11483 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11484 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11485 CRTC_STEREO_DOUBLE);
135c81b8 11486
7758a113
SV		 11487 /* Pass our mode to the connectors and the CRTC to give them a chance to
11488 * adjust it according to limitations or connector properties, and also
11489 * a chance to reject the mode entirely.
47f1c6c9 11490 */
da3ced29 11491 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11492 if (connector_state->crtc != crtc)
7758a113 11493 continue;
7ae89233 11494
0b901879
ACO		 11495 encoder = to_intel_encoder(connector_state->best_encoder);
11496
efea6e8e
SV		 11497 if (!(encoder->compute_config(encoder, pipe_config))) {
11498 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
SV		 11499 goto fail;
11500 }
ee7b9f93 11501 }
47f1c6c9 11502
ff9a6750
SV		 11503 /* Set default port clock if not overwritten by the encoder. Needs to be
11504 * done afterwards in case the encoder adjusts the mode. */
11505 if (!pipe_config->port_clock)
2d112de7 11506 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11507 * pipe_config->pixel_multiplier;
ff9a6750 11508
a43f6e0f 11509 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11510 if (ret < 0) {
7758a113
SV		 11511 DRM_DEBUG_KMS("CRTC fixup failed\n");
11512 goto fail;
ee7b9f93 11513 }
e29c22c0
SV		 11514
11515 if (ret == RETRY) {
11516 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11517 ret = -EINVAL;
11518 goto fail;
11519 }
11520
11521 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11522 retry = false;
11523 goto encoder_retry;
11524 }
11525
d328c9d7 11526 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11527 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11528 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11529
548ee15b 11530 return 0;
7758a113 11531fail:
548ee15b 11532 return ret;
ee7b9f93 11533}
47f1c6c9 11534
ea9d758d 11535static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11536{
ea9d758d 11537 struct drm_encoder *encoder;
f6e5b160 11538 struct drm_device *dev = crtc->dev;
f6e5b160 11539
ea9d758d
SV		 11540 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11541 if (encoder->crtc == crtc)
11542 return true;
11543
11544 return false;
11545}
11546
0a9ab303
ACO		 11547static bool
11548needs_modeset(struct drm_crtc_state *state)
11549{
11550 return state->mode_changed || state->active_changed;
11551}
11552
ea9d758d 11553static void
0a9ab303 11554intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 11555{
0a9ab303 11556 struct drm_device *dev = state->dev;
ba41c0de 11557 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 11558 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 11559 struct drm_crtc *crtc;
11560 struct drm_crtc_state *crtc_state;
ea9d758d 11561 struct drm_connector *connector;
0a9ab303 11562 int i;
ea9d758d 11563
ba41c0de
SV		 11564 intel_shared_dpll_commit(dev_priv);
11565
b2784e15 11566 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
SV		 11567 if (!intel_encoder->base.crtc)
11568 continue;
11569
0a9ab303
ACO		 11570 for_each_crtc_in_state(state, crtc, crtc_state, i)
11571 if (crtc == intel_encoder->base.crtc)
11572 break;
11573
11574 if (crtc != intel_encoder->base.crtc)
11575 continue;
ea9d758d 11576
0a9ab303 11577 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
SV		 11578 intel_encoder->connectors_active = false;
11579 }
11580
11581 intel_modeset_commit_output_state(dev);
11582
7668851f 11583 /* Double check state. */
0a9ab303
ACO		 11584 for_each_crtc(dev, crtc) {
11585 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
SV		 11586 }
11587
11588 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11589 if (!connector->encoder || !connector->encoder->crtc)
11590 continue;
11591
0a9ab303
ACO		 11592 for_each_crtc_in_state(state, crtc, crtc_state, i)
11593 if (crtc == connector->encoder->crtc)
11594 break;
11595
11596 if (crtc != connector->encoder->crtc)
11597 continue;
ea9d758d 11598
0a9ab303 11599 if (crtc_state->enable && needs_modeset(crtc_state)) {
68d34720
SV		 11600 struct drm_property *dpms_property =
11601 dev->mode_config.dpms_property;
11602
ea9d758d 11603 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11604 drm_object_property_set_value(&connector->base,
68d34720
SV		 11605 dpms_property,
11606 DRM_MODE_DPMS_ON);
ea9d758d
SV		 11607
11608 intel_encoder = to_intel_encoder(connector->encoder);
11609 intel_encoder->connectors_active = true;
11610 }
11611 }
11612
11613}
11614
3bd26263 11615static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11616{
3bd26263 11617 int diff;
f1f644dc
JB		 11618
11619 if (clock1 == clock2)
11620 return true;
11621
11622 if (!clock1 || !clock2)
11623 return false;
11624
11625 diff = abs(clock1 - clock2);
11626
11627 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11628 return true;
11629
11630 return false;
11631}
11632
25c5b266
SV		 11633#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11634 list_for_each_entry((intel_crtc), \
11635 &(dev)->mode_config.crtc_list, \
11636 base.head) \
0973f18f 11637 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11638
0e8ffe1b 11639static bool
2fa2fe9a 11640intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11641 struct intel_crtc_state *current_config,
11642 struct intel_crtc_state *pipe_config)
0e8ffe1b 11643{
66e985c0
SV		 11644#define PIPE_CONF_CHECK_X(name) \
11645 if (current_config->name != pipe_config->name) { \
11646 DRM_ERROR("mismatch in " #name " " \
11647 "(expected 0x%08x, found 0x%08x)\n", \
11648 current_config->name, \
11649 pipe_config->name); \
11650 return false; \
11651 }
11652
08a24034
SV		 11653#define PIPE_CONF_CHECK_I(name) \
11654 if (current_config->name != pipe_config->name) { \
11655 DRM_ERROR("mismatch in " #name " " \
11656 "(expected %i, found %i)\n", \
11657 current_config->name, \
11658 pipe_config->name); \
11659 return false; \
88adfff1
SV		 11660 }
11661
b95af8be
VK		 11662/* This is required for BDW+ where there is only one set of registers for
11663 * switching between high and low RR.
11664 * This macro can be used whenever a comparison has to be made between one
11665 * hw state and multiple sw state variables.
11666 */
11667#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11668 if ((current_config->name != pipe_config->name) && \
11669 (current_config->alt_name != pipe_config->name)) { \
11670 DRM_ERROR("mismatch in " #name " " \
11671 "(expected %i or %i, found %i)\n", \
11672 current_config->name, \
11673 current_config->alt_name, \
11674 pipe_config->name); \
11675 return false; \
11676 }
11677
1bd1bd80
SV		 11678#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11679 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11680 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
SV		 11681 "(expected %i, found %i)\n", \
11682 current_config->name & (mask), \
11683 pipe_config->name & (mask)); \
11684 return false; \
11685 }
11686
5e550656
VS		 11687#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11688 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11689 DRM_ERROR("mismatch in " #name " " \
11690 "(expected %i, found %i)\n", \
11691 current_config->name, \
11692 pipe_config->name); \
11693 return false; \
11694 }
11695
bb760063
SV		 11696#define PIPE_CONF_QUIRK(quirk) \
11697 ((current_config->quirks | pipe_config->quirks) & (quirk))
11698
eccb140b
SV		 11699 PIPE_CONF_CHECK_I(cpu_transcoder);
11700
08a24034
SV		 11701 PIPE_CONF_CHECK_I(has_pch_encoder);
11702 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
SV		 11703 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11704 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11705 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11706 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11707 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11708
eb14cb74 11709 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11710
11711 if (INTEL_INFO(dev)->gen < 8) {
11712 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11713 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11714 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11715 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11716 PIPE_CONF_CHECK_I(dp_m_n.tu);
11717
11718 if (current_config->has_drrs) {
11719 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11720 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11721 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11722 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11723 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11724 }
11725 } else {
11726 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11727 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11728 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11729 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11730 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11731 }
eb14cb74 11732
2d112de7
ACO		 11733 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11734 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11735 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11736 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11737 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11738 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11739
2d112de7
ACO		 11740 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11741 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11742 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11743 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11744 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11745 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11746
c93f54cf 11747 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11748 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
SV		 11749 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11750 IS_VALLEYVIEW(dev))
11751 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11752 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11753
9ed109a7
SV		 11754 PIPE_CONF_CHECK_I(has_audio);
11755
2d112de7 11756 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
SV		 11757 DRM_MODE_FLAG_INTERLACE);
11758
bb760063 11759 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11760 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11761 DRM_MODE_FLAG_PHSYNC);
2d112de7 11762 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11763 DRM_MODE_FLAG_NHSYNC);
2d112de7 11764 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11765 DRM_MODE_FLAG_PVSYNC);
2d112de7 11766 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
SV		 11767 DRM_MODE_FLAG_NVSYNC);
11768 }
045ac3b5 11769
37327abd
VS		 11770 PIPE_CONF_CHECK_I(pipe_src_w);
11771 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11772
9953599b
SV		 11773 /*
11774 * FIXME: BIOS likes to set up a cloned config with lvds+external
11775 * screen. Since we don't yet re-compute the pipe config when moving
11776 * just the lvds port away to another pipe the sw tracking won't match.
11777 *
11778 * Proper atomic modesets with recomputed global state will fix this.
11779 * Until then just don't check gmch state for inherited modes.
11780 */
11781 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11782 PIPE_CONF_CHECK_I(gmch_pfit.control);
11783 /* pfit ratios are autocomputed by the hw on gen4+ */
11784 if (INTEL_INFO(dev)->gen < 4)
11785 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11786 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11787 }
11788
fd4daa9c
CW		 11789 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11790 if (current_config->pch_pfit.enabled) {
11791 PIPE_CONF_CHECK_I(pch_pfit.pos);
11792 PIPE_CONF_CHECK_I(pch_pfit.size);
11793 }
2fa2fe9a 11794
a1b2278e
CK		 11795 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11796
e59150dc
JB		 11797 /* BDW+ don't expose a synchronous way to read the state */
11798 if (IS_HASWELL(dev))
11799 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11800
282740f7
VS		 11801 PIPE_CONF_CHECK_I(double_wide);
11802
26804afd
SV		 11803 PIPE_CONF_CHECK_X(ddi_pll_sel);
11804
c0d43d62 11805 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11806 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11807 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
SV		 11808 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11809 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11810 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11811 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11812 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11813 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11814
42571aef
VS		 11815 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11816 PIPE_CONF_CHECK_I(pipe_bpp);
11817
2d112de7 11818 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11819 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11820
66e985c0 11821#undef PIPE_CONF_CHECK_X
08a24034 11822#undef PIPE_CONF_CHECK_I
b95af8be 11823#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11824#undef PIPE_CONF_CHECK_FLAGS
5e550656 11825#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11826#undef PIPE_CONF_QUIRK
88adfff1 11827
0e8ffe1b
SV		 11828 return true;
11829}
11830
08db6652
DL		 11831static void check_wm_state(struct drm_device *dev)
11832{
11833 struct drm_i915_private *dev_priv = dev->dev_private;
11834 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11835 struct intel_crtc *intel_crtc;
11836 int plane;
11837
11838 if (INTEL_INFO(dev)->gen < 9)
11839 return;
11840
11841 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11842 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11843
11844 for_each_intel_crtc(dev, intel_crtc) {
11845 struct skl_ddb_entry *hw_entry, *sw_entry;
11846 const enum pipe pipe = intel_crtc->pipe;
11847
11848 if (!intel_crtc->active)
11849 continue;
11850
11851 /* planes */
dd740780 11852 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11853 hw_entry = &hw_ddb.plane[pipe][plane];
11854 sw_entry = &sw_ddb->plane[pipe][plane];
11855
11856 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11857 continue;
11858
11859 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11860 "(expected (%u,%u), found (%u,%u))\n",
11861 pipe_name(pipe), plane + 1,
11862 sw_entry->start, sw_entry->end,
11863 hw_entry->start, hw_entry->end);
11864 }
11865
11866 /* cursor */
11867 hw_entry = &hw_ddb.cursor[pipe];
11868 sw_entry = &sw_ddb->cursor[pipe];
11869
11870 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11871 continue;
11872
11873 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11874 "(expected (%u,%u), found (%u,%u))\n",
11875 pipe_name(pipe),
11876 sw_entry->start, sw_entry->end,
11877 hw_entry->start, hw_entry->end);
11878 }
11879}
11880
91d1b4bd
SV		 11881static void
11882check_connector_state(struct drm_device *dev)
8af6cf88 11883{
8af6cf88
SV		 11884 struct intel_connector *connector;
11885
3a3371ff 11886 for_each_intel_connector(dev, connector) {
8af6cf88
SV		 11887 /* This also checks the encoder/connector hw state with the
11888 * ->get_hw_state callbacks. */
11889 intel_connector_check_state(connector);
11890
e2c719b7 11891 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
SV		 11892 "connector's staged encoder doesn't match current encoder\n");
11893 }
91d1b4bd
SV		 11894}
11895
11896static void
11897check_encoder_state(struct drm_device *dev)
11898{
11899 struct intel_encoder *encoder;
11900 struct intel_connector *connector;
8af6cf88 11901
b2784e15 11902 for_each_intel_encoder(dev, encoder) {
8af6cf88
SV		 11903 bool enabled = false;
11904 bool active = false;
11905 enum pipe pipe, tracked_pipe;
11906
11907 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11908 encoder->base.base.id,
8e329a03 11909 encoder->base.name);
8af6cf88 11910
e2c719b7 11911 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11912 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11913 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
SV		 11914 "encoder's active_connectors set, but no crtc\n");
11915
3a3371ff 11916 for_each_intel_connector(dev, connector) {
8af6cf88
SV		 11917 if (connector->base.encoder != &encoder->base)
11918 continue;
11919 enabled = true;
11920 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11921 active = true;
11922 }
0e32b39c
DA		 11923 /*
11924 * for MST connectors if we unplug the connector is gone
11925 * away but the encoder is still connected to a crtc
11926 * until a modeset happens in response to the hotplug.
11927 */
11928 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11929 continue;
11930
e2c719b7 11931 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
SV		 11932 "encoder's enabled state mismatch "
11933 "(expected %i, found %i)\n",
11934 !!encoder->base.crtc, enabled);
e2c719b7 11935 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
SV		 11936 "active encoder with no crtc\n");
11937
e2c719b7 11938 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
SV		 11939 "encoder's computed active state doesn't match tracked active state "
11940 "(expected %i, found %i)\n", active, encoder->connectors_active);
11941
11942 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11943 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
SV		 11944 "encoder's hw state doesn't match sw tracking "
11945 "(expected %i, found %i)\n",
11946 encoder->connectors_active, active);
11947
11948 if (!encoder->base.crtc)
11949 continue;
11950
11951 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11952 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
SV		 11953 "active encoder's pipe doesn't match"
11954 "(expected %i, found %i)\n",
11955 tracked_pipe, pipe);
11956
11957 }
91d1b4bd
SV		 11958}
11959
11960static void
11961check_crtc_state(struct drm_device *dev)
11962{
fbee40df 11963 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
SV		 11964 struct intel_crtc *crtc;
11965 struct intel_encoder *encoder;
5cec258b 11966 struct intel_crtc_state pipe_config;
8af6cf88 11967
d3fcc808 11968 for_each_intel_crtc(dev, crtc) {
8af6cf88
SV		 11969 bool enabled = false;
11970 bool active = false;
11971
045ac3b5
JB		 11972 memset(&pipe_config, 0, sizeof(pipe_config));
11973
8af6cf88
SV		 11974 DRM_DEBUG_KMS("[CRTC:%d]\n",
11975 crtc->base.base.id);
11976
83d65738 11977 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
SV		 11978 "active crtc, but not enabled in sw tracking\n");
11979
b2784e15 11980 for_each_intel_encoder(dev, encoder) {
8af6cf88
SV		 11981 if (encoder->base.crtc != &crtc->base)
11982 continue;
11983 enabled = true;
11984 if (encoder->connectors_active)
11985 active = true;
11986 }
6c49f241 11987
e2c719b7 11988 I915_STATE_WARN(active != crtc->active,
8af6cf88
SV		 11989 "crtc's computed active state doesn't match tracked active state "
11990 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11991 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11992 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11993 "(expected %i, found %i)\n", enabled,
11994 crtc->base.state->enable);
8af6cf88 11995
0e8ffe1b
SV		 11996 active = dev_priv->display.get_pipe_config(crtc,
11997 &pipe_config);
d62cf62a 11998
b6b5d049
VS		 11999 /* hw state is inconsistent with the pipe quirk */
12000 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12001 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
SV		 12002 active = crtc->active;
12003
b2784e15 12004 for_each_intel_encoder(dev, encoder) {
3eaba51c 12005 enum pipe pipe;
6c49f241
SV		 12006 if (encoder->base.crtc != &crtc->base)
12007 continue;
1d37b689 12008 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
SV		 12009 encoder->get_config(encoder, &pipe_config);
12010 }
12011
e2c719b7 12012 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
SV		 12013 "crtc active state doesn't match with hw state "
12014 "(expected %i, found %i)\n", crtc->active, active);
12015
c0b03411 12016 if (active &&
6e3c9717 12017 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12018 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
SV		 12019 intel_dump_pipe_config(crtc, &pipe_config,
12020 "[hw state]");
6e3c9717 12021 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
SV		 12022 "[sw state]");
12023 }
8af6cf88
SV		 12024 }
12025}
12026
91d1b4bd
SV		 12027static void
12028check_shared_dpll_state(struct drm_device *dev)
12029{
fbee40df 12030 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
SV		 12031 struct intel_crtc *crtc;
12032 struct intel_dpll_hw_state dpll_hw_state;
12033 int i;
5358901f
SV		 12034
12035 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12036 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12037 int enabled_crtcs = 0, active_crtcs = 0;
12038 bool active;
12039
12040 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12041
12042 DRM_DEBUG_KMS("%s\n", pll->name);
12043
12044 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12045
e2c719b7 12046 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12047 "more active pll users than references: %i vs %i\n",
3e369b76 12048 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12049 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12050 "pll in active use but not on in sw tracking\n");
e2c719b7 12051 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12052 "pll in on but not on in use in sw tracking\n");
e2c719b7 12053 I915_STATE_WARN(pll->on != active,
5358901f
SV		 12054 "pll on state mismatch (expected %i, found %i)\n",
12055 pll->on, active);
12056
d3fcc808 12057 for_each_intel_crtc(dev, crtc) {
83d65738 12058 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
SV		 12059 enabled_crtcs++;
12060 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12061 active_crtcs++;
12062 }
e2c719b7 12063 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
SV		 12064 "pll active crtcs mismatch (expected %i, found %i)\n",
12065 pll->active, active_crtcs);
e2c719b7 12066 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12067 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12068 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12069
e2c719b7 12070 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
SV		 12071 sizeof(dpll_hw_state)),
12072 "pll hw state mismatch\n");
5358901f 12073 }
8af6cf88
SV		 12074}
12075
91d1b4bd
SV		 12076void
12077intel_modeset_check_state(struct drm_device *dev)
12078{
08db6652 12079 check_wm_state(dev);
91d1b4bd
SV		 12080 check_connector_state(dev);
12081 check_encoder_state(dev);
12082 check_crtc_state(dev);
12083 check_shared_dpll_state(dev);
12084}
12085
5cec258b 12086void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12087 int dotclock)
12088{
12089 /*
12090 * FDI already provided one idea for the dotclock.
12091 * Yell if the encoder disagrees.
12092 */
2d112de7 12093 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12094 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12095 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12096}
12097
80715b2f
VS		 12098static void update_scanline_offset(struct intel_crtc *crtc)
12099{
12100 struct drm_device *dev = crtc->base.dev;
12101
12102 /*
12103 * The scanline counter increments at the leading edge of hsync.
12104 *
12105 * On most platforms it starts counting from vtotal-1 on the
12106 * first active line. That means the scanline counter value is
12107 * always one less than what we would expect. Ie. just after
12108 * start of vblank, which also occurs at start of hsync (on the
12109 * last active line), the scanline counter will read vblank_start-1.
12110 *
12111 * On gen2 the scanline counter starts counting from 1 instead
12112 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12113 * to keep the value positive), instead of adding one.
12114 *
12115 * On HSW+ the behaviour of the scanline counter depends on the output
12116 * type. For DP ports it behaves like most other platforms, but on HDMI
12117 * there's an extra 1 line difference. So we need to add two instead of
12118 * one to the value.
12119 */
12120 if (IS_GEN2(dev)) {
6e3c9717 12121 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12122 int vtotal;
12123
12124 vtotal = mode->crtc_vtotal;
12125 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12126 vtotal /= 2;
12127
12128 crtc->scanline_offset = vtotal - 1;
12129 } else if (HAS_DDI(dev) &&
409ee761 12130 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12131 crtc->scanline_offset = 2;
12132 } else
12133 crtc->scanline_offset = 1;
12134}
12135
0a9ab303
ACO		 12136static void
12137intel_atomic_modeset_compute_changed_flags(struct drm_atomic_state *state,
12138 struct drm_crtc *modeset_crtc)
12139{
12140 struct drm_crtc_state *crtc_state;
12141 struct drm_crtc *crtc;
12142 int i;
12143
12144 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12145 if (crtc_state->enable != crtc->state->enable)
12146 crtc_state->mode_changed = true;
12147
12148 /* FIXME: Do we need to always set mode_changed for
12149 * modeset_crtc if it is enabled? modeset_affect_pipes()
12150 * did that. */
12151 }
12152}
12153
5cec258b 12154static struct intel_crtc_state *
7f27126e
JB		 12155intel_modeset_compute_config(struct drm_crtc *crtc,
12156 struct drm_display_mode *mode,
0a9ab303 12157 struct drm_atomic_state *state)
7f27126e 12158{
548ee15b 12159 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12160 int ret = 0;
12161
12162 ret = drm_atomic_add_affected_connectors(state, crtc);
12163 if (ret)
12164 return ERR_PTR(ret);
7f27126e 12165
0a9ab303 12166 intel_atomic_modeset_compute_changed_flags(state, crtc);
7f27126e 12167
7f27126e
JB		 12168 /*
12169 * Note this needs changes when we start tracking multiple modes
12170 * and crtcs. At that point we'll need to compute the whole config
12171 * (i.e. one pipe_config for each crtc) rather than just the one
12172 * for this crtc.
12173 */
548ee15b
ACO		 12174 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12175 if (IS_ERR(pipe_config))
12176 return pipe_config;
83a57153 12177
4fed33f6 12178 if (!pipe_config->base.enable)
548ee15b 12179 return pipe_config;
7f27126e 12180
548ee15b
ACO		 12181 ret = intel_modeset_pipe_config(crtc, mode, state, pipe_config);
12182 if (ret)
12183 return ERR_PTR(ret);
12184
12185 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12186
548ee15b 12187 return pipe_config;
7f27126e
JB		 12188}
12189
0a9ab303 12190static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12191{
225da59b 12192 struct drm_device *dev = state->dev;
ed6739ef 12193 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12194 unsigned clear_pipes = 0;
ed6739ef 12195 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12196 struct intel_crtc_state *intel_crtc_state;
12197 struct drm_crtc *crtc;
12198 struct drm_crtc_state *crtc_state;
ed6739ef 12199 int ret = 0;
0a9ab303 12200 int i;
ed6739ef
ACO		 12201
12202 if (!dev_priv->display.crtc_compute_clock)
12203 return 0;
12204
0a9ab303
ACO		 12205 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12206 intel_crtc = to_intel_crtc(crtc);
12207
12208 if (needs_modeset(crtc_state))
12209 clear_pipes |= 1 << intel_crtc->pipe;
12210 }
12211
ed6739ef
ACO		 12212 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12213 if (ret)
12214 goto done;
12215
0a9ab303
ACO		 12216 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12217 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12218 continue;
12219
0a9ab303
ACO		 12220 intel_crtc = to_intel_crtc(crtc);
12221 intel_crtc_state = to_intel_crtc_state(crtc_state);
12222
ed6739ef 12223 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12224 intel_crtc_state);
ed6739ef
ACO		 12225 if (ret) {
12226 intel_shared_dpll_abort_config(dev_priv);
12227 goto done;
12228 }
12229 }
12230
12231done:
12232 return ret;
12233}
12234
054518dd
ACO		 12235/* Code that should eventually be part of atomic_check() */
12236static int __intel_set_mode_checks(struct drm_atomic_state *state)
12237{
12238 struct drm_device *dev = state->dev;
12239 int ret;
12240
12241 /*
12242 * See if the config requires any additional preparation, e.g.
12243 * to adjust global state with pipes off. We need to do this
12244 * here so we can get the modeset_pipe updated config for the new
12245 * mode set on this crtc. For other crtcs we need to use the
12246 * adjusted_mode bits in the crtc directly.
12247 */
12248 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12249 ret = valleyview_modeset_global_pipes(state);
12250 if (ret)
12251 return ret;
12252 }
12253
12254 ret = __intel_set_mode_setup_plls(state);
12255 if (ret)
12256 return ret;
12257
12258 return 0;
12259}
12260
0a9ab303 12261static int __intel_set_mode(struct drm_crtc *modeset_crtc,
f30da187 12262 struct drm_display_mode *mode,
7f27126e 12263 int x, int y, struct drm_framebuffer *fb,
0a9ab303 12264 struct intel_crtc_state *pipe_config)
a6778b3c 12265{
0a9ab303 12266 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12267 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12268 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 12269 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 12270 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12271 struct drm_crtc *crtc;
12272 struct drm_crtc_state *crtc_state;
c0c36b94 12273 int ret = 0;
0a9ab303 12274 int i;
a6778b3c 12275
054518dd
ACO		 12276 ret = __intel_set_mode_checks(state);
12277 if (ret < 0)
12278 return ret;
12279
83a57153
ACO		 12280 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12281 if (!crtc_state_copy) {
12282 ret = -ENOMEM;
12283 goto done;
12284 }
12285
0a9ab303
ACO		 12286 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12287 if (!needs_modeset(crtc_state))
12288 continue;
460da916 12289
0a9ab303
ACO		 12290 if (!crtc_state->enable) {
12291 intel_crtc_disable(crtc);
12292 } else if (crtc->state->enable) {
12293 intel_crtc_disable_planes(crtc);
12294 dev_priv->display.crtc_disable(crtc);
ce22dba9 12295 }
ea9d758d 12296 }
a6778b3c 12297
6c4c86f5
SV		 12298 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12299 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12300 *
12301 * Note we'll need to fix this up when we start tracking multiple
12302 * pipes; here we assume a single modeset_pipe and only track the
12303 * single crtc and mode.
f6e5b160 12304 */
0a9ab303
ACO		 12305 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12306 modeset_crtc->mode = *mode;
b8cecdf5
SV		 12307 /* mode_set/enable/disable functions rely on a correct pipe
12308 * config. */
0a9ab303 12309 intel_crtc_set_state(to_intel_crtc(modeset_crtc), pipe_config);
c326c0a9
VS		 12310
12311 /*
12312 * Calculate and store various constants which
12313 * are later needed by vblank and swap-completion
12314 * timestamping. They are derived from true hwmode.
12315 */
0a9ab303 12316 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12317 &pipe_config->base.adjusted_mode);
b8cecdf5 12318 }
7758a113 12319
ea9d758d
SV		 12320 /* Only after disabling all output pipelines that will be changed can we
12321 * update the the output configuration. */
0a9ab303 12322 intel_modeset_update_state(state);
f6e5b160 12323
304603f4 12324 modeset_update_crtc_power_domains(state);
47fab737 12325
0a9ab303
ACO		 12326 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12327 struct drm_plane *primary;
455a6808 12328 int vdisplay, hdisplay;
4c10794f 12329
0a9ab303
ACO		 12330 intel_crtc = to_intel_crtc(modeset_crtc);
12331 primary = intel_crtc->base.primary;
12332
455a6808 12333 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
0a9ab303 12334
70a101f8
MR		 12335 ret = drm_plane_helper_update(primary, &intel_crtc->base,
12336 fb, 0, 0,
12337 hdisplay, vdisplay,
12338 x << 16, y << 16,
12339 hdisplay << 16, vdisplay << 16);
a6778b3c
SV		 12340 }
12341
12342 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303
ACO		 12343 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12344 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12345 continue;
12346
12347 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12348
0a9ab303
ACO		 12349 dev_priv->display.crtc_enable(crtc);
12350 intel_crtc_enable_planes(crtc);
80715b2f 12351 }
a6778b3c 12352
a6778b3c
SV		 12353 /* FIXME: add subpixel order */
12354done:
83a57153 12355 if (ret == 0 && pipe_config) {
0a9ab303 12356 struct intel_crtc *intel_crtc = to_intel_crtc(modeset_crtc);
83a57153
ACO		 12357
12358 /* The pipe_config will be freed with the atomic state, so
12359 * make a copy. */
12360 memcpy(crtc_state_copy, intel_crtc->config,
12361 sizeof *crtc_state_copy);
12362 intel_crtc->config = crtc_state_copy;
12363 intel_crtc->base.state = &crtc_state_copy->base;
83a57153
ACO		 12364 } else {
12365 kfree(crtc_state_copy);
12366 }
12367
a6778b3c 12368 return ret;
f6e5b160
CW		 12369}
12370
0a9ab303
ACO		 12371static int intel_set_mode_with_config(struct drm_crtc *crtc,
12372 struct drm_display_mode *mode,
12373 int x, int y, struct drm_framebuffer *fb,
12374 struct intel_crtc_state *pipe_config)
f30da187
SV		 12375{
12376 int ret;
12377
0a9ab303 12378 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config);
f30da187
SV		 12379
12380 if (ret == 0)
12381 intel_modeset_check_state(crtc->dev);
12382
12383 return ret;
12384}
12385
7f27126e
JB		 12386static int intel_set_mode(struct drm_crtc *crtc,
12387 struct drm_display_mode *mode,
83a57153
ACO		 12388 int x, int y, struct drm_framebuffer *fb,
12389 struct drm_atomic_state *state)
7f27126e 12390{
5cec258b 12391 struct intel_crtc_state *pipe_config;
83a57153 12392 int ret = 0;
7f27126e 12393
0a9ab303 12394 pipe_config = intel_modeset_compute_config(crtc, mode, state);
83a57153
ACO		 12395 if (IS_ERR(pipe_config)) {
12396 ret = PTR_ERR(pipe_config);
12397 goto out;
12398 }
12399
0a9ab303 12400 ret = intel_set_mode_with_config(crtc, mode, x, y, fb, pipe_config);
83a57153
ACO		 12401 if (ret)
12402 goto out;
7f27126e 12403
83a57153
ACO		 12404out:
12405 return ret;
7f27126e
JB		 12406}
12407
c0c36b94
CW		 12408void intel_crtc_restore_mode(struct drm_crtc *crtc)
12409{
83a57153
ACO		 12410 struct drm_device *dev = crtc->dev;
12411 struct drm_atomic_state *state;
4be07317 12412 struct intel_crtc *intel_crtc;
83a57153
ACO		 12413 struct intel_encoder *encoder;
12414 struct intel_connector *connector;
12415 struct drm_connector_state *connector_state;
4be07317 12416 struct intel_crtc_state *crtc_state;
83a57153
ACO		 12417
12418 state = drm_atomic_state_alloc(dev);
12419 if (!state) {
12420 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12421 crtc->base.id);
12422 return;
12423 }
12424
12425 state->acquire_ctx = dev->mode_config.acquire_ctx;
12426
12427 /* The force restore path in the HW readout code relies on the staged
12428 * config still keeping the user requested config while the actual
12429 * state has been overwritten by the configuration read from HW. We
12430 * need to copy the staged config to the atomic state, otherwise the
12431 * mode set will just reapply the state the HW is already in. */
12432 for_each_intel_encoder(dev, encoder) {
12433 if (&encoder->new_crtc->base != crtc)
12434 continue;
12435
12436 for_each_intel_connector(dev, connector) {
12437 if (connector->new_encoder != encoder)
12438 continue;
12439
12440 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12441 if (IS_ERR(connector_state)) {
12442 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12443 connector->base.base.id,
12444 connector->base.name,
12445 PTR_ERR(connector_state));
12446 continue;
12447 }
12448
12449 connector_state->crtc = crtc;
12450 connector_state->best_encoder = &encoder->base;
12451 }
12452 }
12453
4be07317
ACO		 12454 for_each_intel_crtc(dev, intel_crtc) {
12455 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12456 continue;
12457
12458 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12459 if (IS_ERR(crtc_state)) {
12460 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12461 intel_crtc->base.base.id,
12462 PTR_ERR(crtc_state));
12463 continue;
12464 }
12465
12466 crtc_state->base.enable = intel_crtc->new_enabled;
12467 }
12468
83a57153
ACO		 12469 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
12470 state);
12471
12472 drm_atomic_state_free(state);
c0c36b94
CW		 12473}
12474
25c5b266
SV		 12475#undef for_each_intel_crtc_masked
12476
d9e55608
SV		 12477static void intel_set_config_free(struct intel_set_config *config)
12478{
12479 if (!config)
12480 return;
12481
1aa4b628
SV		 12482 kfree(config->save_connector_encoders);
12483 kfree(config->save_encoder_crtcs);
7668851f 12484 kfree(config->save_crtc_enabled);
d9e55608
SV		 12485 kfree(config);
12486}
12487
85f9eb71
SV		 12488static int intel_set_config_save_state(struct drm_device *dev,
12489 struct intel_set_config *config)
12490{
7668851f 12491 struct drm_crtc *crtc;
85f9eb71
SV		 12492 struct drm_encoder *encoder;
12493 struct drm_connector *connector;
12494 int count;
12495
7668851f
VS		 12496 config->save_crtc_enabled =
12497 kcalloc(dev->mode_config.num_crtc,
12498 sizeof(bool), GFP_KERNEL);
12499 if (!config->save_crtc_enabled)
12500 return -ENOMEM;
12501
1aa4b628
SV		 12502 config->save_encoder_crtcs =
12503 kcalloc(dev->mode_config.num_encoder,
12504 sizeof(struct drm_crtc *), GFP_KERNEL);
12505 if (!config->save_encoder_crtcs)
85f9eb71
SV		 12506 return -ENOMEM;
12507
1aa4b628
SV		 12508 config->save_connector_encoders =
12509 kcalloc(dev->mode_config.num_connector,
12510 sizeof(struct drm_encoder *), GFP_KERNEL);
12511 if (!config->save_connector_encoders)
85f9eb71
SV		 12512 return -ENOMEM;
12513
12514 /* Copy data. Note that driver private data is not affected.
12515 * Should anything bad happen only the expected state is
12516 * restored, not the drivers personal bookkeeping.
12517 */
7668851f 12518 count = 0;
70e1e0ec 12519 for_each_crtc(dev, crtc) {
83d65738 12520 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 12521 }
12522
85f9eb71
SV		 12523 count = 0;
12524 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 12525 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
SV		 12526 }
12527
12528 count = 0;
12529 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 12530 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
SV		 12531 }
12532
12533 return 0;
12534}
12535
12536static void intel_set_config_restore_state(struct drm_device *dev,
12537 struct intel_set_config *config)
12538{
7668851f 12539 struct intel_crtc *crtc;
9a935856
SV		 12540 struct intel_encoder *encoder;
12541 struct intel_connector *connector;
85f9eb71
SV		 12542 int count;
12543
7668851f 12544 count = 0;
d3fcc808 12545 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12546 crtc->new_enabled = config->save_crtc_enabled[count++];
12547 }
12548
85f9eb71 12549 count = 0;
b2784e15 12550 for_each_intel_encoder(dev, encoder) {
9a935856
SV		 12551 encoder->new_crtc =
12552 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
SV		 12553 }
12554
12555 count = 0;
3a3371ff 12556 for_each_intel_connector(dev, connector) {
9a935856
SV		 12557 connector->new_encoder =
12558 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
SV		 12559 }
12560}
12561
e3de42b6 12562static bool
2e57f47d 12563is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 12564{
12565 int i;
12566
2e57f47d
CW		 12567 if (set->num_connectors == 0)
12568 return false;
12569
12570 if (WARN_ON(set->connectors == NULL))
12571 return false;
12572
12573 for (i = 0; i < set->num_connectors; i++)
12574 if (set->connectors[i]->encoder &&
12575 set->connectors[i]->encoder->crtc == set->crtc &&
12576 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 12577 return true;
12578
12579 return false;
12580}
12581
5e2b584e
SV		 12582static void
12583intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12584 struct intel_set_config *config)
12585{
462a425a
ACO		 12586 struct drm_device *dev = set->crtc->dev;
12587 struct intel_connector *connector;
12588 struct intel_encoder *encoder;
12589 struct intel_crtc *crtc;
5e2b584e
SV		 12590
12591 /* We should be able to check here if the fb has the same properties
12592 * and then just flip_or_move it */
2e57f47d
CW		 12593 if (is_crtc_connector_off(set)) {
12594 config->mode_changed = true;
f4510a27 12595 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 12596 /*
12597 * If we have no fb, we can only flip as long as the crtc is
12598 * active, otherwise we need a full mode set. The crtc may
12599 * be active if we've only disabled the primary plane, or
12600 * in fastboot situations.
12601 */
f4510a27 12602 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 12603 struct intel_crtc *intel_crtc =
12604 to_intel_crtc(set->crtc);
12605
3b150f08 12606 if (intel_crtc->active) {
319d9827
JB		 12607 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12608 config->fb_changed = true;
12609 } else {
12610 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12611 config->mode_changed = true;
12612 }
5e2b584e
SV		 12613 } else if (set->fb == NULL) {
12614 config->mode_changed = true;
72f4901e 12615 } else if (set->fb->pixel_format !=
f4510a27 12616 set->crtc->primary->fb->pixel_format) {
5e2b584e 12617 config->mode_changed = true;
e3de42b6 12618 } else {
5e2b584e 12619 config->fb_changed = true;
e3de42b6 12620 }
5e2b584e
SV		 12621 }
12622
835c5873 12623 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
SV		 12624 config->fb_changed = true;
12625
12626 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12627 DRM_DEBUG_KMS("modes are different, full mode set\n");
12628 drm_mode_debug_printmodeline(&set->crtc->mode);
12629 drm_mode_debug_printmodeline(set->mode);
12630 config->mode_changed = true;
12631 }
a1d95703 12632
462a425a
ACO		 12633 for_each_intel_connector(dev, connector) {
12634 if (&connector->new_encoder->base == connector->base.encoder)
12635 continue;
12636
12637 config->mode_changed = true;
12638 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12639 connector->base.base.id,
12640 connector->base.name);
12641 }
12642
12643 for_each_intel_encoder(dev, encoder) {
12644 if (&encoder->new_crtc->base == encoder->base.crtc)
12645 continue;
12646
12647 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12648 encoder->base.base.id,
12649 encoder->base.name);
12650 config->mode_changed = true;
12651 }
12652
12653 for_each_intel_crtc(dev, crtc) {
12654 if (crtc->new_enabled == crtc->base.state->enable)
12655 continue;
12656
12657 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12658 crtc->base.base.id,
12659 crtc->new_enabled ? "en" : "dis");
12660 config->mode_changed = true;
12661 }
12662
a1d95703
CW		 12663 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12664 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
SV		 12665}
12666
2e431051 12667static int
9a935856
SV		 12668intel_modeset_stage_output_state(struct drm_device *dev,
12669 struct drm_mode_set *set,
944b0c76 12670 struct drm_atomic_state *state)
50f56119 12671{
9a935856 12672 struct intel_connector *connector;
944b0c76 12673 struct drm_connector_state *connector_state;
9a935856 12674 struct intel_encoder *encoder;
7668851f 12675 struct intel_crtc *crtc;
4be07317 12676 struct intel_crtc_state *crtc_state;
f3f08572 12677 int ro;
50f56119 12678
9abdda74 12679 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
SV		 12680 * of connectors. For paranoia, double-check this. */
12681 WARN_ON(!set->fb && (set->num_connectors != 0));
12682 WARN_ON(set->fb && (set->num_connectors == 0));
12683
3a3371ff 12684 for_each_intel_connector(dev, connector) {
9a935856
SV		 12685 /* Otherwise traverse passed in connector list and get encoders
12686 * for them. */
50f56119 12687 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12688 if (set->connectors[ro] == &connector->base) {
0e32b39c 12689 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
SV		 12690 break;
12691 }
12692 }
12693
9a935856
SV		 12694 /* If we disable the crtc, disable all its connectors. Also, if
12695 * the connector is on the changing crtc but not on the new
12696 * connector list, disable it. */
12697 if ((!set->fb || ro == set->num_connectors) &&
12698 connector->base.encoder &&
12699 connector->base.encoder->crtc == set->crtc) {
12700 connector->new_encoder = NULL;
12701
12702 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12703 connector->base.base.id,
c23cc417 12704 connector->base.name);
9a935856 12705 }
50f56119 12706 }
9a935856 12707 /* connector->new_encoder is now updated for all connectors. */
50f56119 12708
9a935856 12709 /* Update crtc of enabled connectors. */
3a3371ff 12710 for_each_intel_connector(dev, connector) {
7668851f
VS		 12711 struct drm_crtc *new_crtc;
12712
9a935856 12713 if (!connector->new_encoder)
50f56119
SV		 12714 continue;
12715
9a935856 12716 new_crtc = connector->new_encoder->base.crtc;
50f56119
SV		 12717
12718 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12719 if (set->connectors[ro] == &connector->base)
50f56119
SV		 12720 new_crtc = set->crtc;
12721 }
12722
12723 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12724 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12725 new_crtc)) {
5e2b584e 12726 return -EINVAL;
50f56119 12727 }
0e32b39c 12728 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12729
944b0c76
ACO		 12730 connector_state =
12731 drm_atomic_get_connector_state(state, &connector->base);
12732 if (IS_ERR(connector_state))
12733 return PTR_ERR(connector_state);
12734
12735 connector_state->crtc = new_crtc;
12736 connector_state->best_encoder = &connector->new_encoder->base;
12737
9a935856
SV		 12738 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12739 connector->base.base.id,
c23cc417 12740 connector->base.name,
9a935856
SV		 12741 new_crtc->base.id);
12742 }
12743
12744 /* Check for any encoders that needs to be disabled. */
b2784e15 12745 for_each_intel_encoder(dev, encoder) {
5a65f358 12746 int num_connectors = 0;
3a3371ff 12747 for_each_intel_connector(dev, connector) {
9a935856
SV		 12748 if (connector->new_encoder == encoder) {
12749 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12750 num_connectors++;
9a935856
SV		 12751 }
12752 }
5a65f358
PZ		 12753
12754 if (num_connectors == 0)
12755 encoder->new_crtc = NULL;
12756 else if (num_connectors > 1)
12757 return -EINVAL;
50f56119 12758 }
9a935856 12759 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12760 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12761 connector_state =
12762 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12763 if (IS_ERR(connector_state))
12764 return PTR_ERR(connector_state);
944b0c76
ACO		 12765
12766 if (connector->new_encoder) {
0e32b39c
DA		 12767 if (connector->new_encoder != connector->encoder)
12768 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12769 } else {
12770 connector_state->crtc = NULL;
f61cccf3 12771 connector_state->best_encoder = NULL;
944b0c76 12772 }
0e32b39c 12773 }
d3fcc808 12774 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12775 crtc->new_enabled = false;
12776
b2784e15 12777 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12778 if (encoder->new_crtc == crtc) {
12779 crtc->new_enabled = true;
12780 break;
12781 }
12782 }
4be07317
ACO		 12783
12784 if (crtc->new_enabled != crtc->base.state->enable) {
12785 crtc_state = intel_atomic_get_crtc_state(state, crtc);
12786 if (IS_ERR(crtc_state))
12787 return PTR_ERR(crtc_state);
12788
12789 crtc_state->base.enable = crtc->new_enabled;
12790 }
7668851f
VS		 12791 }
12792
2e431051
SV		 12793 return 0;
12794}
12795
7d00a1f5
VS		 12796static void disable_crtc_nofb(struct intel_crtc *crtc)
12797{
12798 struct drm_device *dev = crtc->base.dev;
12799 struct intel_encoder *encoder;
12800 struct intel_connector *connector;
12801
12802 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12803 pipe_name(crtc->pipe));
12804
3a3371ff 12805 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12806 if (connector->new_encoder &&
12807 connector->new_encoder->new_crtc == crtc)
12808 connector->new_encoder = NULL;
12809 }
12810
b2784e15 12811 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12812 if (encoder->new_crtc == crtc)
12813 encoder->new_crtc = NULL;
12814 }
12815
12816 crtc->new_enabled = false;
12817}
12818
2e431051
SV		 12819static int intel_crtc_set_config(struct drm_mode_set *set)
12820{
12821 struct drm_device *dev;
2e431051 12822 struct drm_mode_set save_set;
83a57153 12823 struct drm_atomic_state *state = NULL;
2e431051 12824 struct intel_set_config *config;
5cec258b 12825 struct intel_crtc_state *pipe_config;
2e431051 12826 int ret;
2e431051 12827
8d3e375e
SV		 12828 BUG_ON(!set);
12829 BUG_ON(!set->crtc);
12830 BUG_ON(!set->crtc->helper_private);
2e431051 12831
7e53f3a4
SV		 12832 /* Enforce sane interface api - has been abused by the fb helper. */
12833 BUG_ON(!set->mode && set->fb);
12834 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12835
2e431051
SV		 12836 if (set->fb) {
12837 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12838 set->crtc->base.id, set->fb->base.id,
12839 (int)set->num_connectors, set->x, set->y);
12840 } else {
12841 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
SV		 12842 }
12843
12844 dev = set->crtc->dev;
12845
12846 ret = -ENOMEM;
12847 config = kzalloc(sizeof(*config), GFP_KERNEL);
12848 if (!config)
12849 goto out_config;
12850
12851 ret = intel_set_config_save_state(dev, config);
12852 if (ret)
12853 goto out_config;
12854
12855 save_set.crtc = set->crtc;
12856 save_set.mode = &set->crtc->mode;
12857 save_set.x = set->crtc->x;
12858 save_set.y = set->crtc->y;
f4510a27 12859 save_set.fb = set->crtc->primary->fb;
2e431051 12860
83a57153
ACO		 12861 state = drm_atomic_state_alloc(dev);
12862 if (!state) {
12863 ret = -ENOMEM;
12864 goto out_config;
12865 }
12866
12867 state->acquire_ctx = dev->mode_config.acquire_ctx;
12868
462a425a 12869 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051
SV		 12870 if (ret)
12871 goto fail;
12872
462a425a
ACO		 12873 /* Compute whether we need a full modeset, only an fb base update or no
12874 * change at all. In the future we might also check whether only the
12875 * mode changed, e.g. for LVDS where we only change the panel fitter in
12876 * such cases. */
12877 intel_set_config_compute_mode_changes(set, config);
12878
50f52756 12879 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
0a9ab303 12880 state);
20664591 12881 if (IS_ERR(pipe_config)) {
6ac0483b 12882 ret = PTR_ERR(pipe_config);
50f52756 12883 goto fail;
20664591 12884 } else if (pipe_config) {
b9950a13 12885 if (pipe_config->has_audio !=
6e3c9717 12886 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12887 config->mode_changed = true;
12888
af15d2ce
JB		 12889 /*
12890 * Note we have an issue here with infoframes: current code
12891 * only updates them on the full mode set path per hw
12892 * requirements. So here we should be checking for any
12893 * required changes and forcing a mode set.
12894 */
20664591 12895 }
50f52756 12896
1f9954d0
JB		 12897 intel_update_pipe_size(to_intel_crtc(set->crtc));
12898
5e2b584e 12899 if (config->mode_changed) {
0a9ab303
ACO		 12900 ret = intel_set_mode_with_config(set->crtc, set->mode,
12901 set->x, set->y, set->fb,
12902 pipe_config);
5e2b584e 12903 } else if (config->fb_changed) {
3b150f08 12904 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808 12905 struct drm_plane *primary = set->crtc->primary;
b70709a6
ML		 12906 struct intel_plane_state *plane_state =
12907 to_intel_plane_state(primary->state);
12908 bool was_visible = plane_state->visible;
455a6808 12909 int vdisplay, hdisplay;
3b150f08 12910
455a6808 12911 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
70a101f8
MR		 12912 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12913 0, 0, hdisplay, vdisplay,
12914 set->x << 16, set->y << 16,
12915 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12916
12917 /*
12918 * We need to make sure the primary plane is re-enabled if it
12919 * has previously been turned off.
12920 */
b70709a6
ML		 12921 plane_state = to_intel_plane_state(primary->state);
12922 if (ret == 0 && !was_visible && plane_state->visible) {
3b150f08 12923 WARN_ON(!intel_crtc->active);
87d4300a 12924 intel_post_enable_primary(set->crtc);
3b150f08
MR		 12925 }
12926
7ca51a3a
JB		 12927 /*
12928 * In the fastboot case this may be our only check of the
12929 * state after boot. It would be better to only do it on
12930 * the first update, but we don't have a nice way of doing that
12931 * (and really, set_config isn't used much for high freq page
12932 * flipping, so increasing its cost here shouldn't be a big
12933 * deal).
12934 */
d330a953 12935 if (i915.fastboot && ret == 0)
7ca51a3a 12936 intel_modeset_check_state(set->crtc->dev);
50f56119
SV		 12937 }
12938
2d05eae1 12939 if (ret) {
bf67dfeb
SV		 12940 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12941 set->crtc->base.id, ret);
50f56119 12942fail:
2d05eae1 12943 intel_set_config_restore_state(dev, config);
50f56119 12944
83a57153
ACO		 12945 drm_atomic_state_clear(state);
12946
7d00a1f5
VS		 12947 /*
12948 * HACK: if the pipe was on, but we didn't have a framebuffer,
12949 * force the pipe off to avoid oopsing in the modeset code
12950 * due to fb==NULL. This should only happen during boot since
12951 * we don't yet reconstruct the FB from the hardware state.
12952 */
12953 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12954 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12955
2d05eae1
CW		 12956 /* Try to restore the config */
12957 if (config->mode_changed &&
12958 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12959 save_set.x, save_set.y, save_set.fb,
12960 state))
2d05eae1
CW		 12961 DRM_ERROR("failed to restore config after modeset failure\n");
12962 }
50f56119 12963
d9e55608 12964out_config:
e5d958ef 12965 drm_atomic_state_free(state);
83a57153 12966
d9e55608 12967 intel_set_config_free(config);
50f56119
SV		 12968 return ret;
12969}
f6e5b160
CW		 12970
12971static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12972 .gamma_set = intel_crtc_gamma_set,
50f56119 12973 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12974 .destroy = intel_crtc_destroy,
12975 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12976 .atomic_duplicate_state = intel_crtc_duplicate_state,
12977 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12978};
12979
5358901f
SV		 12980static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12981 struct intel_shared_dpll *pll,
12982 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12983{
5358901f 12984 uint32_t val;
ee7b9f93 12985
f458ebbc 12986 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12987 return false;
12988
5358901f 12989 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
SV		 12990 hw_state->dpll = val;
12991 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12992 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
SV		 12993
12994 return val & DPLL_VCO_ENABLE;
12995}
12996
15bdd4cf
SV		 12997static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12998 struct intel_shared_dpll *pll)
12999{
3e369b76
ACO		 13000 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13001 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
SV		 13002}
13003
e7b903d2
SV		 13004static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13005 struct intel_shared_dpll *pll)
13006{
e7b903d2 13007 /* PCH refclock must be enabled first */
89eff4be 13008 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13009
3e369b76 13010 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
SV		 13011
13012 /* Wait for the clocks to stabilize. */
13013 POSTING_READ(PCH_DPLL(pll->id));
13014 udelay(150);
13015
13016 /* The pixel multiplier can only be updated once the
13017 * DPLL is enabled and the clocks are stable.
13018 *
13019 * So write it again.
13020 */
3e369b76 13021 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13022 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
SV		 13023 udelay(200);
13024}
13025
13026static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13027 struct intel_shared_dpll *pll)
13028{
13029 struct drm_device *dev = dev_priv->dev;
13030 struct intel_crtc *crtc;
e7b903d2
SV		 13031
13032 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13033 for_each_intel_crtc(dev, crtc) {
e7b903d2
SV		 13034 if (intel_crtc_to_shared_dpll(crtc) == pll)
13035 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13036 }
13037
15bdd4cf
SV		 13038 I915_WRITE(PCH_DPLL(pll->id), 0);
13039 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
SV		 13040 udelay(200);
13041}
13042
46edb027
SV		 13043static char *ibx_pch_dpll_names[] = {
13044 "PCH DPLL A",
13045 "PCH DPLL B",
13046};
13047
7c74ade1 13048static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13049{
e7b903d2 13050 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13051 int i;
13052
7c74ade1 13053 dev_priv->num_shared_dpll = 2;
ee7b9f93 13054
e72f9fbf 13055 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
SV		 13056 dev_priv->shared_dplls[i].id = i;
13057 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13058 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
SV		 13059 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13060 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
SV		 13061 dev_priv->shared_dplls[i].get_hw_state =
13062 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13063 }
13064}
13065
7c74ade1
SV		 13066static void intel_shared_dpll_init(struct drm_device *dev)
13067{
e7b903d2 13068 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13069
9cd86933
SV		 13070 if (HAS_DDI(dev))
13071 intel_ddi_pll_init(dev);
13072 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
SV		 13073 ibx_pch_dpll_init(dev);
13074 else
13075 dev_priv->num_shared_dpll = 0;
13076
13077 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
SV		 13078}
13079
1fc0a8f7
TU		 13080/**
13081 * intel_wm_need_update - Check whether watermarks need updating
13082 * @plane: drm plane
13083 * @state: new plane state
13084 *
13085 * Check current plane state versus the new one to determine whether
13086 * watermarks need to be recalculated.
13087 *
13088 * Returns true or false.
13089 */
13090bool intel_wm_need_update(struct drm_plane *plane,
13091 struct drm_plane_state *state)
13092{
13093 /* Update watermarks on tiling changes. */
13094 if (!plane->state->fb || !state->fb ||
13095 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13096 plane->state->rotation != state->rotation)
13097 return true;
13098
13099 return false;
13100}
13101
6beb8c23
MR		 13102/**
13103 * intel_prepare_plane_fb - Prepare fb for usage on plane
13104 * @plane: drm plane to prepare for
13105 * @fb: framebuffer to prepare for presentation
13106 *
13107 * Prepares a framebuffer for usage on a display plane. Generally this
13108 * involves pinning the underlying object and updating the frontbuffer tracking
13109 * bits. Some older platforms need special physical address handling for
13110 * cursor planes.
13111 *
13112 * Returns 0 on success, negative error code on failure.
13113 */
13114int
13115intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13116 struct drm_framebuffer *fb,
13117 const struct drm_plane_state *new_state)
465c120c
MR		 13118{
13119 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13120 struct intel_plane *intel_plane = to_intel_plane(plane);
13121 enum pipe pipe = intel_plane->pipe;
13122 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13123 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13124 unsigned frontbuffer_bits = 0;
13125 int ret = 0;
465c120c 13126
ea2c67bb 13127 if (!obj)
465c120c
MR		 13128 return 0;
13129
6beb8c23
MR		 13130 switch (plane->type) {
13131 case DRM_PLANE_TYPE_PRIMARY:
13132 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13133 break;
13134 case DRM_PLANE_TYPE_CURSOR:
13135 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13136 break;
13137 case DRM_PLANE_TYPE_OVERLAY:
13138 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13139 break;
13140 }
465c120c 13141
6beb8c23 13142 mutex_lock(&dev->struct_mutex);
465c120c 13143
6beb8c23
MR		 13144 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13145 INTEL_INFO(dev)->cursor_needs_physical) {
13146 int align = IS_I830(dev) ? 16 * 1024 : 256;
13147 ret = i915_gem_object_attach_phys(obj, align);
13148 if (ret)
13149 DRM_DEBUG_KMS("failed to attach phys object\n");
13150 } else {
82bc3b2d 13151 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13152 }
465c120c 13153
6beb8c23
MR		 13154 if (ret == 0)
13155 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13156
4c34574f 13157 mutex_unlock(&dev->struct_mutex);
465c120c 13158
6beb8c23
MR		 13159 return ret;
13160}
13161
38f3ce3a
MR		 13162/**
13163 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13164 * @plane: drm plane to clean up for
13165 * @fb: old framebuffer that was on plane
13166 *
13167 * Cleans up a framebuffer that has just been removed from a plane.
13168 */
13169void
13170intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13171 struct drm_framebuffer *fb,
13172 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13173{
13174 struct drm_device *dev = plane->dev;
13175 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13176
13177 if (WARN_ON(!obj))
13178 return;
13179
13180 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13181 !INTEL_INFO(dev)->cursor_needs_physical) {
13182 mutex_lock(&dev->struct_mutex);
82bc3b2d 13183 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13184 mutex_unlock(&dev->struct_mutex);
13185 }
465c120c
MR		 13186}
13187
6156a456
CK		 13188int
13189skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13190{
13191 int max_scale;
13192 struct drm_device *dev;
13193 struct drm_i915_private *dev_priv;
13194 int crtc_clock, cdclk;
13195
13196 if (!intel_crtc || !crtc_state)
13197 return DRM_PLANE_HELPER_NO_SCALING;
13198
13199 dev = intel_crtc->base.dev;
13200 dev_priv = dev->dev_private;
13201 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13202 cdclk = dev_priv->display.get_display_clock_speed(dev);
13203
13204 if (!crtc_clock || !cdclk)
13205 return DRM_PLANE_HELPER_NO_SCALING;
13206
13207 /*
13208 * skl max scale is lower of:
13209 * close to 3 but not 3, -1 is for that purpose
13210 * or
13211 * cdclk/crtc_clock
13212 */
13213 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13214
13215 return max_scale;
13216}
13217
465c120c 13218static int
3c692a41
GP		 13219intel_check_primary_plane(struct drm_plane *plane,
13220 struct intel_plane_state *state)
13221{
32b7eeec
MR		 13222 struct drm_device *dev = plane->dev;
13223 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13224 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13225 struct intel_crtc *intel_crtc;
6156a456 13226 struct intel_crtc_state *crtc_state;
2b875c22 13227 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13228 struct drm_rect *dest = &state->dst;
13229 struct drm_rect *src = &state->src;
13230 const struct drm_rect *clip = &state->clip;
d8106366 13231 bool can_position = false;
6156a456
CK		 13232 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13233 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13234 int ret;
13235
ea2c67bb
MR		 13236 crtc = crtc ? crtc : plane->crtc;
13237 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13238 crtc_state = state->base.state ?
13239 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13240
6156a456
CK		 13241 if (INTEL_INFO(dev)->gen >= 9) {
13242 min_scale = 1;
13243 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13244 can_position = true;
6156a456 13245 }
d8106366 13246
c59cb179
MR		 13247 ret = drm_plane_helper_check_update(plane, crtc, fb,
13248 src, dest, clip,
6156a456
CK		 13249 min_scale,
13250 max_scale,
d8106366
SJ		 13251 can_position, true,
13252 &state->visible);
c59cb179
MR		 13253 if (ret)
13254 return ret;
465c120c 13255
32b7eeec 13256 if (intel_crtc->active) {
b70709a6
ML		 13257 struct intel_plane_state *old_state =
13258 to_intel_plane_state(plane->state);
13259
32b7eeec
MR		 13260 intel_crtc->atomic.wait_for_flips = true;
13261
13262 /*
13263 * FBC does not work on some platforms for rotated
13264 * planes, so disable it when rotation is not 0 and
13265 * update it when rotation is set back to 0.
13266 *
13267 * FIXME: This is redundant with the fbc update done in
13268 * the primary plane enable function except that that
13269 * one is done too late. We eventually need to unify
13270 * this.
13271 */
b70709a6 13272 if (state->visible &&
32b7eeec 13273 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13274 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13275 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13276 intel_crtc->atomic.disable_fbc = true;
13277 }
13278
b70709a6 13279 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13280 /*
13281 * BDW signals flip done immediately if the plane
13282 * is disabled, even if the plane enable is already
13283 * armed to occur at the next vblank :(
13284 */
b70709a6 13285 if (IS_BROADWELL(dev))
32b7eeec
MR		 13286 intel_crtc->atomic.wait_vblank = true;
13287 }
13288
13289 intel_crtc->atomic.fb_bits |=
13290 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13291
13292 intel_crtc->atomic.update_fbc = true;
0fda6568 13293
1fc0a8f7 13294 if (intel_wm_need_update(plane, &state->base))
0fda6568 13295 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13296 }
13297
6156a456
CK		 13298 if (INTEL_INFO(dev)->gen >= 9) {
13299 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13300 to_intel_plane(plane), state, 0);
13301 if (ret)
13302 return ret;
13303 }
13304
14af293f
GP		 13305 return 0;
13306}
13307
13308static void
13309intel_commit_primary_plane(struct drm_plane *plane,
13310 struct intel_plane_state *state)
13311{
2b875c22
MR		 13312 struct drm_crtc *crtc = state->base.crtc;
13313 struct drm_framebuffer *fb = state->base.fb;
13314 struct drm_device *dev = plane->dev;
14af293f 13315 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13316 struct intel_crtc *intel_crtc;
14af293f
GP		 13317 struct drm_rect *src = &state->src;
13318
ea2c67bb
MR		 13319 crtc = crtc ? crtc : plane->crtc;
13320 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13321
13322 plane->fb = fb;
9dc806fc
MR		 13323 crtc->x = src->x1 >> 16;
13324 crtc->y = src->y1 >> 16;
ccc759dc 13325
ccc759dc 13326 if (intel_crtc->active) {
27321ae8 13327 if (state->visible)
ccc759dc
GP		 13328 /* FIXME: kill this fastboot hack */
13329 intel_update_pipe_size(intel_crtc);
465c120c 13330
27321ae8
ML		 13331 dev_priv->display.update_primary_plane(crtc, plane->fb,
13332 crtc->x, crtc->y);
ccc759dc 13333 }
465c120c
MR		 13334}
13335
a8ad0d8e
ML		 13336static void
13337intel_disable_primary_plane(struct drm_plane *plane,
13338 struct drm_crtc *crtc,
13339 bool force)
13340{
13341 struct drm_device *dev = plane->dev;
13342 struct drm_i915_private *dev_priv = dev->dev_private;
13343
a8ad0d8e
ML		 13344 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13345}
13346
32b7eeec 13347static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13348{
32b7eeec 13349 struct drm_device *dev = crtc->dev;
140fd38d 13350 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13352 struct intel_plane *intel_plane;
13353 struct drm_plane *p;
13354 unsigned fb_bits = 0;
13355
13356 /* Track fb's for any planes being disabled */
13357 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13358 intel_plane = to_intel_plane(p);
13359
13360 if (intel_crtc->atomic.disabled_planes &
13361 (1 << drm_plane_index(p))) {
13362 switch (p->type) {
13363 case DRM_PLANE_TYPE_PRIMARY:
13364 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13365 break;
13366 case DRM_PLANE_TYPE_CURSOR:
13367 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13368 break;
13369 case DRM_PLANE_TYPE_OVERLAY:
13370 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13371 break;
13372 }
3c692a41 13373
ea2c67bb
MR		 13374 mutex_lock(&dev->struct_mutex);
13375 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13376 mutex_unlock(&dev->struct_mutex);
13377 }
13378 }
3c692a41 13379
32b7eeec
MR		 13380 if (intel_crtc->atomic.wait_for_flips)
13381 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13382
32b7eeec
MR		 13383 if (intel_crtc->atomic.disable_fbc)
13384 intel_fbc_disable(dev);
3c692a41 13385
32b7eeec
MR		 13386 if (intel_crtc->atomic.pre_disable_primary)
13387 intel_pre_disable_primary(crtc);
3c692a41 13388
32b7eeec
MR		 13389 if (intel_crtc->atomic.update_wm)
13390 intel_update_watermarks(crtc);
3c692a41 13391
32b7eeec 13392 intel_runtime_pm_get(dev_priv);
3c692a41 13393
c34c9ee4
MR		 13394 /* Perform vblank evasion around commit operation */
13395 if (intel_crtc->active)
13396 intel_crtc->atomic.evade =
13397 intel_pipe_update_start(intel_crtc,
13398 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13399}
13400
13401static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13402{
13403 struct drm_device *dev = crtc->dev;
13404 struct drm_i915_private *dev_priv = dev->dev_private;
13405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13406 struct drm_plane *p;
13407
c34c9ee4
MR		 13408 if (intel_crtc->atomic.evade)
13409 intel_pipe_update_end(intel_crtc,
13410 intel_crtc->atomic.start_vbl_count);
3c692a41 13411
140fd38d 13412 intel_runtime_pm_put(dev_priv);
3c692a41 13413
32b7eeec
MR		 13414 if (intel_crtc->atomic.wait_vblank)
13415 intel_wait_for_vblank(dev, intel_crtc->pipe);
13416
13417 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13418
13419 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13420 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13421 intel_fbc_update(dev);
ccc759dc 13422 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13423 }
3c692a41 13424
32b7eeec
MR		 13425 if (intel_crtc->atomic.post_enable_primary)
13426 intel_post_enable_primary(crtc);
3c692a41 13427
32b7eeec
MR		 13428 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13429 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13430 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13431 false, false);
13432
13433 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13434}
13435
cf4c7c12 13436/**
4a3b8769
MR		 13437 * intel_plane_destroy - destroy a plane
13438 * @plane: plane to destroy
cf4c7c12 13439 *
4a3b8769
MR		 13440 * Common destruction function for all types of planes (primary, cursor,
13441 * sprite).
cf4c7c12 13442 */
4a3b8769 13443void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13444{
13445 struct intel_plane *intel_plane = to_intel_plane(plane);
13446 drm_plane_cleanup(plane);
13447 kfree(intel_plane);
13448}
13449
65a3fea0 13450const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13451 .update_plane = drm_atomic_helper_update_plane,
13452 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13453 .destroy = intel_plane_destroy,
c196e1d6 13454 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13455 .atomic_get_property = intel_plane_atomic_get_property,
13456 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13457 .atomic_duplicate_state = intel_plane_duplicate_state,
13458 .atomic_destroy_state = intel_plane_destroy_state,
13459
465c120c
MR		 13460};
13461
13462static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13463 int pipe)
13464{
13465 struct intel_plane *primary;
8e7d688b 13466 struct intel_plane_state *state;
465c120c
MR		 13467 const uint32_t *intel_primary_formats;
13468 int num_formats;
13469
13470 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13471 if (primary == NULL)
13472 return NULL;
13473
8e7d688b
MR		 13474 state = intel_create_plane_state(&primary->base);
13475 if (!state) {
ea2c67bb
MR		 13476 kfree(primary);
13477 return NULL;
13478 }
8e7d688b 13479 primary->base.state = &state->base;
ea2c67bb 13480
465c120c
MR		 13481 primary->can_scale = false;
13482 primary->max_downscale = 1;
6156a456
CK		 13483 if (INTEL_INFO(dev)->gen >= 9) {
13484 primary->can_scale = true;
13485 }
549e2bfb 13486 state->scaler_id = -1;
465c120c
MR		 13487 primary->pipe = pipe;
13488 primary->plane = pipe;
c59cb179
MR		 13489 primary->check_plane = intel_check_primary_plane;
13490 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13491 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13492 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13493 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13494 primary->plane = !pipe;
13495
13496 if (INTEL_INFO(dev)->gen <= 3) {
13497 intel_primary_formats = intel_primary_formats_gen2;
13498 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13499 } else {
13500 intel_primary_formats = intel_primary_formats_gen4;
13501 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13502 }
13503
13504 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13505 &intel_plane_funcs,
465c120c
MR		 13506 intel_primary_formats, num_formats,
13507 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13508
3b7a5119
SJ		 13509 if (INTEL_INFO(dev)->gen >= 4)
13510 intel_create_rotation_property(dev, primary);
48404c1e 13511
ea2c67bb
MR		 13512 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13513
465c120c
MR		 13514 return &primary->base;
13515}
13516
3b7a5119
SJ		 13517void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13518{
13519 if (!dev->mode_config.rotation_property) {
13520 unsigned long flags = BIT(DRM_ROTATE_0) |
13521 BIT(DRM_ROTATE_180);
13522
13523 if (INTEL_INFO(dev)->gen >= 9)
13524 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13525
13526 dev->mode_config.rotation_property =
13527 drm_mode_create_rotation_property(dev, flags);
13528 }
13529 if (dev->mode_config.rotation_property)
13530 drm_object_attach_property(&plane->base.base,
13531 dev->mode_config.rotation_property,
13532 plane->base.state->rotation);
13533}
13534
3d7d6510 13535static int
852e787c
GP		 13536intel_check_cursor_plane(struct drm_plane *plane,
13537 struct intel_plane_state *state)
3d7d6510 13538{
2b875c22 13539 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13540 struct drm_device *dev = plane->dev;
2b875c22 13541 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13542 struct drm_rect *dest = &state->dst;
13543 struct drm_rect *src = &state->src;
13544 const struct drm_rect *clip = &state->clip;
757f9a3e 13545 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13546 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13547 unsigned stride;
13548 int ret;
3d7d6510 13549
ea2c67bb
MR		 13550 crtc = crtc ? crtc : plane->crtc;
13551 intel_crtc = to_intel_crtc(crtc);
13552
757f9a3e 13553 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13554 src, dest, clip,
3d7d6510
MR		 13555 DRM_PLANE_HELPER_NO_SCALING,
13556 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13557 true, true, &state->visible);
757f9a3e
GP		 13558 if (ret)
13559 return ret;
13560
13561
13562 /* if we want to turn off the cursor ignore width and height */
13563 if (!obj)
32b7eeec 13564 goto finish;
757f9a3e 13565
757f9a3e 13566 /* Check for which cursor types we support */
ea2c67bb
MR		 13567 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13568 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13569 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13570 return -EINVAL;
13571 }
13572
ea2c67bb
MR		 13573 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13574 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13575 DRM_DEBUG_KMS("buffer is too small\n");
13576 return -ENOMEM;
13577 }
13578
3a656b54 13579 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13580 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13581 ret = -EINVAL;
13582 }
757f9a3e 13583
32b7eeec
MR		 13584finish:
13585 if (intel_crtc->active) {
3749f463 13586 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13587 intel_crtc->atomic.update_wm = true;
13588
13589 intel_crtc->atomic.fb_bits |=
13590 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13591 }
13592
757f9a3e 13593 return ret;
852e787c 13594}
3d7d6510 13595
a8ad0d8e
ML		 13596static void
13597intel_disable_cursor_plane(struct drm_plane *plane,
13598 struct drm_crtc *crtc,
13599 bool force)
13600{
13601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13602
13603 if (!force) {
13604 plane->fb = NULL;
13605 intel_crtc->cursor_bo = NULL;
13606 intel_crtc->cursor_addr = 0;
13607 }
13608
13609 intel_crtc_update_cursor(crtc, false);
13610}
13611
f4a2cf29 13612static void
852e787c
GP		 13613intel_commit_cursor_plane(struct drm_plane *plane,
13614 struct intel_plane_state *state)
13615{
2b875c22 13616 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13617 struct drm_device *dev = plane->dev;
13618 struct intel_crtc *intel_crtc;
2b875c22 13619 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13620 uint32_t addr;
852e787c 13621
ea2c67bb
MR		 13622 crtc = crtc ? crtc : plane->crtc;
13623 intel_crtc = to_intel_crtc(crtc);
13624
2b875c22 13625 plane->fb = state->base.fb;
ea2c67bb
MR		 13626 crtc->cursor_x = state->base.crtc_x;
13627 crtc->cursor_y = state->base.crtc_y;
13628
a912f12f
GP		 13629 if (intel_crtc->cursor_bo == obj)
13630 goto update;
4ed91096 13631
f4a2cf29 13632 if (!obj)
a912f12f 13633 addr = 0;
f4a2cf29 13634 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13635 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13636 else
a912f12f 13637 addr = obj->phys_handle->busaddr;
852e787c 13638
a912f12f
GP		 13639 intel_crtc->cursor_addr = addr;
13640 intel_crtc->cursor_bo = obj;
13641update:
852e787c 13642
32b7eeec 13643 if (intel_crtc->active)
a912f12f 13644 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13645}
13646
3d7d6510
MR		 13647static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13648 int pipe)
13649{
13650 struct intel_plane *cursor;
8e7d688b 13651 struct intel_plane_state *state;
3d7d6510
MR		 13652
13653 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13654 if (cursor == NULL)
13655 return NULL;
13656
8e7d688b
MR		 13657 state = intel_create_plane_state(&cursor->base);
13658 if (!state) {
ea2c67bb
MR		 13659 kfree(cursor);
13660 return NULL;
13661 }
8e7d688b 13662 cursor->base.state = &state->base;
ea2c67bb 13663
3d7d6510
MR		 13664 cursor->can_scale = false;
13665 cursor->max_downscale = 1;
13666 cursor->pipe = pipe;
13667 cursor->plane = pipe;
549e2bfb 13668 state->scaler_id = -1;
c59cb179
MR		 13669 cursor->check_plane = intel_check_cursor_plane;
13670 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13671 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13672
13673 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13674 &intel_plane_funcs,
3d7d6510
MR		 13675 intel_cursor_formats,
13676 ARRAY_SIZE(intel_cursor_formats),
13677 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13678
13679 if (INTEL_INFO(dev)->gen >= 4) {
13680 if (!dev->mode_config.rotation_property)
13681 dev->mode_config.rotation_property =
13682 drm_mode_create_rotation_property(dev,
13683 BIT(DRM_ROTATE_0) |
13684 BIT(DRM_ROTATE_180));
13685 if (dev->mode_config.rotation_property)
13686 drm_object_attach_property(&cursor->base.base,
13687 dev->mode_config.rotation_property,
8e7d688b 13688 state->base.rotation);
4398ad45
VS		 13689 }
13690
ea2c67bb
MR		 13691 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13692
3d7d6510
MR		 13693 return &cursor->base;
13694}
13695
549e2bfb
CK		 13696static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13697 struct intel_crtc_state *crtc_state)
13698{
13699 int i;
13700 struct intel_scaler *intel_scaler;
13701 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13702
13703 for (i = 0; i < intel_crtc->num_scalers; i++) {
13704 intel_scaler = &scaler_state->scalers[i];
13705 intel_scaler->in_use = 0;
13706 intel_scaler->id = i;
13707
13708 intel_scaler->mode = PS_SCALER_MODE_DYN;
13709 }
13710
13711 scaler_state->scaler_id = -1;
13712}
13713
b358d0a6 13714static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13715{
fbee40df 13716 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13717 struct intel_crtc *intel_crtc;
f5de6e07 13718 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13719 struct drm_plane *primary = NULL;
13720 struct drm_plane *cursor = NULL;
465c120c 13721 int i, ret;
79e53945 13722
955382f3 13723 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13724 if (intel_crtc == NULL)
13725 return;
13726
f5de6e07
ACO		 13727 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13728 if (!crtc_state)
13729 goto fail;
13730 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 13731 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13732
549e2bfb
CK		 13733 /* initialize shared scalers */
13734 if (INTEL_INFO(dev)->gen >= 9) {
13735 if (pipe == PIPE_C)
13736 intel_crtc->num_scalers = 1;
13737 else
13738 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13739
13740 skl_init_scalers(dev, intel_crtc, crtc_state);
13741 }
13742
465c120c 13743 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13744 if (!primary)
13745 goto fail;
13746
13747 cursor = intel_cursor_plane_create(dev, pipe);
13748 if (!cursor)
13749 goto fail;
13750
465c120c 13751 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13752 cursor, &intel_crtc_funcs);
13753 if (ret)
13754 goto fail;
79e53945
JB		 13755
13756 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13757 for (i = 0; i < 256; i++) {
13758 intel_crtc->lut_r[i] = i;
13759 intel_crtc->lut_g[i] = i;
13760 intel_crtc->lut_b[i] = i;
13761 }
13762
1f1c2e24
VS		 13763 /*
13764 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13765 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13766 */
80824003
JB		 13767 intel_crtc->pipe = pipe;
13768 intel_crtc->plane = pipe;
3a77c4c4 13769 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13770 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13771 intel_crtc->plane = !pipe;
80824003
JB		 13772 }
13773
4b0e333e
CW		 13774 intel_crtc->cursor_base = ~0;
13775 intel_crtc->cursor_cntl = ~0;
dc41c154 13776 intel_crtc->cursor_size = ~0;
8d7849db 13777
22fd0fab
JB		 13778 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13779 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13780 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13781 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13782
9362c7c5
ACO		 13783 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13784
79e53945 13785 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
SV		 13786
13787 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13788 return;
13789
13790fail:
13791 if (primary)
13792 drm_plane_cleanup(primary);
13793 if (cursor)
13794 drm_plane_cleanup(cursor);
f5de6e07 13795 kfree(crtc_state);
3d7d6510 13796 kfree(intel_crtc);
79e53945
JB		 13797}
13798
752aa88a
JB		 13799enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13800{
13801 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13802 struct drm_device *dev = connector->base.dev;
752aa88a 13803
51fd371b 13804 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13805
d3babd3f 13806 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13807 return INVALID_PIPE;
13808
13809 return to_intel_crtc(encoder->crtc)->pipe;
13810}
13811
08d7b3d1 13812int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13813 struct drm_file *file)
08d7b3d1 13814{
08d7b3d1 13815 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13816 struct drm_crtc *drmmode_crtc;
c05422d5 13817 struct intel_crtc *crtc;
08d7b3d1 13818
7707e653 13819 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13820
7707e653 13821 if (!drmmode_crtc) {
08d7b3d1 13822 DRM_ERROR("no such CRTC id\n");
3f2c2057 13823 return -ENOENT;
08d7b3d1
CW		 13824 }
13825
7707e653 13826 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13827 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13828
c05422d5 13829 return 0;
08d7b3d1
CW		 13830}
13831
66a9278e 13832static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13833{
66a9278e
SV		 13834 struct drm_device *dev = encoder->base.dev;
13835 struct intel_encoder *source_encoder;
79e53945 13836 int index_mask = 0;
79e53945
JB		 13837 int entry = 0;
13838
b2784e15 13839 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13840 if (encoders_cloneable(encoder, source_encoder))
66a9278e
SV		 13841 index_mask |= (1 << entry);
13842
79e53945
JB		 13843 entry++;
13844 }
4ef69c7a 13845
79e53945
JB		 13846 return index_mask;
13847}
13848
4d302442
CW		 13849static bool has_edp_a(struct drm_device *dev)
13850{
13851 struct drm_i915_private *dev_priv = dev->dev_private;
13852
13853 if (!IS_MOBILE(dev))
13854 return false;
13855
13856 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13857 return false;
13858
e3589908 13859 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13860 return false;
13861
13862 return true;
13863}
13864
84b4e042
JB		 13865static bool intel_crt_present(struct drm_device *dev)
13866{
13867 struct drm_i915_private *dev_priv = dev->dev_private;
13868
884497ed
DL		 13869 if (INTEL_INFO(dev)->gen >= 9)
13870 return false;
13871
cf404ce4 13872 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13873 return false;
13874
13875 if (IS_CHERRYVIEW(dev))
13876 return false;
13877
13878 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13879 return false;
13880
13881 return true;
13882}
13883
79e53945
JB		 13884static void intel_setup_outputs(struct drm_device *dev)
13885{
725e30ad 13886 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13887 struct intel_encoder *encoder;
cb0953d7 13888 bool dpd_is_edp = false;
79e53945 13889
c9093354 13890 intel_lvds_init(dev);
79e53945 13891
84b4e042 13892 if (intel_crt_present(dev))
79935fca 13893 intel_crt_init(dev);
cb0953d7 13894
c776eb2e
VK		 13895 if (IS_BROXTON(dev)) {
13896 /*
13897 * FIXME: Broxton doesn't support port detection via the
13898 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13899 * detect the ports.
13900 */
13901 intel_ddi_init(dev, PORT_A);
13902 intel_ddi_init(dev, PORT_B);
13903 intel_ddi_init(dev, PORT_C);
13904 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13905 int found;
13906
de31facd
JB		 13907 /*
13908 * Haswell uses DDI functions to detect digital outputs.
13909 * On SKL pre-D0 the strap isn't connected, so we assume
13910 * it's there.
13911 */
0e72a5b5 13912 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13913 /* WaIgnoreDDIAStrap: skl */
13914 if (found ||
13915 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13916 intel_ddi_init(dev, PORT_A);
13917
13918 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13919 * register */
13920 found = I915_READ(SFUSE_STRAP);
13921
13922 if (found & SFUSE_STRAP_DDIB_DETECTED)
13923 intel_ddi_init(dev, PORT_B);
13924 if (found & SFUSE_STRAP_DDIC_DETECTED)
13925 intel_ddi_init(dev, PORT_C);
13926 if (found & SFUSE_STRAP_DDID_DETECTED)
13927 intel_ddi_init(dev, PORT_D);
13928 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13929 int found;
5d8a7752 13930 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
SV		 13931
13932 if (has_edp_a(dev))
13933 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13934
dc0fa718 13935 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13936 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13937 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13938 if (!found)
e2debe91 13939 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13940 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13941 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13942 }
13943
dc0fa718 13944 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13945 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13946
dc0fa718 13947 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13948 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13949
5eb08b69 13950 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13951 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13952
270b3042 13953 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13954 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13955 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13956 /*
13957 * The DP_DETECTED bit is the latched state of the DDC
13958 * SDA pin at boot. However since eDP doesn't require DDC
13959 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13960 * eDP ports may have been muxed to an alternate function.
13961 * Thus we can't rely on the DP_DETECTED bit alone to detect
13962 * eDP ports. Consult the VBT as well as DP_DETECTED to
13963 * detect eDP ports.
13964 */
d2182a66
VS		 13965 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13966 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13967 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13968 PORT_B);
e17ac6db
VS		 13969 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13970 intel_dp_is_edp(dev, PORT_B))
13971 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13972
d2182a66
VS		 13973 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13974 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13975 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13976 PORT_C);
e17ac6db
VS		 13977 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13978 intel_dp_is_edp(dev, PORT_C))
13979 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13980
9418c1f1 13981 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13982 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13983 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13984 PORT_D);
e17ac6db
VS		 13985 /* eDP not supported on port D, so don't check VBT */
13986 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13987 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13988 }
13989
3cfca973 13990 intel_dsi_init(dev);
103a196f 13991 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13992 bool found = false;
7d57382e 13993
e2debe91 13994 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13995 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13996 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13997 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13998 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13999 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14000 }
27185ae1 14001
e7281eab 14002 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14003 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14004 }
13520b05
KH		 14005
14006 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14007
e2debe91 14008 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14009 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14010 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14011 }
27185ae1 14012
e2debe91 14013 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14014
b01f2c3a
JB		 14015 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14016 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14017 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14018 }
e7281eab 14019 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14020 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14021 }
27185ae1 14022
b01f2c3a 14023 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14024 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14025 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14026 } else if (IS_GEN2(dev))
79e53945
JB		 14027 intel_dvo_init(dev);
14028
103a196f 14029 if (SUPPORTS_TV(dev))
79e53945
JB		 14030 intel_tv_init(dev);
14031
0bc12bcb 14032 intel_psr_init(dev);
7c8f8a70 14033
b2784e15 14034 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14035 encoder->base.possible_crtcs = encoder->crtc_mask;
14036 encoder->base.possible_clones =
66a9278e 14037 intel_encoder_clones(encoder);
79e53945 14038 }
47356eb6 14039
dde86e2d 14040 intel_init_pch_refclk(dev);
270b3042
SV		 14041
14042 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14043}
14044
14045static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14046{
60a5ca01 14047 struct drm_device *dev = fb->dev;
79e53945 14048 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14049
ef2d633e 14050 drm_framebuffer_cleanup(fb);
60a5ca01 14051 mutex_lock(&dev->struct_mutex);
ef2d633e 14052 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14053 drm_gem_object_unreference(&intel_fb->obj->base);
14054 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14055 kfree(intel_fb);
14056}
14057
14058static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14059 struct drm_file *file,
79e53945
JB		 14060 unsigned int *handle)
14061{
14062 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14063 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14064
05394f39 14065 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14066}
14067
14068static const struct drm_framebuffer_funcs intel_fb_funcs = {
14069 .destroy = intel_user_framebuffer_destroy,
14070 .create_handle = intel_user_framebuffer_create_handle,
14071};
14072
b321803d
DL		 14073static
14074u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14075 uint32_t pixel_format)
14076{
14077 u32 gen = INTEL_INFO(dev)->gen;
14078
14079 if (gen >= 9) {
14080 /* "The stride in bytes must not exceed the of the size of 8K
14081 * pixels and 32K bytes."
14082 */
14083 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14084 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14085 return 32*1024;
14086 } else if (gen >= 4) {
14087 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14088 return 16*1024;
14089 else
14090 return 32*1024;
14091 } else if (gen >= 3) {
14092 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14093 return 8*1024;
14094 else
14095 return 16*1024;
14096 } else {
14097 /* XXX DSPC is limited to 4k tiled */
14098 return 8*1024;
14099 }
14100}
14101
b5ea642a
SV		 14102static int intel_framebuffer_init(struct drm_device *dev,
14103 struct intel_framebuffer *intel_fb,
14104 struct drm_mode_fb_cmd2 *mode_cmd,
14105 struct drm_i915_gem_object *obj)
79e53945 14106{
6761dd31 14107 unsigned int aligned_height;
79e53945 14108 int ret;
b321803d 14109 u32 pitch_limit, stride_alignment;
79e53945 14110
dd4916c5
SV		 14111 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14112
2a80eada
SV		 14113 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14114 /* Enforce that fb modifier and tiling mode match, but only for
14115 * X-tiled. This is needed for FBC. */
14116 if (!!(obj->tiling_mode == I915_TILING_X) !=
14117 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14118 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14119 return -EINVAL;
14120 }
14121 } else {
14122 if (obj->tiling_mode == I915_TILING_X)
14123 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14124 else if (obj->tiling_mode == I915_TILING_Y) {
14125 DRM_DEBUG("No Y tiling for legacy addfb\n");
14126 return -EINVAL;
14127 }
14128 }
14129
9a8f0a12
TU		 14130 /* Passed in modifier sanity checking. */
14131 switch (mode_cmd->modifier[0]) {
14132 case I915_FORMAT_MOD_Y_TILED:
14133 case I915_FORMAT_MOD_Yf_TILED:
14134 if (INTEL_INFO(dev)->gen < 9) {
14135 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14136 mode_cmd->modifier[0]);
14137 return -EINVAL;
14138 }
14139 case DRM_FORMAT_MOD_NONE:
14140 case I915_FORMAT_MOD_X_TILED:
14141 break;
14142 default:
c0f40428
JB		 14143 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14144 mode_cmd->modifier[0]);
57cd6508 14145 return -EINVAL;
c16ed4be 14146 }
57cd6508 14147
b321803d
DL		 14148 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14149 mode_cmd->pixel_format);
14150 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14151 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14152 mode_cmd->pitches[0], stride_alignment);
57cd6508 14153 return -EINVAL;
c16ed4be 14154 }
57cd6508 14155
b321803d
DL		 14156 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14157 mode_cmd->pixel_format);
a35cdaa0 14158 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14159 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14160 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14161 "tiled" : "linear",
a35cdaa0 14162 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14163 return -EINVAL;
c16ed4be 14164 }
5d7bd705 14165
2a80eada 14166 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14167 mode_cmd->pitches[0] != obj->stride) {
14168 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14169 mode_cmd->pitches[0], obj->stride);
5d7bd705 14170 return -EINVAL;
c16ed4be 14171 }
5d7bd705 14172
57779d06 14173 /* Reject formats not supported by any plane early. */
308e5bcb 14174 switch (mode_cmd->pixel_format) {
57779d06 14175 case DRM_FORMAT_C8:
04b3924d
VS		 14176 case DRM_FORMAT_RGB565:
14177 case DRM_FORMAT_XRGB8888:
14178 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14179 break;
14180 case DRM_FORMAT_XRGB1555:
14181 case DRM_FORMAT_ARGB1555:
c16ed4be 14182 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14183 DRM_DEBUG("unsupported pixel format: %s\n",
14184 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14185 return -EINVAL;
c16ed4be 14186 }
57779d06
VS		 14187 break;
14188 case DRM_FORMAT_XBGR8888:
14189 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 14190 case DRM_FORMAT_XRGB2101010:
14191 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 14192 case DRM_FORMAT_XBGR2101010:
14193 case DRM_FORMAT_ABGR2101010:
c16ed4be 14194 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14195 DRM_DEBUG("unsupported pixel format: %s\n",
14196 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14197 return -EINVAL;
c16ed4be 14198 }
b5626747 14199 break;
04b3924d
VS		 14200 case DRM_FORMAT_YUYV:
14201 case DRM_FORMAT_UYVY:
14202 case DRM_FORMAT_YVYU:
14203 case DRM_FORMAT_VYUY:
c16ed4be 14204 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14205 DRM_DEBUG("unsupported pixel format: %s\n",
14206 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14207 return -EINVAL;
c16ed4be 14208 }
57cd6508
CW		 14209 break;
14210 default:
4ee62c76
VS		 14211 DRM_DEBUG("unsupported pixel format: %s\n",
14212 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14213 return -EINVAL;
14214 }
14215
90f9a336
VS		 14216 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14217 if (mode_cmd->offsets[0] != 0)
14218 return -EINVAL;
14219
ec2c981e 14220 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
SV		 14221 mode_cmd->pixel_format,
14222 mode_cmd->modifier[0]);
53155c0a
SV		 14223 /* FIXME drm helper for size checks (especially planar formats)? */
14224 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14225 return -EINVAL;
14226
c7d73f6a
SV		 14227 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14228 intel_fb->obj = obj;
80075d49 14229 intel_fb->obj->framebuffer_references++;
c7d73f6a 14230
79e53945
JB		 14231 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14232 if (ret) {
14233 DRM_ERROR("framebuffer init failed %d\n", ret);
14234 return ret;
14235 }
14236
79e53945
JB		 14237 return 0;
14238}
14239
79e53945
JB		 14240static struct drm_framebuffer *
14241intel_user_framebuffer_create(struct drm_device *dev,
14242 struct drm_file *filp,
308e5bcb 14243 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14244{
05394f39 14245 struct drm_i915_gem_object *obj;
79e53945 14246
308e5bcb
JB		 14247 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14248 mode_cmd->handles[0]));
c8725226 14249 if (&obj->base == NULL)
cce13ff7 14250 return ERR_PTR(-ENOENT);
79e53945 14251
d2dff872 14252 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14253}
14254
4520f53a 14255#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14256static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
SV		 14257{
14258}
14259#endif
14260
79e53945 14261static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14262 .fb_create = intel_user_framebuffer_create,
0632fef6 14263 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14264 .atomic_check = intel_atomic_check,
14265 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14266};
14267
e70236a8
JB		 14268/* Set up chip specific display functions */
14269static void intel_init_display(struct drm_device *dev)
14270{
14271 struct drm_i915_private *dev_priv = dev->dev_private;
14272
ee9300bb
SV		 14273 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14274 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14275 else if (IS_CHERRYVIEW(dev))
14276 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
SV		 14277 else if (IS_VALLEYVIEW(dev))
14278 dev_priv->display.find_dpll = vlv_find_best_dpll;
14279 else if (IS_PINEVIEW(dev))
14280 dev_priv->display.find_dpll = pnv_find_best_dpll;
14281 else
14282 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14283
bc8d7dff
DL		 14284 if (INTEL_INFO(dev)->gen >= 9) {
14285 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14286 dev_priv->display.get_initial_plane_config =
14287 skylake_get_initial_plane_config;
bc8d7dff
DL		 14288 dev_priv->display.crtc_compute_clock =
14289 haswell_crtc_compute_clock;
14290 dev_priv->display.crtc_enable = haswell_crtc_enable;
14291 dev_priv->display.crtc_disable = haswell_crtc_disable;
14292 dev_priv->display.off = ironlake_crtc_off;
14293 dev_priv->display.update_primary_plane =
14294 skylake_update_primary_plane;
14295 } else if (HAS_DDI(dev)) {
0e8ffe1b 14296 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14297 dev_priv->display.get_initial_plane_config =
14298 ironlake_get_initial_plane_config;
797d0259
ACO		 14299 dev_priv->display.crtc_compute_clock =
14300 haswell_crtc_compute_clock;
4f771f10
PZ		 14301 dev_priv->display.crtc_enable = haswell_crtc_enable;
14302 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14303 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14304 dev_priv->display.update_primary_plane =
14305 ironlake_update_primary_plane;
09b4ddf9 14306 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14307 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14308 dev_priv->display.get_initial_plane_config =
14309 ironlake_get_initial_plane_config;
3fb37703
ACO		 14310 dev_priv->display.crtc_compute_clock =
14311 ironlake_crtc_compute_clock;
76e5a89c
SV		 14312 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14313 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14314 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14315 dev_priv->display.update_primary_plane =
14316 ironlake_update_primary_plane;
89b667f8
JB		 14317 } else if (IS_VALLEYVIEW(dev)) {
14318 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14319 dev_priv->display.get_initial_plane_config =
14320 i9xx_get_initial_plane_config;
d6dfee7a 14321 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14322 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14323 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14324 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14325 dev_priv->display.update_primary_plane =
14326 i9xx_update_primary_plane;
f564048e 14327 } else {
0e8ffe1b 14328 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14329 dev_priv->display.get_initial_plane_config =
14330 i9xx_get_initial_plane_config;
d6dfee7a 14331 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
SV		 14332 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14333 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14334 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14335 dev_priv->display.update_primary_plane =
14336 i9xx_update_primary_plane;
f564048e 14337 }
e70236a8 14338
e70236a8 14339 /* Returns the core display clock speed */
1652d19e
VS		 14340 if (IS_SKYLAKE(dev))
14341 dev_priv->display.get_display_clock_speed =
14342 skylake_get_display_clock_speed;
14343 else if (IS_BROADWELL(dev))
14344 dev_priv->display.get_display_clock_speed =
14345 broadwell_get_display_clock_speed;
14346 else if (IS_HASWELL(dev))
14347 dev_priv->display.get_display_clock_speed =
14348 haswell_get_display_clock_speed;
14349 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14350 dev_priv->display.get_display_clock_speed =
14351 valleyview_get_display_clock_speed;
b37a6434
VS		 14352 else if (IS_GEN5(dev))
14353 dev_priv->display.get_display_clock_speed =
14354 ilk_get_display_clock_speed;
a7c66cd8
VS		 14355 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14356 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14357 dev_priv->display.get_display_clock_speed =
14358 i945_get_display_clock_speed;
14359 else if (IS_I915G(dev))
14360 dev_priv->display.get_display_clock_speed =
14361 i915_get_display_clock_speed;
257a7ffc 14362 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14363 dev_priv->display.get_display_clock_speed =
14364 i9xx_misc_get_display_clock_speed;
257a7ffc
SV		 14365 else if (IS_PINEVIEW(dev))
14366 dev_priv->display.get_display_clock_speed =
14367 pnv_get_display_clock_speed;
e70236a8
JB		 14368 else if (IS_I915GM(dev))
14369 dev_priv->display.get_display_clock_speed =
14370 i915gm_get_display_clock_speed;
14371 else if (IS_I865G(dev))
14372 dev_priv->display.get_display_clock_speed =
14373 i865_get_display_clock_speed;
f0f8a9ce 14374 else if (IS_I85X(dev))
e70236a8
JB		 14375 dev_priv->display.get_display_clock_speed =
14376 i855_get_display_clock_speed;
14377 else /* 852, 830 */
14378 dev_priv->display.get_display_clock_speed =
14379 i830_get_display_clock_speed;
14380
7c10a2b5 14381 if (IS_GEN5(dev)) {
3bb11b53 14382 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14383 } else if (IS_GEN6(dev)) {
14384 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14385 } else if (IS_IVYBRIDGE(dev)) {
14386 /* FIXME: detect B0+ stepping and use auto training */
14387 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14388 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14389 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14390 } else if (IS_VALLEYVIEW(dev)) {
14391 dev_priv->display.modeset_global_resources =
14392 valleyview_modeset_global_resources;
f8437dd1
VK		 14393 } else if (IS_BROXTON(dev)) {
14394 dev_priv->display.modeset_global_resources =
14395 broxton_modeset_global_resources;
e70236a8 14396 }
8c9f3aaf 14397
8c9f3aaf
JB		 14398 switch (INTEL_INFO(dev)->gen) {
14399 case 2:
14400 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14401 break;
14402
14403 case 3:
14404 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14405 break;
14406
14407 case 4:
14408 case 5:
14409 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14410 break;
14411
14412 case 6:
14413 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14414 break;
7c9017e5 14415 case 7:
4e0bbc31 14416 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14417 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14418 break;
830c81db 14419 case 9:
ba343e02
TU		 14420 /* Drop through - unsupported since execlist only. */
14421 default:
14422 /* Default just returns -ENODEV to indicate unsupported */
14423 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14424 }
7bd688cd
JN		 14425
14426 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14427
14428 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14429}
14430
b690e96c
JB		 14431/*
14432 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14433 * resume, or other times. This quirk makes sure that's the case for
14434 * affected systems.
14435 */
0206e353 14436static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14437{
14438 struct drm_i915_private *dev_priv = dev->dev_private;
14439
14440 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14441 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14442}
14443
b6b5d049
VS		 14444static void quirk_pipeb_force(struct drm_device *dev)
14445{
14446 struct drm_i915_private *dev_priv = dev->dev_private;
14447
14448 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14449 DRM_INFO("applying pipe b force quirk\n");
14450}
14451
435793df
KP		 14452/*
14453 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14454 */
14455static void quirk_ssc_force_disable(struct drm_device *dev)
14456{
14457 struct drm_i915_private *dev_priv = dev->dev_private;
14458 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14459 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14460}
14461
4dca20ef 14462/*
5a15ab5b
CE		 14463 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14464 * brightness value
4dca20ef
CE		 14465 */
14466static void quirk_invert_brightness(struct drm_device *dev)
14467{
14468 struct drm_i915_private *dev_priv = dev->dev_private;
14469 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14470 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14471}
14472
9c72cc6f
SD		 14473/* Some VBT's incorrectly indicate no backlight is present */
14474static void quirk_backlight_present(struct drm_device *dev)
14475{
14476 struct drm_i915_private *dev_priv = dev->dev_private;
14477 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14478 DRM_INFO("applying backlight present quirk\n");
14479}
14480
b690e96c
JB		 14481struct intel_quirk {
14482 int device;
14483 int subsystem_vendor;
14484 int subsystem_device;
14485 void (*hook)(struct drm_device *dev);
14486};
14487
5f85f176
EE		 14488/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14489struct intel_dmi_quirk {
14490 void (*hook)(struct drm_device *dev);
14491 const struct dmi_system_id (*dmi_id_list)[];
14492};
14493
14494static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14495{
14496 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14497 return 1;
14498}
14499
14500static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14501 {
14502 .dmi_id_list = &(const struct dmi_system_id[]) {
14503 {
14504 .callback = intel_dmi_reverse_brightness,
14505 .ident = "NCR Corporation",
14506 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14507 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14508 },
14509 },
14510 { } /* terminating entry */
14511 },
14512 .hook = quirk_invert_brightness,
14513 },
14514};
14515
c43b5634 14516static struct intel_quirk intel_quirks[] = {
b690e96c 14517 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 14518 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 14519
b690e96c
JB		 14520 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14521 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14522
b690e96c
JB		 14523 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14524 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14525
5f080c0f
VS		 14526 /* 830 needs to leave pipe A & dpll A up */
14527 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14528
b6b5d049
VS		 14529 /* 830 needs to leave pipe B & dpll B up */
14530 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14531
435793df
KP		 14532 /* Lenovo U160 cannot use SSC on LVDS */
14533 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14534
14535 /* Sony Vaio Y cannot use SSC on LVDS */
14536 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14537
be505f64
AH		 14538 /* Acer Aspire 5734Z must invert backlight brightness */
14539 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14540
14541 /* Acer/eMachines G725 */
14542 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14543
14544 /* Acer/eMachines e725 */
14545 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14546
14547 /* Acer/Packard Bell NCL20 */
14548 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14549
14550 /* Acer Aspire 4736Z */
14551 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14552
14553 /* Acer Aspire 5336 */
14554 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14555
14556 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14557 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14558
dfb3d47b
SD		 14559 /* Acer C720 Chromebook (Core i3 4005U) */
14560 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14561
b2a9601c 14562 /* Apple Macbook 2,1 (Core 2 T7400) */
14563 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14564
d4967d8c
SD		 14565 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14566 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14567
14568 /* HP Chromebook 14 (Celeron 2955U) */
14569 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14570
14571 /* Dell Chromebook 11 */
14572 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14573};
14574
14575static void intel_init_quirks(struct drm_device *dev)
14576{
14577 struct pci_dev *d = dev->pdev;
14578 int i;
14579
14580 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14581 struct intel_quirk *q = &intel_quirks[i];
14582
14583 if (d->device == q->device &&
14584 (d->subsystem_vendor == q->subsystem_vendor ||
14585 q->subsystem_vendor == PCI_ANY_ID) &&
14586 (d->subsystem_device == q->subsystem_device ||
14587 q->subsystem_device == PCI_ANY_ID))
14588 q->hook(dev);
14589 }
5f85f176
EE		 14590 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14591 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14592 intel_dmi_quirks[i].hook(dev);
14593 }
b690e96c
JB		 14594}
14595
9cce37f4
JB		 14596/* Disable the VGA plane that we never use */
14597static void i915_disable_vga(struct drm_device *dev)
14598{
14599 struct drm_i915_private *dev_priv = dev->dev_private;
14600 u8 sr1;
766aa1c4 14601 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14602
2b37c616 14603 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14604 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14605 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14606 sr1 = inb(VGA_SR_DATA);
14607 outb(sr1 | 1<<5, VGA_SR_DATA);
14608 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14609 udelay(300);
14610
01f5a626 14611 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14612 POSTING_READ(vga_reg);
14613}
14614
f817586c
SV		 14615void intel_modeset_init_hw(struct drm_device *dev)
14616{
a8f78b58
ED		 14617 intel_prepare_ddi(dev);
14618
f8bf63fd
VS		 14619 if (IS_VALLEYVIEW(dev))
14620 vlv_update_cdclk(dev);
14621
f817586c
SV		 14622 intel_init_clock_gating(dev);
14623
8090c6b9 14624 intel_enable_gt_powersave(dev);
f817586c
SV		 14625}
14626
79e53945
JB		 14627void intel_modeset_init(struct drm_device *dev)
14628{
652c393a 14629 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14630 int sprite, ret;
8cc87b75 14631 enum pipe pipe;
46f297fb 14632 struct intel_crtc *crtc;
79e53945
JB		 14633
14634 drm_mode_config_init(dev);
14635
14636 dev->mode_config.min_width = 0;
14637 dev->mode_config.min_height = 0;
14638
019d96cb
DA		 14639 dev->mode_config.preferred_depth = 24;
14640 dev->mode_config.prefer_shadow = 1;
14641
25bab385
TU		 14642 dev->mode_config.allow_fb_modifiers = true;
14643
e6ecefaa 14644 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14645
b690e96c
JB		 14646 intel_init_quirks(dev);
14647
1fa61106
ED		 14648 intel_init_pm(dev);
14649
e3c74757
BW		 14650 if (INTEL_INFO(dev)->num_pipes == 0)
14651 return;
14652
e70236a8 14653 intel_init_display(dev);
7c10a2b5 14654 intel_init_audio(dev);
e70236a8 14655
a6c45cf0
CW		 14656 if (IS_GEN2(dev)) {
14657 dev->mode_config.max_width = 2048;
14658 dev->mode_config.max_height = 2048;
14659 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14660 dev->mode_config.max_width = 4096;
14661 dev->mode_config.max_height = 4096;
79e53945 14662 } else {
a6c45cf0
CW		 14663 dev->mode_config.max_width = 8192;
14664 dev->mode_config.max_height = 8192;
79e53945 14665 }
068be561 14666
dc41c154
VS		 14667 if (IS_845G(dev) || IS_I865G(dev)) {
14668 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14669 dev->mode_config.cursor_height = 1023;
14670 } else if (IS_GEN2(dev)) {
068be561
DL		 14671 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14672 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14673 } else {
14674 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14675 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14676 }
14677
5d4545ae 14678 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14679
28c97730 14680 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14681 INTEL_INFO(dev)->num_pipes,
14682 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14683
055e393f 14684 for_each_pipe(dev_priv, pipe) {
8cc87b75 14685 intel_crtc_init(dev, pipe);
3bdcfc0c 14686 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14687 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14688 if (ret)
06da8da2 14689 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14690 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14691 }
79e53945
JB		 14692 }
14693
f42bb70d
JB		 14694 intel_init_dpio(dev);
14695
e72f9fbf 14696 intel_shared_dpll_init(dev);
ee7b9f93 14697
9cce37f4
JB		 14698 /* Just disable it once at startup */
14699 i915_disable_vga(dev);
79e53945 14700 intel_setup_outputs(dev);
11be49eb
CW		 14701
14702 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14703 intel_fbc_disable(dev);
fa9fa083 14704
6e9f798d 14705 drm_modeset_lock_all(dev);
fa9fa083 14706 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14707 drm_modeset_unlock_all(dev);
46f297fb 14708
d3fcc808 14709 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14710 if (!crtc->active)
14711 continue;
14712
46f297fb 14713 /*
46f297fb
JB		 14714 * Note that reserving the BIOS fb up front prevents us
14715 * from stuffing other stolen allocations like the ring
14716 * on top. This prevents some ugliness at boot time, and
14717 * can even allow for smooth boot transitions if the BIOS
14718 * fb is large enough for the active pipe configuration.
14719 */
5724dbd1
DL		 14720 if (dev_priv->display.get_initial_plane_config) {
14721 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14722 &crtc->plane_config);
14723 /*
14724 * If the fb is shared between multiple heads, we'll
14725 * just get the first one.
14726 */
f6936e29 14727 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14728 }
46f297fb 14729 }
2c7111db
CW		 14730}
14731
7fad798e
SV		 14732static void intel_enable_pipe_a(struct drm_device *dev)
14733{
14734 struct intel_connector *connector;
14735 struct drm_connector *crt = NULL;
14736 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14737 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
SV		 14738
14739 /* We can't just switch on the pipe A, we need to set things up with a
14740 * proper mode and output configuration. As a gross hack, enable pipe A
14741 * by enabling the load detect pipe once. */
3a3371ff 14742 for_each_intel_connector(dev, connector) {
7fad798e
SV		 14743 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14744 crt = &connector->base;
14745 break;
14746 }
14747 }
14748
14749 if (!crt)
14750 return;
14751
208bf9fd 14752 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14753 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
SV		 14754}
14755
fa555837
SV		 14756static bool
14757intel_check_plane_mapping(struct intel_crtc *crtc)
14758{
7eb552ae
BW		 14759 struct drm_device *dev = crtc->base.dev;
14760 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
SV		 14761 u32 reg, val;
14762
7eb552ae 14763 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
SV		 14764 return true;
14765
14766 reg = DSPCNTR(!crtc->plane);
14767 val = I915_READ(reg);
14768
14769 if ((val & DISPLAY_PLANE_ENABLE) &&
14770 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14771 return false;
14772
14773 return true;
14774}
14775
24929352
SV		 14776static void intel_sanitize_crtc(struct intel_crtc *crtc)
14777{
14778 struct drm_device *dev = crtc->base.dev;
14779 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14780 u32 reg;
24929352 14781
24929352 14782 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14783 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
SV		 14784 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14785
d3eaf884 14786 /* restore vblank interrupts to correct state */
9625604c 14787 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14788 if (crtc->active) {
14789 update_scanline_offset(crtc);
9625604c
SV		 14790 drm_crtc_vblank_on(&crtc->base);
14791 }
d3eaf884 14792
24929352 14793 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
SV		 14794 * disable the crtc (and hence change the state) if it is wrong. Note
14795 * that gen4+ has a fixed plane -> pipe mapping. */
14796 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
SV		 14797 struct intel_connector *connector;
14798 bool plane;
14799
24929352
SV		 14800 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14801 crtc->base.base.id);
14802
14803 /* Pipe has the wrong plane attached and the plane is active.
14804 * Temporarily change the plane mapping and disable everything
14805 * ... */
14806 plane = crtc->plane;
b70709a6 14807 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14808 crtc->plane = !plane;
ce22dba9 14809 intel_crtc_disable_planes(&crtc->base);
24929352
SV		 14810 dev_priv->display.crtc_disable(&crtc->base);
14811 crtc->plane = plane;
14812
14813 /* ... and break all links. */
3a3371ff 14814 for_each_intel_connector(dev, connector) {
24929352
SV		 14815 if (connector->encoder->base.crtc != &crtc->base)
14816 continue;
14817
7f1950fb
EE		 14818 connector->base.dpms = DRM_MODE_DPMS_OFF;
14819 connector->base.encoder = NULL;
24929352 14820 }
7f1950fb
EE		 14821 /* multiple connectors may have the same encoder:
14822 * handle them and break crtc link separately */
3a3371ff 14823 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14824 if (connector->encoder->base.crtc == &crtc->base) {
14825 connector->encoder->base.crtc = NULL;
14826 connector->encoder->connectors_active = false;
14827 }
24929352
SV		 14828
14829 WARN_ON(crtc->active);
83d65738 14830 crtc->base.state->enable = false;
24929352
SV		 14831 crtc->base.enabled = false;
14832 }
24929352 14833
7fad798e
SV		 14834 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14835 crtc->pipe == PIPE_A && !crtc->active) {
14836 /* BIOS forgot to enable pipe A, this mostly happens after
14837 * resume. Force-enable the pipe to fix this, the update_dpms
14838 * call below we restore the pipe to the right state, but leave
14839 * the required bits on. */
14840 intel_enable_pipe_a(dev);
14841 }
14842
24929352
SV		 14843 /* Adjust the state of the output pipe according to whether we
14844 * have active connectors/encoders. */
14845 intel_crtc_update_dpms(&crtc->base);
14846
83d65738 14847 if (crtc->active != crtc->base.state->enable) {
24929352
SV		 14848 struct intel_encoder *encoder;
14849
14850 /* This can happen either due to bugs in the get_hw_state
14851 * functions or because the pipe is force-enabled due to the
14852 * pipe A quirk. */
14853 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14854 crtc->base.base.id,
83d65738 14855 crtc->base.state->enable ? "enabled" : "disabled",
24929352
SV		 14856 crtc->active ? "enabled" : "disabled");
14857
83d65738 14858 crtc->base.state->enable = crtc->active;
24929352
SV		 14859 crtc->base.enabled = crtc->active;
14860
14861 /* Because we only establish the connector -> encoder ->
14862 * crtc links if something is active, this means the
14863 * crtc is now deactivated. Break the links. connector
14864 * -> encoder links are only establish when things are
14865 * actually up, hence no need to break them. */
14866 WARN_ON(crtc->active);
14867
14868 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14869 WARN_ON(encoder->connectors_active);
14870 encoder->base.crtc = NULL;
14871 }
14872 }
c5ab3bc0 14873
a3ed6aad 14874 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
SV		 14875 /*
14876 * We start out with underrun reporting disabled to avoid races.
14877 * For correct bookkeeping mark this on active crtcs.
14878 *
c5ab3bc0
SV		 14879 * Also on gmch platforms we dont have any hardware bits to
14880 * disable the underrun reporting. Which means we need to start
14881 * out with underrun reporting disabled also on inactive pipes,
14882 * since otherwise we'll complain about the garbage we read when
14883 * e.g. coming up after runtime pm.
14884 *
4cc31489
SV		 14885 * No protection against concurrent access is required - at
14886 * worst a fifo underrun happens which also sets this to false.
14887 */
14888 crtc->cpu_fifo_underrun_disabled = true;
14889 crtc->pch_fifo_underrun_disabled = true;
14890 }
24929352
SV		 14891}
14892
14893static void intel_sanitize_encoder(struct intel_encoder *encoder)
14894{
14895 struct intel_connector *connector;
14896 struct drm_device *dev = encoder->base.dev;
14897
14898 /* We need to check both for a crtc link (meaning that the
14899 * encoder is active and trying to read from a pipe) and the
14900 * pipe itself being active. */
14901 bool has_active_crtc = encoder->base.crtc &&
14902 to_intel_crtc(encoder->base.crtc)->active;
14903
14904 if (encoder->connectors_active && !has_active_crtc) {
14905 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14906 encoder->base.base.id,
8e329a03 14907 encoder->base.name);
24929352
SV		 14908
14909 /* Connector is active, but has no active pipe. This is
14910 * fallout from our resume register restoring. Disable
14911 * the encoder manually again. */
14912 if (encoder->base.crtc) {
14913 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14914 encoder->base.base.id,
8e329a03 14915 encoder->base.name);
24929352 14916 encoder->disable(encoder);
a62d1497
VS		 14917 if (encoder->post_disable)
14918 encoder->post_disable(encoder);
24929352 14919 }
7f1950fb
EE		 14920 encoder->base.crtc = NULL;
14921 encoder->connectors_active = false;
24929352
SV		 14922
14923 /* Inconsistent output/port/pipe state happens presumably due to
14924 * a bug in one of the get_hw_state functions. Or someplace else
14925 * in our code, like the register restore mess on resume. Clamp
14926 * things to off as a safer default. */
3a3371ff 14927 for_each_intel_connector(dev, connector) {
24929352
SV		 14928 if (connector->encoder != encoder)
14929 continue;
7f1950fb
EE		 14930 connector->base.dpms = DRM_MODE_DPMS_OFF;
14931 connector->base.encoder = NULL;
24929352
SV		 14932 }
14933 }
14934 /* Enabled encoders without active connectors will be fixed in
14935 * the crtc fixup. */
14936}
14937
04098753 14938void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14939{
14940 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14941 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14942
04098753
ID		 14943 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14944 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14945 i915_disable_vga(dev);
14946 }
14947}
14948
14949void i915_redisable_vga(struct drm_device *dev)
14950{
14951 struct drm_i915_private *dev_priv = dev->dev_private;
14952
8dc8a27c
PZ		 14953 /* This function can be called both from intel_modeset_setup_hw_state or
14954 * at a very early point in our resume sequence, where the power well
14955 * structures are not yet restored. Since this function is at a very
14956 * paranoid "someone might have enabled VGA while we were not looking"
14957 * level, just check if the power well is enabled instead of trying to
14958 * follow the "don't touch the power well if we don't need it" policy
14959 * the rest of the driver uses. */
f458ebbc 14960 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14961 return;
14962
04098753 14963 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14964}
14965
98ec7739
VS		 14966static bool primary_get_hw_state(struct intel_crtc *crtc)
14967{
14968 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14969
14970 if (!crtc->active)
14971 return false;
14972
14973 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14974}
14975
30e984df 14976static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
SV		 14977{
14978 struct drm_i915_private *dev_priv = dev->dev_private;
14979 enum pipe pipe;
24929352
SV		 14980 struct intel_crtc *crtc;
14981 struct intel_encoder *encoder;
14982 struct intel_connector *connector;
5358901f 14983 int i;
24929352 14984
d3fcc808 14985 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 14986 struct drm_plane *primary = crtc->base.primary;
14987 struct intel_plane_state *plane_state;
14988
6e3c9717 14989 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14990
6e3c9717 14991 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14992
0e8ffe1b 14993 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14994 crtc->config);
24929352 14995
83d65738 14996 crtc->base.state->enable = crtc->active;
24929352 14997 crtc->base.enabled = crtc->active;
b70709a6
ML		 14998
14999 plane_state = to_intel_plane_state(primary->state);
15000 plane_state->visible = primary_get_hw_state(crtc);
24929352
SV		 15001
15002 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15003 crtc->base.base.id,
15004 crtc->active ? "enabled" : "disabled");
15005 }
15006
5358901f
SV		 15007 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15008 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15009
3e369b76
ACO		 15010 pll->on = pll->get_hw_state(dev_priv, pll,
15011 &pll->config.hw_state);
5358901f 15012 pll->active = 0;
3e369b76 15013 pll->config.crtc_mask = 0;
d3fcc808 15014 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15015 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15016 pll->active++;
3e369b76 15017 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15018 }
5358901f 15019 }
5358901f 15020
1e6f2ddc 15021 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15022 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15023
3e369b76 15024 if (pll->config.crtc_mask)
bd2bb1b9 15025 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
SV		 15026 }
15027
b2784e15 15028 for_each_intel_encoder(dev, encoder) {
24929352
SV		 15029 pipe = 0;
15030
15031 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15032 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15033 encoder->base.crtc = &crtc->base;
6e3c9717 15034 encoder->get_config(encoder, crtc->config);
24929352
SV		 15035 } else {
15036 encoder->base.crtc = NULL;
15037 }
15038
15039 encoder->connectors_active = false;
6f2bcceb 15040 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15041 encoder->base.base.id,
8e329a03 15042 encoder->base.name,
24929352 15043 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15044 pipe_name(pipe));
24929352
SV		 15045 }
15046
3a3371ff 15047 for_each_intel_connector(dev, connector) {
24929352
SV		 15048 if (connector->get_hw_state(connector)) {
15049 connector->base.dpms = DRM_MODE_DPMS_ON;
15050 connector->encoder->connectors_active = true;
15051 connector->base.encoder = &connector->encoder->base;
15052 } else {
15053 connector->base.dpms = DRM_MODE_DPMS_OFF;
15054 connector->base.encoder = NULL;
15055 }
15056 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15057 connector->base.base.id,
c23cc417 15058 connector->base.name,
24929352
SV		 15059 connector->base.encoder ? "enabled" : "disabled");
15060 }
30e984df
SV		 15061}
15062
15063/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15064 * and i915 state tracking structures. */
15065void intel_modeset_setup_hw_state(struct drm_device *dev,
15066 bool force_restore)
15067{
15068 struct drm_i915_private *dev_priv = dev->dev_private;
15069 enum pipe pipe;
30e984df
SV		 15070 struct intel_crtc *crtc;
15071 struct intel_encoder *encoder;
35c95375 15072 int i;
30e984df
SV		 15073
15074 intel_modeset_readout_hw_state(dev);
24929352 15075
babea61d
JB		 15076 /*
15077 * Now that we have the config, copy it to each CRTC struct
15078 * Note that this could go away if we move to using crtc_config
15079 * checking everywhere.
15080 */
d3fcc808 15081 for_each_intel_crtc(dev, crtc) {
d330a953 15082 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15083 intel_mode_from_pipe_config(&crtc->base.mode,
15084 crtc->config);
babea61d
JB		 15085 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15086 crtc->base.base.id);
15087 drm_mode_debug_printmodeline(&crtc->base.mode);
15088 }
15089 }
15090
24929352 15091 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15092 for_each_intel_encoder(dev, encoder) {
24929352
SV		 15093 intel_sanitize_encoder(encoder);
15094 }
15095
055e393f 15096 for_each_pipe(dev_priv, pipe) {
24929352
SV		 15097 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15098 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15099 intel_dump_pipe_config(crtc, crtc->config,
15100 "[setup_hw_state]");
24929352 15101 }
9a935856 15102
d29b2f9d
ACO		 15103 intel_modeset_update_connector_atomic_state(dev);
15104
35c95375
SV		 15105 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15106 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15107
15108 if (!pll->on || pll->active)
15109 continue;
15110
15111 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15112
15113 pll->disable(dev_priv, pll);
15114 pll->on = false;
15115 }
15116
3078999f
PB		 15117 if (IS_GEN9(dev))
15118 skl_wm_get_hw_state(dev);
15119 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15120 ilk_wm_get_hw_state(dev);
15121
45e2b5f6 15122 if (force_restore) {
7d0bc1ea
VS		 15123 i915_redisable_vga(dev);
15124
f30da187
SV		 15125 /*
15126 * We need to use raw interfaces for restoring state to avoid
15127 * checking (bogus) intermediate states.
15128 */
055e393f 15129 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15130 struct drm_crtc *crtc =
15131 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15132
83a57153 15133 intel_crtc_restore_mode(crtc);
45e2b5f6
SV		 15134 }
15135 } else {
15136 intel_modeset_update_staged_output_state(dev);
15137 }
8af6cf88
SV		 15138
15139 intel_modeset_check_state(dev);
2c7111db
CW		 15140}
15141
15142void intel_modeset_gem_init(struct drm_device *dev)
15143{
92122789 15144 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15145 struct drm_crtc *c;
2ff8fde1 15146 struct drm_i915_gem_object *obj;
e0d6149b 15147 int ret;
484b41dd 15148
ae48434c
ID		 15149 mutex_lock(&dev->struct_mutex);
15150 intel_init_gt_powersave(dev);
15151 mutex_unlock(&dev->struct_mutex);
15152
92122789
JB		 15153 /*
15154 * There may be no VBT; and if the BIOS enabled SSC we can
15155 * just keep using it to avoid unnecessary flicker. Whereas if the
15156 * BIOS isn't using it, don't assume it will work even if the VBT
15157 * indicates as much.
15158 */
15159 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15160 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15161 DREF_SSC1_ENABLE);
15162
1833b134 15163 intel_modeset_init_hw(dev);
02e792fb
SV		 15164
15165 intel_setup_overlay(dev);
484b41dd
JB		 15166
15167 /*
15168 * Make sure any fbs we allocated at startup are properly
15169 * pinned & fenced. When we do the allocation it's too early
15170 * for this.
15171 */
70e1e0ec 15172 for_each_crtc(dev, c) {
2ff8fde1
MR		 15173 obj = intel_fb_obj(c->primary->fb);
15174 if (obj == NULL)
484b41dd
JB		 15175 continue;
15176
e0d6149b
TU		 15177 mutex_lock(&dev->struct_mutex);
15178 ret = intel_pin_and_fence_fb_obj(c->primary,
15179 c->primary->fb,
15180 c->primary->state,
15181 NULL);
15182 mutex_unlock(&dev->struct_mutex);
15183 if (ret) {
484b41dd
JB		 15184 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15185 to_intel_crtc(c)->pipe);
66e514c1
DA		 15186 drm_framebuffer_unreference(c->primary->fb);
15187 c->primary->fb = NULL;
afd65eb4 15188 update_state_fb(c->primary);
484b41dd
JB		 15189 }
15190 }
0962c3c9
VS		 15191
15192 intel_backlight_register(dev);
79e53945
JB		 15193}
15194
4932e2c3
ID		 15195void intel_connector_unregister(struct intel_connector *intel_connector)
15196{
15197 struct drm_connector *connector = &intel_connector->base;
15198
15199 intel_panel_destroy_backlight(connector);
34ea3d38 15200 drm_connector_unregister(connector);
4932e2c3
ID		 15201}
15202
79e53945
JB		 15203void intel_modeset_cleanup(struct drm_device *dev)
15204{
652c393a 15205 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15206 struct drm_connector *connector;
652c393a 15207
2eb5252e
ID		 15208 intel_disable_gt_powersave(dev);
15209
0962c3c9
VS		 15210 intel_backlight_unregister(dev);
15211
fd0c0642
SV		 15212 /*
15213 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15214 * Too much stuff here (turning of connectors, ...) would
fd0c0642
SV		 15215 * experience fancy races otherwise.
15216 */
2aeb7d3a 15217 intel_irq_uninstall(dev_priv);
eb21b92b 15218
fd0c0642
SV		 15219 /*
15220 * Due to the hpd irq storm handling the hotplug work can re-arm the
15221 * poll handlers. Hence disable polling after hpd handling is shut down.
15222 */
f87ea761 15223 drm_kms_helper_poll_fini(dev);
fd0c0642 15224
652c393a
JB		 15225 mutex_lock(&dev->struct_mutex);
15226
723bfd70
JB		 15227 intel_unregister_dsm_handler();
15228
7ff0ebcc 15229 intel_fbc_disable(dev);
e70236a8 15230
69341a5e
KH		 15231 mutex_unlock(&dev->struct_mutex);
15232
1630fe75
CW		 15233 /* flush any delayed tasks or pending work */
15234 flush_scheduled_work();
15235
db31af1d
JN		 15236 /* destroy the backlight and sysfs files before encoders/connectors */
15237 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15238 struct intel_connector *intel_connector;
15239
15240 intel_connector = to_intel_connector(connector);
15241 intel_connector->unregister(intel_connector);
db31af1d 15242 }
d9255d57 15243
79e53945 15244 drm_mode_config_cleanup(dev);
4d7bb011
SV		 15245
15246 intel_cleanup_overlay(dev);
ae48434c
ID		 15247
15248 mutex_lock(&dev->struct_mutex);
15249 intel_cleanup_gt_powersave(dev);
15250 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15251}
15252
f1c79df3
ZW		 15253/*
15254 * Return which encoder is currently attached for connector.
15255 */
df0e9248 15256struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15257{
df0e9248
CW		 15258 return &intel_attached_encoder(connector)->base;
15259}
f1c79df3 15260
df0e9248
CW		 15261void intel_connector_attach_encoder(struct intel_connector *connector,
15262 struct intel_encoder *encoder)
15263{
15264 connector->encoder = encoder;
15265 drm_mode_connector_attach_encoder(&connector->base,
15266 &encoder->base);
79e53945 15267}
28d52043
DA		 15268
15269/*
15270 * set vga decode state - true == enable VGA decode
15271 */
15272int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15273{
15274 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15275 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15276 u16 gmch_ctrl;
15277
75fa041d
CW		 15278 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15279 DRM_ERROR("failed to read control word\n");
15280 return -EIO;
15281 }
15282
c0cc8a55
CW		 15283 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15284 return 0;
15285
28d52043
DA		 15286 if (state)
15287 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15288 else
15289 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15290
15291 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15292 DRM_ERROR("failed to write control word\n");
15293 return -EIO;
15294 }
15295
28d52043
DA		 15296 return 0;
15297}
c4a1d9e4 15298
c4a1d9e4 15299struct intel_display_error_state {
ff57f1b0
PZ		 15300
15301 u32 power_well_driver;
15302
63b66e5b
CW		 15303 int num_transcoders;
15304
c4a1d9e4
CW		 15305 struct intel_cursor_error_state {
15306 u32 control;
15307 u32 position;
15308 u32 base;
15309 u32 size;
52331309 15310 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15311
15312 struct intel_pipe_error_state {
ddf9c536 15313 bool power_domain_on;
c4a1d9e4 15314 u32 source;
f301b1e1 15315 u32 stat;
52331309 15316 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15317
15318 struct intel_plane_error_state {
15319 u32 control;
15320 u32 stride;
15321 u32 size;
15322 u32 pos;
15323 u32 addr;
15324 u32 surface;
15325 u32 tile_offset;
52331309 15326 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15327
15328 struct intel_transcoder_error_state {
ddf9c536 15329 bool power_domain_on;
63b66e5b
CW		 15330 enum transcoder cpu_transcoder;
15331
15332 u32 conf;
15333
15334 u32 htotal;
15335 u32 hblank;
15336 u32 hsync;
15337 u32 vtotal;
15338 u32 vblank;
15339 u32 vsync;
15340 } transcoder[4];
c4a1d9e4
CW		 15341};
15342
15343struct intel_display_error_state *
15344intel_display_capture_error_state(struct drm_device *dev)
15345{
fbee40df 15346 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15347 struct intel_display_error_state *error;
63b66e5b
CW		 15348 int transcoders[] = {
15349 TRANSCODER_A,
15350 TRANSCODER_B,
15351 TRANSCODER_C,
15352 TRANSCODER_EDP,
15353 };
c4a1d9e4
CW		 15354 int i;
15355
63b66e5b
CW		 15356 if (INTEL_INFO(dev)->num_pipes == 0)
15357 return NULL;
15358
9d1cb914 15359 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15360 if (error == NULL)
15361 return NULL;
15362
190be112 15363 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15364 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15365
055e393f 15366 for_each_pipe(dev_priv, i) {
ddf9c536 15367 error->pipe[i].power_domain_on =
f458ebbc
SV		 15368 __intel_display_power_is_enabled(dev_priv,
15369 POWER_DOMAIN_PIPE(i));
ddf9c536 15370 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15371 continue;
15372
5efb3e28
VS		 15373 error->cursor[i].control = I915_READ(CURCNTR(i));
15374 error->cursor[i].position = I915_READ(CURPOS(i));
15375 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15376
15377 error->plane[i].control = I915_READ(DSPCNTR(i));
15378 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15379 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15380 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15381 error->plane[i].pos = I915_READ(DSPPOS(i));
15382 }
ca291363
PZ		 15383 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15384 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15385 if (INTEL_INFO(dev)->gen >= 4) {
15386 error->plane[i].surface = I915_READ(DSPSURF(i));
15387 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15388 }
15389
c4a1d9e4 15390 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15391
3abfce77 15392 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15393 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15394 }
15395
15396 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15397 if (HAS_DDI(dev_priv->dev))
15398 error->num_transcoders++; /* Account for eDP. */
15399
15400 for (i = 0; i < error->num_transcoders; i++) {
15401 enum transcoder cpu_transcoder = transcoders[i];
15402
ddf9c536 15403 error->transcoder[i].power_domain_on =
f458ebbc 15404 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15405 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15406 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15407 continue;
15408
63b66e5b
CW		 15409 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15410
15411 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15412 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15413 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15414 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15415 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15416 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15417 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15418 }
15419
15420 return error;
15421}
15422
edc3d884
MK		 15423#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15424
c4a1d9e4 15425void
edc3d884 15426intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15427 struct drm_device *dev,
15428 struct intel_display_error_state *error)
15429{
055e393f 15430 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15431 int i;
15432
63b66e5b
CW		 15433 if (!error)
15434 return;
15435
edc3d884 15436 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15437 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15438 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15439 error->power_well_driver);
055e393f 15440 for_each_pipe(dev_priv, i) {
edc3d884 15441 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15442 err_printf(m, " Power: %s\n",
15443 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15444 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15445 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15446
15447 err_printf(m, "Plane [%d]:\n", i);
15448 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15449 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15450 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15451 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15452 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15453 }
4b71a570 15454 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15455 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15456 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15457 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15458 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15459 }
15460
edc3d884
MK		 15461 err_printf(m, "Cursor [%d]:\n", i);
15462 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15463 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15464 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15465 }
63b66e5b
CW		 15466
15467 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15468 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15469 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15470 err_printf(m, " Power: %s\n",
15471 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15472 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15473 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15474 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15475 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15476 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15477 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15478 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15479 }
c4a1d9e4 15480}
e2fcdaa9
VS		 15481
15482void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15483{
15484 struct intel_crtc *crtc;
15485
15486 for_each_intel_crtc(dev, crtc) {
15487 struct intel_unpin_work *work;
e2fcdaa9 15488
5e2d7afc 15489 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15490
15491 work = crtc->unpin_work;
15492
15493 if (work && work->event &&
15494 work->event->base.file_priv == file) {
15495 kfree(work->event);
15496 work->event = NULL;
15497 }
15498
5e2d7afc 15499 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15500 }
15501}
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