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drm/i915: add comment about pch pll enabling rules
[linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <[email protected]>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
SV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
SV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
SV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
SV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
SV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
SV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
SV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a
JB		 1581/**
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
ee7b9f93 1589static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
040484af
JB		 1673static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
59c859d6
ED		 1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
040484af
JB		 1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
5f7f726d 1698 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
5f7f726d 1706 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1707 }
5f7f726d
PZ		 1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
040484af
JB		 1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722}
1723
1724static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726{
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
291906f1
JB		 1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
040484af
JB		 1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1744}
1745
b24e7179 1746/**
309cfea8 1747 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
040484af 1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
040484af
JB		 1760static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
b24e7179 1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
b24e7179 1783
702e7a56 1784 reg = PIPECONF(cpu_transcoder);
b24e7179 1785 val = I915_READ(reg);
00d70b15
CW		 1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791}
1792
1793/**
309cfea8 1794 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807{
702e7a56
PZ		 1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
b24e7179
JB		 1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
702e7a56 1823 reg = PIPECONF(cpu_transcoder);
b24e7179 1824 val = I915_READ(reg);
00d70b15
CW		 1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830}
1831
d74362c9
KP		 1832/*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
6f1d69b0 1836void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1837 enum plane plane)
1838{
1839 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841}
1842
b24e7179
JB		 1843/**
1844 * intel_enable_plane - enable a display plane on a given pipe
1845 * @dev_priv: i915 private structure
1846 * @plane: plane to enable
1847 * @pipe: pipe being fed
1848 *
1849 * Enable @plane on @pipe, making sure that @pipe is running first.
1850 */
1851static void intel_enable_plane(struct drm_i915_private *dev_priv,
1852 enum plane plane, enum pipe pipe)
1853{
1854 int reg;
1855 u32 val;
1856
1857 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1858 assert_pipe_enabled(dev_priv, pipe);
1859
1860 reg = DSPCNTR(plane);
1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & DISPLAY_PLANE_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1866 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1867 intel_wait_for_vblank(dev_priv->dev, pipe);
1868}
1869
b24e7179
JB		 1870/**
1871 * intel_disable_plane - disable a display plane
1872 * @dev_priv: i915 private structure
1873 * @plane: plane to disable
1874 * @pipe: pipe consuming the data
1875 *
1876 * Disable @plane; should be an independent operation.
1877 */
1878static void intel_disable_plane(struct drm_i915_private *dev_priv,
1879 enum plane plane, enum pipe pipe)
1880{
1881 int reg;
1882 u32 val;
1883
1884 reg = DSPCNTR(plane);
1885 val = I915_READ(reg);
00d70b15
CW		 1886 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1887 return;
1888
1889 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1890 intel_flush_display_plane(dev_priv, plane);
1891 intel_wait_for_vblank(dev_priv->dev, pipe);
1892}
1893
127bd2ac 1894int
48b956c5 1895intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1896 struct drm_i915_gem_object *obj,
919926ae 1897 struct intel_ring_buffer *pipelined)
6b95a207 1898{
ce453d81 1899 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1900 u32 alignment;
1901 int ret;
1902
05394f39 1903 switch (obj->tiling_mode) {
6b95a207 1904 case I915_TILING_NONE:
534843da
CW		 1905 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1906 alignment = 128 * 1024;
a6c45cf0 1907 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1908 alignment = 4 * 1024;
1909 else
1910 alignment = 64 * 1024;
6b95a207
KH		 1911 break;
1912 case I915_TILING_X:
1913 /* pin() will align the object as required by fence */
1914 alignment = 0;
1915 break;
1916 case I915_TILING_Y:
1917 /* FIXME: Is this true? */
1918 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1919 return -EINVAL;
1920 default:
1921 BUG();
1922 }
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
SV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
1958static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1959 unsigned int bpp,
1960 unsigned int pitch)
1961{
1962 int tile_rows, tiles;
1963
1964 tile_rows = *y / 8;
1965 *y %= 8;
1966 tiles = *x / (512/bpp);
1967 *x %= 512/bpp;
1968
1969 return tile_rows * pitch * 8 + tiles * 4096;
1970}
1971
17638cd6
JB		 1972static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1973 int x, int y)
81255565
JB		 1974{
1975 struct drm_device *dev = crtc->dev;
1976 struct drm_i915_private *dev_priv = dev->dev_private;
1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978 struct intel_framebuffer *intel_fb;
05394f39 1979 struct drm_i915_gem_object *obj;
81255565 1980 int plane = intel_crtc->plane;
e506a0c6 1981 unsigned long linear_offset;
81255565 1982 u32 dspcntr;
5eddb70b 1983 u32 reg;
81255565
JB		 1984
1985 switch (plane) {
1986 case 0:
1987 case 1:
1988 break;
1989 default:
1990 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1991 return -EINVAL;
1992 }
1993
1994 intel_fb = to_intel_framebuffer(fb);
1995 obj = intel_fb->obj;
81255565 1996
5eddb70b
CW		 1997 reg = DSPCNTR(plane);
1998 dspcntr = I915_READ(reg);
81255565
JB		 1999 /* Mask out pixel format bits in case we change it */
2000 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2001 switch (fb->bits_per_pixel) {
2002 case 8:
2003 dspcntr |= DISPPLANE_8BPP;
2004 break;
2005 case 16:
2006 if (fb->depth == 15)
2007 dspcntr |= DISPPLANE_15_16BPP;
2008 else
2009 dspcntr |= DISPPLANE_16BPP;
2010 break;
2011 case 24:
2012 case 32:
2013 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2014 break;
2015 default:
17638cd6 2016 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2017 return -EINVAL;
2018 }
a6c45cf0 2019 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2020 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2021 dspcntr |= DISPPLANE_TILED;
2022 else
2023 dspcntr &= ~DISPPLANE_TILED;
2024 }
2025
5eddb70b 2026 I915_WRITE(reg, dspcntr);
81255565 2027
e506a0c6 2028 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2029
c2c75131
SV		 2030 if (INTEL_INFO(dev)->gen >= 4) {
2031 intel_crtc->dspaddr_offset =
2032 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2033 fb->bits_per_pixel / 8,
2034 fb->pitches[0]);
2035 linear_offset -= intel_crtc->dspaddr_offset;
2036 } else {
e506a0c6 2037 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2038 }
e506a0c6
SV		 2039
2040 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2041 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2042 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
SV		 2044 I915_MODIFY_DISPBASE(DSPSURF(plane),
2045 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2046 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2047 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2048 } else
e506a0c6 2049 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2050 POSTING_READ(reg);
81255565 2051
17638cd6
JB		 2052 return 0;
2053}
2054
2055static int ironlake_update_plane(struct drm_crtc *crtc,
2056 struct drm_framebuffer *fb, int x, int y)
2057{
2058 struct drm_device *dev = crtc->dev;
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061 struct intel_framebuffer *intel_fb;
2062 struct drm_i915_gem_object *obj;
2063 int plane = intel_crtc->plane;
e506a0c6 2064 unsigned long linear_offset;
17638cd6
JB		 2065 u32 dspcntr;
2066 u32 reg;
2067
2068 switch (plane) {
2069 case 0:
2070 case 1:
27f8227b 2071 case 2:
17638cd6
JB		 2072 break;
2073 default:
2074 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2075 return -EINVAL;
2076 }
2077
2078 intel_fb = to_intel_framebuffer(fb);
2079 obj = intel_fb->obj;
2080
2081 reg = DSPCNTR(plane);
2082 dspcntr = I915_READ(reg);
2083 /* Mask out pixel format bits in case we change it */
2084 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2085 switch (fb->bits_per_pixel) {
2086 case 8:
2087 dspcntr |= DISPPLANE_8BPP;
2088 break;
2089 case 16:
2090 if (fb->depth != 16)
2091 return -EINVAL;
2092
2093 dspcntr |= DISPPLANE_16BPP;
2094 break;
2095 case 24:
2096 case 32:
2097 if (fb->depth == 24)
2098 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2099 else if (fb->depth == 30)
2100 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2101 else
2102 return -EINVAL;
2103 break;
2104 default:
2105 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2106 return -EINVAL;
2107 }
2108
2109 if (obj->tiling_mode != I915_TILING_NONE)
2110 dspcntr |= DISPPLANE_TILED;
2111 else
2112 dspcntr &= ~DISPPLANE_TILED;
2113
2114 /* must disable */
2115 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2116
2117 I915_WRITE(reg, dspcntr);
2118
e506a0c6 2119 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
SV		 2120 intel_crtc->dspaddr_offset =
2121 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2122 fb->bits_per_pixel / 8,
2123 fb->pitches[0]);
2124 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2125
e506a0c6
SV		 2126 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2127 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2128 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
SV		 2129 I915_MODIFY_DISPBASE(DSPSURF(plane),
2130 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2131 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2132 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2133 POSTING_READ(reg);
2134
2135 return 0;
2136}
2137
2138/* Assume fb object is pinned & idle & fenced and just update base pointers */
2139static int
2140intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2141 int x, int y, enum mode_set_atomic state)
2142{
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2145
6b8e6ed0
CW		 2146 if (dev_priv->display.disable_fbc)
2147 dev_priv->display.disable_fbc(dev);
3dec0095 2148 intel_increase_pllclock(crtc);
81255565 2149
6b8e6ed0 2150 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2151}
2152
14667a4b
CW		 2153static int
2154intel_finish_fb(struct drm_framebuffer *old_fb)
2155{
2156 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2157 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2158 bool was_interruptible = dev_priv->mm.interruptible;
2159 int ret;
2160
2161 wait_event(dev_priv->pending_flip_queue,
2162 atomic_read(&dev_priv->mm.wedged) ||
2163 atomic_read(&obj->pending_flip) == 0);
2164
2165 /* Big Hammer, we also need to ensure that any pending
2166 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2167 * current scanout is retired before unpinning the old
2168 * framebuffer.
2169 *
2170 * This should only fail upon a hung GPU, in which case we
2171 * can safely continue.
2172 */
2173 dev_priv->mm.interruptible = false;
2174 ret = i915_gem_object_finish_gpu(obj);
2175 dev_priv->mm.interruptible = was_interruptible;
2176
2177 return ret;
2178}
2179
5c3b82e2 2180static int
3c4fdcfb 2181intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2182 struct drm_framebuffer *fb)
79e53945
JB		 2183{
2184 struct drm_device *dev = crtc->dev;
6b8e6ed0 2185 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2186 struct drm_i915_master_private *master_priv;
2187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2188 struct drm_framebuffer *old_fb;
5c3b82e2 2189 int ret;
79e53945
JB		 2190
2191 /* no fb bound */
94352cf9 2192 if (!fb) {
a5071c2f 2193 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2194 return 0;
2195 }
2196
5826eca5
ED		 2197 if(intel_crtc->plane > dev_priv->num_pipe) {
2198 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2199 intel_crtc->plane,
2200 dev_priv->num_pipe);
5c3b82e2 2201 return -EINVAL;
79e53945
JB		 2202 }
2203
5c3b82e2 2204 mutex_lock(&dev->struct_mutex);
265db958 2205 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2206 to_intel_framebuffer(fb)->obj,
919926ae 2207 NULL);
5c3b82e2
CW		 2208 if (ret != 0) {
2209 mutex_unlock(&dev->struct_mutex);
a5071c2f 2210 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2211 return ret;
2212 }
79e53945 2213
94352cf9
SV		 2214 if (crtc->fb)
2215 intel_finish_fb(crtc->fb);
265db958 2216
94352cf9 2217 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2218 if (ret) {
94352cf9 2219 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2220 mutex_unlock(&dev->struct_mutex);
a5071c2f 2221 DRM_ERROR("failed to update base address\n");
4e6cfefc 2222 return ret;
79e53945 2223 }
3c4fdcfb 2224
94352cf9
SV		 2225 old_fb = crtc->fb;
2226 crtc->fb = fb;
6c4c86f5
SV		 2227 crtc->x = x;
2228 crtc->y = y;
94352cf9 2229
b7f1de28
CW		 2230 if (old_fb) {
2231 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2232 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2233 }
652c393a 2234
6b8e6ed0 2235 intel_update_fbc(dev);
5c3b82e2 2236 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2237
2238 if (!dev->primary->master)
5c3b82e2 2239 return 0;
79e53945
JB		 2240
2241 master_priv = dev->primary->master->driver_priv;
2242 if (!master_priv->sarea_priv)
5c3b82e2 2243 return 0;
79e53945 2244
265db958 2245 if (intel_crtc->pipe) {
79e53945
JB		 2246 master_priv->sarea_priv->pipeB_x = x;
2247 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2248 } else {
2249 master_priv->sarea_priv->pipeA_x = x;
2250 master_priv->sarea_priv->pipeA_y = y;
79e53945 2251 }
5c3b82e2
CW		 2252
2253 return 0;
79e53945
JB		 2254}
2255
5eddb70b 2256static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2257{
2258 struct drm_device *dev = crtc->dev;
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 u32 dpa_ctl;
2261
28c97730 2262 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2263 dpa_ctl = I915_READ(DP_A);
2264 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2265
2266 if (clock < 200000) {
2267 u32 temp;
2268 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2269 /* workaround for 160Mhz:
2270 1) program 0x4600c bits 15:0 = 0x8124
2271 2) program 0x46010 bit 0 = 1
2272 3) program 0x46034 bit 24 = 1
2273 4) program 0x64000 bit 14 = 1
2274 */
2275 temp = I915_READ(0x4600c);
2276 temp &= 0xffff0000;
2277 I915_WRITE(0x4600c, temp | 0x8124);
2278
2279 temp = I915_READ(0x46010);
2280 I915_WRITE(0x46010, temp | 1);
2281
2282 temp = I915_READ(0x46034);
2283 I915_WRITE(0x46034, temp | (1 << 24));
2284 } else {
2285 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2286 }
2287 I915_WRITE(DP_A, dpa_ctl);
2288
5eddb70b 2289 POSTING_READ(DP_A);
32f9d658
ZW		 2290 udelay(500);
2291}
2292
5e84e1a4
ZW		 2293static void intel_fdi_normal_train(struct drm_crtc *crtc)
2294{
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298 int pipe = intel_crtc->pipe;
2299 u32 reg, temp;
2300
2301 /* enable normal train */
2302 reg = FDI_TX_CTL(pipe);
2303 temp = I915_READ(reg);
61e499bf 2304 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2305 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2306 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2307 } else {
2308 temp &= ~FDI_LINK_TRAIN_NONE;
2309 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2310 }
5e84e1a4
ZW		 2311 I915_WRITE(reg, temp);
2312
2313 reg = FDI_RX_CTL(pipe);
2314 temp = I915_READ(reg);
2315 if (HAS_PCH_CPT(dev)) {
2316 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2317 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2318 } else {
2319 temp &= ~FDI_LINK_TRAIN_NONE;
2320 temp |= FDI_LINK_TRAIN_NONE;
2321 }
2322 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2323
2324 /* wait one idle pattern time */
2325 POSTING_READ(reg);
2326 udelay(1000);
357555c0
JB		 2327
2328 /* IVB wants error correction enabled */
2329 if (IS_IVYBRIDGE(dev))
2330 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2331 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2332}
2333
291427f5
JB		 2334static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2335{
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 u32 flags = I915_READ(SOUTH_CHICKEN1);
2338
2339 flags |= FDI_PHASE_SYNC_OVR(pipe);
2340 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2341 flags |= FDI_PHASE_SYNC_EN(pipe);
2342 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2343 POSTING_READ(SOUTH_CHICKEN1);
2344}
2345
8db9d77b
ZW		 2346/* The FDI link training functions for ILK/Ibexpeak. */
2347static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2348{
2349 struct drm_device *dev = crtc->dev;
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352 int pipe = intel_crtc->pipe;
0fc932b8 2353 int plane = intel_crtc->plane;
5eddb70b 2354 u32 reg, temp, tries;
8db9d77b 2355
0fc932b8
JB		 2356 /* FDI needs bits from pipe & plane first */
2357 assert_pipe_enabled(dev_priv, pipe);
2358 assert_plane_enabled(dev_priv, plane);
2359
e1a44743
AJ		 2360 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2361 for train result */
5eddb70b
CW		 2362 reg = FDI_RX_IMR(pipe);
2363 temp = I915_READ(reg);
e1a44743
AJ		 2364 temp &= ~FDI_RX_SYMBOL_LOCK;
2365 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2366 I915_WRITE(reg, temp);
2367 I915_READ(reg);
e1a44743
AJ		 2368 udelay(150);
2369
8db9d77b 2370 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2371 reg = FDI_TX_CTL(pipe);
2372 temp = I915_READ(reg);
77ffb597
AJ		 2373 temp &= ~(7 << 19);
2374 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2375 temp &= ~FDI_LINK_TRAIN_NONE;
2376 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2377 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2378
5eddb70b
CW		 2379 reg = FDI_RX_CTL(pipe);
2380 temp = I915_READ(reg);
8db9d77b
ZW		 2381 temp &= ~FDI_LINK_TRAIN_NONE;
2382 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2383 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2384
2385 POSTING_READ(reg);
8db9d77b
ZW		 2386 udelay(150);
2387
5b2adf89 2388 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2389 if (HAS_PCH_IBX(dev)) {
2390 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2391 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2392 FDI_RX_PHASE_SYNC_POINTER_EN);
2393 }
5b2adf89 2394
5eddb70b 2395 reg = FDI_RX_IIR(pipe);
e1a44743 2396 for (tries = 0; tries < 5; tries++) {
5eddb70b 2397 temp = I915_READ(reg);
8db9d77b
ZW		 2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if ((temp & FDI_RX_BIT_LOCK)) {
2401 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2402 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2403 break;
2404 }
8db9d77b 2405 }
e1a44743 2406 if (tries == 5)
5eddb70b 2407 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2408
2409 /* Train 2 */
5eddb70b
CW		 2410 reg = FDI_TX_CTL(pipe);
2411 temp = I915_READ(reg);
8db9d77b
ZW		 2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2414 I915_WRITE(reg, temp);
8db9d77b 2415
5eddb70b
CW		 2416 reg = FDI_RX_CTL(pipe);
2417 temp = I915_READ(reg);
8db9d77b
ZW		 2418 temp &= ~FDI_LINK_TRAIN_NONE;
2419 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2420 I915_WRITE(reg, temp);
8db9d77b 2421
5eddb70b
CW		 2422 POSTING_READ(reg);
2423 udelay(150);
8db9d77b 2424
5eddb70b 2425 reg = FDI_RX_IIR(pipe);
e1a44743 2426 for (tries = 0; tries < 5; tries++) {
5eddb70b 2427 temp = I915_READ(reg);
8db9d77b
ZW		 2428 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2429
2430 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2431 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2432 DRM_DEBUG_KMS("FDI train 2 done.\n");
2433 break;
2434 }
8db9d77b 2435 }
e1a44743 2436 if (tries == 5)
5eddb70b 2437 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2438
2439 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2440
8db9d77b
ZW		 2441}
2442
0206e353 2443static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2444 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2445 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2446 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2447 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2448};
2449
2450/* The FDI link training functions for SNB/Cougarpoint. */
2451static void gen6_fdi_link_train(struct drm_crtc *crtc)
2452{
2453 struct drm_device *dev = crtc->dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456 int pipe = intel_crtc->pipe;
fa37d39e 2457 u32 reg, temp, i, retry;
8db9d77b 2458
e1a44743
AJ		 2459 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2460 for train result */
5eddb70b
CW		 2461 reg = FDI_RX_IMR(pipe);
2462 temp = I915_READ(reg);
e1a44743
AJ		 2463 temp &= ~FDI_RX_SYMBOL_LOCK;
2464 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2465 I915_WRITE(reg, temp);
2466
2467 POSTING_READ(reg);
e1a44743
AJ		 2468 udelay(150);
2469
8db9d77b 2470 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2471 reg = FDI_TX_CTL(pipe);
2472 temp = I915_READ(reg);
77ffb597
AJ		 2473 temp &= ~(7 << 19);
2474 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2475 temp &= ~FDI_LINK_TRAIN_NONE;
2476 temp |= FDI_LINK_TRAIN_PATTERN_1;
2477 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478 /* SNB-B */
2479 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2480 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2481
d74cf324
SV		 2482 I915_WRITE(FDI_RX_MISC(pipe),
2483 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2484
5eddb70b
CW		 2485 reg = FDI_RX_CTL(pipe);
2486 temp = I915_READ(reg);
8db9d77b
ZW		 2487 if (HAS_PCH_CPT(dev)) {
2488 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2490 } else {
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 }
5eddb70b
CW		 2494 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2495
2496 POSTING_READ(reg);
8db9d77b
ZW		 2497 udelay(150);
2498
291427f5
JB		 2499 if (HAS_PCH_CPT(dev))
2500 cpt_phase_pointer_enable(dev, pipe);
2501
0206e353 2502 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2503 reg = FDI_TX_CTL(pipe);
2504 temp = I915_READ(reg);
8db9d77b
ZW		 2505 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2506 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2507 I915_WRITE(reg, temp);
2508
2509 POSTING_READ(reg);
8db9d77b
ZW		 2510 udelay(500);
2511
fa37d39e
SP		 2512 for (retry = 0; retry < 5; retry++) {
2513 reg = FDI_RX_IIR(pipe);
2514 temp = I915_READ(reg);
2515 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2516 if (temp & FDI_RX_BIT_LOCK) {
2517 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2518 DRM_DEBUG_KMS("FDI train 1 done.\n");
2519 break;
2520 }
2521 udelay(50);
8db9d77b 2522 }
fa37d39e
SP		 2523 if (retry < 5)
2524 break;
8db9d77b
ZW		 2525 }
2526 if (i == 4)
5eddb70b 2527 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2528
2529 /* Train 2 */
5eddb70b
CW		 2530 reg = FDI_TX_CTL(pipe);
2531 temp = I915_READ(reg);
8db9d77b
ZW		 2532 temp &= ~FDI_LINK_TRAIN_NONE;
2533 temp |= FDI_LINK_TRAIN_PATTERN_2;
2534 if (IS_GEN6(dev)) {
2535 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536 /* SNB-B */
2537 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2538 }
5eddb70b 2539 I915_WRITE(reg, temp);
8db9d77b 2540
5eddb70b
CW		 2541 reg = FDI_RX_CTL(pipe);
2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 if (HAS_PCH_CPT(dev)) {
2544 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2545 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2546 } else {
2547 temp &= ~FDI_LINK_TRAIN_NONE;
2548 temp |= FDI_LINK_TRAIN_PATTERN_2;
2549 }
5eddb70b
CW		 2550 I915_WRITE(reg, temp);
2551
2552 POSTING_READ(reg);
8db9d77b
ZW		 2553 udelay(150);
2554
0206e353 2555 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2556 reg = FDI_TX_CTL(pipe);
2557 temp = I915_READ(reg);
8db9d77b
ZW		 2558 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2559 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2560 I915_WRITE(reg, temp);
2561
2562 POSTING_READ(reg);
8db9d77b
ZW		 2563 udelay(500);
2564
fa37d39e
SP		 2565 for (retry = 0; retry < 5; retry++) {
2566 reg = FDI_RX_IIR(pipe);
2567 temp = I915_READ(reg);
2568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2569 if (temp & FDI_RX_SYMBOL_LOCK) {
2570 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2571 DRM_DEBUG_KMS("FDI train 2 done.\n");
2572 break;
2573 }
2574 udelay(50);
8db9d77b 2575 }
fa37d39e
SP		 2576 if (retry < 5)
2577 break;
8db9d77b
ZW		 2578 }
2579 if (i == 4)
5eddb70b 2580 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2581
2582 DRM_DEBUG_KMS("FDI train done.\n");
2583}
2584
357555c0
JB		 2585/* Manual link training for Ivy Bridge A0 parts */
2586static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2587{
2588 struct drm_device *dev = crtc->dev;
2589 struct drm_i915_private *dev_priv = dev->dev_private;
2590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2591 int pipe = intel_crtc->pipe;
2592 u32 reg, temp, i;
2593
2594 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2595 for train result */
2596 reg = FDI_RX_IMR(pipe);
2597 temp = I915_READ(reg);
2598 temp &= ~FDI_RX_SYMBOL_LOCK;
2599 temp &= ~FDI_RX_BIT_LOCK;
2600 I915_WRITE(reg, temp);
2601
2602 POSTING_READ(reg);
2603 udelay(150);
2604
2605 /* enable CPU FDI TX and PCH FDI RX */
2606 reg = FDI_TX_CTL(pipe);
2607 temp = I915_READ(reg);
2608 temp &= ~(7 << 19);
2609 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2610 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2611 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2612 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2614 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2615 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2616
d74cf324
SV		 2617 I915_WRITE(FDI_RX_MISC(pipe),
2618 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2619
357555c0
JB		 2620 reg = FDI_RX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~FDI_LINK_TRAIN_AUTO;
2623 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2625 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2626 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2627
2628 POSTING_READ(reg);
2629 udelay(150);
2630
291427f5
JB		 2631 if (HAS_PCH_CPT(dev))
2632 cpt_phase_pointer_enable(dev, pipe);
2633
0206e353 2634 for (i = 0; i < 4; i++) {
357555c0
JB		 2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
2637 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638 temp |= snb_b_fdi_train_param[i];
2639 I915_WRITE(reg, temp);
2640
2641 POSTING_READ(reg);
2642 udelay(500);
2643
2644 reg = FDI_RX_IIR(pipe);
2645 temp = I915_READ(reg);
2646 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2647
2648 if (temp & FDI_RX_BIT_LOCK ||
2649 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2650 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2651 DRM_DEBUG_KMS("FDI train 1 done.\n");
2652 break;
2653 }
2654 }
2655 if (i == 4)
2656 DRM_ERROR("FDI train 1 fail!\n");
2657
2658 /* Train 2 */
2659 reg = FDI_TX_CTL(pipe);
2660 temp = I915_READ(reg);
2661 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2662 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2665 I915_WRITE(reg, temp);
2666
2667 reg = FDI_RX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2671 I915_WRITE(reg, temp);
2672
2673 POSTING_READ(reg);
2674 udelay(150);
2675
0206e353 2676 for (i = 0; i < 4; i++) {
357555c0
JB		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2680 temp |= snb_b_fdi_train_param[i];
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(500);
2685
2686 reg = FDI_RX_IIR(pipe);
2687 temp = I915_READ(reg);
2688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2689
2690 if (temp & FDI_RX_SYMBOL_LOCK) {
2691 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2692 DRM_DEBUG_KMS("FDI train 2 done.\n");
2693 break;
2694 }
2695 }
2696 if (i == 4)
2697 DRM_ERROR("FDI train 2 fail!\n");
2698
2699 DRM_DEBUG_KMS("FDI train done.\n");
2700}
2701
88cefb6c 2702static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2703{
88cefb6c 2704 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2705 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2706 int pipe = intel_crtc->pipe;
5eddb70b 2707 u32 reg, temp;
79e53945 2708
c64e311e 2709
c98e9dcf 2710 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2714 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2715 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2716 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2717
2718 POSTING_READ(reg);
c98e9dcf
JB		 2719 udelay(200);
2720
2721 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2722 temp = I915_READ(reg);
2723 I915_WRITE(reg, temp | FDI_PCDCLK);
2724
2725 POSTING_READ(reg);
c98e9dcf
JB		 2726 udelay(200);
2727
bf507ef7
ED		 2728 /* On Haswell, the PLL configuration for ports and pipes is handled
2729 * separately, as part of DDI setup */
2730 if (!IS_HASWELL(dev)) {
2731 /* Enable CPU FDI TX PLL, always on for Ironlake */
2732 reg = FDI_TX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2735 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2736
bf507ef7
ED		 2737 POSTING_READ(reg);
2738 udelay(100);
2739 }
6be4a607 2740 }
0e23b99d
JB		 2741}
2742
88cefb6c
SV		 2743static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2744{
2745 struct drm_device *dev = intel_crtc->base.dev;
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 int pipe = intel_crtc->pipe;
2748 u32 reg, temp;
2749
2750 /* Switch from PCDclk to Rawclk */
2751 reg = FDI_RX_CTL(pipe);
2752 temp = I915_READ(reg);
2753 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2754
2755 /* Disable CPU FDI TX PLL */
2756 reg = FDI_TX_CTL(pipe);
2757 temp = I915_READ(reg);
2758 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2759
2760 POSTING_READ(reg);
2761 udelay(100);
2762
2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2766
2767 /* Wait for the clocks to turn off. */
2768 POSTING_READ(reg);
2769 udelay(100);
2770}
2771
291427f5
JB		 2772static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2773{
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 u32 flags = I915_READ(SOUTH_CHICKEN1);
2776
2777 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2778 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2779 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2780 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2781 POSTING_READ(SOUTH_CHICKEN1);
2782}
0fc932b8
JB		 2783static void ironlake_fdi_disable(struct drm_crtc *crtc)
2784{
2785 struct drm_device *dev = crtc->dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788 int pipe = intel_crtc->pipe;
2789 u32 reg, temp;
2790
2791 /* disable CPU FDI tx and PCH FDI rx */
2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2795 POSTING_READ(reg);
2796
2797 reg = FDI_RX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~(0x7 << 16);
2800 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2801 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805
2806 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2807 if (HAS_PCH_IBX(dev)) {
2808 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2809 I915_WRITE(FDI_RX_CHICKEN(pipe),
2810 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2811 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2812 } else if (HAS_PCH_CPT(dev)) {
2813 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2814 }
0fc932b8
JB		 2815
2816 /* still set train pattern 1 */
2817 reg = FDI_TX_CTL(pipe);
2818 temp = I915_READ(reg);
2819 temp &= ~FDI_LINK_TRAIN_NONE;
2820 temp |= FDI_LINK_TRAIN_PATTERN_1;
2821 I915_WRITE(reg, temp);
2822
2823 reg = FDI_RX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 if (HAS_PCH_CPT(dev)) {
2826 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2827 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2828 } else {
2829 temp &= ~FDI_LINK_TRAIN_NONE;
2830 temp |= FDI_LINK_TRAIN_PATTERN_1;
2831 }
2832 /* BPC in FDI rx is consistent with that in PIPECONF */
2833 temp &= ~(0x07 << 16);
2834 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2835 I915_WRITE(reg, temp);
2836
2837 POSTING_READ(reg);
2838 udelay(100);
2839}
2840
5bb61643
CW		 2841static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2842{
2843 struct drm_device *dev = crtc->dev;
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845 unsigned long flags;
2846 bool pending;
2847
2848 if (atomic_read(&dev_priv->mm.wedged))
2849 return false;
2850
2851 spin_lock_irqsave(&dev->event_lock, flags);
2852 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2853 spin_unlock_irqrestore(&dev->event_lock, flags);
2854
2855 return pending;
2856}
2857
e6c3a2a6
CW		 2858static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2859{
0f91128d 2860 struct drm_device *dev = crtc->dev;
5bb61643 2861 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2862
2863 if (crtc->fb == NULL)
2864 return;
2865
5bb61643
CW		 2866 wait_event(dev_priv->pending_flip_queue,
2867 !intel_crtc_has_pending_flip(crtc));
2868
0f91128d
CW		 2869 mutex_lock(&dev->struct_mutex);
2870 intel_finish_fb(crtc->fb);
2871 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2872}
2873
fc316cbe 2874static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2875{
2876 struct drm_device *dev = crtc->dev;
228d3e36 2877 struct intel_encoder *intel_encoder;
040484af
JB		 2878
2879 /*
2880 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2881 * must be driven by its own crtc; no sharing is possible.
2882 */
228d3e36 2883 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2884 switch (intel_encoder->type) {
040484af 2885 case INTEL_OUTPUT_EDP:
228d3e36 2886 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2887 return false;
2888 continue;
2889 }
2890 }
2891
2892 return true;
2893}
2894
fc316cbe
PZ		 2895static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2896{
2897 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2898}
2899
e615efe4
ED		 2900/* Program iCLKIP clock to the desired frequency */
2901static void lpt_program_iclkip(struct drm_crtc *crtc)
2902{
2903 struct drm_device *dev = crtc->dev;
2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2906 u32 temp;
2907
2908 /* It is necessary to ungate the pixclk gate prior to programming
2909 * the divisors, and gate it back when it is done.
2910 */
2911 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2912
2913 /* Disable SSCCTL */
2914 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2915 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2916 SBI_SSCCTL_DISABLE);
2917
2918 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2919 if (crtc->mode.clock == 20000) {
2920 auxdiv = 1;
2921 divsel = 0x41;
2922 phaseinc = 0x20;
2923 } else {
2924 /* The iCLK virtual clock root frequency is in MHz,
2925 * but the crtc->mode.clock in in KHz. To get the divisors,
2926 * it is necessary to divide one by another, so we
2927 * convert the virtual clock precision to KHz here for higher
2928 * precision.
2929 */
2930 u32 iclk_virtual_root_freq = 172800 * 1000;
2931 u32 iclk_pi_range = 64;
2932 u32 desired_divisor, msb_divisor_value, pi_value;
2933
2934 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2935 msb_divisor_value = desired_divisor / iclk_pi_range;
2936 pi_value = desired_divisor % iclk_pi_range;
2937
2938 auxdiv = 0;
2939 divsel = msb_divisor_value - 2;
2940 phaseinc = pi_value;
2941 }
2942
2943 /* This should not happen with any sane values */
2944 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2945 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2946 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2947 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2948
2949 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2950 crtc->mode.clock,
2951 auxdiv,
2952 divsel,
2953 phasedir,
2954 phaseinc);
2955
2956 /* Program SSCDIVINTPHASE6 */
2957 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2958 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2959 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2960 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2961 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2962 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2963 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2964
2965 intel_sbi_write(dev_priv,
2966 SBI_SSCDIVINTPHASE6,
2967 temp);
2968
2969 /* Program SSCAUXDIV */
2970 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2971 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2972 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2973 intel_sbi_write(dev_priv,
2974 SBI_SSCAUXDIV6,
2975 temp);
2976
2977
2978 /* Enable modulator and associated divider */
2979 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2980 temp &= ~SBI_SSCCTL_DISABLE;
2981 intel_sbi_write(dev_priv,
2982 SBI_SSCCTL6,
2983 temp);
2984
2985 /* Wait for initialization time */
2986 udelay(24);
2987
2988 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2989}
2990
f67a559d
JB		 2991/*
2992 * Enable PCH resources required for PCH ports:
2993 * - PCH PLLs
2994 * - FDI training & RX/TX
2995 * - update transcoder timings
2996 * - DP transcoding bits
2997 * - transcoder
2998 */
2999static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3000{
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004 int pipe = intel_crtc->pipe;
ee7b9f93 3005 u32 reg, temp;
2c07245f 3006
e7e164db
CW		 3007 assert_transcoder_disabled(dev_priv, pipe);
3008
cd986abb
SV		 3009 /* Write the TU size bits before fdi link training, so that error
3010 * detection works. */
3011 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3012 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3013
c98e9dcf 3014 /* For PCH output, training FDI link */
674cf967 3015 dev_priv->display.fdi_link_train(crtc);
2c07245f 3016
572deb37
SV		 3017 /* XXX: pch pll's can be enabled any time before we enable the PCH
3018 * transcoder, and we actually should do this to not upset any PCH
3019 * transcoder that already use the clock when we share it.
3020 *
3021 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3022 * unconditionally resets the pll - we need that to have the right LVDS
3023 * enable sequence. */
6f13b7b5
CW		 3024 intel_enable_pch_pll(intel_crtc);
3025
e615efe4
ED		 3026 if (HAS_PCH_LPT(dev)) {
3027 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3028 lpt_program_iclkip(crtc);
3029 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3030 u32 sel;
4b645f14 3031
c98e9dcf 3032 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3033 switch (pipe) {
3034 default:
3035 case 0:
3036 temp |= TRANSA_DPLL_ENABLE;
3037 sel = TRANSA_DPLLB_SEL;
3038 break;
3039 case 1:
3040 temp |= TRANSB_DPLL_ENABLE;
3041 sel = TRANSB_DPLLB_SEL;
3042 break;
3043 case 2:
3044 temp |= TRANSC_DPLL_ENABLE;
3045 sel = TRANSC_DPLLB_SEL;
3046 break;
d64311ab 3047 }
ee7b9f93
JB		 3048 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3049 temp |= sel;
3050 else
3051 temp &= ~sel;
c98e9dcf 3052 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3053 }
5eddb70b 3054
d9b6cb56
JB		 3055 /* set transcoder timing, panel must allow it */
3056 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3057 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3058 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3059 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3060
5eddb70b
CW		 3061 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3062 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3063 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3064 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3065
f57e1e3a
ED		 3066 if (!IS_HASWELL(dev))
3067 intel_fdi_normal_train(crtc);
5e84e1a4 3068
c98e9dcf
JB		 3069 /* For PCH DP, enable TRANS_DP_CTL */
3070 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3071 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3072 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3073 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3074 reg = TRANS_DP_CTL(pipe);
3075 temp = I915_READ(reg);
3076 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3077 TRANS_DP_SYNC_MASK |
3078 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3079 temp |= (TRANS_DP_OUTPUT_ENABLE |
3080 TRANS_DP_ENH_FRAMING);
9325c9f0 3081 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3082
3083 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3084 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3085 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3086 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3087
3088 switch (intel_trans_dp_port_sel(crtc)) {
3089 case PCH_DP_B:
5eddb70b 3090 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3091 break;
3092 case PCH_DP_C:
5eddb70b 3093 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3094 break;
3095 case PCH_DP_D:
5eddb70b 3096 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3097 break;
3098 default:
3099 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3100 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3101 break;
32f9d658 3102 }
2c07245f 3103
5eddb70b 3104 I915_WRITE(reg, temp);
6be4a607 3105 }
b52eb4dc 3106
040484af 3107 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3108}
3109
ee7b9f93
JB		 3110static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3111{
3112 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3113
3114 if (pll == NULL)
3115 return;
3116
3117 if (pll->refcount == 0) {
3118 WARN(1, "bad PCH PLL refcount\n");
3119 return;
3120 }
3121
3122 --pll->refcount;
3123 intel_crtc->pch_pll = NULL;
3124}
3125
3126static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3127{
3128 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3129 struct intel_pch_pll *pll;
3130 int i;
3131
3132 pll = intel_crtc->pch_pll;
3133 if (pll) {
3134 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3135 intel_crtc->base.base.id, pll->pll_reg);
3136 goto prepare;
3137 }
3138
98b6bd99
SV		 3139 if (HAS_PCH_IBX(dev_priv->dev)) {
3140 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3141 i = intel_crtc->pipe;
3142 pll = &dev_priv->pch_plls[i];
3143
3144 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3145 intel_crtc->base.base.id, pll->pll_reg);
3146
3147 goto found;
3148 }
3149
ee7b9f93
JB		 3150 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3151 pll = &dev_priv->pch_plls[i];
3152
3153 /* Only want to check enabled timings first */
3154 if (pll->refcount == 0)
3155 continue;
3156
3157 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3158 fp == I915_READ(pll->fp0_reg)) {
3159 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3160 intel_crtc->base.base.id,
3161 pll->pll_reg, pll->refcount, pll->active);
3162
3163 goto found;
3164 }
3165 }
3166
3167 /* Ok no matching timings, maybe there's a free one? */
3168 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3169 pll = &dev_priv->pch_plls[i];
3170 if (pll->refcount == 0) {
3171 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3172 intel_crtc->base.base.id, pll->pll_reg);
3173 goto found;
3174 }
3175 }
3176
3177 return NULL;
3178
3179found:
3180 intel_crtc->pch_pll = pll;
3181 pll->refcount++;
3182 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3183prepare: /* separate function? */
3184 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3185
e04c7350
CW		 3186 /* Wait for the clocks to stabilize before rewriting the regs */
3187 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3188 POSTING_READ(pll->pll_reg);
3189 udelay(150);
e04c7350
CW		 3190
3191 I915_WRITE(pll->fp0_reg, fp);
3192 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3193 pll->on = false;
3194 return pll;
3195}
3196
d4270e57
JB		 3197void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3198{
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3201 u32 temp;
3202
3203 temp = I915_READ(dslreg);
3204 udelay(500);
3205 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3206 /* Without this, mode sets may fail silently on FDI */
3207 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3208 udelay(250);
3209 I915_WRITE(tc2reg, 0);
3210 if (wait_for(I915_READ(dslreg) != temp, 5))
3211 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3212 }
3213}
3214
f67a559d
JB		 3215static void ironlake_crtc_enable(struct drm_crtc *crtc)
3216{
3217 struct drm_device *dev = crtc->dev;
3218 struct drm_i915_private *dev_priv = dev->dev_private;
3219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3220 struct intel_encoder *encoder;
f67a559d
JB		 3221 int pipe = intel_crtc->pipe;
3222 int plane = intel_crtc->plane;
3223 u32 temp;
3224 bool is_pch_port;
3225
08a48469
SV		 3226 WARN_ON(!crtc->enabled);
3227
f67a559d
JB		 3228 if (intel_crtc->active)
3229 return;
3230
3231 intel_crtc->active = true;
3232 intel_update_watermarks(dev);
3233
3234 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3235 temp = I915_READ(PCH_LVDS);
3236 if ((temp & LVDS_PORT_EN) == 0)
3237 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3238 }
3239
fc316cbe 3240 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3241
46b6f814 3242 if (is_pch_port) {
fff367c7
SV		 3243 /* Note: FDI PLL enabling _must_ be done before we enable the
3244 * cpu pipes, hence this is separate from all the other fdi/pch
3245 * enabling. */
88cefb6c 3246 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
SV		 3247 } else {
3248 assert_fdi_tx_disabled(dev_priv, pipe);
3249 assert_fdi_rx_disabled(dev_priv, pipe);
3250 }
f67a559d 3251
bf49ec8c
SV		 3252 for_each_encoder_on_crtc(dev, crtc, encoder)
3253 if (encoder->pre_enable)
3254 encoder->pre_enable(encoder);
3255
f67a559d
JB		 3256 /* Enable panel fitting for LVDS */
3257 if (dev_priv->pch_pf_size &&
3258 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3259 /* Force use of hard-coded filter coefficients
3260 * as some pre-programmed values are broken,
3261 * e.g. x201.
3262 */
9db4a9c7
JB		 3263 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3264 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3265 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3266 }
3267
9c54c0dd
JB		 3268 /*
3269 * On ILK+ LUT must be loaded before the pipe is running but with
3270 * clocks enabled
3271 */
3272 intel_crtc_load_lut(crtc);
3273
f67a559d
JB		 3274 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3275 intel_enable_plane(dev_priv, plane, pipe);
3276
3277 if (is_pch_port)
3278 ironlake_pch_enable(crtc);
c98e9dcf 3279
d1ebd816 3280 mutex_lock(&dev->struct_mutex);
bed4a673 3281 intel_update_fbc(dev);
d1ebd816
BW		 3282 mutex_unlock(&dev->struct_mutex);
3283
6b383a7f 3284 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3285
fa5c73b1
SV		 3286 for_each_encoder_on_crtc(dev, crtc, encoder)
3287 encoder->enable(encoder);
61b77ddd
SV		 3288
3289 if (HAS_PCH_CPT(dev))
3290 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
SV		 3291
3292 /*
3293 * There seems to be a race in PCH platform hw (at least on some
3294 * outputs) where an enabled pipe still completes any pageflip right
3295 * away (as if the pipe is off) instead of waiting for vblank. As soon
3296 * as the first vblank happend, everything works as expected. Hence just
3297 * wait for one vblank before returning to avoid strange things
3298 * happening.
3299 */
3300 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3301}
3302
4f771f10
PZ		 3303static void haswell_crtc_enable(struct drm_crtc *crtc)
3304{
3305 struct drm_device *dev = crtc->dev;
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3308 struct intel_encoder *encoder;
3309 int pipe = intel_crtc->pipe;
3310 int plane = intel_crtc->plane;
4f771f10
PZ		 3311 bool is_pch_port;
3312
3313 WARN_ON(!crtc->enabled);
3314
3315 if (intel_crtc->active)
3316 return;
3317
3318 intel_crtc->active = true;
3319 intel_update_watermarks(dev);
3320
fc316cbe 3321 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3322
83616634 3323 if (is_pch_port)
4f771f10 3324 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3325
3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3327 if (encoder->pre_enable)
3328 encoder->pre_enable(encoder);
3329
1f544388 3330 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3331
1f544388
PZ		 3332 /* Enable panel fitting for eDP */
3333 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3334 /* Force use of hard-coded filter coefficients
3335 * as some pre-programmed values are broken,
3336 * e.g. x201.
3337 */
3338 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3339 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3340 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3341 }
3342
3343 /*
3344 * On ILK+ LUT must be loaded before the pipe is running but with
3345 * clocks enabled
3346 */
3347 intel_crtc_load_lut(crtc);
3348
1f544388
PZ		 3349 intel_ddi_set_pipe_settings(crtc);
3350 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3351
3352 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3353 intel_enable_plane(dev_priv, plane, pipe);
3354
3355 if (is_pch_port)
3356 ironlake_pch_enable(crtc);
3357
3358 mutex_lock(&dev->struct_mutex);
3359 intel_update_fbc(dev);
3360 mutex_unlock(&dev->struct_mutex);
3361
3362 intel_crtc_update_cursor(crtc, true);
3363
3364 for_each_encoder_on_crtc(dev, crtc, encoder)
3365 encoder->enable(encoder);
3366
4f771f10
PZ		 3367 /*
3368 * There seems to be a race in PCH platform hw (at least on some
3369 * outputs) where an enabled pipe still completes any pageflip right
3370 * away (as if the pipe is off) instead of waiting for vblank. As soon
3371 * as the first vblank happend, everything works as expected. Hence just
3372 * wait for one vblank before returning to avoid strange things
3373 * happening.
3374 */
3375 intel_wait_for_vblank(dev, intel_crtc->pipe);
3376}
3377
6be4a607
JB		 3378static void ironlake_crtc_disable(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3383 struct intel_encoder *encoder;
6be4a607
JB		 3384 int pipe = intel_crtc->pipe;
3385 int plane = intel_crtc->plane;
5eddb70b 3386 u32 reg, temp;
b52eb4dc 3387
ef9c3aee 3388
f7abfe8b
CW		 3389 if (!intel_crtc->active)
3390 return;
3391
ea9d758d
SV		 3392 for_each_encoder_on_crtc(dev, crtc, encoder)
3393 encoder->disable(encoder);
3394
e6c3a2a6 3395 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3396 drm_vblank_off(dev, pipe);
6b383a7f 3397 intel_crtc_update_cursor(crtc, false);
5eddb70b 3398
b24e7179 3399 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3400
973d04f9
CW		 3401 if (dev_priv->cfb_plane == plane)
3402 intel_disable_fbc(dev);
2c07245f 3403
b24e7179 3404 intel_disable_pipe(dev_priv, pipe);
32f9d658 3405
6be4a607 3406 /* Disable PF */
9db4a9c7
JB		 3407 I915_WRITE(PF_CTL(pipe), 0);
3408 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3409
bf49ec8c
SV		 3410 for_each_encoder_on_crtc(dev, crtc, encoder)
3411 if (encoder->post_disable)
3412 encoder->post_disable(encoder);
3413
0fc932b8 3414 ironlake_fdi_disable(crtc);
2c07245f 3415
040484af 3416 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3417
6be4a607
JB		 3418 if (HAS_PCH_CPT(dev)) {
3419 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3420 reg = TRANS_DP_CTL(pipe);
3421 temp = I915_READ(reg);
3422 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3423 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3424 I915_WRITE(reg, temp);
6be4a607
JB		 3425
3426 /* disable DPLL_SEL */
3427 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3428 switch (pipe) {
3429 case 0:
d64311ab 3430 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3431 break;
3432 case 1:
6be4a607 3433 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3434 break;
3435 case 2:
4b645f14 3436 /* C shares PLL A or B */
d64311ab 3437 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3438 break;
3439 default:
3440 BUG(); /* wtf */
3441 }
6be4a607 3442 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3443 }
e3421a18 3444
6be4a607 3445 /* disable PCH DPLL */
ee7b9f93 3446 intel_disable_pch_pll(intel_crtc);
8db9d77b 3447
88cefb6c 3448 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3449
f7abfe8b 3450 intel_crtc->active = false;
6b383a7f 3451 intel_update_watermarks(dev);
d1ebd816
BW		 3452
3453 mutex_lock(&dev->struct_mutex);
6b383a7f 3454 intel_update_fbc(dev);
d1ebd816 3455 mutex_unlock(&dev->struct_mutex);
6be4a607 3456}
1b3c7a47 3457
4f771f10
PZ		 3458static void haswell_crtc_disable(struct drm_crtc *crtc)
3459{
3460 struct drm_device *dev = crtc->dev;
3461 struct drm_i915_private *dev_priv = dev->dev_private;
3462 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463 struct intel_encoder *encoder;
3464 int pipe = intel_crtc->pipe;
3465 int plane = intel_crtc->plane;
ad80a810 3466 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3467 bool is_pch_port;
4f771f10
PZ		 3468
3469 if (!intel_crtc->active)
3470 return;
3471
83616634
PZ		 3472 is_pch_port = haswell_crtc_driving_pch(crtc);
3473
4f771f10
PZ		 3474 for_each_encoder_on_crtc(dev, crtc, encoder)
3475 encoder->disable(encoder);
3476
3477 intel_crtc_wait_for_pending_flips(crtc);
3478 drm_vblank_off(dev, pipe);
3479 intel_crtc_update_cursor(crtc, false);
3480
3481 intel_disable_plane(dev_priv, plane, pipe);
3482
3483 if (dev_priv->cfb_plane == plane)
3484 intel_disable_fbc(dev);
3485
3486 intel_disable_pipe(dev_priv, pipe);
3487
ad80a810 3488 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3489
3490 /* Disable PF */
3491 I915_WRITE(PF_CTL(pipe), 0);
3492 I915_WRITE(PF_WIN_SZ(pipe), 0);
3493
1f544388 3494 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3495
3496 for_each_encoder_on_crtc(dev, crtc, encoder)
3497 if (encoder->post_disable)
3498 encoder->post_disable(encoder);
3499
83616634
PZ		 3500 if (is_pch_port) {
3501 ironlake_fdi_disable(crtc);
3502 intel_disable_transcoder(dev_priv, pipe);
3503 intel_disable_pch_pll(intel_crtc);
3504 ironlake_fdi_pll_disable(intel_crtc);
3505 }
4f771f10
PZ		 3506
3507 intel_crtc->active = false;
3508 intel_update_watermarks(dev);
3509
3510 mutex_lock(&dev->struct_mutex);
3511 intel_update_fbc(dev);
3512 mutex_unlock(&dev->struct_mutex);
3513}
3514
ee7b9f93
JB		 3515static void ironlake_crtc_off(struct drm_crtc *crtc)
3516{
3517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3518 intel_put_pch_pll(intel_crtc);
3519}
3520
6441ab5f
PZ		 3521static void haswell_crtc_off(struct drm_crtc *crtc)
3522{
a5c961d1
PZ		 3523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3524
3525 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3526 * start using it. */
3527 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3528
6441ab5f
PZ		 3529 intel_ddi_put_crtc_pll(crtc);
3530}
3531
02e792fb
SV		 3532static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3533{
02e792fb 3534 if (!enable && intel_crtc->overlay) {
23f09ce3 3535 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3536 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3537
23f09ce3 3538 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3539 dev_priv->mm.interruptible = false;
3540 (void) intel_overlay_switch_off(intel_crtc->overlay);
3541 dev_priv->mm.interruptible = true;
23f09ce3 3542 mutex_unlock(&dev->struct_mutex);
02e792fb 3543 }
02e792fb 3544
5dcdbcb0
CW		 3545 /* Let userspace switch the overlay on again. In most cases userspace
3546 * has to recompute where to put it anyway.
3547 */
02e792fb
SV		 3548}
3549
0b8765c6 3550static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3551{
3552 struct drm_device *dev = crtc->dev;
79e53945
JB		 3553 struct drm_i915_private *dev_priv = dev->dev_private;
3554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3555 struct intel_encoder *encoder;
79e53945 3556 int pipe = intel_crtc->pipe;
80824003 3557 int plane = intel_crtc->plane;
79e53945 3558
08a48469
SV		 3559 WARN_ON(!crtc->enabled);
3560
f7abfe8b
CW		 3561 if (intel_crtc->active)
3562 return;
3563
3564 intel_crtc->active = true;
6b383a7f
CW		 3565 intel_update_watermarks(dev);
3566
63d7bbe9 3567 intel_enable_pll(dev_priv, pipe);
040484af 3568 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3569 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3570
0b8765c6 3571 intel_crtc_load_lut(crtc);
bed4a673 3572 intel_update_fbc(dev);
79e53945 3573
0b8765c6
JB		 3574 /* Give the overlay scaler a chance to enable if it's on this pipe */
3575 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3576 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3577
fa5c73b1
SV		 3578 for_each_encoder_on_crtc(dev, crtc, encoder)
3579 encoder->enable(encoder);
0b8765c6 3580}
79e53945 3581
0b8765c6
JB		 3582static void i9xx_crtc_disable(struct drm_crtc *crtc)
3583{
3584 struct drm_device *dev = crtc->dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3587 struct intel_encoder *encoder;
0b8765c6
JB		 3588 int pipe = intel_crtc->pipe;
3589 int plane = intel_crtc->plane;
b690e96c 3590
ef9c3aee 3591
f7abfe8b
CW		 3592 if (!intel_crtc->active)
3593 return;
3594
ea9d758d
SV		 3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 encoder->disable(encoder);
3597
0b8765c6 3598 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3599 intel_crtc_wait_for_pending_flips(crtc);
3600 drm_vblank_off(dev, pipe);
0b8765c6 3601 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3602 intel_crtc_update_cursor(crtc, false);
0b8765c6 3603
973d04f9
CW		 3604 if (dev_priv->cfb_plane == plane)
3605 intel_disable_fbc(dev);
79e53945 3606
b24e7179 3607 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3608 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3609 intel_disable_pll(dev_priv, pipe);
0b8765c6 3610
f7abfe8b 3611 intel_crtc->active = false;
6b383a7f
CW		 3612 intel_update_fbc(dev);
3613 intel_update_watermarks(dev);
0b8765c6
JB		 3614}
3615
ee7b9f93
JB		 3616static void i9xx_crtc_off(struct drm_crtc *crtc)
3617{
3618}
3619
976f8a20
SV		 3620static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3621 bool enabled)
2c07245f
ZW		 3622{
3623 struct drm_device *dev = crtc->dev;
3624 struct drm_i915_master_private *master_priv;
3625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626 int pipe = intel_crtc->pipe;
79e53945
JB		 3627
3628 if (!dev->primary->master)
3629 return;
3630
3631 master_priv = dev->primary->master->driver_priv;
3632 if (!master_priv->sarea_priv)
3633 return;
3634
79e53945
JB		 3635 switch (pipe) {
3636 case 0:
3637 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3638 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3639 break;
3640 case 1:
3641 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3642 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3643 break;
3644 default:
9db4a9c7 3645 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3646 break;
3647 }
79e53945
JB		 3648}
3649
976f8a20
SV		 3650/**
3651 * Sets the power management mode of the pipe and plane.
3652 */
3653void intel_crtc_update_dpms(struct drm_crtc *crtc)
3654{
3655 struct drm_device *dev = crtc->dev;
3656 struct drm_i915_private *dev_priv = dev->dev_private;
3657 struct intel_encoder *intel_encoder;
3658 bool enable = false;
3659
3660 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3661 enable |= intel_encoder->connectors_active;
3662
3663 if (enable)
3664 dev_priv->display.crtc_enable(crtc);
3665 else
3666 dev_priv->display.crtc_disable(crtc);
3667
3668 intel_crtc_update_sarea(crtc, enable);
3669}
3670
3671static void intel_crtc_noop(struct drm_crtc *crtc)
3672{
3673}
3674
cdd59983
CW		 3675static void intel_crtc_disable(struct drm_crtc *crtc)
3676{
cdd59983 3677 struct drm_device *dev = crtc->dev;
976f8a20 3678 struct drm_connector *connector;
ee7b9f93 3679 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3680
976f8a20
SV		 3681 /* crtc should still be enabled when we disable it. */
3682 WARN_ON(!crtc->enabled);
3683
3684 dev_priv->display.crtc_disable(crtc);
3685 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3686 dev_priv->display.off(crtc);
3687
931872fc
CW		 3688 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3689 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3690
3691 if (crtc->fb) {
3692 mutex_lock(&dev->struct_mutex);
1690e1eb 3693 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3694 mutex_unlock(&dev->struct_mutex);
976f8a20
SV		 3695 crtc->fb = NULL;
3696 }
3697
3698 /* Update computed state. */
3699 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3700 if (!connector->encoder || !connector->encoder->crtc)
3701 continue;
3702
3703 if (connector->encoder->crtc != crtc)
3704 continue;
3705
3706 connector->dpms = DRM_MODE_DPMS_OFF;
3707 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3708 }
3709}
3710
a261b246 3711void intel_modeset_disable(struct drm_device *dev)
79e53945 3712{
a261b246
SV		 3713 struct drm_crtc *crtc;
3714
3715 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3716 if (crtc->enabled)
3717 intel_crtc_disable(crtc);
3718 }
79e53945
JB		 3719}
3720
1f703855 3721void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3722{
7e7d76c3
JB		 3723}
3724
ea5b213a 3725void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3726{
4ef69c7a 3727 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3728
ea5b213a
CW		 3729 drm_encoder_cleanup(encoder);
3730 kfree(intel_encoder);
7e7d76c3
JB		 3731}
3732
5ab432ef
SV		 3733/* Simple dpms helper for encodres with just one connector, no cloning and only
3734 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3735 * state of the entire output pipe. */
3736void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3737{
5ab432ef
SV		 3738 if (mode == DRM_MODE_DPMS_ON) {
3739 encoder->connectors_active = true;
3740
b2cabb0e 3741 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
SV		 3742 } else {
3743 encoder->connectors_active = false;
3744
b2cabb0e 3745 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3746 }
79e53945
JB		 3747}
3748
0a91ca29
SV		 3749/* Cross check the actual hw state with our own modeset state tracking (and it's
3750 * internal consistency). */
b980514c 3751static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3752{
0a91ca29
SV		 3753 if (connector->get_hw_state(connector)) {
3754 struct intel_encoder *encoder = connector->encoder;
3755 struct drm_crtc *crtc;
3756 bool encoder_enabled;
3757 enum pipe pipe;
3758
3759 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3760 connector->base.base.id,
3761 drm_get_connector_name(&connector->base));
3762
3763 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3764 "wrong connector dpms state\n");
3765 WARN(connector->base.encoder != &encoder->base,
3766 "active connector not linked to encoder\n");
3767 WARN(!encoder->connectors_active,
3768 "encoder->connectors_active not set\n");
3769
3770 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3771 WARN(!encoder_enabled, "encoder not enabled\n");
3772 if (WARN_ON(!encoder->base.crtc))
3773 return;
3774
3775 crtc = encoder->base.crtc;
3776
3777 WARN(!crtc->enabled, "crtc not enabled\n");
3778 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3779 WARN(pipe != to_intel_crtc(crtc)->pipe,
3780 "encoder active on the wrong pipe\n");
3781 }
79e53945
JB		 3782}
3783
5ab432ef
SV		 3784/* Even simpler default implementation, if there's really no special case to
3785 * consider. */
3786void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3787{
5ab432ef 3788 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3789
5ab432ef
SV		 3790 /* All the simple cases only support two dpms states. */
3791 if (mode != DRM_MODE_DPMS_ON)
3792 mode = DRM_MODE_DPMS_OFF;
d4270e57 3793
5ab432ef
SV		 3794 if (mode == connector->dpms)
3795 return;
3796
3797 connector->dpms = mode;
3798
3799 /* Only need to change hw state when actually enabled */
3800 if (encoder->base.crtc)
3801 intel_encoder_dpms(encoder, mode);
3802 else
8af6cf88 3803 WARN_ON(encoder->connectors_active != false);
0a91ca29 3804
b980514c 3805 intel_modeset_check_state(connector->dev);
79e53945
JB		 3806}
3807
f0947c37
SV		 3808/* Simple connector->get_hw_state implementation for encoders that support only
3809 * one connector and no cloning and hence the encoder state determines the state
3810 * of the connector. */
3811bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3812{
24929352 3813 enum pipe pipe = 0;
f0947c37 3814 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3815
f0947c37 3816 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3817}
3818
79e53945 3819static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3820 const struct drm_display_mode *mode,
79e53945
JB		 3821 struct drm_display_mode *adjusted_mode)
3822{
2c07245f 3823 struct drm_device *dev = crtc->dev;
89749350 3824
bad720ff 3825 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3826 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3827 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3828 return false;
2c07245f 3829 }
89749350 3830
f9bef081
SV		 3831 /* All interlaced capable intel hw wants timings in frames. Note though
3832 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3833 * timings, so we need to be careful not to clobber these.*/
3834 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3835 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3836
44f46b42
CW		 3837 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3838 * with a hsync front porch of 0.
3839 */
3840 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3841 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3842 return false;
3843
79e53945
JB		 3844 return true;
3845}
3846
25eb05fc
JB		 3847static int valleyview_get_display_clock_speed(struct drm_device *dev)
3848{
3849 return 400000; /* FIXME */
3850}
3851
e70236a8
JB		 3852static int i945_get_display_clock_speed(struct drm_device *dev)
3853{
3854 return 400000;
3855}
79e53945 3856
e70236a8 3857static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3858{
e70236a8
JB		 3859 return 333000;
3860}
79e53945 3861
e70236a8
JB		 3862static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3863{
3864 return 200000;
3865}
79e53945 3866
e70236a8
JB		 3867static int i915gm_get_display_clock_speed(struct drm_device *dev)
3868{
3869 u16 gcfgc = 0;
79e53945 3870
e70236a8
JB		 3871 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3872
3873 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3874 return 133000;
3875 else {
3876 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3877 case GC_DISPLAY_CLOCK_333_MHZ:
3878 return 333000;
3879 default:
3880 case GC_DISPLAY_CLOCK_190_200_MHZ:
3881 return 190000;
79e53945 3882 }
e70236a8
JB		 3883 }
3884}
3885
3886static int i865_get_display_clock_speed(struct drm_device *dev)
3887{
3888 return 266000;
3889}
3890
3891static int i855_get_display_clock_speed(struct drm_device *dev)
3892{
3893 u16 hpllcc = 0;
3894 /* Assume that the hardware is in the high speed state. This
3895 * should be the default.
3896 */
3897 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3898 case GC_CLOCK_133_200:
3899 case GC_CLOCK_100_200:
3900 return 200000;
3901 case GC_CLOCK_166_250:
3902 return 250000;
3903 case GC_CLOCK_100_133:
79e53945 3904 return 133000;
e70236a8 3905 }
79e53945 3906
e70236a8
JB		 3907 /* Shouldn't happen */
3908 return 0;
3909}
79e53945 3910
e70236a8
JB		 3911static int i830_get_display_clock_speed(struct drm_device *dev)
3912{
3913 return 133000;
79e53945
JB		 3914}
3915
2c07245f
ZW		 3916struct fdi_m_n {
3917 u32 tu;
3918 u32 gmch_m;
3919 u32 gmch_n;
3920 u32 link_m;
3921 u32 link_n;
3922};
3923
3924static void
3925fdi_reduce_ratio(u32 *num, u32 *den)
3926{
3927 while (*num > 0xffffff || *den > 0xffffff) {
3928 *num >>= 1;
3929 *den >>= 1;
3930 }
3931}
3932
2c07245f 3933static void
f2b115e6
AJ		 3934ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3935 int link_clock, struct fdi_m_n *m_n)
2c07245f 3936{
2c07245f
ZW		 3937 m_n->tu = 64; /* default size */
3938
22ed1113
CW		 3939 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3940 m_n->gmch_m = bits_per_pixel * pixel_clock;
3941 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3942 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3943
22ed1113
CW		 3944 m_n->link_m = pixel_clock;
3945 m_n->link_n = link_clock;
2c07245f
ZW		 3946 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3947}
3948
a7615030
CW		 3949static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3950{
72bbe58c
KP		 3951 if (i915_panel_use_ssc >= 0)
3952 return i915_panel_use_ssc != 0;
3953 return dev_priv->lvds_use_ssc
435793df 3954 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3955}
3956
5a354204
JB		 3957/**
3958 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3959 * @crtc: CRTC structure
3b5c78a3 3960 * @mode: requested mode
5a354204
JB		 3961 *
3962 * A pipe may be connected to one or more outputs. Based on the depth of the
3963 * attached framebuffer, choose a good color depth to use on the pipe.
3964 *
3965 * If possible, match the pipe depth to the fb depth. In some cases, this
3966 * isn't ideal, because the connected output supports a lesser or restricted
3967 * set of depths. Resolve that here:
3968 * LVDS typically supports only 6bpc, so clamp down in that case
3969 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3970 * Displays may support a restricted set as well, check EDID and clamp as
3971 * appropriate.
3b5c78a3 3972 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3973 *
3974 * RETURNS:
3975 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3976 * true if they don't match).
3977 */
3978static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 3979 struct drm_framebuffer *fb,
3b5c78a3
AJ		 3980 unsigned int *pipe_bpp,
3981 struct drm_display_mode *mode)
5a354204
JB		 3982{
3983 struct drm_device *dev = crtc->dev;
3984 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3985 struct drm_connector *connector;
6c2b7c12 3986 struct intel_encoder *intel_encoder;
5a354204
JB		 3987 unsigned int display_bpc = UINT_MAX, bpc;
3988
3989 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3990 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3991
3992 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3993 unsigned int lvds_bpc;
3994
3995 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3996 LVDS_A3_POWER_UP)
3997 lvds_bpc = 8;
3998 else
3999 lvds_bpc = 6;
4000
4001 if (lvds_bpc < display_bpc) {
82820490 4002 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4003 display_bpc = lvds_bpc;
4004 }
4005 continue;
4006 }
4007
5a354204
JB		 4008 /* Not one of the known troublemakers, check the EDID */
4009 list_for_each_entry(connector, &dev->mode_config.connector_list,
4010 head) {
6c2b7c12 4011 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4012 continue;
4013
62ac41a6
JB		 4014 /* Don't use an invalid EDID bpc value */
4015 if (connector->display_info.bpc &&
4016 connector->display_info.bpc < display_bpc) {
82820490 4017 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4018 display_bpc = connector->display_info.bpc;
4019 }
4020 }
4021
4022 /*
4023 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4024 * through, clamp it down. (Note: >12bpc will be caught below.)
4025 */
4026 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4027 if (display_bpc > 8 && display_bpc < 12) {
82820490 4028 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4029 display_bpc = 12;
4030 } else {
82820490 4031 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4032 display_bpc = 8;
4033 }
4034 }
4035 }
4036
3b5c78a3
AJ		 4037 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4038 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4039 display_bpc = 6;
4040 }
4041
5a354204
JB		 4042 /*
4043 * We could just drive the pipe at the highest bpc all the time and
4044 * enable dithering as needed, but that costs bandwidth. So choose
4045 * the minimum value that expresses the full color range of the fb but
4046 * also stays within the max display bpc discovered above.
4047 */
4048
94352cf9 4049 switch (fb->depth) {
5a354204
JB		 4050 case 8:
4051 bpc = 8; /* since we go through a colormap */
4052 break;
4053 case 15:
4054 case 16:
4055 bpc = 6; /* min is 18bpp */
4056 break;
4057 case 24:
578393cd 4058 bpc = 8;
5a354204
JB		 4059 break;
4060 case 30:
578393cd 4061 bpc = 10;
5a354204
JB		 4062 break;
4063 case 48:
578393cd 4064 bpc = 12;
5a354204
JB		 4065 break;
4066 default:
4067 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4068 bpc = min((unsigned int)8, display_bpc);
4069 break;
4070 }
4071
578393cd
KP		 4072 display_bpc = min(display_bpc, bpc);
4073
82820490
AJ		 4074 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4075 bpc, display_bpc);
5a354204 4076
578393cd 4077 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4078
4079 return display_bpc != bpc;
4080}
4081
a0c4da24
JB		 4082static int vlv_get_refclk(struct drm_crtc *crtc)
4083{
4084 struct drm_device *dev = crtc->dev;
4085 struct drm_i915_private *dev_priv = dev->dev_private;
4086 int refclk = 27000; /* for DP & HDMI */
4087
4088 return 100000; /* only one validated so far */
4089
4090 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4091 refclk = 96000;
4092 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4093 if (intel_panel_use_ssc(dev_priv))
4094 refclk = 100000;
4095 else
4096 refclk = 96000;
4097 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4098 refclk = 100000;
4099 }
4100
4101 return refclk;
4102}
4103
c65d77d8
JB		 4104static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4105{
4106 struct drm_device *dev = crtc->dev;
4107 struct drm_i915_private *dev_priv = dev->dev_private;
4108 int refclk;
4109
a0c4da24
JB		 4110 if (IS_VALLEYVIEW(dev)) {
4111 refclk = vlv_get_refclk(crtc);
4112 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4113 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4114 refclk = dev_priv->lvds_ssc_freq * 1000;
4115 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4116 refclk / 1000);
4117 } else if (!IS_GEN2(dev)) {
4118 refclk = 96000;
4119 } else {
4120 refclk = 48000;
4121 }
4122
4123 return refclk;
4124}
4125
4126static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4127 intel_clock_t *clock)
4128{
4129 /* SDVO TV has fixed PLL values depend on its clock range,
4130 this mirrors vbios setting. */
4131 if (adjusted_mode->clock >= 100000
4132 && adjusted_mode->clock < 140500) {
4133 clock->p1 = 2;
4134 clock->p2 = 10;
4135 clock->n = 3;
4136 clock->m1 = 16;
4137 clock->m2 = 8;
4138 } else if (adjusted_mode->clock >= 140500
4139 && adjusted_mode->clock <= 200000) {
4140 clock->p1 = 1;
4141 clock->p2 = 10;
4142 clock->n = 6;
4143 clock->m1 = 12;
4144 clock->m2 = 8;
4145 }
4146}
4147
a7516a05
JB		 4148static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4149 intel_clock_t *clock,
4150 intel_clock_t *reduced_clock)
4151{
4152 struct drm_device *dev = crtc->dev;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4155 int pipe = intel_crtc->pipe;
4156 u32 fp, fp2 = 0;
4157
4158 if (IS_PINEVIEW(dev)) {
4159 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4160 if (reduced_clock)
4161 fp2 = (1 << reduced_clock->n) << 16 |
4162 reduced_clock->m1 << 8 | reduced_clock->m2;
4163 } else {
4164 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4165 if (reduced_clock)
4166 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4167 reduced_clock->m2;
4168 }
4169
4170 I915_WRITE(FP0(pipe), fp);
4171
4172 intel_crtc->lowfreq_avail = false;
4173 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4174 reduced_clock && i915_powersave) {
4175 I915_WRITE(FP1(pipe), fp2);
4176 intel_crtc->lowfreq_avail = true;
4177 } else {
4178 I915_WRITE(FP1(pipe), fp);
4179 }
4180}
4181
93e537a1
SV		 4182static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4183 struct drm_display_mode *adjusted_mode)
4184{
4185 struct drm_device *dev = crtc->dev;
4186 struct drm_i915_private *dev_priv = dev->dev_private;
4187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4188 int pipe = intel_crtc->pipe;
284d5df5 4189 u32 temp;
93e537a1
SV		 4190
4191 temp = I915_READ(LVDS);
4192 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4193 if (pipe == 1) {
4194 temp |= LVDS_PIPEB_SELECT;
4195 } else {
4196 temp &= ~LVDS_PIPEB_SELECT;
4197 }
4198 /* set the corresponsding LVDS_BORDER bit */
4199 temp |= dev_priv->lvds_border_bits;
4200 /* Set the B0-B3 data pairs corresponding to whether we're going to
4201 * set the DPLLs for dual-channel mode or not.
4202 */
4203 if (clock->p2 == 7)
4204 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4205 else
4206 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4207
4208 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4209 * appropriately here, but we need to look more thoroughly into how
4210 * panels behave in the two modes.
4211 */
4212 /* set the dithering flag on LVDS as needed */
4213 if (INTEL_INFO(dev)->gen >= 4) {
4214 if (dev_priv->lvds_dither)
4215 temp |= LVDS_ENABLE_DITHER;
4216 else
4217 temp &= ~LVDS_ENABLE_DITHER;
4218 }
284d5df5 4219 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4220 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4221 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4222 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4223 temp |= LVDS_VSYNC_POLARITY;
93e537a1
SV		 4224 I915_WRITE(LVDS, temp);
4225}
4226
a0c4da24
JB		 4227static void vlv_update_pll(struct drm_crtc *crtc,
4228 struct drm_display_mode *mode,
4229 struct drm_display_mode *adjusted_mode,
4230 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4231 int num_connectors)
a0c4da24
JB		 4232{
4233 struct drm_device *dev = crtc->dev;
4234 struct drm_i915_private *dev_priv = dev->dev_private;
4235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4236 int pipe = intel_crtc->pipe;
4237 u32 dpll, mdiv, pdiv;
4238 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4239 bool is_sdvo;
4240 u32 temp;
4241
4242 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4243 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4244
2a8f64ca
VP		 4245 dpll = DPLL_VGA_MODE_DIS;
4246 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4247 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4248 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4249
4250 I915_WRITE(DPLL(pipe), dpll);
4251 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4252
4253 bestn = clock->n;
4254 bestm1 = clock->m1;
4255 bestm2 = clock->m2;
4256 bestp1 = clock->p1;
4257 bestp2 = clock->p2;
4258
2a8f64ca
VP		 4259 /*
4260 * In Valleyview PLL and program lane counter registers are exposed
4261 * through DPIO interface
4262 */
a0c4da24
JB		 4263 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4264 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4265 mdiv |= ((bestn << DPIO_N_SHIFT));
4266 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4267 mdiv |= (1 << DPIO_K_SHIFT);
4268 mdiv |= DPIO_ENABLE_CALIBRATION;
4269 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4270
4271 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4272
2a8f64ca 4273 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4274 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4275 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4276 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4277 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4278
2a8f64ca 4279 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4280
4281 dpll |= DPLL_VCO_ENABLE;
4282 I915_WRITE(DPLL(pipe), dpll);
4283 POSTING_READ(DPLL(pipe));
4284 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4285 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4286
2a8f64ca
VP		 4287 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4288
4289 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4290 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4291
4292 I915_WRITE(DPLL(pipe), dpll);
4293
4294 /* Wait for the clocks to stabilize. */
4295 POSTING_READ(DPLL(pipe));
4296 udelay(150);
a0c4da24 4297
2a8f64ca
VP		 4298 temp = 0;
4299 if (is_sdvo) {
4300 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4301 if (temp > 1)
4302 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4303 else
4304 temp = 0;
a0c4da24 4305 }
2a8f64ca
VP		 4306 I915_WRITE(DPLL_MD(pipe), temp);
4307 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4308
2a8f64ca
VP		 4309 /* Now program lane control registers */
4310 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4311 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4312 {
4313 temp = 0x1000C4;
4314 if(pipe == 1)
4315 temp |= (1 << 21);
4316 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4317 }
4318 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4319 {
4320 temp = 0x1000C4;
4321 if(pipe == 1)
4322 temp |= (1 << 21);
4323 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4324 }
a0c4da24
JB		 4325}
4326
eb1cbe48
SV		 4327static void i9xx_update_pll(struct drm_crtc *crtc,
4328 struct drm_display_mode *mode,
4329 struct drm_display_mode *adjusted_mode,
4330 intel_clock_t *clock, intel_clock_t *reduced_clock,
4331 int num_connectors)
4332{
4333 struct drm_device *dev = crtc->dev;
4334 struct drm_i915_private *dev_priv = dev->dev_private;
4335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4336 int pipe = intel_crtc->pipe;
4337 u32 dpll;
4338 bool is_sdvo;
4339
2a8f64ca
VP		 4340 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4341
eb1cbe48
SV		 4342 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4343 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4344
4345 dpll = DPLL_VGA_MODE_DIS;
4346
4347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4348 dpll |= DPLLB_MODE_LVDS;
4349 else
4350 dpll |= DPLLB_MODE_DAC_SERIAL;
4351 if (is_sdvo) {
4352 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4353 if (pixel_multiplier > 1) {
4354 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4355 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4356 }
4357 dpll |= DPLL_DVO_HIGH_SPEED;
4358 }
4359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4360 dpll |= DPLL_DVO_HIGH_SPEED;
4361
4362 /* compute bitmask from p1 value */
4363 if (IS_PINEVIEW(dev))
4364 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4365 else {
4366 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4367 if (IS_G4X(dev) && reduced_clock)
4368 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4369 }
4370 switch (clock->p2) {
4371 case 5:
4372 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4373 break;
4374 case 7:
4375 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4376 break;
4377 case 10:
4378 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4379 break;
4380 case 14:
4381 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4382 break;
4383 }
4384 if (INTEL_INFO(dev)->gen >= 4)
4385 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4386
4387 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4388 dpll |= PLL_REF_INPUT_TVCLKINBC;
4389 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4390 /* XXX: just matching BIOS for now */
4391 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4392 dpll |= 3;
4393 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4394 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4395 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4396 else
4397 dpll |= PLL_REF_INPUT_DREFCLK;
4398
4399 dpll |= DPLL_VCO_ENABLE;
4400 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4401 POSTING_READ(DPLL(pipe));
4402 udelay(150);
4403
4404 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4405 * This is an exception to the general rule that mode_set doesn't turn
4406 * things on.
4407 */
4408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4409 intel_update_lvds(crtc, clock, adjusted_mode);
4410
4411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4412 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4413
4414 I915_WRITE(DPLL(pipe), dpll);
4415
4416 /* Wait for the clocks to stabilize. */
4417 POSTING_READ(DPLL(pipe));
4418 udelay(150);
4419
4420 if (INTEL_INFO(dev)->gen >= 4) {
4421 u32 temp = 0;
4422 if (is_sdvo) {
4423 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4424 if (temp > 1)
4425 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4426 else
4427 temp = 0;
4428 }
4429 I915_WRITE(DPLL_MD(pipe), temp);
4430 } else {
4431 /* The pixel multiplier can only be updated once the
4432 * DPLL is enabled and the clocks are stable.
4433 *
4434 * So write it again.
4435 */
4436 I915_WRITE(DPLL(pipe), dpll);
4437 }
4438}
4439
4440static void i8xx_update_pll(struct drm_crtc *crtc,
4441 struct drm_display_mode *adjusted_mode,
2a8f64ca 4442 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
SV		 4443 int num_connectors)
4444{
4445 struct drm_device *dev = crtc->dev;
4446 struct drm_i915_private *dev_priv = dev->dev_private;
4447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4448 int pipe = intel_crtc->pipe;
4449 u32 dpll;
4450
2a8f64ca
VP		 4451 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4452
eb1cbe48
SV		 4453 dpll = DPLL_VGA_MODE_DIS;
4454
4455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4456 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4457 } else {
4458 if (clock->p1 == 2)
4459 dpll |= PLL_P1_DIVIDE_BY_TWO;
4460 else
4461 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4462 if (clock->p2 == 4)
4463 dpll |= PLL_P2_DIVIDE_BY_4;
4464 }
4465
4466 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4467 /* XXX: just matching BIOS for now */
4468 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4469 dpll |= 3;
4470 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4471 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4472 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4473 else
4474 dpll |= PLL_REF_INPUT_DREFCLK;
4475
4476 dpll |= DPLL_VCO_ENABLE;
4477 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4478 POSTING_READ(DPLL(pipe));
4479 udelay(150);
4480
eb1cbe48
SV		 4481 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4482 * This is an exception to the general rule that mode_set doesn't turn
4483 * things on.
4484 */
4485 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4486 intel_update_lvds(crtc, clock, adjusted_mode);
4487
5b5896e4
SV		 4488 I915_WRITE(DPLL(pipe), dpll);
4489
4490 /* Wait for the clocks to stabilize. */
4491 POSTING_READ(DPLL(pipe));
4492 udelay(150);
4493
eb1cbe48
SV		 4494 /* The pixel multiplier can only be updated once the
4495 * DPLL is enabled and the clocks are stable.
4496 *
4497 * So write it again.
4498 */
4499 I915_WRITE(DPLL(pipe), dpll);
4500}
4501
b0e77b9c
PZ		 4502static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4503 struct drm_display_mode *mode,
4504 struct drm_display_mode *adjusted_mode)
4505{
4506 struct drm_device *dev = intel_crtc->base.dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4509 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4510 uint32_t vsyncshift;
4511
4512 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4513 /* the chip adds 2 halflines automatically */
4514 adjusted_mode->crtc_vtotal -= 1;
4515 adjusted_mode->crtc_vblank_end -= 1;
4516 vsyncshift = adjusted_mode->crtc_hsync_start
4517 - adjusted_mode->crtc_htotal / 2;
4518 } else {
4519 vsyncshift = 0;
4520 }
4521
4522 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4523 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4524
fe2b8f9d 4525 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4526 (adjusted_mode->crtc_hdisplay - 1) |
4527 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4528 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4529 (adjusted_mode->crtc_hblank_start - 1) |
4530 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4531 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4532 (adjusted_mode->crtc_hsync_start - 1) |
4533 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4534
fe2b8f9d 4535 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4536 (adjusted_mode->crtc_vdisplay - 1) |
4537 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4538 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4539 (adjusted_mode->crtc_vblank_start - 1) |
4540 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4541 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4542 (adjusted_mode->crtc_vsync_start - 1) |
4543 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4544
b5e508d4
PZ		 4545 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4546 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4547 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4548 * bits. */
4549 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4550 (pipe == PIPE_B || pipe == PIPE_C))
4551 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4552
b0e77b9c
PZ		 4553 /* pipesrc controls the size that is scaled from, which should
4554 * always be the user's requested size.
4555 */
4556 I915_WRITE(PIPESRC(pipe),
4557 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4558}
4559
f564048e
EA		 4560static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4561 struct drm_display_mode *mode,
4562 struct drm_display_mode *adjusted_mode,
4563 int x, int y,
94352cf9 4564 struct drm_framebuffer *fb)
79e53945
JB		 4565{
4566 struct drm_device *dev = crtc->dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4569 int pipe = intel_crtc->pipe;
80824003 4570 int plane = intel_crtc->plane;
c751ce4f 4571 int refclk, num_connectors = 0;
652c393a 4572 intel_clock_t clock, reduced_clock;
b0e77b9c 4573 u32 dspcntr, pipeconf;
eb1cbe48
SV		 4574 bool ok, has_reduced_clock = false, is_sdvo = false;
4575 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4576 struct intel_encoder *encoder;
d4906093 4577 const intel_limit_t *limit;
5c3b82e2 4578 int ret;
79e53945 4579
6c2b7c12 4580 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4581 switch (encoder->type) {
79e53945
JB		 4582 case INTEL_OUTPUT_LVDS:
4583 is_lvds = true;
4584 break;
4585 case INTEL_OUTPUT_SDVO:
7d57382e 4586 case INTEL_OUTPUT_HDMI:
79e53945 4587 is_sdvo = true;
5eddb70b 4588 if (encoder->needs_tv_clock)
e2f0ba97 4589 is_tv = true;
79e53945 4590 break;
79e53945
JB		 4591 case INTEL_OUTPUT_TVOUT:
4592 is_tv = true;
4593 break;
a4fc5ed6
KP		 4594 case INTEL_OUTPUT_DISPLAYPORT:
4595 is_dp = true;
4596 break;
79e53945 4597 }
43565a06 4598
c751ce4f 4599 num_connectors++;
79e53945
JB		 4600 }
4601
c65d77d8 4602 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4603
d4906093
ML		 4604 /*
4605 * Returns a set of divisors for the desired target clock with the given
4606 * refclk, or FALSE. The returned values represent the clock equation:
4607 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4608 */
1b894b59 4609 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4610 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4611 &clock);
79e53945
JB		 4612 if (!ok) {
4613 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4614 return -EINVAL;
79e53945
JB		 4615 }
4616
cda4b7d3 4617 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4618 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4619
ddc9003c 4620 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4621 /*
4622 * Ensure we match the reduced clock's P to the target clock.
4623 * If the clocks don't match, we can't switch the display clock
4624 * by using the FP0/FP1. In such case we will disable the LVDS
4625 * downclock feature.
4626 */
ddc9003c 4627 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4628 dev_priv->lvds_downclock,
4629 refclk,
cec2f356 4630 &clock,
5eddb70b 4631 &reduced_clock);
7026d4ac
ZW		 4632 }
4633
c65d77d8
JB		 4634 if (is_sdvo && is_tv)
4635 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4636
eb1cbe48 4637 if (IS_GEN2(dev))
2a8f64ca
VP		 4638 i8xx_update_pll(crtc, adjusted_mode, &clock,
4639 has_reduced_clock ? &reduced_clock : NULL,
4640 num_connectors);
a0c4da24 4641 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4642 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4643 has_reduced_clock ? &reduced_clock : NULL,
4644 num_connectors);
79e53945 4645 else
eb1cbe48
SV		 4646 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4647 has_reduced_clock ? &reduced_clock : NULL,
4648 num_connectors);
79e53945
JB		 4649
4650 /* setup pipeconf */
5eddb70b 4651 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4652
4653 /* Set up the display plane register */
4654 dspcntr = DISPPLANE_GAMMA_ENABLE;
4655
929c77fb
EA		 4656 if (pipe == 0)
4657 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4658 else
4659 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4660
a6c45cf0 4661 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4662 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4663 * core speed.
4664 *
4665 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4666 * pipe == 0 check?
4667 */
e70236a8
JB		 4668 if (mode->clock >
4669 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4670 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4671 else
5eddb70b 4672 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4673 }
4674
3b5c78a3
AJ		 4675 /* default to 8bpc */
4676 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4677 if (is_dp) {
0c96c65b 4678 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4679 pipeconf |= PIPECONF_BPP_6 |
4680 PIPECONF_DITHER_EN |
4681 PIPECONF_DITHER_TYPE_SP;
4682 }
4683 }
4684
19c03924
GB		 4685 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4686 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4687 pipeconf |= PIPECONF_BPP_6 |
4688 PIPECONF_ENABLE |
4689 I965_PIPECONF_ACTIVE;
4690 }
4691 }
4692
28c97730 4693 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4694 drm_mode_debug_printmodeline(mode);
4695
a7516a05
JB		 4696 if (HAS_PIPE_CXSR(dev)) {
4697 if (intel_crtc->lowfreq_avail) {
28c97730 4698 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4699 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4700 } else {
28c97730 4701 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4702 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4703 }
4704 }
4705
617cf884 4706 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4707 if (!IS_GEN2(dev) &&
b0e77b9c 4708 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4709 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4710 else
617cf884 4711 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4712
b0e77b9c 4713 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4714
4715 /* pipesrc and dspsize control the size that is scaled from,
4716 * which should always be the user's requested size.
79e53945 4717 */
929c77fb
EA		 4718 I915_WRITE(DSPSIZE(plane),
4719 ((mode->vdisplay - 1) << 16) |
4720 (mode->hdisplay - 1));
4721 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4722
f564048e
EA		 4723 I915_WRITE(PIPECONF(pipe), pipeconf);
4724 POSTING_READ(PIPECONF(pipe));
929c77fb 4725 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4726
4727 intel_wait_for_vblank(dev, pipe);
4728
f564048e
EA		 4729 I915_WRITE(DSPCNTR(plane), dspcntr);
4730 POSTING_READ(DSPCNTR(plane));
4731
94352cf9 4732 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4733
4734 intel_update_watermarks(dev);
4735
f564048e
EA		 4736 return ret;
4737}
4738
9fb526db
KP		 4739/*
4740 * Initialize reference clocks when the driver loads
4741 */
4742void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4743{
4744 struct drm_i915_private *dev_priv = dev->dev_private;
4745 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4746 struct intel_encoder *encoder;
13d83a67
JB		 4747 u32 temp;
4748 bool has_lvds = false;
199e5d79
KP		 4749 bool has_cpu_edp = false;
4750 bool has_pch_edp = false;
4751 bool has_panel = false;
99eb6a01
KP		 4752 bool has_ck505 = false;
4753 bool can_ssc = false;
13d83a67
JB		 4754
4755 /* We need to take the global config into account */
199e5d79
KP		 4756 list_for_each_entry(encoder, &mode_config->encoder_list,
4757 base.head) {
4758 switch (encoder->type) {
4759 case INTEL_OUTPUT_LVDS:
4760 has_panel = true;
4761 has_lvds = true;
4762 break;
4763 case INTEL_OUTPUT_EDP:
4764 has_panel = true;
4765 if (intel_encoder_is_pch_edp(&encoder->base))
4766 has_pch_edp = true;
4767 else
4768 has_cpu_edp = true;
4769 break;
13d83a67
JB		 4770 }
4771 }
4772
99eb6a01
KP		 4773 if (HAS_PCH_IBX(dev)) {
4774 has_ck505 = dev_priv->display_clock_mode;
4775 can_ssc = has_ck505;
4776 } else {
4777 has_ck505 = false;
4778 can_ssc = true;
4779 }
4780
4781 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4782 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4783 has_ck505);
13d83a67
JB		 4784
4785 /* Ironlake: try to setup display ref clock before DPLL
4786 * enabling. This is only under driver's control after
4787 * PCH B stepping, previous chipset stepping should be
4788 * ignoring this setting.
4789 */
4790 temp = I915_READ(PCH_DREF_CONTROL);
4791 /* Always enable nonspread source */
4792 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4793
99eb6a01
KP		 4794 if (has_ck505)
4795 temp |= DREF_NONSPREAD_CK505_ENABLE;
4796 else
4797 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4798
199e5d79
KP		 4799 if (has_panel) {
4800 temp &= ~DREF_SSC_SOURCE_MASK;
4801 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4802
199e5d79 4803 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4804 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4805 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4806 temp |= DREF_SSC1_ENABLE;
e77166b5
SV		 4807 } else
4808 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4809
4810 /* Get SSC going before enabling the outputs */
4811 I915_WRITE(PCH_DREF_CONTROL, temp);
4812 POSTING_READ(PCH_DREF_CONTROL);
4813 udelay(200);
4814
13d83a67
JB		 4815 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4816
4817 /* Enable CPU source on CPU attached eDP */
199e5d79 4818 if (has_cpu_edp) {
99eb6a01 4819 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4820 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4821 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4822 }
13d83a67
JB		 4823 else
4824 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4825 } else
4826 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4827
4828 I915_WRITE(PCH_DREF_CONTROL, temp);
4829 POSTING_READ(PCH_DREF_CONTROL);
4830 udelay(200);
4831 } else {
4832 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4833
4834 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4835
4836 /* Turn off CPU output */
4837 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4838
4839 I915_WRITE(PCH_DREF_CONTROL, temp);
4840 POSTING_READ(PCH_DREF_CONTROL);
4841 udelay(200);
4842
4843 /* Turn off the SSC source */
4844 temp &= ~DREF_SSC_SOURCE_MASK;
4845 temp |= DREF_SSC_SOURCE_DISABLE;
4846
4847 /* Turn off SSC1 */
4848 temp &= ~ DREF_SSC1_ENABLE;
4849
13d83a67
JB		 4850 I915_WRITE(PCH_DREF_CONTROL, temp);
4851 POSTING_READ(PCH_DREF_CONTROL);
4852 udelay(200);
4853 }
4854}
4855
d9d444cb
JB		 4856static int ironlake_get_refclk(struct drm_crtc *crtc)
4857{
4858 struct drm_device *dev = crtc->dev;
4859 struct drm_i915_private *dev_priv = dev->dev_private;
4860 struct intel_encoder *encoder;
d9d444cb
JB		 4861 struct intel_encoder *edp_encoder = NULL;
4862 int num_connectors = 0;
4863 bool is_lvds = false;
4864
6c2b7c12 4865 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4866 switch (encoder->type) {
4867 case INTEL_OUTPUT_LVDS:
4868 is_lvds = true;
4869 break;
4870 case INTEL_OUTPUT_EDP:
4871 edp_encoder = encoder;
4872 break;
4873 }
4874 num_connectors++;
4875 }
4876
4877 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4878 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4879 dev_priv->lvds_ssc_freq);
4880 return dev_priv->lvds_ssc_freq * 1000;
4881 }
4882
4883 return 120000;
4884}
4885
c8203565
PZ		 4886static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4887 struct drm_display_mode *adjusted_mode,
4888 bool dither)
4889{
4890 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4892 int pipe = intel_crtc->pipe;
4893 uint32_t val;
4894
4895 val = I915_READ(PIPECONF(pipe));
4896
4897 val &= ~PIPE_BPC_MASK;
4898 switch (intel_crtc->bpp) {
4899 case 18:
4900 val |= PIPE_6BPC;
4901 break;
4902 case 24:
4903 val |= PIPE_8BPC;
4904 break;
4905 case 30:
4906 val |= PIPE_10BPC;
4907 break;
4908 case 36:
4909 val |= PIPE_12BPC;
4910 break;
4911 default:
cc769b62
PZ		 4912 /* Case prevented by intel_choose_pipe_bpp_dither. */
4913 BUG();
c8203565
PZ		 4914 }
4915
4916 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4917 if (dither)
4918 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4919
4920 val &= ~PIPECONF_INTERLACE_MASK;
4921 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4922 val |= PIPECONF_INTERLACED_ILK;
4923 else
4924 val |= PIPECONF_PROGRESSIVE;
4925
4926 I915_WRITE(PIPECONF(pipe), val);
4927 POSTING_READ(PIPECONF(pipe));
4928}
4929
ee2b0b38
PZ		 4930static void haswell_set_pipeconf(struct drm_crtc *crtc,
4931 struct drm_display_mode *adjusted_mode,
4932 bool dither)
4933{
4934 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 4936 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 4937 uint32_t val;
4938
702e7a56 4939 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4940
4941 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4942 if (dither)
4943 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4944
4945 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4946 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4947 val |= PIPECONF_INTERLACED_ILK;
4948 else
4949 val |= PIPECONF_PROGRESSIVE;
4950
702e7a56
PZ		 4951 I915_WRITE(PIPECONF(cpu_transcoder), val);
4952 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4953}
4954
6591c6e4
PZ		 4955static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4956 struct drm_display_mode *adjusted_mode,
4957 intel_clock_t *clock,
4958 bool *has_reduced_clock,
4959 intel_clock_t *reduced_clock)
4960{
4961 struct drm_device *dev = crtc->dev;
4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 struct intel_encoder *intel_encoder;
4964 int refclk;
4965 const intel_limit_t *limit;
4966 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4967
4968 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4969 switch (intel_encoder->type) {
4970 case INTEL_OUTPUT_LVDS:
4971 is_lvds = true;
4972 break;
4973 case INTEL_OUTPUT_SDVO:
4974 case INTEL_OUTPUT_HDMI:
4975 is_sdvo = true;
4976 if (intel_encoder->needs_tv_clock)
4977 is_tv = true;
4978 break;
4979 case INTEL_OUTPUT_TVOUT:
4980 is_tv = true;
4981 break;
4982 }
4983 }
4984
4985 refclk = ironlake_get_refclk(crtc);
4986
4987 /*
4988 * Returns a set of divisors for the desired target clock with the given
4989 * refclk, or FALSE. The returned values represent the clock equation:
4990 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4991 */
4992 limit = intel_limit(crtc, refclk);
4993 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4994 clock);
4995 if (!ret)
4996 return false;
4997
4998 if (is_lvds && dev_priv->lvds_downclock_avail) {
4999 /*
5000 * Ensure we match the reduced clock's P to the target clock.
5001 * If the clocks don't match, we can't switch the display clock
5002 * by using the FP0/FP1. In such case we will disable the LVDS
5003 * downclock feature.
5004 */
5005 *has_reduced_clock = limit->find_pll(limit, crtc,
5006 dev_priv->lvds_downclock,
5007 refclk,
5008 clock,
5009 reduced_clock);
5010 }
5011
5012 if (is_sdvo && is_tv)
5013 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5014
5015 return true;
5016}
5017
f48d8f23
PZ		 5018static void ironlake_set_m_n(struct drm_crtc *crtc,
5019 struct drm_display_mode *mode,
5020 struct drm_display_mode *adjusted_mode)
5021{
5022 struct drm_device *dev = crtc->dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5025 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5026 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5027 struct fdi_m_n m_n = {0};
5028 int target_clock, pixel_multiplier, lane, link_bw;
5029 bool is_dp = false, is_cpu_edp = false;
5030
5031 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5032 switch (intel_encoder->type) {
5033 case INTEL_OUTPUT_DISPLAYPORT:
5034 is_dp = true;
5035 break;
5036 case INTEL_OUTPUT_EDP:
5037 is_dp = true;
5038 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5039 is_cpu_edp = true;
5040 edp_encoder = intel_encoder;
5041 break;
5042 }
5043 }
5044
5045 /* FDI link */
5046 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5047 lane = 0;
5048 /* CPU eDP doesn't require FDI link, so just set DP M/N
5049 according to current link config */
5050 if (is_cpu_edp) {
5051 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5052 } else {
5053 /* FDI is a binary signal running at ~2.7GHz, encoding
5054 * each output octet as 10 bits. The actual frequency
5055 * is stored as a divider into a 100MHz clock, and the
5056 * mode pixel clock is stored in units of 1KHz.
5057 * Hence the bw of each lane in terms of the mode signal
5058 * is:
5059 */
5060 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5061 }
5062
5063 /* [e]DP over FDI requires target mode clock instead of link clock. */
5064 if (edp_encoder)
5065 target_clock = intel_edp_target_clock(edp_encoder, mode);
5066 else if (is_dp)
5067 target_clock = mode->clock;
5068 else
5069 target_clock = adjusted_mode->clock;
5070
5071 if (!lane) {
5072 /*
5073 * Account for spread spectrum to avoid
5074 * oversubscribing the link. Max center spread
5075 * is 2.5%; use 5% for safety's sake.
5076 */
5077 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5078 lane = bps / (link_bw * 8) + 1;
5079 }
5080
5081 intel_crtc->fdi_lanes = lane;
5082
5083 if (pixel_multiplier > 1)
5084 link_bw *= pixel_multiplier;
5085 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5086 &m_n);
5087
afe2fcf5
PZ		 5088 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5089 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5090 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5091 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5092}
5093
de13a2e3
PZ		 5094static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5095 struct drm_display_mode *adjusted_mode,
5096 intel_clock_t *clock, u32 fp)
79e53945 5097{
de13a2e3 5098 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5099 struct drm_device *dev = crtc->dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5101 struct intel_encoder *intel_encoder;
5102 uint32_t dpll;
5103 int factor, pixel_multiplier, num_connectors = 0;
5104 bool is_lvds = false, is_sdvo = false, is_tv = false;
5105 bool is_dp = false, is_cpu_edp = false;
79e53945 5106
de13a2e3
PZ		 5107 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5108 switch (intel_encoder->type) {
79e53945
JB		 5109 case INTEL_OUTPUT_LVDS:
5110 is_lvds = true;
5111 break;
5112 case INTEL_OUTPUT_SDVO:
7d57382e 5113 case INTEL_OUTPUT_HDMI:
79e53945 5114 is_sdvo = true;
de13a2e3 5115 if (intel_encoder->needs_tv_clock)
e2f0ba97 5116 is_tv = true;
79e53945 5117 break;
79e53945
JB		 5118 case INTEL_OUTPUT_TVOUT:
5119 is_tv = true;
5120 break;
a4fc5ed6
KP		 5121 case INTEL_OUTPUT_DISPLAYPORT:
5122 is_dp = true;
5123 break;
32f9d658 5124 case INTEL_OUTPUT_EDP:
e3aef172 5125 is_dp = true;
de13a2e3 5126 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5127 is_cpu_edp = true;
32f9d658 5128 break;
79e53945 5129 }
43565a06 5130
c751ce4f 5131 num_connectors++;
79e53945
JB		 5132 }
5133
c1858123 5134 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5135 factor = 21;
5136 if (is_lvds) {
5137 if ((intel_panel_use_ssc(dev_priv) &&
5138 dev_priv->lvds_ssc_freq == 100) ||
5139 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5140 factor = 25;
5141 } else if (is_sdvo && is_tv)
5142 factor = 20;
c1858123 5143
de13a2e3 5144 if (clock->m < factor * clock->n)
8febb297 5145 fp |= FP_CB_TUNE;
2c07245f 5146
5eddb70b 5147 dpll = 0;
2c07245f 5148
a07d6787
EA		 5149 if (is_lvds)
5150 dpll |= DPLLB_MODE_LVDS;
5151 else
5152 dpll |= DPLLB_MODE_DAC_SERIAL;
5153 if (is_sdvo) {
de13a2e3 5154 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5155 if (pixel_multiplier > 1) {
5156 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5157 }
a07d6787
EA		 5158 dpll |= DPLL_DVO_HIGH_SPEED;
5159 }
e3aef172 5160 if (is_dp && !is_cpu_edp)
a07d6787 5161 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5162
a07d6787 5163 /* compute bitmask from p1 value */
de13a2e3 5164 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5165 /* also FPA1 */
de13a2e3 5166 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5167
de13a2e3 5168 switch (clock->p2) {
a07d6787
EA		 5169 case 5:
5170 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5171 break;
5172 case 7:
5173 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5174 break;
5175 case 10:
5176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5177 break;
5178 case 14:
5179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5180 break;
79e53945
JB		 5181 }
5182
43565a06
KH		 5183 if (is_sdvo && is_tv)
5184 dpll |= PLL_REF_INPUT_TVCLKINBC;
5185 else if (is_tv)
79e53945 5186 /* XXX: just matching BIOS for now */
43565a06 5187 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5188 dpll |= 3;
a7615030 5189 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5190 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5191 else
5192 dpll |= PLL_REF_INPUT_DREFCLK;
5193
de13a2e3
PZ		 5194 return dpll;
5195}
5196
5197static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5198 struct drm_display_mode *mode,
5199 struct drm_display_mode *adjusted_mode,
5200 int x, int y,
5201 struct drm_framebuffer *fb)
5202{
5203 struct drm_device *dev = crtc->dev;
5204 struct drm_i915_private *dev_priv = dev->dev_private;
5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206 int pipe = intel_crtc->pipe;
5207 int plane = intel_crtc->plane;
5208 int num_connectors = 0;
5209 intel_clock_t clock, reduced_clock;
5210 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5211 bool ok, has_reduced_clock = false;
5212 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5213 struct intel_encoder *encoder;
5214 u32 temp;
5215 int ret;
5216 bool dither;
de13a2e3
PZ		 5217
5218 for_each_encoder_on_crtc(dev, crtc, encoder) {
5219 switch (encoder->type) {
5220 case INTEL_OUTPUT_LVDS:
5221 is_lvds = true;
5222 break;
de13a2e3
PZ		 5223 case INTEL_OUTPUT_DISPLAYPORT:
5224 is_dp = true;
5225 break;
5226 case INTEL_OUTPUT_EDP:
5227 is_dp = true;
e2f12b07 5228 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5229 is_cpu_edp = true;
5230 break;
5231 }
5232
5233 num_connectors++;
5234 }
5235
5dc5298b
PZ		 5236 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5237 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5238
de13a2e3
PZ		 5239 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5240 &has_reduced_clock, &reduced_clock);
5241 if (!ok) {
5242 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5243 return -EINVAL;
5244 }
5245
5246 /* Ensure that the cursor is valid for the new mode before changing... */
5247 intel_crtc_update_cursor(crtc, true);
5248
5249 /* determine panel color depth */
c8241969
JN		 5250 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5251 adjusted_mode);
de13a2e3
PZ		 5252 if (is_lvds && dev_priv->lvds_dither)
5253 dither = true;
5254
5255 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5256 if (has_reduced_clock)
5257 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5258 reduced_clock.m2;
5259
5260 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5261
f7cb34d4 5262 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5263 drm_mode_debug_printmodeline(mode);
5264
5dc5298b
PZ		 5265 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5266 if (!is_cpu_edp) {
ee7b9f93 5267 struct intel_pch_pll *pll;
4b645f14 5268
ee7b9f93
JB		 5269 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5270 if (pll == NULL) {
5271 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5272 pipe);
4b645f14
JB		 5273 return -EINVAL;
5274 }
ee7b9f93
JB		 5275 } else
5276 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5277
5278 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5279 * This is an exception to the general rule that mode_set doesn't turn
5280 * things on.
5281 */
5282 if (is_lvds) {
fae14981 5283 temp = I915_READ(PCH_LVDS);
5eddb70b 5284 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5285 if (HAS_PCH_CPT(dev)) {
5286 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5287 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5288 } else {
5289 if (pipe == 1)
5290 temp |= LVDS_PIPEB_SELECT;
5291 else
5292 temp &= ~LVDS_PIPEB_SELECT;
5293 }
4b645f14 5294
a3e17eb8 5295 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5296 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5297 /* Set the B0-B3 data pairs corresponding to whether we're going to
5298 * set the DPLLs for dual-channel mode or not.
5299 */
5300 if (clock.p2 == 7)
5eddb70b 5301 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5302 else
5eddb70b 5303 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5304
5305 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5306 * appropriately here, but we need to look more thoroughly into how
5307 * panels behave in the two modes.
5308 */
284d5df5 5309 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5310 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5311 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5312 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5313 temp |= LVDS_VSYNC_POLARITY;
fae14981 5314 I915_WRITE(PCH_LVDS, temp);
79e53945 5315 }
434ed097 5316
e3aef172 5317 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5318 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5319 } else {
8db9d77b 5320 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5321 I915_WRITE(TRANSDATA_M1(pipe), 0);
5322 I915_WRITE(TRANSDATA_N1(pipe), 0);
5323 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5324 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5325 }
79e53945 5326
ee7b9f93
JB		 5327 if (intel_crtc->pch_pll) {
5328 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5329
32f9d658 5330 /* Wait for the clocks to stabilize. */
ee7b9f93 5331 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5332 udelay(150);
5333
8febb297
EA		 5334 /* The pixel multiplier can only be updated once the
5335 * DPLL is enabled and the clocks are stable.
5336 *
5337 * So write it again.
5338 */
ee7b9f93 5339 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5340 }
79e53945 5341
5eddb70b 5342 intel_crtc->lowfreq_avail = false;
ee7b9f93 5343 if (intel_crtc->pch_pll) {
4b645f14 5344 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5345 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5346 intel_crtc->lowfreq_avail = true;
4b645f14 5347 } else {
ee7b9f93 5348 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5349 }
5350 }
5351
b0e77b9c 5352 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5353
f48d8f23 5354 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5355
e3aef172 5356 if (is_cpu_edp)
8febb297 5357 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5358
c8203565 5359 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5360
9d0498a2 5361 intel_wait_for_vblank(dev, pipe);
79e53945 5362
a1f9e77e
PZ		 5363 /* Set up the display plane register */
5364 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5365 POSTING_READ(DSPCNTR(plane));
79e53945 5366
94352cf9 5367 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5368
5369 intel_update_watermarks(dev);
5370
1f8eeabf
ED		 5371 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5372
1f803ee5 5373 return ret;
79e53945
JB		 5374}
5375
09b4ddf9
PZ		 5376static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5377 struct drm_display_mode *mode,
5378 struct drm_display_mode *adjusted_mode,
5379 int x, int y,
5380 struct drm_framebuffer *fb)
5381{
5382 struct drm_device *dev = crtc->dev;
5383 struct drm_i915_private *dev_priv = dev->dev_private;
5384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5385 int pipe = intel_crtc->pipe;
5386 int plane = intel_crtc->plane;
5387 int num_connectors = 0;
5388 intel_clock_t clock, reduced_clock;
5dc5298b 5389 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5390 bool ok, has_reduced_clock = false;
5391 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5392 struct intel_encoder *encoder;
5393 u32 temp;
5394 int ret;
5395 bool dither;
5396
5397 for_each_encoder_on_crtc(dev, crtc, encoder) {
5398 switch (encoder->type) {
5399 case INTEL_OUTPUT_LVDS:
5400 is_lvds = true;
5401 break;
5402 case INTEL_OUTPUT_DISPLAYPORT:
5403 is_dp = true;
5404 break;
5405 case INTEL_OUTPUT_EDP:
5406 is_dp = true;
5407 if (!intel_encoder_is_pch_edp(&encoder->base))
5408 is_cpu_edp = true;
5409 break;
5410 }
5411
5412 num_connectors++;
5413 }
5414
a5c961d1
PZ		 5415 if (is_cpu_edp)
5416 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5417 else
5418 intel_crtc->cpu_transcoder = pipe;
5419
5dc5298b
PZ		 5420 /* We are not sure yet this won't happen. */
5421 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5422 INTEL_PCH_TYPE(dev));
5423
5424 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5425 num_connectors, pipe_name(pipe));
5426
702e7a56 5427 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5428 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5429
5430 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5431
6441ab5f
PZ		 5432 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5433 return -EINVAL;
5434
5dc5298b
PZ		 5435 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5436 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5437 &has_reduced_clock,
5438 &reduced_clock);
5439 if (!ok) {
5440 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5441 return -EINVAL;
5442 }
09b4ddf9
PZ		 5443 }
5444
5445 /* Ensure that the cursor is valid for the new mode before changing... */
5446 intel_crtc_update_cursor(crtc, true);
5447
5448 /* determine panel color depth */
c8241969
JN		 5449 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5450 adjusted_mode);
09b4ddf9
PZ		 5451 if (is_lvds && dev_priv->lvds_dither)
5452 dither = true;
5453
09b4ddf9
PZ		 5454 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5455 drm_mode_debug_printmodeline(mode);
5456
5dc5298b
PZ		 5457 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5458 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5459 if (has_reduced_clock)
5460 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5461 reduced_clock.m2;
5462
5463 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5464 fp);
5465
5466 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5467 * own on pre-Haswell/LPT generation */
5468 if (!is_cpu_edp) {
5469 struct intel_pch_pll *pll;
5470
5471 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5472 if (pll == NULL) {
5473 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5474 pipe);
5475 return -EINVAL;
5476 }
5477 } else
5478 intel_put_pch_pll(intel_crtc);
09b4ddf9 5479
5dc5298b
PZ		 5480 /* The LVDS pin pair needs to be on before the DPLLs are
5481 * enabled. This is an exception to the general rule that
5482 * mode_set doesn't turn things on.
5483 */
5484 if (is_lvds) {
5485 temp = I915_READ(PCH_LVDS);
5486 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5487 if (HAS_PCH_CPT(dev)) {
5488 temp &= ~PORT_TRANS_SEL_MASK;
5489 temp |= PORT_TRANS_SEL_CPT(pipe);
5490 } else {
5491 if (pipe == 1)
5492 temp |= LVDS_PIPEB_SELECT;
5493 else
5494 temp &= ~LVDS_PIPEB_SELECT;
5495 }
09b4ddf9 5496
5dc5298b
PZ		 5497 /* set the corresponsding LVDS_BORDER bit */
5498 temp |= dev_priv->lvds_border_bits;
5499 /* Set the B0-B3 data pairs corresponding to whether
5500 * we're going to set the DPLLs for dual-channel mode or
5501 * not.
5502 */
5503 if (clock.p2 == 7)
5504 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5505 else
5dc5298b
PZ		 5506 temp &= ~(LVDS_B0B3_POWER_UP |
5507 LVDS_CLKB_POWER_UP);
5508
5509 /* It would be nice to set 24 vs 18-bit mode
5510 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5511 * look more thoroughly into how panels behave in the
5512 * two modes.
5513 */
5514 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5515 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5516 temp |= LVDS_HSYNC_POLARITY;
5517 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5518 temp |= LVDS_VSYNC_POLARITY;
5519 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5520 }
09b4ddf9
PZ		 5521 }
5522
5523 if (is_dp && !is_cpu_edp) {
5524 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5525 } else {
5dc5298b
PZ		 5526 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5527 /* For non-DP output, clear any trans DP clock recovery
5528 * setting.*/
5529 I915_WRITE(TRANSDATA_M1(pipe), 0);
5530 I915_WRITE(TRANSDATA_N1(pipe), 0);
5531 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5532 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5533 }
09b4ddf9
PZ		 5534 }
5535
5536 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5537 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5538 if (intel_crtc->pch_pll) {
5539 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5540
5541 /* Wait for the clocks to stabilize. */
5542 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5543 udelay(150);
5544
5545 /* The pixel multiplier can only be updated once the
5546 * DPLL is enabled and the clocks are stable.
5547 *
5548 * So write it again.
5549 */
5550 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5551 }
5552
5553 if (intel_crtc->pch_pll) {
5554 if (is_lvds && has_reduced_clock && i915_powersave) {
5555 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5556 intel_crtc->lowfreq_avail = true;
5557 } else {
5558 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5559 }
09b4ddf9
PZ		 5560 }
5561 }
5562
5563 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5564
1eb8dfec
PZ		 5565 if (!is_dp || is_cpu_edp)
5566 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5567
5dc5298b
PZ		 5568 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5569 if (is_cpu_edp)
5570 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5571
ee2b0b38 5572 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5573
09b4ddf9
PZ		 5574 /* Set up the display plane register */
5575 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5576 POSTING_READ(DSPCNTR(plane));
5577
5578 ret = intel_pipe_set_base(crtc, x, y, fb);
5579
5580 intel_update_watermarks(dev);
5581
5582 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5583
5584 return ret;
5585}
5586
f564048e
EA		 5587static int intel_crtc_mode_set(struct drm_crtc *crtc,
5588 struct drm_display_mode *mode,
5589 struct drm_display_mode *adjusted_mode,
5590 int x, int y,
94352cf9 5591 struct drm_framebuffer *fb)
f564048e
EA		 5592{
5593 struct drm_device *dev = crtc->dev;
5594 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5596 int pipe = intel_crtc->pipe;
f564048e
EA		 5597 int ret;
5598
0b701d27 5599 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5600
f564048e 5601 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5602 x, y, fb);
79e53945 5603 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5604
1f803ee5 5605 return ret;
79e53945
JB		 5606}
5607
3a9627f4
WF		 5608static bool intel_eld_uptodate(struct drm_connector *connector,
5609 int reg_eldv, uint32_t bits_eldv,
5610 int reg_elda, uint32_t bits_elda,
5611 int reg_edid)
5612{
5613 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5614 uint8_t *eld = connector->eld;
5615 uint32_t i;
5616
5617 i = I915_READ(reg_eldv);
5618 i &= bits_eldv;
5619
5620 if (!eld[0])
5621 return !i;
5622
5623 if (!i)
5624 return false;
5625
5626 i = I915_READ(reg_elda);
5627 i &= ~bits_elda;
5628 I915_WRITE(reg_elda, i);
5629
5630 for (i = 0; i < eld[2]; i++)
5631 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5632 return false;
5633
5634 return true;
5635}
5636
e0dac65e
WF		 5637static void g4x_write_eld(struct drm_connector *connector,
5638 struct drm_crtc *crtc)
5639{
5640 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5641 uint8_t *eld = connector->eld;
5642 uint32_t eldv;
5643 uint32_t len;
5644 uint32_t i;
5645
5646 i = I915_READ(G4X_AUD_VID_DID);
5647
5648 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5649 eldv = G4X_ELDV_DEVCL_DEVBLC;
5650 else
5651 eldv = G4X_ELDV_DEVCTG;
5652
3a9627f4
WF		 5653 if (intel_eld_uptodate(connector,
5654 G4X_AUD_CNTL_ST, eldv,
5655 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5656 G4X_HDMIW_HDMIEDID))
5657 return;
5658
e0dac65e
WF		 5659 i = I915_READ(G4X_AUD_CNTL_ST);
5660 i &= ~(eldv | G4X_ELD_ADDR);
5661 len = (i >> 9) & 0x1f; /* ELD buffer size */
5662 I915_WRITE(G4X_AUD_CNTL_ST, i);
5663
5664 if (!eld[0])
5665 return;
5666
5667 len = min_t(uint8_t, eld[2], len);
5668 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5669 for (i = 0; i < len; i++)
5670 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5671
5672 i = I915_READ(G4X_AUD_CNTL_ST);
5673 i |= eldv;
5674 I915_WRITE(G4X_AUD_CNTL_ST, i);
5675}
5676
83358c85
WX		 5677static void haswell_write_eld(struct drm_connector *connector,
5678 struct drm_crtc *crtc)
5679{
5680 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5681 uint8_t *eld = connector->eld;
5682 struct drm_device *dev = crtc->dev;
5683 uint32_t eldv;
5684 uint32_t i;
5685 int len;
5686 int pipe = to_intel_crtc(crtc)->pipe;
5687 int tmp;
5688
5689 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5690 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5691 int aud_config = HSW_AUD_CFG(pipe);
5692 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5693
5694
5695 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5696
5697 /* Audio output enable */
5698 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5699 tmp = I915_READ(aud_cntrl_st2);
5700 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5701 I915_WRITE(aud_cntrl_st2, tmp);
5702
5703 /* Wait for 1 vertical blank */
5704 intel_wait_for_vblank(dev, pipe);
5705
5706 /* Set ELD valid state */
5707 tmp = I915_READ(aud_cntrl_st2);
5708 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5709 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5710 I915_WRITE(aud_cntrl_st2, tmp);
5711 tmp = I915_READ(aud_cntrl_st2);
5712 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5713
5714 /* Enable HDMI mode */
5715 tmp = I915_READ(aud_config);
5716 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5717 /* clear N_programing_enable and N_value_index */
5718 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5719 I915_WRITE(aud_config, tmp);
5720
5721 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5722
5723 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5724
5725 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5726 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5727 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5728 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5729 } else
5730 I915_WRITE(aud_config, 0);
5731
5732 if (intel_eld_uptodate(connector,
5733 aud_cntrl_st2, eldv,
5734 aud_cntl_st, IBX_ELD_ADDRESS,
5735 hdmiw_hdmiedid))
5736 return;
5737
5738 i = I915_READ(aud_cntrl_st2);
5739 i &= ~eldv;
5740 I915_WRITE(aud_cntrl_st2, i);
5741
5742 if (!eld[0])
5743 return;
5744
5745 i = I915_READ(aud_cntl_st);
5746 i &= ~IBX_ELD_ADDRESS;
5747 I915_WRITE(aud_cntl_st, i);
5748 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5749 DRM_DEBUG_DRIVER("port num:%d\n", i);
5750
5751 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5752 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5753 for (i = 0; i < len; i++)
5754 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5755
5756 i = I915_READ(aud_cntrl_st2);
5757 i |= eldv;
5758 I915_WRITE(aud_cntrl_st2, i);
5759
5760}
5761
e0dac65e
WF		 5762static void ironlake_write_eld(struct drm_connector *connector,
5763 struct drm_crtc *crtc)
5764{
5765 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5766 uint8_t *eld = connector->eld;
5767 uint32_t eldv;
5768 uint32_t i;
5769 int len;
5770 int hdmiw_hdmiedid;
b6daa025 5771 int aud_config;
e0dac65e
WF		 5772 int aud_cntl_st;
5773 int aud_cntrl_st2;
9b138a83 5774 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5775
b3f33cbf 5776 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5777 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5778 aud_config = IBX_AUD_CFG(pipe);
5779 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5780 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5781 } else {
9b138a83
WX		 5782 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5783 aud_config = CPT_AUD_CFG(pipe);
5784 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5785 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5786 }
5787
9b138a83 5788 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5789
5790 i = I915_READ(aud_cntl_st);
9b138a83 5791 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5792 if (!i) {
5793 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5794 /* operate blindly on all ports */
1202b4c6
WF		 5795 eldv = IBX_ELD_VALIDB;
5796 eldv |= IBX_ELD_VALIDB << 4;
5797 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5798 } else {
5799 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5800 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5801 }
5802
3a9627f4
WF		 5803 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5804 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5805 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5806 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5807 } else
5808 I915_WRITE(aud_config, 0);
e0dac65e 5809
3a9627f4
WF		 5810 if (intel_eld_uptodate(connector,
5811 aud_cntrl_st2, eldv,
5812 aud_cntl_st, IBX_ELD_ADDRESS,
5813 hdmiw_hdmiedid))
5814 return;
5815
e0dac65e
WF		 5816 i = I915_READ(aud_cntrl_st2);
5817 i &= ~eldv;
5818 I915_WRITE(aud_cntrl_st2, i);
5819
5820 if (!eld[0])
5821 return;
5822
e0dac65e 5823 i = I915_READ(aud_cntl_st);
1202b4c6 5824 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5825 I915_WRITE(aud_cntl_st, i);
5826
5827 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5828 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5829 for (i = 0; i < len; i++)
5830 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5831
5832 i = I915_READ(aud_cntrl_st2);
5833 i |= eldv;
5834 I915_WRITE(aud_cntrl_st2, i);
5835}
5836
5837void intel_write_eld(struct drm_encoder *encoder,
5838 struct drm_display_mode *mode)
5839{
5840 struct drm_crtc *crtc = encoder->crtc;
5841 struct drm_connector *connector;
5842 struct drm_device *dev = encoder->dev;
5843 struct drm_i915_private *dev_priv = dev->dev_private;
5844
5845 connector = drm_select_eld(encoder, mode);
5846 if (!connector)
5847 return;
5848
5849 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5850 connector->base.id,
5851 drm_get_connector_name(connector),
5852 connector->encoder->base.id,
5853 drm_get_encoder_name(connector->encoder));
5854
5855 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5856
5857 if (dev_priv->display.write_eld)
5858 dev_priv->display.write_eld(connector, crtc);
5859}
5860
79e53945
JB		 5861/** Loads the palette/gamma unit for the CRTC with the prepared values */
5862void intel_crtc_load_lut(struct drm_crtc *crtc)
5863{
5864 struct drm_device *dev = crtc->dev;
5865 struct drm_i915_private *dev_priv = dev->dev_private;
5866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5867 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5868 int i;
5869
5870 /* The clocks have to be on to load the palette. */
aed3f09d 5871 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5872 return;
5873
f2b115e6 5874 /* use legacy palette for Ironlake */
bad720ff 5875 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5876 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5877
79e53945
JB		 5878 for (i = 0; i < 256; i++) {
5879 I915_WRITE(palreg + 4 * i,
5880 (intel_crtc->lut_r[i] << 16) |
5881 (intel_crtc->lut_g[i] << 8) |
5882 intel_crtc->lut_b[i]);
5883 }
5884}
5885
560b85bb
CW		 5886static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5887{
5888 struct drm_device *dev = crtc->dev;
5889 struct drm_i915_private *dev_priv = dev->dev_private;
5890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5891 bool visible = base != 0;
5892 u32 cntl;
5893
5894 if (intel_crtc->cursor_visible == visible)
5895 return;
5896
9db4a9c7 5897 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5898 if (visible) {
5899 /* On these chipsets we can only modify the base whilst
5900 * the cursor is disabled.
5901 */
9db4a9c7 5902 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5903
5904 cntl &= ~(CURSOR_FORMAT_MASK);
5905 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5906 cntl |= CURSOR_ENABLE |
5907 CURSOR_GAMMA_ENABLE |
5908 CURSOR_FORMAT_ARGB;
5909 } else
5910 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5911 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5912
5913 intel_crtc->cursor_visible = visible;
5914}
5915
5916static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5917{
5918 struct drm_device *dev = crtc->dev;
5919 struct drm_i915_private *dev_priv = dev->dev_private;
5920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5921 int pipe = intel_crtc->pipe;
5922 bool visible = base != 0;
5923
5924 if (intel_crtc->cursor_visible != visible) {
548f245b 5925 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5926 if (base) {
5927 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5928 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5929 cntl |= pipe << 28; /* Connect to correct pipe */
5930 } else {
5931 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5932 cntl |= CURSOR_MODE_DISABLE;
5933 }
9db4a9c7 5934 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5935
5936 intel_crtc->cursor_visible = visible;
5937 }
5938 /* and commit changes on next vblank */
9db4a9c7 5939 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5940}
5941
65a21cd6
JB		 5942static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5943{
5944 struct drm_device *dev = crtc->dev;
5945 struct drm_i915_private *dev_priv = dev->dev_private;
5946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5947 int pipe = intel_crtc->pipe;
5948 bool visible = base != 0;
5949
5950 if (intel_crtc->cursor_visible != visible) {
5951 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5952 if (base) {
5953 cntl &= ~CURSOR_MODE;
5954 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5955 } else {
5956 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5957 cntl |= CURSOR_MODE_DISABLE;
5958 }
5959 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5960
5961 intel_crtc->cursor_visible = visible;
5962 }
5963 /* and commit changes on next vblank */
5964 I915_WRITE(CURBASE_IVB(pipe), base);
5965}
5966
cda4b7d3 5967/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5968static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5969 bool on)
cda4b7d3
CW		 5970{
5971 struct drm_device *dev = crtc->dev;
5972 struct drm_i915_private *dev_priv = dev->dev_private;
5973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5974 int pipe = intel_crtc->pipe;
5975 int x = intel_crtc->cursor_x;
5976 int y = intel_crtc->cursor_y;
560b85bb 5977 u32 base, pos;
cda4b7d3
CW		 5978 bool visible;
5979
5980 pos = 0;
5981
6b383a7f 5982 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5983 base = intel_crtc->cursor_addr;
5984 if (x > (int) crtc->fb->width)
5985 base = 0;
5986
5987 if (y > (int) crtc->fb->height)
5988 base = 0;
5989 } else
5990 base = 0;
5991
5992 if (x < 0) {
5993 if (x + intel_crtc->cursor_width < 0)
5994 base = 0;
5995
5996 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5997 x = -x;
5998 }
5999 pos |= x << CURSOR_X_SHIFT;
6000
6001 if (y < 0) {
6002 if (y + intel_crtc->cursor_height < 0)
6003 base = 0;
6004
6005 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6006 y = -y;
6007 }
6008 pos |= y << CURSOR_Y_SHIFT;
6009
6010 visible = base != 0;
560b85bb 6011 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6012 return;
6013
0cd83aa9 6014 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6015 I915_WRITE(CURPOS_IVB(pipe), pos);
6016 ivb_update_cursor(crtc, base);
6017 } else {
6018 I915_WRITE(CURPOS(pipe), pos);
6019 if (IS_845G(dev) || IS_I865G(dev))
6020 i845_update_cursor(crtc, base);
6021 else
6022 i9xx_update_cursor(crtc, base);
6023 }
cda4b7d3
CW		 6024}
6025
79e53945 6026static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6027 struct drm_file *file,
79e53945
JB		 6028 uint32_t handle,
6029 uint32_t width, uint32_t height)
6030{
6031 struct drm_device *dev = crtc->dev;
6032 struct drm_i915_private *dev_priv = dev->dev_private;
6033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6034 struct drm_i915_gem_object *obj;
cda4b7d3 6035 uint32_t addr;
3f8bc370 6036 int ret;
79e53945 6037
79e53945
JB		 6038 /* if we want to turn off the cursor ignore width and height */
6039 if (!handle) {
28c97730 6040 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6041 addr = 0;
05394f39 6042 obj = NULL;
5004417d 6043 mutex_lock(&dev->struct_mutex);
3f8bc370 6044 goto finish;
79e53945
JB		 6045 }
6046
6047 /* Currently we only support 64x64 cursors */
6048 if (width != 64 || height != 64) {
6049 DRM_ERROR("we currently only support 64x64 cursors\n");
6050 return -EINVAL;
6051 }
6052
05394f39 6053 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6054 if (&obj->base == NULL)
79e53945
JB		 6055 return -ENOENT;
6056
05394f39 6057 if (obj->base.size < width * height * 4) {
79e53945 6058 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6059 ret = -ENOMEM;
6060 goto fail;
79e53945
JB		 6061 }
6062
71acb5eb 6063 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6064 mutex_lock(&dev->struct_mutex);
b295d1b6 6065 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6066 if (obj->tiling_mode) {
6067 DRM_ERROR("cursor cannot be tiled\n");
6068 ret = -EINVAL;
6069 goto fail_locked;
6070 }
6071
2da3b9b9 6072 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6073 if (ret) {
6074 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6075 goto fail_locked;
e7b526bb
CW		 6076 }
6077
d9e86c0e
CW		 6078 ret = i915_gem_object_put_fence(obj);
6079 if (ret) {
2da3b9b9 6080 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6081 goto fail_unpin;
6082 }
6083
05394f39 6084 addr = obj->gtt_offset;
71acb5eb 6085 } else {
6eeefaf3 6086 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6087 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6088 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6089 align);
71acb5eb
DA		 6090 if (ret) {
6091 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6092 goto fail_locked;
71acb5eb 6093 }
05394f39 6094 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6095 }
6096
a6c45cf0 6097 if (IS_GEN2(dev))
14b60391
JB		 6098 I915_WRITE(CURSIZE, (height << 12) | width);
6099
3f8bc370 6100 finish:
3f8bc370 6101 if (intel_crtc->cursor_bo) {
b295d1b6 6102 if (dev_priv->info->cursor_needs_physical) {
05394f39 6103 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6104 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6105 } else
6106 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6107 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6108 }
80824003 6109
7f9872e0 6110 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6111
6112 intel_crtc->cursor_addr = addr;
05394f39 6113 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6114 intel_crtc->cursor_width = width;
6115 intel_crtc->cursor_height = height;
6116
6b383a7f 6117 intel_crtc_update_cursor(crtc, true);
3f8bc370 6118
79e53945 6119 return 0;
e7b526bb 6120fail_unpin:
05394f39 6121 i915_gem_object_unpin(obj);
7f9872e0 6122fail_locked:
34b8686e 6123 mutex_unlock(&dev->struct_mutex);
bc9025bd 6124fail:
05394f39 6125 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6126 return ret;
79e53945
JB		 6127}
6128
6129static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6130{
79e53945 6131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6132
cda4b7d3
CW		 6133 intel_crtc->cursor_x = x;
6134 intel_crtc->cursor_y = y;
652c393a 6135
6b383a7f 6136 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6137
6138 return 0;
6139}
6140
6141/** Sets the color ramps on behalf of RandR */
6142void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6143 u16 blue, int regno)
6144{
6145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6146
6147 intel_crtc->lut_r[regno] = red >> 8;
6148 intel_crtc->lut_g[regno] = green >> 8;
6149 intel_crtc->lut_b[regno] = blue >> 8;
6150}
6151
b8c00ac5
DA		 6152void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6153 u16 *blue, int regno)
6154{
6155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6156
6157 *red = intel_crtc->lut_r[regno] << 8;
6158 *green = intel_crtc->lut_g[regno] << 8;
6159 *blue = intel_crtc->lut_b[regno] << 8;
6160}
6161
79e53945 6162static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6163 u16 *blue, uint32_t start, uint32_t size)
79e53945 6164{
7203425a 6165 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6167
7203425a 6168 for (i = start; i < end; i++) {
79e53945
JB		 6169 intel_crtc->lut_r[i] = red[i] >> 8;
6170 intel_crtc->lut_g[i] = green[i] >> 8;
6171 intel_crtc->lut_b[i] = blue[i] >> 8;
6172 }
6173
6174 intel_crtc_load_lut(crtc);
6175}
6176
6177/**
6178 * Get a pipe with a simple mode set on it for doing load-based monitor
6179 * detection.
6180 *
6181 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6182 * its requirements. The pipe will be connected to no other encoders.
79e53945 6183 *
c751ce4f 6184 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6185 * configured for it. In the future, it could choose to temporarily disable
6186 * some outputs to free up a pipe for its use.
6187 *
6188 * \return crtc, or NULL if no pipes are available.
6189 */
6190
6191/* VESA 640x480x72Hz mode to set on the pipe */
6192static struct drm_display_mode load_detect_mode = {
6193 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6194 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6195};
6196
d2dff872
CW		 6197static struct drm_framebuffer *
6198intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6199 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6200 struct drm_i915_gem_object *obj)
6201{
6202 struct intel_framebuffer *intel_fb;
6203 int ret;
6204
6205 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6206 if (!intel_fb) {
6207 drm_gem_object_unreference_unlocked(&obj->base);
6208 return ERR_PTR(-ENOMEM);
6209 }
6210
6211 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6212 if (ret) {
6213 drm_gem_object_unreference_unlocked(&obj->base);
6214 kfree(intel_fb);
6215 return ERR_PTR(ret);
6216 }
6217
6218 return &intel_fb->base;
6219}
6220
6221static u32
6222intel_framebuffer_pitch_for_width(int width, int bpp)
6223{
6224 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6225 return ALIGN(pitch, 64);
6226}
6227
6228static u32
6229intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6230{
6231 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6232 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6233}
6234
6235static struct drm_framebuffer *
6236intel_framebuffer_create_for_mode(struct drm_device *dev,
6237 struct drm_display_mode *mode,
6238 int depth, int bpp)
6239{
6240 struct drm_i915_gem_object *obj;
308e5bcb 6241 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6242
6243 obj = i915_gem_alloc_object(dev,
6244 intel_framebuffer_size_for_mode(mode, bpp));
6245 if (obj == NULL)
6246 return ERR_PTR(-ENOMEM);
6247
6248 mode_cmd.width = mode->hdisplay;
6249 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6250 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6251 bpp);
5ca0c34a 6252 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6253
6254 return intel_framebuffer_create(dev, &mode_cmd, obj);
6255}
6256
6257static struct drm_framebuffer *
6258mode_fits_in_fbdev(struct drm_device *dev,
6259 struct drm_display_mode *mode)
6260{
6261 struct drm_i915_private *dev_priv = dev->dev_private;
6262 struct drm_i915_gem_object *obj;
6263 struct drm_framebuffer *fb;
6264
6265 if (dev_priv->fbdev == NULL)
6266 return NULL;
6267
6268 obj = dev_priv->fbdev->ifb.obj;
6269 if (obj == NULL)
6270 return NULL;
6271
6272 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6273 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6274 fb->bits_per_pixel))
d2dff872
CW		 6275 return NULL;
6276
01f2c773 6277 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6278 return NULL;
6279
6280 return fb;
6281}
6282
d2434ab7 6283bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6284 struct drm_display_mode *mode,
8261b191 6285 struct intel_load_detect_pipe *old)
79e53945
JB		 6286{
6287 struct intel_crtc *intel_crtc;
d2434ab7
SV		 6288 struct intel_encoder *intel_encoder =
6289 intel_attached_encoder(connector);
79e53945 6290 struct drm_crtc *possible_crtc;
4ef69c7a 6291 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6292 struct drm_crtc *crtc = NULL;
6293 struct drm_device *dev = encoder->dev;
94352cf9 6294 struct drm_framebuffer *fb;
79e53945
JB		 6295 int i = -1;
6296
d2dff872
CW		 6297 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6298 connector->base.id, drm_get_connector_name(connector),
6299 encoder->base.id, drm_get_encoder_name(encoder));
6300
79e53945
JB		 6301 /*
6302 * Algorithm gets a little messy:
7a5e4805 6303 *
79e53945
JB		 6304 * - if the connector already has an assigned crtc, use it (but make
6305 * sure it's on first)
7a5e4805 6306 *
79e53945
JB		 6307 * - try to find the first unused crtc that can drive this connector,
6308 * and use that if we find one
79e53945
JB		 6309 */
6310
6311 /* See if we already have a CRTC for this connector */
6312 if (encoder->crtc) {
6313 crtc = encoder->crtc;
8261b191 6314
24218aac 6315 old->dpms_mode = connector->dpms;
8261b191
CW		 6316 old->load_detect_temp = false;
6317
6318 /* Make sure the crtc and connector are running */
24218aac
SV		 6319 if (connector->dpms != DRM_MODE_DPMS_ON)
6320 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6321
7173188d 6322 return true;
79e53945
JB		 6323 }
6324
6325 /* Find an unused one (if possible) */
6326 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6327 i++;
6328 if (!(encoder->possible_crtcs & (1 << i)))
6329 continue;
6330 if (!possible_crtc->enabled) {
6331 crtc = possible_crtc;
6332 break;
6333 }
79e53945
JB		 6334 }
6335
6336 /*
6337 * If we didn't find an unused CRTC, don't use any.
6338 */
6339 if (!crtc) {
7173188d
CW		 6340 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6341 return false;
79e53945
JB		 6342 }
6343
fc303101
SV		 6344 intel_encoder->new_crtc = to_intel_crtc(crtc);
6345 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6346
6347 intel_crtc = to_intel_crtc(crtc);
24218aac 6348 old->dpms_mode = connector->dpms;
8261b191 6349 old->load_detect_temp = true;
d2dff872 6350 old->release_fb = NULL;
79e53945 6351
6492711d
CW		 6352 if (!mode)
6353 mode = &load_detect_mode;
79e53945 6354
d2dff872
CW		 6355 /* We need a framebuffer large enough to accommodate all accesses
6356 * that the plane may generate whilst we perform load detection.
6357 * We can not rely on the fbcon either being present (we get called
6358 * during its initialisation to detect all boot displays, or it may
6359 * not even exist) or that it is large enough to satisfy the
6360 * requested mode.
6361 */
94352cf9
SV		 6362 fb = mode_fits_in_fbdev(dev, mode);
6363 if (fb == NULL) {
d2dff872 6364 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
SV		 6365 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6366 old->release_fb = fb;
d2dff872
CW		 6367 } else
6368 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6369 if (IS_ERR(fb)) {
d2dff872 6370 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6371 goto fail;
79e53945 6372 }
79e53945 6373
94352cf9 6374 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6375 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6376 if (old->release_fb)
6377 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6378 goto fail;
79e53945 6379 }
7173188d 6380
79e53945 6381 /* let the connector get through one full cycle before testing */
9d0498a2 6382 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6383
7173188d 6384 return true;
24218aac
SV		 6385fail:
6386 connector->encoder = NULL;
6387 encoder->crtc = NULL;
24218aac 6388 return false;
79e53945
JB		 6389}
6390
d2434ab7 6391void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6392 struct intel_load_detect_pipe *old)
79e53945 6393{
d2434ab7
SV		 6394 struct intel_encoder *intel_encoder =
6395 intel_attached_encoder(connector);
4ef69c7a 6396 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6397
d2dff872
CW		 6398 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6399 connector->base.id, drm_get_connector_name(connector),
6400 encoder->base.id, drm_get_encoder_name(encoder));
6401
8261b191 6402 if (old->load_detect_temp) {
fc303101
SV		 6403 struct drm_crtc *crtc = encoder->crtc;
6404
6405 to_intel_connector(connector)->new_encoder = NULL;
6406 intel_encoder->new_crtc = NULL;
6407 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6408
6409 if (old->release_fb)
6410 old->release_fb->funcs->destroy(old->release_fb);
6411
0622a53c 6412 return;
79e53945
JB		 6413 }
6414
c751ce4f 6415 /* Switch crtc and encoder back off if necessary */
24218aac
SV		 6416 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6417 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6418}
6419
6420/* Returns the clock of the currently programmed mode of the given pipe. */
6421static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6422{
6423 struct drm_i915_private *dev_priv = dev->dev_private;
6424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6425 int pipe = intel_crtc->pipe;
548f245b 6426 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6427 u32 fp;
6428 intel_clock_t clock;
6429
6430 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6431 fp = I915_READ(FP0(pipe));
79e53945 6432 else
39adb7a5 6433 fp = I915_READ(FP1(pipe));
79e53945
JB		 6434
6435 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6436 if (IS_PINEVIEW(dev)) {
6437 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6438 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6439 } else {
6440 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6441 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6442 }
6443
a6c45cf0 6444 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6445 if (IS_PINEVIEW(dev))
6446 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6447 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6448 else
6449 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6450 DPLL_FPA01_P1_POST_DIV_SHIFT);
6451
6452 switch (dpll & DPLL_MODE_MASK) {
6453 case DPLLB_MODE_DAC_SERIAL:
6454 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6455 5 : 10;
6456 break;
6457 case DPLLB_MODE_LVDS:
6458 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6459 7 : 14;
6460 break;
6461 default:
28c97730 6462 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6463 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6464 return 0;
6465 }
6466
6467 /* XXX: Handle the 100Mhz refclk */
2177832f 6468 intel_clock(dev, 96000, &clock);
79e53945
JB		 6469 } else {
6470 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6471
6472 if (is_lvds) {
6473 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6474 DPLL_FPA01_P1_POST_DIV_SHIFT);
6475 clock.p2 = 14;
6476
6477 if ((dpll & PLL_REF_INPUT_MASK) ==
6478 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6479 /* XXX: might not be 66MHz */
2177832f 6480 intel_clock(dev, 66000, &clock);
79e53945 6481 } else
2177832f 6482 intel_clock(dev, 48000, &clock);
79e53945
JB		 6483 } else {
6484 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6485 clock.p1 = 2;
6486 else {
6487 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6488 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6489 }
6490 if (dpll & PLL_P2_DIVIDE_BY_4)
6491 clock.p2 = 4;
6492 else
6493 clock.p2 = 2;
6494
2177832f 6495 intel_clock(dev, 48000, &clock);
79e53945
JB		 6496 }
6497 }
6498
6499 /* XXX: It would be nice to validate the clocks, but we can't reuse
6500 * i830PllIsValid() because it relies on the xf86_config connector
6501 * configuration being accurate, which it isn't necessarily.
6502 */
6503
6504 return clock.dot;
6505}
6506
6507/** Returns the currently programmed mode of the given pipe. */
6508struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6509 struct drm_crtc *crtc)
6510{
548f245b 6511 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6513 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6514 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6515 int htot = I915_READ(HTOTAL(cpu_transcoder));
6516 int hsync = I915_READ(HSYNC(cpu_transcoder));
6517 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6518 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6519
6520 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6521 if (!mode)
6522 return NULL;
6523
6524 mode->clock = intel_crtc_clock_get(dev, crtc);
6525 mode->hdisplay = (htot & 0xffff) + 1;
6526 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6527 mode->hsync_start = (hsync & 0xffff) + 1;
6528 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6529 mode->vdisplay = (vtot & 0xffff) + 1;
6530 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6531 mode->vsync_start = (vsync & 0xffff) + 1;
6532 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6533
6534 drm_mode_set_name(mode);
79e53945
JB		 6535
6536 return mode;
6537}
6538
3dec0095 6539static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6540{
6541 struct drm_device *dev = crtc->dev;
6542 drm_i915_private_t *dev_priv = dev->dev_private;
6543 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6544 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6545 int dpll_reg = DPLL(pipe);
6546 int dpll;
652c393a 6547
bad720ff 6548 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6549 return;
6550
6551 if (!dev_priv->lvds_downclock_avail)
6552 return;
6553
dbdc6479 6554 dpll = I915_READ(dpll_reg);
652c393a 6555 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6556 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6557
8ac5a6d5 6558 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6559
6560 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6561 I915_WRITE(dpll_reg, dpll);
9d0498a2 6562 intel_wait_for_vblank(dev, pipe);
dbdc6479 6563
652c393a
JB		 6564 dpll = I915_READ(dpll_reg);
6565 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6566 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6567 }
652c393a
JB		 6568}
6569
6570static void intel_decrease_pllclock(struct drm_crtc *crtc)
6571{
6572 struct drm_device *dev = crtc->dev;
6573 drm_i915_private_t *dev_priv = dev->dev_private;
6574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6575
bad720ff 6576 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6577 return;
6578
6579 if (!dev_priv->lvds_downclock_avail)
6580 return;
6581
6582 /*
6583 * Since this is called by a timer, we should never get here in
6584 * the manual case.
6585 */
6586 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
SV		 6587 int pipe = intel_crtc->pipe;
6588 int dpll_reg = DPLL(pipe);
6589 int dpll;
f6e5b160 6590
44d98a61 6591 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6592
8ac5a6d5 6593 assert_panel_unlocked(dev_priv, pipe);
652c393a 6594
dc257cf1 6595 dpll = I915_READ(dpll_reg);
652c393a
JB		 6596 dpll |= DISPLAY_RATE_SELECT_FPA1;
6597 I915_WRITE(dpll_reg, dpll);
9d0498a2 6598 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6599 dpll = I915_READ(dpll_reg);
6600 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6601 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6602 }
6603
6604}
6605
f047e395
CW		 6606void intel_mark_busy(struct drm_device *dev)
6607{
f047e395
CW		 6608 i915_update_gfx_val(dev->dev_private);
6609}
6610
6611void intel_mark_idle(struct drm_device *dev)
652c393a 6612{
f047e395
CW		 6613}
6614
6615void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6616{
6617 struct drm_device *dev = obj->base.dev;
652c393a 6618 struct drm_crtc *crtc;
652c393a
JB		 6619
6620 if (!i915_powersave)
6621 return;
6622
652c393a 6623 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6624 if (!crtc->fb)
6625 continue;
6626
f047e395
CW		 6627 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6628 intel_increase_pllclock(crtc);
652c393a 6629 }
652c393a
JB		 6630}
6631
f047e395 6632void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6633{
f047e395
CW		 6634 struct drm_device *dev = obj->base.dev;
6635 struct drm_crtc *crtc;
652c393a 6636
f047e395 6637 if (!i915_powersave)
acb87dfb
CW		 6638 return;
6639
652c393a
JB		 6640 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6641 if (!crtc->fb)
6642 continue;
6643
f047e395
CW		 6644 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6645 intel_decrease_pllclock(crtc);
652c393a
JB		 6646 }
6647}
6648
79e53945
JB		 6649static void intel_crtc_destroy(struct drm_crtc *crtc)
6650{
6651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
SV		 6652 struct drm_device *dev = crtc->dev;
6653 struct intel_unpin_work *work;
6654 unsigned long flags;
6655
6656 spin_lock_irqsave(&dev->event_lock, flags);
6657 work = intel_crtc->unpin_work;
6658 intel_crtc->unpin_work = NULL;
6659 spin_unlock_irqrestore(&dev->event_lock, flags);
6660
6661 if (work) {
6662 cancel_work_sync(&work->work);
6663 kfree(work);
6664 }
79e53945
JB		 6665
6666 drm_crtc_cleanup(crtc);
67e77c5a 6667
79e53945
JB		 6668 kfree(intel_crtc);
6669}
6670
6b95a207
KH		 6671static void intel_unpin_work_fn(struct work_struct *__work)
6672{
6673 struct intel_unpin_work *work =
6674 container_of(__work, struct intel_unpin_work, work);
6675
6676 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6677 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6678 drm_gem_object_unreference(&work->pending_flip_obj->base);
6679 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6680
7782de3b 6681 intel_update_fbc(work->dev);
6b95a207
KH		 6682 mutex_unlock(&work->dev->struct_mutex);
6683 kfree(work);
6684}
6685
1afe3e9d 6686static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6687 struct drm_crtc *crtc)
6b95a207
KH		 6688{
6689 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6691 struct intel_unpin_work *work;
05394f39 6692 struct drm_i915_gem_object *obj;
6b95a207 6693 struct drm_pending_vblank_event *e;
95cb1b02 6694 struct timeval tvbl;
6b95a207
KH		 6695 unsigned long flags;
6696
6697 /* Ignore early vblank irqs */
6698 if (intel_crtc == NULL)
6699 return;
6700
6701 spin_lock_irqsave(&dev->event_lock, flags);
6702 work = intel_crtc->unpin_work;
6703 if (work == NULL || !work->pending) {
6704 spin_unlock_irqrestore(&dev->event_lock, flags);
6705 return;
6706 }
6707
6708 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6709
6710 if (work->event) {
6711 e = work->event;
49b14a5c 6712 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6713
49b14a5c
MK		 6714 e->event.tv_sec = tvbl.tv_sec;
6715 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6716
6b95a207
KH		 6717 list_add_tail(&e->base.link,
6718 &e->base.file_priv->event_list);
6719 wake_up_interruptible(&e->base.file_priv->event_wait);
6720 }
6721
0af7e4df
MK		 6722 drm_vblank_put(dev, intel_crtc->pipe);
6723
6b95a207
KH		 6724 spin_unlock_irqrestore(&dev->event_lock, flags);
6725
05394f39 6726 obj = work->old_fb_obj;
d9e86c0e 6727
e59f2bac 6728 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6729 &obj->pending_flip.counter);
d9e86c0e 6730
5bb61643 6731 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6732 schedule_work(&work->work);
e5510fac
JB		 6733
6734 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6735}
6736
1afe3e9d
JB		 6737void intel_finish_page_flip(struct drm_device *dev, int pipe)
6738{
6739 drm_i915_private_t *dev_priv = dev->dev_private;
6740 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6741
49b14a5c 6742 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6743}
6744
6745void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6746{
6747 drm_i915_private_t *dev_priv = dev->dev_private;
6748 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6749
49b14a5c 6750 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6751}
6752
6b95a207
KH		 6753void intel_prepare_page_flip(struct drm_device *dev, int plane)
6754{
6755 drm_i915_private_t *dev_priv = dev->dev_private;
6756 struct intel_crtc *intel_crtc =
6757 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6758 unsigned long flags;
6759
6760 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6761 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6762 if ((++intel_crtc->unpin_work->pending) > 1)
6763 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6764 } else {
6765 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6766 }
6b95a207
KH		 6767 spin_unlock_irqrestore(&dev->event_lock, flags);
6768}
6769
8c9f3aaf
JB		 6770static int intel_gen2_queue_flip(struct drm_device *dev,
6771 struct drm_crtc *crtc,
6772 struct drm_framebuffer *fb,
6773 struct drm_i915_gem_object *obj)
6774{
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6777 u32 flip_mask;
6d90c952 6778 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6779 int ret;
6780
6d90c952 6781 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6782 if (ret)
83d4092b 6783 goto err;
8c9f3aaf 6784
6d90c952 6785 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6786 if (ret)
83d4092b 6787 goto err_unpin;
8c9f3aaf
JB		 6788
6789 /* Can't queue multiple flips, so wait for the previous
6790 * one to finish before executing the next.
6791 */
6792 if (intel_crtc->plane)
6793 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6794 else
6795 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
SV		 6796 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6797 intel_ring_emit(ring, MI_NOOP);
6798 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6799 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6800 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6801 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
SV		 6802 intel_ring_emit(ring, 0); /* aux display base address, unused */
6803 intel_ring_advance(ring);
83d4092b
CW		 6804 return 0;
6805
6806err_unpin:
6807 intel_unpin_fb_obj(obj);
6808err:
8c9f3aaf
JB		 6809 return ret;
6810}
6811
6812static int intel_gen3_queue_flip(struct drm_device *dev,
6813 struct drm_crtc *crtc,
6814 struct drm_framebuffer *fb,
6815 struct drm_i915_gem_object *obj)
6816{
6817 struct drm_i915_private *dev_priv = dev->dev_private;
6818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6819 u32 flip_mask;
6d90c952 6820 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6821 int ret;
6822
6d90c952 6823 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6824 if (ret)
83d4092b 6825 goto err;
8c9f3aaf 6826
6d90c952 6827 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6828 if (ret)
83d4092b 6829 goto err_unpin;
8c9f3aaf
JB		 6830
6831 if (intel_crtc->plane)
6832 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6833 else
6834 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
SV		 6835 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6836 intel_ring_emit(ring, MI_NOOP);
6837 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6838 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6839 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6840 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
SV		 6841 intel_ring_emit(ring, MI_NOOP);
6842
6843 intel_ring_advance(ring);
83d4092b
CW		 6844 return 0;
6845
6846err_unpin:
6847 intel_unpin_fb_obj(obj);
6848err:
8c9f3aaf
JB		 6849 return ret;
6850}
6851
6852static int intel_gen4_queue_flip(struct drm_device *dev,
6853 struct drm_crtc *crtc,
6854 struct drm_framebuffer *fb,
6855 struct drm_i915_gem_object *obj)
6856{
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6859 uint32_t pf, pipesrc;
6d90c952 6860 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6861 int ret;
6862
6d90c952 6863 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6864 if (ret)
83d4092b 6865 goto err;
8c9f3aaf 6866
6d90c952 6867 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6868 if (ret)
83d4092b 6869 goto err_unpin;
8c9f3aaf
JB		 6870
6871 /* i965+ uses the linear or tiled offsets from the
6872 * Display Registers (which do not change across a page-flip)
6873 * so we need only reprogram the base address.
6874 */
6d90c952
SV		 6875 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6876 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6877 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
SV		 6878 intel_ring_emit(ring,
6879 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6880 obj->tiling_mode);
8c9f3aaf
JB		 6881
6882 /* XXX Enabling the panel-fitter across page-flip is so far
6883 * untested on non-native modes, so ignore it for now.
6884 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6885 */
6886 pf = 0;
6887 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
SV		 6888 intel_ring_emit(ring, pf | pipesrc);
6889 intel_ring_advance(ring);
83d4092b
CW		 6890 return 0;
6891
6892err_unpin:
6893 intel_unpin_fb_obj(obj);
6894err:
8c9f3aaf
JB		 6895 return ret;
6896}
6897
6898static int intel_gen6_queue_flip(struct drm_device *dev,
6899 struct drm_crtc *crtc,
6900 struct drm_framebuffer *fb,
6901 struct drm_i915_gem_object *obj)
6902{
6903 struct drm_i915_private *dev_priv = dev->dev_private;
6904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6905 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6906 uint32_t pf, pipesrc;
6907 int ret;
6908
6d90c952 6909 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6910 if (ret)
83d4092b 6911 goto err;
8c9f3aaf 6912
6d90c952 6913 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6914 if (ret)
83d4092b 6915 goto err_unpin;
8c9f3aaf 6916
6d90c952
SV		 6917 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6918 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6919 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6920 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6921
dc257cf1
SV		 6922 /* Contrary to the suggestions in the documentation,
6923 * "Enable Panel Fitter" does not seem to be required when page
6924 * flipping with a non-native mode, and worse causes a normal
6925 * modeset to fail.
6926 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6927 */
6928 pf = 0;
8c9f3aaf 6929 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
SV		 6930 intel_ring_emit(ring, pf | pipesrc);
6931 intel_ring_advance(ring);
83d4092b
CW		 6932 return 0;
6933
6934err_unpin:
6935 intel_unpin_fb_obj(obj);
6936err:
8c9f3aaf
JB		 6937 return ret;
6938}
6939
7c9017e5
JB		 6940/*
6941 * On gen7 we currently use the blit ring because (in early silicon at least)
6942 * the render ring doesn't give us interrpts for page flip completion, which
6943 * means clients will hang after the first flip is queued. Fortunately the
6944 * blit ring generates interrupts properly, so use it instead.
6945 */
6946static int intel_gen7_queue_flip(struct drm_device *dev,
6947 struct drm_crtc *crtc,
6948 struct drm_framebuffer *fb,
6949 struct drm_i915_gem_object *obj)
6950{
6951 struct drm_i915_private *dev_priv = dev->dev_private;
6952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6953 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6954 uint32_t plane_bit = 0;
7c9017e5
JB		 6955 int ret;
6956
6957 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6958 if (ret)
83d4092b 6959 goto err;
7c9017e5 6960
cb05d8de
SV		 6961 switch(intel_crtc->plane) {
6962 case PLANE_A:
6963 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6964 break;
6965 case PLANE_B:
6966 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6967 break;
6968 case PLANE_C:
6969 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6970 break;
6971 default:
6972 WARN_ONCE(1, "unknown plane in flip command\n");
6973 ret = -ENODEV;
ab3951eb 6974 goto err_unpin;
cb05d8de
SV		 6975 }
6976
7c9017e5
JB		 6977 ret = intel_ring_begin(ring, 4);
6978 if (ret)
83d4092b 6979 goto err_unpin;
7c9017e5 6980
cb05d8de 6981 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6982 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6983 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6984 intel_ring_emit(ring, (MI_NOOP));
6985 intel_ring_advance(ring);
83d4092b
CW		 6986 return 0;
6987
6988err_unpin:
6989 intel_unpin_fb_obj(obj);
6990err:
7c9017e5
JB		 6991 return ret;
6992}
6993
8c9f3aaf
JB		 6994static int intel_default_queue_flip(struct drm_device *dev,
6995 struct drm_crtc *crtc,
6996 struct drm_framebuffer *fb,
6997 struct drm_i915_gem_object *obj)
6998{
6999 return -ENODEV;
7000}
7001
6b95a207
KH		 7002static int intel_crtc_page_flip(struct drm_crtc *crtc,
7003 struct drm_framebuffer *fb,
7004 struct drm_pending_vblank_event *event)
7005{
7006 struct drm_device *dev = crtc->dev;
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 struct intel_framebuffer *intel_fb;
05394f39 7009 struct drm_i915_gem_object *obj;
6b95a207
KH		 7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7011 struct intel_unpin_work *work;
8c9f3aaf 7012 unsigned long flags;
52e68630 7013 int ret;
6b95a207 7014
e6a595d2
VS		 7015 /* Can't change pixel format via MI display flips. */
7016 if (fb->pixel_format != crtc->fb->pixel_format)
7017 return -EINVAL;
7018
7019 /*
7020 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7021 * Note that pitch changes could also affect these register.
7022 */
7023 if (INTEL_INFO(dev)->gen > 3 &&
7024 (fb->offsets[0] != crtc->fb->offsets[0] ||
7025 fb->pitches[0] != crtc->fb->pitches[0]))
7026 return -EINVAL;
7027
6b95a207
KH		 7028 work = kzalloc(sizeof *work, GFP_KERNEL);
7029 if (work == NULL)
7030 return -ENOMEM;
7031
6b95a207
KH		 7032 work->event = event;
7033 work->dev = crtc->dev;
7034 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7035 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7036 INIT_WORK(&work->work, intel_unpin_work_fn);
7037
7317c75e
JB		 7038 ret = drm_vblank_get(dev, intel_crtc->pipe);
7039 if (ret)
7040 goto free_work;
7041
6b95a207
KH		 7042 /* We borrow the event spin lock for protecting unpin_work */
7043 spin_lock_irqsave(&dev->event_lock, flags);
7044 if (intel_crtc->unpin_work) {
7045 spin_unlock_irqrestore(&dev->event_lock, flags);
7046 kfree(work);
7317c75e 7047 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7048
7049 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7050 return -EBUSY;
7051 }
7052 intel_crtc->unpin_work = work;
7053 spin_unlock_irqrestore(&dev->event_lock, flags);
7054
7055 intel_fb = to_intel_framebuffer(fb);
7056 obj = intel_fb->obj;
7057
79158103
CW		 7058 ret = i915_mutex_lock_interruptible(dev);
7059 if (ret)
7060 goto cleanup;
6b95a207 7061
75dfca80 7062 /* Reference the objects for the scheduled work. */
05394f39
CW		 7063 drm_gem_object_reference(&work->old_fb_obj->base);
7064 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7065
7066 crtc->fb = fb;
96b099fd 7067
e1f99ce6 7068 work->pending_flip_obj = obj;
e1f99ce6 7069
4e5359cd
SF		 7070 work->enable_stall_check = true;
7071
e1f99ce6
CW		 7072 /* Block clients from rendering to the new back buffer until
7073 * the flip occurs and the object is no longer visible.
7074 */
05394f39 7075 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7076
8c9f3aaf
JB		 7077 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7078 if (ret)
7079 goto cleanup_pending;
6b95a207 7080
7782de3b 7081 intel_disable_fbc(dev);
f047e395 7082 intel_mark_fb_busy(obj);
6b95a207
KH		 7083 mutex_unlock(&dev->struct_mutex);
7084
e5510fac
JB		 7085 trace_i915_flip_request(intel_crtc->plane, obj);
7086
6b95a207 7087 return 0;
96b099fd 7088
8c9f3aaf
JB		 7089cleanup_pending:
7090 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7091 drm_gem_object_unreference(&work->old_fb_obj->base);
7092 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7093 mutex_unlock(&dev->struct_mutex);
7094
79158103 7095cleanup:
96b099fd
CW		 7096 spin_lock_irqsave(&dev->event_lock, flags);
7097 intel_crtc->unpin_work = NULL;
7098 spin_unlock_irqrestore(&dev->event_lock, flags);
7099
7317c75e
JB		 7100 drm_vblank_put(dev, intel_crtc->pipe);
7101free_work:
96b099fd
CW		 7102 kfree(work);
7103
7104 return ret;
6b95a207
KH		 7105}
7106
f6e5b160 7107static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7108 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7109 .load_lut = intel_crtc_load_lut,
976f8a20 7110 .disable = intel_crtc_noop,
f6e5b160
CW		 7111};
7112
6ed0f796 7113bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7114{
6ed0f796
SV		 7115 struct intel_encoder *other_encoder;
7116 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7117
6ed0f796
SV		 7118 if (WARN_ON(!crtc))
7119 return false;
7120
7121 list_for_each_entry(other_encoder,
7122 &crtc->dev->mode_config.encoder_list,
7123 base.head) {
7124
7125 if (&other_encoder->new_crtc->base != crtc ||
7126 encoder == other_encoder)
7127 continue;
7128 else
7129 return true;
f47166d2
CW		 7130 }
7131
6ed0f796
SV		 7132 return false;
7133}
47f1c6c9 7134
50f56119
SV		 7135static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7136 struct drm_crtc *crtc)
7137{
7138 struct drm_device *dev;
7139 struct drm_crtc *tmp;
7140 int crtc_mask = 1;
47f1c6c9 7141
50f56119 7142 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7143
50f56119 7144 dev = crtc->dev;
47f1c6c9 7145
50f56119
SV		 7146 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7147 if (tmp == crtc)
7148 break;
7149 crtc_mask <<= 1;
7150 }
47f1c6c9 7151
50f56119
SV		 7152 if (encoder->possible_crtcs & crtc_mask)
7153 return true;
7154 return false;
47f1c6c9 7155}
79e53945 7156
9a935856
SV		 7157/**
7158 * intel_modeset_update_staged_output_state
7159 *
7160 * Updates the staged output configuration state, e.g. after we've read out the
7161 * current hw state.
7162 */
7163static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7164{
9a935856
SV		 7165 struct intel_encoder *encoder;
7166 struct intel_connector *connector;
f6e5b160 7167
9a935856
SV		 7168 list_for_each_entry(connector, &dev->mode_config.connector_list,
7169 base.head) {
7170 connector->new_encoder =
7171 to_intel_encoder(connector->base.encoder);
7172 }
f6e5b160 7173
9a935856
SV		 7174 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7175 base.head) {
7176 encoder->new_crtc =
7177 to_intel_crtc(encoder->base.crtc);
7178 }
f6e5b160
CW		 7179}
7180
9a935856
SV		 7181/**
7182 * intel_modeset_commit_output_state
7183 *
7184 * This function copies the stage display pipe configuration to the real one.
7185 */
7186static void intel_modeset_commit_output_state(struct drm_device *dev)
7187{
7188 struct intel_encoder *encoder;
7189 struct intel_connector *connector;
f6e5b160 7190
9a935856
SV		 7191 list_for_each_entry(connector, &dev->mode_config.connector_list,
7192 base.head) {
7193 connector->base.encoder = &connector->new_encoder->base;
7194 }
f6e5b160 7195
9a935856
SV		 7196 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7197 base.head) {
7198 encoder->base.crtc = &encoder->new_crtc->base;
7199 }
7200}
7201
7758a113
SV		 7202static struct drm_display_mode *
7203intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7204 struct drm_display_mode *mode)
ee7b9f93 7205{
7758a113
SV		 7206 struct drm_device *dev = crtc->dev;
7207 struct drm_display_mode *adjusted_mode;
7208 struct drm_encoder_helper_funcs *encoder_funcs;
7209 struct intel_encoder *encoder;
ee7b9f93 7210
7758a113
SV		 7211 adjusted_mode = drm_mode_duplicate(dev, mode);
7212 if (!adjusted_mode)
7213 return ERR_PTR(-ENOMEM);
7214
7215 /* Pass our mode to the connectors and the CRTC to give them a chance to
7216 * adjust it according to limitations or connector properties, and also
7217 * a chance to reject the mode entirely.
7218 */
7219 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7220 base.head) {
7221
7222 if (&encoder->new_crtc->base != crtc)
7223 continue;
7224 encoder_funcs = encoder->base.helper_private;
7225 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7226 adjusted_mode))) {
7227 DRM_DEBUG_KMS("Encoder fixup failed\n");
7228 goto fail;
7229 }
ee7b9f93
JB		 7230 }
7231
7758a113
SV		 7232 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7233 DRM_DEBUG_KMS("CRTC fixup failed\n");
7234 goto fail;
ee7b9f93 7235 }
7758a113
SV		 7236 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7237
7238 return adjusted_mode;
7239fail:
7240 drm_mode_destroy(dev, adjusted_mode);
7241 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7242}
7243
e2e1ed41
SV		 7244/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7245 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7246static void
7247intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7248 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7249{
7250 struct intel_crtc *intel_crtc;
e2e1ed41
SV		 7251 struct drm_device *dev = crtc->dev;
7252 struct intel_encoder *encoder;
7253 struct intel_connector *connector;
7254 struct drm_crtc *tmp_crtc;
79e53945 7255
e2e1ed41 7256 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7257
e2e1ed41
SV		 7258 /* Check which crtcs have changed outputs connected to them, these need
7259 * to be part of the prepare_pipes mask. We don't (yet) support global
7260 * modeset across multiple crtcs, so modeset_pipes will only have one
7261 * bit set at most. */
7262 list_for_each_entry(connector, &dev->mode_config.connector_list,
7263 base.head) {
7264 if (connector->base.encoder == &connector->new_encoder->base)
7265 continue;
79e53945 7266
e2e1ed41
SV		 7267 if (connector->base.encoder) {
7268 tmp_crtc = connector->base.encoder->crtc;
7269
7270 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7271 }
7272
7273 if (connector->new_encoder)
7274 *prepare_pipes |=
7275 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7276 }
7277
e2e1ed41
SV		 7278 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7279 base.head) {
7280 if (encoder->base.crtc == &encoder->new_crtc->base)
7281 continue;
7282
7283 if (encoder->base.crtc) {
7284 tmp_crtc = encoder->base.crtc;
7285
7286 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7287 }
7288
7289 if (encoder->new_crtc)
7290 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7291 }
7292
e2e1ed41
SV		 7293 /* Check for any pipes that will be fully disabled ... */
7294 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7295 base.head) {
7296 bool used = false;
22fd0fab 7297
e2e1ed41
SV		 7298 /* Don't try to disable disabled crtcs. */
7299 if (!intel_crtc->base.enabled)
7300 continue;
7e7d76c3 7301
e2e1ed41
SV		 7302 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7303 base.head) {
7304 if (encoder->new_crtc == intel_crtc)
7305 used = true;
7306 }
7307
7308 if (!used)
7309 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7310 }
7311
e2e1ed41
SV		 7312
7313 /* set_mode is also used to update properties on life display pipes. */
7314 intel_crtc = to_intel_crtc(crtc);
7315 if (crtc->enabled)
7316 *prepare_pipes |= 1 << intel_crtc->pipe;
7317
7318 /* We only support modeset on one single crtc, hence we need to do that
7319 * only for the passed in crtc iff we change anything else than just
7320 * disable crtcs.
7321 *
7322 * This is actually not true, to be fully compatible with the old crtc
7323 * helper we automatically disable _any_ output (i.e. doesn't need to be
7324 * connected to the crtc we're modesetting on) if it's disconnected.
7325 * Which is a rather nutty api (since changed the output configuration
7326 * without userspace's explicit request can lead to confusion), but
7327 * alas. Hence we currently need to modeset on all pipes we prepare. */
7328 if (*prepare_pipes)
7329 *modeset_pipes = *prepare_pipes;
7330
7331 /* ... and mask these out. */
7332 *modeset_pipes &= ~(*disable_pipes);
7333 *prepare_pipes &= ~(*disable_pipes);
7334}
7335
ea9d758d
SV		 7336static bool intel_crtc_in_use(struct drm_crtc *crtc)
7337{
7338 struct drm_encoder *encoder;
7339 struct drm_device *dev = crtc->dev;
7340
7341 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7342 if (encoder->crtc == crtc)
7343 return true;
7344
7345 return false;
7346}
7347
7348static void
7349intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7350{
7351 struct intel_encoder *intel_encoder;
7352 struct intel_crtc *intel_crtc;
7353 struct drm_connector *connector;
7354
7355 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7356 base.head) {
7357 if (!intel_encoder->base.crtc)
7358 continue;
7359
7360 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7361
7362 if (prepare_pipes & (1 << intel_crtc->pipe))
7363 intel_encoder->connectors_active = false;
7364 }
7365
7366 intel_modeset_commit_output_state(dev);
7367
7368 /* Update computed state. */
7369 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7370 base.head) {
7371 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7372 }
7373
7374 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7375 if (!connector->encoder || !connector->encoder->crtc)
7376 continue;
7377
7378 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7379
7380 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
SV		 7381 struct drm_property *dpms_property =
7382 dev->mode_config.dpms_property;
7383
ea9d758d 7384 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
SV		 7385 drm_connector_property_set_value(connector,
7386 dpms_property,
7387 DRM_MODE_DPMS_ON);
ea9d758d
SV		 7388
7389 intel_encoder = to_intel_encoder(connector->encoder);
7390 intel_encoder->connectors_active = true;
7391 }
7392 }
7393
7394}
7395
25c5b266
SV		 7396#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7397 list_for_each_entry((intel_crtc), \
7398 &(dev)->mode_config.crtc_list, \
7399 base.head) \
7400 if (mask & (1 <<(intel_crtc)->pipe)) \
7401
b980514c 7402void
8af6cf88
SV		 7403intel_modeset_check_state(struct drm_device *dev)
7404{
7405 struct intel_crtc *crtc;
7406 struct intel_encoder *encoder;
7407 struct intel_connector *connector;
7408
7409 list_for_each_entry(connector, &dev->mode_config.connector_list,
7410 base.head) {
7411 /* This also checks the encoder/connector hw state with the
7412 * ->get_hw_state callbacks. */
7413 intel_connector_check_state(connector);
7414
7415 WARN(&connector->new_encoder->base != connector->base.encoder,
7416 "connector's staged encoder doesn't match current encoder\n");
7417 }
7418
7419 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7420 base.head) {
7421 bool enabled = false;
7422 bool active = false;
7423 enum pipe pipe, tracked_pipe;
7424
7425 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7426 encoder->base.base.id,
7427 drm_get_encoder_name(&encoder->base));
7428
7429 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7430 "encoder's stage crtc doesn't match current crtc\n");
7431 WARN(encoder->connectors_active && !encoder->base.crtc,
7432 "encoder's active_connectors set, but no crtc\n");
7433
7434 list_for_each_entry(connector, &dev->mode_config.connector_list,
7435 base.head) {
7436 if (connector->base.encoder != &encoder->base)
7437 continue;
7438 enabled = true;
7439 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7440 active = true;
7441 }
7442 WARN(!!encoder->base.crtc != enabled,
7443 "encoder's enabled state mismatch "
7444 "(expected %i, found %i)\n",
7445 !!encoder->base.crtc, enabled);
7446 WARN(active && !encoder->base.crtc,
7447 "active encoder with no crtc\n");
7448
7449 WARN(encoder->connectors_active != active,
7450 "encoder's computed active state doesn't match tracked active state "
7451 "(expected %i, found %i)\n", active, encoder->connectors_active);
7452
7453 active = encoder->get_hw_state(encoder, &pipe);
7454 WARN(active != encoder->connectors_active,
7455 "encoder's hw state doesn't match sw tracking "
7456 "(expected %i, found %i)\n",
7457 encoder->connectors_active, active);
7458
7459 if (!encoder->base.crtc)
7460 continue;
7461
7462 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7463 WARN(active && pipe != tracked_pipe,
7464 "active encoder's pipe doesn't match"
7465 "(expected %i, found %i)\n",
7466 tracked_pipe, pipe);
7467
7468 }
7469
7470 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7471 base.head) {
7472 bool enabled = false;
7473 bool active = false;
7474
7475 DRM_DEBUG_KMS("[CRTC:%d]\n",
7476 crtc->base.base.id);
7477
7478 WARN(crtc->active && !crtc->base.enabled,
7479 "active crtc, but not enabled in sw tracking\n");
7480
7481 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7482 base.head) {
7483 if (encoder->base.crtc != &crtc->base)
7484 continue;
7485 enabled = true;
7486 if (encoder->connectors_active)
7487 active = true;
7488 }
7489 WARN(active != crtc->active,
7490 "crtc's computed active state doesn't match tracked active state "
7491 "(expected %i, found %i)\n", active, crtc->active);
7492 WARN(enabled != crtc->base.enabled,
7493 "crtc's computed enabled state doesn't match tracked enabled state "
7494 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7495
7496 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7497 }
7498}
7499
a6778b3c
SV		 7500bool intel_set_mode(struct drm_crtc *crtc,
7501 struct drm_display_mode *mode,
94352cf9 7502 int x, int y, struct drm_framebuffer *fb)
a6778b3c
SV		 7503{
7504 struct drm_device *dev = crtc->dev;
dbf2b54e 7505 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7506 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 7507 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 7508 struct drm_encoder *encoder;
25c5b266
SV		 7509 struct intel_crtc *intel_crtc;
7510 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
SV		 7511 bool ret = true;
7512
e2e1ed41 7513 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
SV		 7514 &prepare_pipes, &disable_pipes);
7515
7516 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7517 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7518
976f8a20
SV		 7519 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7520 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7521
a6778b3c
SV		 7522 saved_hwmode = crtc->hwmode;
7523 saved_mode = crtc->mode;
a6778b3c 7524
25c5b266
SV		 7525 /* Hack: Because we don't (yet) support global modeset on multiple
7526 * crtcs, we don't keep track of the new mode for more than one crtc.
7527 * Hence simply check whether any bit is set in modeset_pipes in all the
7528 * pieces of code that are not yet converted to deal with mutliple crtcs
7529 * changing their mode at the same time. */
7530 adjusted_mode = NULL;
7531 if (modeset_pipes) {
7532 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7533 if (IS_ERR(adjusted_mode)) {
7534 return false;
7535 }
25c5b266 7536 }
a6778b3c 7537
ea9d758d
SV		 7538 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7539 if (intel_crtc->base.enabled)
7540 dev_priv->display.crtc_disable(&intel_crtc->base);
7541 }
a6778b3c 7542
6c4c86f5
SV		 7543 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7544 * to set it here already despite that we pass it down the callchain.
7545 */
7546 if (modeset_pipes)
25c5b266 7547 crtc->mode = *mode;
7758a113 7548
ea9d758d
SV		 7549 /* Only after disabling all output pipelines that will be changed can we
7550 * update the the output configuration. */
7551 intel_modeset_update_state(dev, prepare_pipes);
7552
a6778b3c
SV		 7553 /* Set up the DPLL and any encoders state that needs to adjust or depend
7554 * on the DPLL.
7555 */
25c5b266
SV		 7556 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7557 ret = !intel_crtc_mode_set(&intel_crtc->base,
7558 mode, adjusted_mode,
7559 x, y, fb);
7560 if (!ret)
7561 goto done;
a6778b3c 7562
25c5b266 7563 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7564
25c5b266
SV		 7565 if (encoder->crtc != &intel_crtc->base)
7566 continue;
a6778b3c 7567
25c5b266
SV		 7568 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7569 encoder->base.id, drm_get_encoder_name(encoder),
7570 mode->base.id, mode->name);
7571 encoder_funcs = encoder->helper_private;
7572 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7573 }
a6778b3c
SV		 7574 }
7575
7576 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
SV		 7577 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7578 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7579
25c5b266
SV		 7580 if (modeset_pipes) {
7581 /* Store real post-adjustment hardware mode. */
7582 crtc->hwmode = *adjusted_mode;
a6778b3c 7583
25c5b266
SV		 7584 /* Calculate and store various constants which
7585 * are later needed by vblank and swap-completion
7586 * timestamping. They are derived from true hwmode.
7587 */
7588 drm_calc_timestamping_constants(crtc);
7589 }
a6778b3c
SV		 7590
7591 /* FIXME: add subpixel order */
7592done:
7593 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7594 if (!ret && crtc->enabled) {
a6778b3c
SV		 7595 crtc->hwmode = saved_hwmode;
7596 crtc->mode = saved_mode;
8af6cf88
SV		 7597 } else {
7598 intel_modeset_check_state(dev);
a6778b3c
SV		 7599 }
7600
7601 return ret;
7602}
7603
25c5b266
SV		 7604#undef for_each_intel_crtc_masked
7605
d9e55608
SV		 7606static void intel_set_config_free(struct intel_set_config *config)
7607{
7608 if (!config)
7609 return;
7610
1aa4b628
SV		 7611 kfree(config->save_connector_encoders);
7612 kfree(config->save_encoder_crtcs);
d9e55608
SV		 7613 kfree(config);
7614}
7615
85f9eb71
SV		 7616static int intel_set_config_save_state(struct drm_device *dev,
7617 struct intel_set_config *config)
7618{
85f9eb71
SV		 7619 struct drm_encoder *encoder;
7620 struct drm_connector *connector;
7621 int count;
7622
1aa4b628
SV		 7623 config->save_encoder_crtcs =
7624 kcalloc(dev->mode_config.num_encoder,
7625 sizeof(struct drm_crtc *), GFP_KERNEL);
7626 if (!config->save_encoder_crtcs)
85f9eb71
SV		 7627 return -ENOMEM;
7628
1aa4b628
SV		 7629 config->save_connector_encoders =
7630 kcalloc(dev->mode_config.num_connector,
7631 sizeof(struct drm_encoder *), GFP_KERNEL);
7632 if (!config->save_connector_encoders)
85f9eb71
SV		 7633 return -ENOMEM;
7634
7635 /* Copy data. Note that driver private data is not affected.
7636 * Should anything bad happen only the expected state is
7637 * restored, not the drivers personal bookkeeping.
7638 */
85f9eb71
SV		 7639 count = 0;
7640 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7641 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
SV		 7642 }
7643
7644 count = 0;
7645 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7646 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
SV		 7647 }
7648
7649 return 0;
7650}
7651
7652static void intel_set_config_restore_state(struct drm_device *dev,
7653 struct intel_set_config *config)
7654{
9a935856
SV		 7655 struct intel_encoder *encoder;
7656 struct intel_connector *connector;
85f9eb71
SV		 7657 int count;
7658
85f9eb71 7659 count = 0;
9a935856
SV		 7660 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7661 encoder->new_crtc =
7662 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
SV		 7663 }
7664
7665 count = 0;
9a935856
SV		 7666 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7667 connector->new_encoder =
7668 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
SV		 7669 }
7670}
7671
5e2b584e
SV		 7672static void
7673intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7674 struct intel_set_config *config)
7675{
7676
7677 /* We should be able to check here if the fb has the same properties
7678 * and then just flip_or_move it */
7679 if (set->crtc->fb != set->fb) {
7680 /* If we have no fb then treat it as a full mode set */
7681 if (set->crtc->fb == NULL) {
7682 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7683 config->mode_changed = true;
7684 } else if (set->fb == NULL) {
7685 config->mode_changed = true;
7686 } else if (set->fb->depth != set->crtc->fb->depth) {
7687 config->mode_changed = true;
7688 } else if (set->fb->bits_per_pixel !=
7689 set->crtc->fb->bits_per_pixel) {
7690 config->mode_changed = true;
7691 } else
7692 config->fb_changed = true;
7693 }
7694
835c5873 7695 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
SV		 7696 config->fb_changed = true;
7697
7698 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7699 DRM_DEBUG_KMS("modes are different, full mode set\n");
7700 drm_mode_debug_printmodeline(&set->crtc->mode);
7701 drm_mode_debug_printmodeline(set->mode);
7702 config->mode_changed = true;
7703 }
7704}
7705
2e431051 7706static int
9a935856
SV		 7707intel_modeset_stage_output_state(struct drm_device *dev,
7708 struct drm_mode_set *set,
7709 struct intel_set_config *config)
50f56119 7710{
85f9eb71 7711 struct drm_crtc *new_crtc;
9a935856
SV		 7712 struct intel_connector *connector;
7713 struct intel_encoder *encoder;
2e431051 7714 int count, ro;
50f56119 7715
9a935856
SV		 7716 /* The upper layers ensure that we either disabl a crtc or have a list
7717 * of connectors. For paranoia, double-check this. */
7718 WARN_ON(!set->fb && (set->num_connectors != 0));
7719 WARN_ON(set->fb && (set->num_connectors == 0));
7720
50f56119 7721 count = 0;
9a935856
SV		 7722 list_for_each_entry(connector, &dev->mode_config.connector_list,
7723 base.head) {
7724 /* Otherwise traverse passed in connector list and get encoders
7725 * for them. */
50f56119 7726 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
SV		 7727 if (set->connectors[ro] == &connector->base) {
7728 connector->new_encoder = connector->encoder;
50f56119
SV		 7729 break;
7730 }
7731 }
7732
9a935856
SV		 7733 /* If we disable the crtc, disable all its connectors. Also, if
7734 * the connector is on the changing crtc but not on the new
7735 * connector list, disable it. */
7736 if ((!set->fb || ro == set->num_connectors) &&
7737 connector->base.encoder &&
7738 connector->base.encoder->crtc == set->crtc) {
7739 connector->new_encoder = NULL;
7740
7741 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7742 connector->base.base.id,
7743 drm_get_connector_name(&connector->base));
7744 }
7745
7746
7747 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7748 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7749 config->mode_changed = true;
50f56119 7750 }
9a935856
SV		 7751
7752 /* Disable all disconnected encoders. */
7753 if (connector->base.status == connector_status_disconnected)
7754 connector->new_encoder = NULL;
50f56119 7755 }
9a935856 7756 /* connector->new_encoder is now updated for all connectors. */
50f56119 7757
9a935856 7758 /* Update crtc of enabled connectors. */
50f56119 7759 count = 0;
9a935856
SV		 7760 list_for_each_entry(connector, &dev->mode_config.connector_list,
7761 base.head) {
7762 if (!connector->new_encoder)
50f56119
SV		 7763 continue;
7764
9a935856 7765 new_crtc = connector->new_encoder->base.crtc;
50f56119
SV		 7766
7767 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7768 if (set->connectors[ro] == &connector->base)
50f56119
SV		 7769 new_crtc = set->crtc;
7770 }
7771
7772 /* Make sure the new CRTC will work with the encoder */
9a935856
SV		 7773 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7774 new_crtc)) {
5e2b584e 7775 return -EINVAL;
50f56119 7776 }
9a935856
SV		 7777 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7778
7779 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7780 connector->base.base.id,
7781 drm_get_connector_name(&connector->base),
7782 new_crtc->base.id);
7783 }
7784
7785 /* Check for any encoders that needs to be disabled. */
7786 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7787 base.head) {
7788 list_for_each_entry(connector,
7789 &dev->mode_config.connector_list,
7790 base.head) {
7791 if (connector->new_encoder == encoder) {
7792 WARN_ON(!connector->new_encoder->new_crtc);
7793
7794 goto next_encoder;
7795 }
7796 }
7797 encoder->new_crtc = NULL;
7798next_encoder:
7799 /* Only now check for crtc changes so we don't miss encoders
7800 * that will be disabled. */
7801 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7802 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7803 config->mode_changed = true;
50f56119
SV		 7804 }
7805 }
9a935856 7806 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7807
2e431051
SV		 7808 return 0;
7809}
7810
7811static int intel_crtc_set_config(struct drm_mode_set *set)
7812{
7813 struct drm_device *dev;
2e431051
SV		 7814 struct drm_mode_set save_set;
7815 struct intel_set_config *config;
7816 int ret;
2e431051 7817
8d3e375e
SV		 7818 BUG_ON(!set);
7819 BUG_ON(!set->crtc);
7820 BUG_ON(!set->crtc->helper_private);
2e431051
SV		 7821
7822 if (!set->mode)
7823 set->fb = NULL;
7824
431e50f7
SV		 7825 /* The fb helper likes to play gross jokes with ->mode_set_config.
7826 * Unfortunately the crtc helper doesn't do much at all for this case,
7827 * so we have to cope with this madness until the fb helper is fixed up. */
7828 if (set->fb && set->num_connectors == 0)
7829 return 0;
7830
2e431051
SV		 7831 if (set->fb) {
7832 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7833 set->crtc->base.id, set->fb->base.id,
7834 (int)set->num_connectors, set->x, set->y);
7835 } else {
7836 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
SV		 7837 }
7838
7839 dev = set->crtc->dev;
7840
7841 ret = -ENOMEM;
7842 config = kzalloc(sizeof(*config), GFP_KERNEL);
7843 if (!config)
7844 goto out_config;
7845
7846 ret = intel_set_config_save_state(dev, config);
7847 if (ret)
7848 goto out_config;
7849
7850 save_set.crtc = set->crtc;
7851 save_set.mode = &set->crtc->mode;
7852 save_set.x = set->crtc->x;
7853 save_set.y = set->crtc->y;
7854 save_set.fb = set->crtc->fb;
7855
7856 /* Compute whether we need a full modeset, only an fb base update or no
7857 * change at all. In the future we might also check whether only the
7858 * mode changed, e.g. for LVDS where we only change the panel fitter in
7859 * such cases. */
7860 intel_set_config_compute_mode_changes(set, config);
7861
9a935856 7862 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
SV		 7863 if (ret)
7864 goto fail;
7865
5e2b584e 7866 if (config->mode_changed) {
87f1faa6 7867 if (set->mode) {
50f56119
SV		 7868 DRM_DEBUG_KMS("attempting to set mode from"
7869 " userspace\n");
7870 drm_mode_debug_printmodeline(set->mode);
87f1faa6
SV		 7871 }
7872
7873 if (!intel_set_mode(set->crtc, set->mode,
7874 set->x, set->y, set->fb)) {
7875 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7876 set->crtc->base.id);
7877 ret = -EINVAL;
7878 goto fail;
7879 }
5e2b584e 7880 } else if (config->fb_changed) {
4f660f49 7881 ret = intel_pipe_set_base(set->crtc,
94352cf9 7882 set->x, set->y, set->fb);
50f56119
SV		 7883 }
7884
d9e55608
SV		 7885 intel_set_config_free(config);
7886
50f56119
SV		 7887 return 0;
7888
7889fail:
85f9eb71 7890 intel_set_config_restore_state(dev, config);
50f56119
SV		 7891
7892 /* Try to restore the config */
5e2b584e 7893 if (config->mode_changed &&
a6778b3c
SV		 7894 !intel_set_mode(save_set.crtc, save_set.mode,
7895 save_set.x, save_set.y, save_set.fb))
50f56119
SV		 7896 DRM_ERROR("failed to restore config after modeset failure\n");
7897
d9e55608
SV		 7898out_config:
7899 intel_set_config_free(config);
50f56119
SV		 7900 return ret;
7901}
7902
f6e5b160 7903static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7904 .cursor_set = intel_crtc_cursor_set,
7905 .cursor_move = intel_crtc_cursor_move,
7906 .gamma_set = intel_crtc_gamma_set,
50f56119 7907 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7908 .destroy = intel_crtc_destroy,
7909 .page_flip = intel_crtc_page_flip,
7910};
7911
79f689aa
PZ		 7912static void intel_cpu_pll_init(struct drm_device *dev)
7913{
7914 if (IS_HASWELL(dev))
7915 intel_ddi_pll_init(dev);
7916}
7917
ee7b9f93
JB		 7918static void intel_pch_pll_init(struct drm_device *dev)
7919{
7920 drm_i915_private_t *dev_priv = dev->dev_private;
7921 int i;
7922
7923 if (dev_priv->num_pch_pll == 0) {
7924 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7925 return;
7926 }
7927
7928 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7929 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7930 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7931 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7932 }
7933}
7934
b358d0a6 7935static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7936{
22fd0fab 7937 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7938 struct intel_crtc *intel_crtc;
7939 int i;
7940
7941 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7942 if (intel_crtc == NULL)
7943 return;
7944
7945 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7946
7947 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7948 for (i = 0; i < 256; i++) {
7949 intel_crtc->lut_r[i] = i;
7950 intel_crtc->lut_g[i] = i;
7951 intel_crtc->lut_b[i] = i;
7952 }
7953
80824003
JB		 7954 /* Swap pipes & planes for FBC on pre-965 */
7955 intel_crtc->pipe = pipe;
7956 intel_crtc->plane = pipe;
a5c961d1 7957 intel_crtc->cpu_transcoder = pipe;
e2e767ab 7958 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7959 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7960 intel_crtc->plane = !pipe;
80824003
JB		 7961 }
7962
22fd0fab
JB		 7963 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7964 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7965 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7966 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7967
5a354204 7968 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7969
79e53945 7970 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7971}
7972
08d7b3d1 7973int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7974 struct drm_file *file)
08d7b3d1 7975{
08d7b3d1 7976 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
SV		 7977 struct drm_mode_object *drmmode_obj;
7978 struct intel_crtc *crtc;
08d7b3d1 7979
1cff8f6b
SV		 7980 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7981 return -ENODEV;
08d7b3d1 7982
c05422d5
SV		 7983 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7984 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7985
c05422d5 7986 if (!drmmode_obj) {
08d7b3d1
CW		 7987 DRM_ERROR("no such CRTC id\n");
7988 return -EINVAL;
7989 }
7990
c05422d5
SV		 7991 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7992 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7993
c05422d5 7994 return 0;
08d7b3d1
CW		 7995}
7996
66a9278e 7997static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7998{
66a9278e
SV		 7999 struct drm_device *dev = encoder->base.dev;
8000 struct intel_encoder *source_encoder;
79e53945 8001 int index_mask = 0;
79e53945
JB		 8002 int entry = 0;
8003
66a9278e
SV		 8004 list_for_each_entry(source_encoder,
8005 &dev->mode_config.encoder_list, base.head) {
8006
8007 if (encoder == source_encoder)
79e53945 8008 index_mask |= (1 << entry);
66a9278e
SV		 8009
8010 /* Intel hw has only one MUX where enocoders could be cloned. */
8011 if (encoder->cloneable && source_encoder->cloneable)
8012 index_mask |= (1 << entry);
8013
79e53945
JB		 8014 entry++;
8015 }
4ef69c7a 8016
79e53945
JB		 8017 return index_mask;
8018}
8019
4d302442
CW		 8020static bool has_edp_a(struct drm_device *dev)
8021{
8022 struct drm_i915_private *dev_priv = dev->dev_private;
8023
8024 if (!IS_MOBILE(dev))
8025 return false;
8026
8027 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8028 return false;
8029
8030 if (IS_GEN5(dev) &&
8031 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8032 return false;
8033
8034 return true;
8035}
8036
79e53945
JB		 8037static void intel_setup_outputs(struct drm_device *dev)
8038{
725e30ad 8039 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8040 struct intel_encoder *encoder;
cb0953d7 8041 bool dpd_is_edp = false;
f3cfcba6 8042 bool has_lvds;
79e53945 8043
f3cfcba6 8044 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8045 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8046 /* disable the panel fitter on everything but LVDS */
8047 I915_WRITE(PFIT_CONTROL, 0);
8048 }
79e53945 8049
bad720ff 8050 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8051 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8052
4d302442 8053 if (has_edp_a(dev))
ab9d7c30 8054 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8055
cb0953d7 8056 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8057 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8058 }
8059
8060 intel_crt_init(dev);
8061
0e72a5b5
ED		 8062 if (IS_HASWELL(dev)) {
8063 int found;
8064
8065 /* Haswell uses DDI functions to detect digital outputs */
8066 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8067 /* DDI A only supports eDP */
8068 if (found)
8069 intel_ddi_init(dev, PORT_A);
8070
8071 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8072 * register */
8073 found = I915_READ(SFUSE_STRAP);
8074
8075 if (found & SFUSE_STRAP_DDIB_DETECTED)
8076 intel_ddi_init(dev, PORT_B);
8077 if (found & SFUSE_STRAP_DDIC_DETECTED)
8078 intel_ddi_init(dev, PORT_C);
8079 if (found & SFUSE_STRAP_DDID_DETECTED)
8080 intel_ddi_init(dev, PORT_D);
8081 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8082 int found;
8083
30ad48b7 8084 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8085 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8086 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8087 if (!found)
08d644ad 8088 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8089 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8090 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8091 }
8092
8093 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8094 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8095
b708a1d5 8096 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8097 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8098
5eb08b69 8099 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8100 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8101
cb0953d7 8102 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8103 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8104 } else if (IS_VALLEYVIEW(dev)) {
8105 int found;
8106
19c03924
GB		 8107 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8108 if (I915_READ(DP_C) & DP_DETECTED)
8109 intel_dp_init(dev, DP_C, PORT_C);
8110
4a87d65d
JB		 8111 if (I915_READ(SDVOB) & PORT_DETECTED) {
8112 /* SDVOB multiplex with HDMIB */
8113 found = intel_sdvo_init(dev, SDVOB, true);
8114 if (!found)
08d644ad 8115 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8116 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8117 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8118 }
8119
8120 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8121 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8122
103a196f 8123 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8124 bool found = false;
7d57382e 8125
725e30ad 8126 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8127 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8128 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8129 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8130 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8131 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8132 }
27185ae1 8133
b01f2c3a
JB		 8134 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8135 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8136 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8137 }
725e30ad 8138 }
13520b05
KH		 8139
8140 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8141
b01f2c3a
JB		 8142 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8143 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8144 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8145 }
27185ae1
ML		 8146
8147 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8148
b01f2c3a
JB		 8149 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8150 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8151 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8152 }
8153 if (SUPPORTS_INTEGRATED_DP(dev)) {
8154 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8155 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8156 }
725e30ad 8157 }
27185ae1 8158
b01f2c3a
JB		 8159 if (SUPPORTS_INTEGRATED_DP(dev) &&
8160 (I915_READ(DP_D) & DP_DETECTED)) {
8161 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8162 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8163 }
bad720ff 8164 } else if (IS_GEN2(dev))
79e53945
JB		 8165 intel_dvo_init(dev);
8166
103a196f 8167 if (SUPPORTS_TV(dev))
79e53945
JB		 8168 intel_tv_init(dev);
8169
4ef69c7a
CW		 8170 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8171 encoder->base.possible_crtcs = encoder->crtc_mask;
8172 encoder->base.possible_clones =
66a9278e 8173 intel_encoder_clones(encoder);
79e53945 8174 }
47356eb6 8175
40579abe 8176 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8177 ironlake_init_pch_refclk(dev);
79e53945
JB		 8178}
8179
8180static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8181{
8182 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8183
8184 drm_framebuffer_cleanup(fb);
05394f39 8185 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8186
8187 kfree(intel_fb);
8188}
8189
8190static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8191 struct drm_file *file,
79e53945
JB		 8192 unsigned int *handle)
8193{
8194 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8195 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8196
05394f39 8197 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8198}
8199
8200static const struct drm_framebuffer_funcs intel_fb_funcs = {
8201 .destroy = intel_user_framebuffer_destroy,
8202 .create_handle = intel_user_framebuffer_create_handle,
8203};
8204
38651674
DA		 8205int intel_framebuffer_init(struct drm_device *dev,
8206 struct intel_framebuffer *intel_fb,
308e5bcb 8207 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8208 struct drm_i915_gem_object *obj)
79e53945 8209{
79e53945
JB		 8210 int ret;
8211
05394f39 8212 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8213 return -EINVAL;
8214
308e5bcb 8215 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8216 return -EINVAL;
8217
308e5bcb 8218 switch (mode_cmd->pixel_format) {
04b3924d
VS		 8219 case DRM_FORMAT_RGB332:
8220 case DRM_FORMAT_RGB565:
8221 case DRM_FORMAT_XRGB8888:
b250da79 8222 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 8223 case DRM_FORMAT_ARGB8888:
8224 case DRM_FORMAT_XRGB2101010:
8225 case DRM_FORMAT_ARGB2101010:
308e5bcb 8226 /* RGB formats are common across chipsets */
b5626747 8227 break;
04b3924d
VS		 8228 case DRM_FORMAT_YUYV:
8229 case DRM_FORMAT_UYVY:
8230 case DRM_FORMAT_YVYU:
8231 case DRM_FORMAT_VYUY:
57cd6508
CW		 8232 break;
8233 default:
aca25848
ED		 8234 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8235 mode_cmd->pixel_format);
57cd6508
CW		 8236 return -EINVAL;
8237 }
8238
79e53945
JB		 8239 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8240 if (ret) {
8241 DRM_ERROR("framebuffer init failed %d\n", ret);
8242 return ret;
8243 }
8244
8245 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8246 intel_fb->obj = obj;
79e53945
JB		 8247 return 0;
8248}
8249
79e53945
JB		 8250static struct drm_framebuffer *
8251intel_user_framebuffer_create(struct drm_device *dev,
8252 struct drm_file *filp,
308e5bcb 8253 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8254{
05394f39 8255 struct drm_i915_gem_object *obj;
79e53945 8256
308e5bcb
JB		 8257 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8258 mode_cmd->handles[0]));
c8725226 8259 if (&obj->base == NULL)
cce13ff7 8260 return ERR_PTR(-ENOENT);
79e53945 8261
d2dff872 8262 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8263}
8264
79e53945 8265static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8266 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8267 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8268};
8269
e70236a8
JB		 8270/* Set up chip specific display functions */
8271static void intel_init_display(struct drm_device *dev)
8272{
8273 struct drm_i915_private *dev_priv = dev->dev_private;
8274
8275 /* We always want a DPMS function */
09b4ddf9
PZ		 8276 if (IS_HASWELL(dev)) {
8277 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8278 dev_priv->display.crtc_enable = haswell_crtc_enable;
8279 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8280 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8281 dev_priv->display.update_plane = ironlake_update_plane;
8282 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8283 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
SV		 8284 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8285 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8286 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8287 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8288 } else {
f564048e 8289 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
SV		 8290 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8291 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8292 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8293 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8294 }
e70236a8 8295
e70236a8 8296 /* Returns the core display clock speed */
25eb05fc
JB		 8297 if (IS_VALLEYVIEW(dev))
8298 dev_priv->display.get_display_clock_speed =
8299 valleyview_get_display_clock_speed;
8300 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8301 dev_priv->display.get_display_clock_speed =
8302 i945_get_display_clock_speed;
8303 else if (IS_I915G(dev))
8304 dev_priv->display.get_display_clock_speed =
8305 i915_get_display_clock_speed;
f2b115e6 8306 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8307 dev_priv->display.get_display_clock_speed =
8308 i9xx_misc_get_display_clock_speed;
8309 else if (IS_I915GM(dev))
8310 dev_priv->display.get_display_clock_speed =
8311 i915gm_get_display_clock_speed;
8312 else if (IS_I865G(dev))
8313 dev_priv->display.get_display_clock_speed =
8314 i865_get_display_clock_speed;
f0f8a9ce 8315 else if (IS_I85X(dev))
e70236a8
JB		 8316 dev_priv->display.get_display_clock_speed =
8317 i855_get_display_clock_speed;
8318 else /* 852, 830 */
8319 dev_priv->display.get_display_clock_speed =
8320 i830_get_display_clock_speed;
8321
7f8a8569 8322 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8323 if (IS_GEN5(dev)) {
674cf967 8324 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8325 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8326 } else if (IS_GEN6(dev)) {
674cf967 8327 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8328 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8329 } else if (IS_IVYBRIDGE(dev)) {
8330 /* FIXME: detect B0+ stepping and use auto training */
8331 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8332 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 8333 } else if (IS_HASWELL(dev)) {
8334 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8335 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8336 } else
8337 dev_priv->display.update_wm = NULL;
6067aaea 8338 } else if (IS_G4X(dev)) {
e0dac65e 8339 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8340 }
8c9f3aaf
JB		 8341
8342 /* Default just returns -ENODEV to indicate unsupported */
8343 dev_priv->display.queue_flip = intel_default_queue_flip;
8344
8345 switch (INTEL_INFO(dev)->gen) {
8346 case 2:
8347 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8348 break;
8349
8350 case 3:
8351 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8352 break;
8353
8354 case 4:
8355 case 5:
8356 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8357 break;
8358
8359 case 6:
8360 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8361 break;
7c9017e5
JB		 8362 case 7:
8363 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8364 break;
8c9f3aaf 8365 }
e70236a8
JB		 8366}
8367
b690e96c
JB		 8368/*
8369 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8370 * resume, or other times. This quirk makes sure that's the case for
8371 * affected systems.
8372 */
0206e353 8373static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8374{
8375 struct drm_i915_private *dev_priv = dev->dev_private;
8376
8377 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8378 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8379}
8380
435793df
KP		 8381/*
8382 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8383 */
8384static void quirk_ssc_force_disable(struct drm_device *dev)
8385{
8386 struct drm_i915_private *dev_priv = dev->dev_private;
8387 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8388 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8389}
8390
4dca20ef 8391/*
5a15ab5b
CE		 8392 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8393 * brightness value
4dca20ef
CE		 8394 */
8395static void quirk_invert_brightness(struct drm_device *dev)
8396{
8397 struct drm_i915_private *dev_priv = dev->dev_private;
8398 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8399 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8400}
8401
b690e96c
JB		 8402struct intel_quirk {
8403 int device;
8404 int subsystem_vendor;
8405 int subsystem_device;
8406 void (*hook)(struct drm_device *dev);
8407};
8408
c43b5634 8409static struct intel_quirk intel_quirks[] = {
b690e96c 8410 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8411 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8412
b690e96c
JB		 8413 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8414 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8415
b690e96c
JB		 8416 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8417 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8418
ccd0d36e 8419 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8420 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8421 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8422
8423 /* Lenovo U160 cannot use SSC on LVDS */
8424 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8425
8426 /* Sony Vaio Y cannot use SSC on LVDS */
8427 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8428
8429 /* Acer Aspire 5734Z must invert backlight brightness */
8430 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8431};
8432
8433static void intel_init_quirks(struct drm_device *dev)
8434{
8435 struct pci_dev *d = dev->pdev;
8436 int i;
8437
8438 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8439 struct intel_quirk *q = &intel_quirks[i];
8440
8441 if (d->device == q->device &&
8442 (d->subsystem_vendor == q->subsystem_vendor ||
8443 q->subsystem_vendor == PCI_ANY_ID) &&
8444 (d->subsystem_device == q->subsystem_device ||
8445 q->subsystem_device == PCI_ANY_ID))
8446 q->hook(dev);
8447 }
8448}
8449
9cce37f4
JB		 8450/* Disable the VGA plane that we never use */
8451static void i915_disable_vga(struct drm_device *dev)
8452{
8453 struct drm_i915_private *dev_priv = dev->dev_private;
8454 u8 sr1;
8455 u32 vga_reg;
8456
8457 if (HAS_PCH_SPLIT(dev))
8458 vga_reg = CPU_VGACNTRL;
8459 else
8460 vga_reg = VGACNTRL;
8461
8462 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8463 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8464 sr1 = inb(VGA_SR_DATA);
8465 outb(sr1 | 1<<5, VGA_SR_DATA);
8466 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8467 udelay(300);
8468
8469 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8470 POSTING_READ(vga_reg);
8471}
8472
f817586c
SV		 8473void intel_modeset_init_hw(struct drm_device *dev)
8474{
0232e927
ED		 8475 /* We attempt to init the necessary power wells early in the initialization
8476 * time, so the subsystems that expect power to be enabled can work.
8477 */
8478 intel_init_power_wells(dev);
8479
a8f78b58
ED		 8480 intel_prepare_ddi(dev);
8481
f817586c
SV		 8482 intel_init_clock_gating(dev);
8483
79f5b2c7 8484 mutex_lock(&dev->struct_mutex);
8090c6b9 8485 intel_enable_gt_powersave(dev);
79f5b2c7 8486 mutex_unlock(&dev->struct_mutex);
f817586c
SV		 8487}
8488
79e53945
JB		 8489void intel_modeset_init(struct drm_device *dev)
8490{
652c393a 8491 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8492 int i, ret;
79e53945
JB		 8493
8494 drm_mode_config_init(dev);
8495
8496 dev->mode_config.min_width = 0;
8497 dev->mode_config.min_height = 0;
8498
019d96cb
DA		 8499 dev->mode_config.preferred_depth = 24;
8500 dev->mode_config.prefer_shadow = 1;
8501
e6ecefaa 8502 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8503
b690e96c
JB		 8504 intel_init_quirks(dev);
8505
1fa61106
ED		 8506 intel_init_pm(dev);
8507
e70236a8
JB		 8508 intel_init_display(dev);
8509
a6c45cf0
CW		 8510 if (IS_GEN2(dev)) {
8511 dev->mode_config.max_width = 2048;
8512 dev->mode_config.max_height = 2048;
8513 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8514 dev->mode_config.max_width = 4096;
8515 dev->mode_config.max_height = 4096;
79e53945 8516 } else {
a6c45cf0
CW		 8517 dev->mode_config.max_width = 8192;
8518 dev->mode_config.max_height = 8192;
79e53945 8519 }
dd2757f8 8520 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8521
28c97730 8522 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8523 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8524
a3524f1b 8525 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8526 intel_crtc_init(dev, i);
00c2064b
JB		 8527 ret = intel_plane_init(dev, i);
8528 if (ret)
8529 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8530 }
8531
79f689aa 8532 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8533 intel_pch_pll_init(dev);
8534
9cce37f4
JB		 8535 /* Just disable it once at startup */
8536 i915_disable_vga(dev);
79e53945 8537 intel_setup_outputs(dev);
2c7111db
CW		 8538}
8539
24929352
SV		 8540static void
8541intel_connector_break_all_links(struct intel_connector *connector)
8542{
8543 connector->base.dpms = DRM_MODE_DPMS_OFF;
8544 connector->base.encoder = NULL;
8545 connector->encoder->connectors_active = false;
8546 connector->encoder->base.crtc = NULL;
8547}
8548
7fad798e
SV		 8549static void intel_enable_pipe_a(struct drm_device *dev)
8550{
8551 struct intel_connector *connector;
8552 struct drm_connector *crt = NULL;
8553 struct intel_load_detect_pipe load_detect_temp;
8554
8555 /* We can't just switch on the pipe A, we need to set things up with a
8556 * proper mode and output configuration. As a gross hack, enable pipe A
8557 * by enabling the load detect pipe once. */
8558 list_for_each_entry(connector,
8559 &dev->mode_config.connector_list,
8560 base.head) {
8561 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8562 crt = &connector->base;
8563 break;
8564 }
8565 }
8566
8567 if (!crt)
8568 return;
8569
8570 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8571 intel_release_load_detect_pipe(crt, &load_detect_temp);
8572
8573
8574}
8575
fa555837
SV		 8576static bool
8577intel_check_plane_mapping(struct intel_crtc *crtc)
8578{
8579 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8580 u32 reg, val;
8581
8582 if (dev_priv->num_pipe == 1)
8583 return true;
8584
8585 reg = DSPCNTR(!crtc->plane);
8586 val = I915_READ(reg);
8587
8588 if ((val & DISPLAY_PLANE_ENABLE) &&
8589 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8590 return false;
8591
8592 return true;
8593}
8594
24929352
SV		 8595static void intel_sanitize_crtc(struct intel_crtc *crtc)
8596{
8597 struct drm_device *dev = crtc->base.dev;
8598 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8599 u32 reg;
24929352 8600
24929352 8601 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8602 reg = PIPECONF(crtc->cpu_transcoder);
24929352
SV		 8603 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8604
8605 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
SV		 8606 * disable the crtc (and hence change the state) if it is wrong. Note
8607 * that gen4+ has a fixed plane -> pipe mapping. */
8608 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
SV		 8609 struct intel_connector *connector;
8610 bool plane;
8611
24929352
SV		 8612 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8613 crtc->base.base.id);
8614
8615 /* Pipe has the wrong plane attached and the plane is active.
8616 * Temporarily change the plane mapping and disable everything
8617 * ... */
8618 plane = crtc->plane;
8619 crtc->plane = !plane;
8620 dev_priv->display.crtc_disable(&crtc->base);
8621 crtc->plane = plane;
8622
8623 /* ... and break all links. */
8624 list_for_each_entry(connector, &dev->mode_config.connector_list,
8625 base.head) {
8626 if (connector->encoder->base.crtc != &crtc->base)
8627 continue;
8628
8629 intel_connector_break_all_links(connector);
8630 }
8631
8632 WARN_ON(crtc->active);
8633 crtc->base.enabled = false;
8634 }
24929352 8635
7fad798e
SV		 8636 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8637 crtc->pipe == PIPE_A && !crtc->active) {
8638 /* BIOS forgot to enable pipe A, this mostly happens after
8639 * resume. Force-enable the pipe to fix this, the update_dpms
8640 * call below we restore the pipe to the right state, but leave
8641 * the required bits on. */
8642 intel_enable_pipe_a(dev);
8643 }
8644
24929352
SV		 8645 /* Adjust the state of the output pipe according to whether we
8646 * have active connectors/encoders. */
8647 intel_crtc_update_dpms(&crtc->base);
8648
8649 if (crtc->active != crtc->base.enabled) {
8650 struct intel_encoder *encoder;
8651
8652 /* This can happen either due to bugs in the get_hw_state
8653 * functions or because the pipe is force-enabled due to the
8654 * pipe A quirk. */
8655 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8656 crtc->base.base.id,
8657 crtc->base.enabled ? "enabled" : "disabled",
8658 crtc->active ? "enabled" : "disabled");
8659
8660 crtc->base.enabled = crtc->active;
8661
8662 /* Because we only establish the connector -> encoder ->
8663 * crtc links if something is active, this means the
8664 * crtc is now deactivated. Break the links. connector
8665 * -> encoder links are only establish when things are
8666 * actually up, hence no need to break them. */
8667 WARN_ON(crtc->active);
8668
8669 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8670 WARN_ON(encoder->connectors_active);
8671 encoder->base.crtc = NULL;
8672 }
8673 }
8674}
8675
8676static void intel_sanitize_encoder(struct intel_encoder *encoder)
8677{
8678 struct intel_connector *connector;
8679 struct drm_device *dev = encoder->base.dev;
8680
8681 /* We need to check both for a crtc link (meaning that the
8682 * encoder is active and trying to read from a pipe) and the
8683 * pipe itself being active. */
8684 bool has_active_crtc = encoder->base.crtc &&
8685 to_intel_crtc(encoder->base.crtc)->active;
8686
8687 if (encoder->connectors_active && !has_active_crtc) {
8688 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8689 encoder->base.base.id,
8690 drm_get_encoder_name(&encoder->base));
8691
8692 /* Connector is active, but has no active pipe. This is
8693 * fallout from our resume register restoring. Disable
8694 * the encoder manually again. */
8695 if (encoder->base.crtc) {
8696 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8697 encoder->base.base.id,
8698 drm_get_encoder_name(&encoder->base));
8699 encoder->disable(encoder);
8700 }
8701
8702 /* Inconsistent output/port/pipe state happens presumably due to
8703 * a bug in one of the get_hw_state functions. Or someplace else
8704 * in our code, like the register restore mess on resume. Clamp
8705 * things to off as a safer default. */
8706 list_for_each_entry(connector,
8707 &dev->mode_config.connector_list,
8708 base.head) {
8709 if (connector->encoder != encoder)
8710 continue;
8711
8712 intel_connector_break_all_links(connector);
8713 }
8714 }
8715 /* Enabled encoders without active connectors will be fixed in
8716 * the crtc fixup. */
8717}
8718
8719/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8720 * and i915 state tracking structures. */
8721void intel_modeset_setup_hw_state(struct drm_device *dev)
8722{
8723 struct drm_i915_private *dev_priv = dev->dev_private;
8724 enum pipe pipe;
8725 u32 tmp;
8726 struct intel_crtc *crtc;
8727 struct intel_encoder *encoder;
8728 struct intel_connector *connector;
8729
e28d54cb
PZ		 8730 if (IS_HASWELL(dev)) {
8731 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8732
8733 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8734 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8735 case TRANS_DDI_EDP_INPUT_A_ON:
8736 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8737 pipe = PIPE_A;
8738 break;
8739 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8740 pipe = PIPE_B;
8741 break;
8742 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8743 pipe = PIPE_C;
8744 break;
8745 }
8746
8747 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8748 crtc->cpu_transcoder = TRANSCODER_EDP;
8749
8750 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8751 pipe_name(pipe));
8752 }
8753 }
8754
24929352
SV		 8755 for_each_pipe(pipe) {
8756 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8757
702e7a56 8758 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
SV		 8759 if (tmp & PIPECONF_ENABLE)
8760 crtc->active = true;
8761 else
8762 crtc->active = false;
8763
8764 crtc->base.enabled = crtc->active;
8765
8766 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8767 crtc->base.base.id,
8768 crtc->active ? "enabled" : "disabled");
8769 }
8770
6441ab5f
PZ		 8771 if (IS_HASWELL(dev))
8772 intel_ddi_setup_hw_pll_state(dev);
8773
24929352
SV		 8774 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8775 base.head) {
8776 pipe = 0;
8777
8778 if (encoder->get_hw_state(encoder, &pipe)) {
8779 encoder->base.crtc =
8780 dev_priv->pipe_to_crtc_mapping[pipe];
8781 } else {
8782 encoder->base.crtc = NULL;
8783 }
8784
8785 encoder->connectors_active = false;
8786 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8787 encoder->base.base.id,
8788 drm_get_encoder_name(&encoder->base),
8789 encoder->base.crtc ? "enabled" : "disabled",
8790 pipe);
8791 }
8792
8793 list_for_each_entry(connector, &dev->mode_config.connector_list,
8794 base.head) {
8795 if (connector->get_hw_state(connector)) {
8796 connector->base.dpms = DRM_MODE_DPMS_ON;
8797 connector->encoder->connectors_active = true;
8798 connector->base.encoder = &connector->encoder->base;
8799 } else {
8800 connector->base.dpms = DRM_MODE_DPMS_OFF;
8801 connector->base.encoder = NULL;
8802 }
8803 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8804 connector->base.base.id,
8805 drm_get_connector_name(&connector->base),
8806 connector->base.encoder ? "enabled" : "disabled");
8807 }
8808
8809 /* HW state is read out, now we need to sanitize this mess. */
8810 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8811 base.head) {
8812 intel_sanitize_encoder(encoder);
8813 }
8814
8815 for_each_pipe(pipe) {
8816 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8817 intel_sanitize_crtc(crtc);
8818 }
9a935856
SV		 8819
8820 intel_modeset_update_staged_output_state(dev);
8af6cf88
SV		 8821
8822 intel_modeset_check_state(dev);
2e938892
SV		 8823
8824 drm_mode_config_reset(dev);
24929352
SV		 8825}
8826
2c7111db
CW		 8827void intel_modeset_gem_init(struct drm_device *dev)
8828{
1833b134 8829 intel_modeset_init_hw(dev);
02e792fb
SV		 8830
8831 intel_setup_overlay(dev);
24929352
SV		 8832
8833 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8834}
8835
8836void intel_modeset_cleanup(struct drm_device *dev)
8837{
652c393a
JB		 8838 struct drm_i915_private *dev_priv = dev->dev_private;
8839 struct drm_crtc *crtc;
8840 struct intel_crtc *intel_crtc;
8841
f87ea761 8842 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8843 mutex_lock(&dev->struct_mutex);
8844
723bfd70
JB		 8845 intel_unregister_dsm_handler();
8846
8847
652c393a
JB		 8848 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8849 /* Skip inactive CRTCs */
8850 if (!crtc->fb)
8851 continue;
8852
8853 intel_crtc = to_intel_crtc(crtc);
3dec0095 8854 intel_increase_pllclock(crtc);
652c393a
JB		 8855 }
8856
973d04f9 8857 intel_disable_fbc(dev);
e70236a8 8858
8090c6b9 8859 intel_disable_gt_powersave(dev);
0cdab21f 8860
930ebb46
SV		 8861 ironlake_teardown_rc6(dev);
8862
57f350b6
JB		 8863 if (IS_VALLEYVIEW(dev))
8864 vlv_init_dpio(dev);
8865
69341a5e
KH		 8866 mutex_unlock(&dev->struct_mutex);
8867
6c0d9350
SV		 8868 /* Disable the irq before mode object teardown, for the irq might
8869 * enqueue unpin/hotplug work. */
8870 drm_irq_uninstall(dev);
8871 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8872 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8873
1630fe75
CW		 8874 /* flush any delayed tasks or pending work */
8875 flush_scheduled_work();
8876
79e53945
JB		 8877 drm_mode_config_cleanup(dev);
8878}
8879
f1c79df3
ZW		 8880/*
8881 * Return which encoder is currently attached for connector.
8882 */
df0e9248 8883struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8884{
df0e9248
CW		 8885 return &intel_attached_encoder(connector)->base;
8886}
f1c79df3 8887
df0e9248
CW		 8888void intel_connector_attach_encoder(struct intel_connector *connector,
8889 struct intel_encoder *encoder)
8890{
8891 connector->encoder = encoder;
8892 drm_mode_connector_attach_encoder(&connector->base,
8893 &encoder->base);
79e53945 8894}
28d52043
DA		 8895
8896/*
8897 * set vga decode state - true == enable VGA decode
8898 */
8899int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8900{
8901 struct drm_i915_private *dev_priv = dev->dev_private;
8902 u16 gmch_ctrl;
8903
8904 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8905 if (state)
8906 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8907 else
8908 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8909 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8910 return 0;
8911}
c4a1d9e4
CW		 8912
8913#ifdef CONFIG_DEBUG_FS
8914#include <linux/seq_file.h>
8915
8916struct intel_display_error_state {
8917 struct intel_cursor_error_state {
8918 u32 control;
8919 u32 position;
8920 u32 base;
8921 u32 size;
52331309 8922 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8923
8924 struct intel_pipe_error_state {
8925 u32 conf;
8926 u32 source;
8927
8928 u32 htotal;
8929 u32 hblank;
8930 u32 hsync;
8931 u32 vtotal;
8932 u32 vblank;
8933 u32 vsync;
52331309 8934 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8935
8936 struct intel_plane_error_state {
8937 u32 control;
8938 u32 stride;
8939 u32 size;
8940 u32 pos;
8941 u32 addr;
8942 u32 surface;
8943 u32 tile_offset;
52331309 8944 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8945};
8946
8947struct intel_display_error_state *
8948intel_display_capture_error_state(struct drm_device *dev)
8949{
0206e353 8950 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 8951 struct intel_display_error_state *error;
702e7a56 8952 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 8953 int i;
8954
8955 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8956 if (error == NULL)
8957 return NULL;
8958
52331309 8959 for_each_pipe(i) {
702e7a56
PZ		 8960 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8961
c4a1d9e4
CW		 8962 error->cursor[i].control = I915_READ(CURCNTR(i));
8963 error->cursor[i].position = I915_READ(CURPOS(i));
8964 error->cursor[i].base = I915_READ(CURBASE(i));
8965
8966 error->plane[i].control = I915_READ(DSPCNTR(i));
8967 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8968 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8969 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8970 error->plane[i].addr = I915_READ(DSPADDR(i));
8971 if (INTEL_INFO(dev)->gen >= 4) {
8972 error->plane[i].surface = I915_READ(DSPSURF(i));
8973 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8974 }
8975
702e7a56 8976 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 8977 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 8978 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8979 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8980 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8981 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8982 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8983 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 8984 }
8985
8986 return error;
8987}
8988
8989void
8990intel_display_print_error_state(struct seq_file *m,
8991 struct drm_device *dev,
8992 struct intel_display_error_state *error)
8993{
52331309 8994 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8995 int i;
8996
52331309
DL		 8997 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8998 for_each_pipe(i) {
c4a1d9e4
CW		 8999 seq_printf(m, "Pipe [%d]:\n", i);
9000 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9001 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9002 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9003 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9004 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9005 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9006 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9007 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9008
9009 seq_printf(m, "Plane [%d]:\n", i);
9010 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9011 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9012 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9013 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9014 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9015 if (INTEL_INFO(dev)->gen >= 4) {
9016 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9017 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9018 }
9019
9020 seq_printf(m, "Cursor [%d]:\n", i);
9021 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9022 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9023 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9024 }
9025}
9026#endif
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