[linux.git] / drivers / irqchip / irq-i8259.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Code to handle x86 style IRQs plus some generic interrupt stuff.
 *
 * Copyright (C) 1992 Linus Torvalds
 * Copyright (C) 1994 - 2000 Ralf Baechle
 */
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irqchip.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/of_irq.h>
#include <linux/spinlock.h>
#include <linux/syscore_ops.h>
#include <linux/irq.h>

#include <asm/i8259.h>
#include <asm/io.h>

/*
 * This is the 'legacy' 8259A Programmable Interrupt Controller,
 * present in the majority of PC/AT boxes.
 * plus some generic x86 specific things if generic specifics makes
 * any sense at all.
 * this file should become arch/i386/kernel/irq.c when the old irq.c
 * moves to arch independent land
 */

static int i8259A_auto_eoi = -1;
DEFINE_RAW_SPINLOCK(i8259A_lock);
static void disable_8259A_irq(struct irq_data *d);
static void enable_8259A_irq(struct irq_data *d);
static void mask_and_ack_8259A(struct irq_data *d);
static void init_8259A(int auto_eoi);
static int (*i8259_poll)(void) = i8259_irq;

static struct irq_chip i8259A_chip = {
	.name			= "XT-PIC",
	.irq_mask		= disable_8259A_irq,
	.irq_disable		= disable_8259A_irq,
	.irq_unmask		= enable_8259A_irq,
	.irq_mask_ack		= mask_and_ack_8259A,
};

/*
 * 8259A PIC functions to handle ISA devices:
 */

void i8259_set_poll(int (*poll)(void))
{
	i8259_poll = poll;
}

/*
 * This contains the irq mask for both 8259A irq controllers,
 */
static unsigned int cached_irq_mask = 0xffff;

#define cached_master_mask	(cached_irq_mask)
#define cached_slave_mask	(cached_irq_mask >> 8)

static void disable_8259A_irq(struct irq_data *d)
{
	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	mask = 1 << irq;
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask |= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

static void enable_8259A_irq(struct irq_data *d)
{
	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	mask = ~(1 << irq);
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	cached_irq_mask &= mask;
	if (irq & 8)
		outb(cached_slave_mask, PIC_SLAVE_IMR);
	else
		outb(cached_master_mask, PIC_MASTER_IMR);
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

void make_8259A_irq(unsigned int irq)
{
	disable_irq_nosync(irq);
	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
	enable_irq(irq);
}

/*
 * This function assumes to be called rarely. Switching between
 * 8259A registers is slow.
 * This has to be protected by the irq controller spinlock
 * before being called.
 */
static inline int i8259A_irq_real(unsigned int irq)
{
	int value;
	int irqmask = 1 << irq;

	if (irq < 8) {
		outb(0x0B, PIC_MASTER_CMD);	/* ISR register */
		value = inb(PIC_MASTER_CMD) & irqmask;
		outb(0x0A, PIC_MASTER_CMD);	/* back to the IRR register */
		return value;
	}
	outb(0x0B, PIC_SLAVE_CMD);	/* ISR register */
	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
	outb(0x0A, PIC_SLAVE_CMD);	/* back to the IRR register */
	return value;
}

/*
 * Careful! The 8259A is a fragile beast, it pretty
 * much _has_ to be done exactly like this (mask it
 * first, _then_ send the EOI, and the order of EOI
 * to the two 8259s is important!
 */
static void mask_and_ack_8259A(struct irq_data *d)
{
	unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
	unsigned long flags;

	irqmask = 1 << irq;
	raw_spin_lock_irqsave(&i8259A_lock, flags);
	/*
	 * Lightweight spurious IRQ detection. We do not want
	 * to overdo spurious IRQ handling - it's usually a sign
	 * of hardware problems, so we only do the checks we can
	 * do without slowing down good hardware unnecessarily.
	 *
	 * Note that IRQ7 and IRQ15 (the two spurious IRQs
	 * usually resulting from the 8259A-1|2 PICs) occur
	 * even if the IRQ is masked in the 8259A. Thus we
	 * can check spurious 8259A IRQs without doing the
	 * quite slow i8259A_irq_real() call for every IRQ.
	 * This does not cover 100% of spurious interrupts,
	 * but should be enough to warn the user that there
	 * is something bad going on ...
	 */
	if (cached_irq_mask & irqmask)
		goto spurious_8259A_irq;
	cached_irq_mask |= irqmask;

handle_real_irq:
	if (irq & 8) {
		inb(PIC_SLAVE_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_slave_mask, PIC_SLAVE_IMR);
		outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
		outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
	} else {
		inb(PIC_MASTER_IMR);	/* DUMMY - (do we need this?) */
		outb(cached_master_mask, PIC_MASTER_IMR);
		outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
	}
	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
	return;

spurious_8259A_irq:
	/*
	 * this is the slow path - should happen rarely.
	 */
	if (i8259A_irq_real(irq))
		/*
		 * oops, the IRQ _is_ in service according to the
		 * 8259A - not spurious, go handle it.
		 */
		goto handle_real_irq;

	{
		static int spurious_irq_mask;
		/*
		 * At this point we can be sure the IRQ is spurious,
		 * lets ACK and report it. [once per IRQ]
		 */
		if (!(spurious_irq_mask & irqmask)) {
			printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
			spurious_irq_mask |= irqmask;
		}
		atomic_inc(&irq_err_count);
		/*
		 * Theoretically we do not have to handle this IRQ,
		 * but in Linux this does not cause problems and is
		 * simpler for us.
		 */
		goto handle_real_irq;
	}
}

static void i8259A_resume(void)
{
	if (i8259A_auto_eoi >= 0)
		init_8259A(i8259A_auto_eoi);
}

static void i8259A_shutdown(void)
{
	/* Put the i8259A into a quiescent state that
	 * the kernel initialization code can get it
	 * out of.
	 */
	if (i8259A_auto_eoi >= 0) {
		outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
		outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */
	}
}

static struct syscore_ops i8259_syscore_ops = {
	.resume = i8259A_resume,
	.shutdown = i8259A_shutdown,
};

static int __init i8259A_init_sysfs(void)
{
	register_syscore_ops(&i8259_syscore_ops);
	return 0;
}

device_initcall(i8259A_init_sysfs);

static void init_8259A(int auto_eoi)
{
	unsigned long flags;

	i8259A_auto_eoi = auto_eoi;

	raw_spin_lock_irqsave(&i8259A_lock, flags);

	outb(0xff, PIC_MASTER_IMR);	/* mask all of 8259A-1 */
	outb(0xff, PIC_SLAVE_IMR);	/* mask all of 8259A-2 */

	/*
	 * outb_p - this has to work on a wide range of PC hardware.
	 */
	outb_p(0x11, PIC_MASTER_CMD);	/* ICW1: select 8259A-1 init */
	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR);	/* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);	/* 8259A-1 (the master) has a slave on IR2 */
	if (auto_eoi)	/* master does Auto EOI */
		outb_p(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
	else		/* master expects normal EOI */
		outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);

	outb_p(0x11, PIC_SLAVE_CMD);	/* ICW1: select 8259A-2 init */
	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR);	/* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR);	/* 8259A-2 is a slave on master's IR2 */
	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
	if (auto_eoi)
		/*
		 * In AEOI mode we just have to mask the interrupt
		 * when acking.
		 */
		i8259A_chip.irq_mask_ack = disable_8259A_irq;
	else
		i8259A_chip.irq_mask_ack = mask_and_ack_8259A;

	udelay(100);		/* wait for 8259A to initialize */

	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
	outb(cached_slave_mask, PIC_SLAVE_IMR);	  /* restore slave IRQ mask */

	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
}

/*
 * IRQ2 is cascade interrupt to second interrupt controller
 */
static struct irqaction irq2 = {
	.handler = no_action,
	.name = "cascade",
	.flags = IRQF_NO_THREAD,
};

static struct resource pic1_io_resource = {
	.name = "pic1",
	.start = PIC_MASTER_CMD,
	.end = PIC_MASTER_IMR,
	.flags = IORESOURCE_BUSY
};

static struct resource pic2_io_resource = {
	.name = "pic2",
	.start = PIC_SLAVE_CMD,
	.end = PIC_SLAVE_IMR,
	.flags = IORESOURCE_BUSY
};

static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq,
				 irq_hw_number_t hw)
{
	irq_set_chip_and_handler(virq, &i8259A_chip, handle_level_irq);
	irq_set_probe(virq);
	return 0;
}

static const struct irq_domain_ops i8259A_ops = {
	.map = i8259A_irq_domain_map,
	.xlate = irq_domain_xlate_onecell,
};

/*
 * On systems with i8259-style interrupt controllers we assume for
 * driver compatibility reasons interrupts 0 - 15 to be the i8259
 * interrupts even if the hardware uses a different interrupt numbering.
 */
struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
{
	struct irq_domain *domain;

	insert_resource(&ioport_resource, &pic1_io_resource);
	insert_resource(&ioport_resource, &pic2_io_resource);

	init_8259A(0);

	domain = irq_domain_add_legacy(node, 16, I8259A_IRQ_BASE, 0,
				       &i8259A_ops, NULL);
	if (!domain)
		panic("Failed to add i8259 IRQ domain");

	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
	return domain;
}

void __init init_i8259_irqs(void)
{
	__init_i8259_irqs(NULL);
}

static void i8259_irq_dispatch(struct irq_desc *desc)
{
	struct irq_domain *domain = irq_desc_get_handler_data(desc);
	int hwirq = i8259_poll();
	unsigned int irq;

	if (hwirq < 0)
		return;

	irq = irq_linear_revmap(domain, hwirq);
	generic_handle_irq(irq);
}

int __init i8259_of_init(struct device_node *node, struct device_node *parent)
{
	struct irq_domain *domain;
	unsigned int parent_irq;

	domain = __init_i8259_irqs(node);

	parent_irq = irq_of_parse_and_map(node, 0);
	if (!parent_irq) {
		pr_err("Failed to map i8259 parent IRQ\n");
		irq_domain_remove(domain);
		return -ENODEV;
	}

	irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch,
					 domain);
	return 0;
}
IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Code to handle x86 style IRQs plus some generic interrupt stuff.
	7	*
	8	* Copyright (C) 1992 Linus Torvalds
	9	* Copyright (C) 1994 - 2000 Ralf Baechle
	10	*/
	11	#include <linux/delay.h>
	12	#include <linux/init.h>
	13	#include <linux/ioport.h>
	14	#include <linux/interrupt.h>
0509cfde	15	#include <linux/irqchip.h>
079a4601	16	#include <linux/irqdomain.h>
1da177e4	17	#include <linux/kernel.h>
5f93ef5c	18	#include <linux/of_irq.h>
1da177e4	19	#include <linux/spinlock.h>
84652e83	20	#include <linux/syscore_ops.h>
ca4d3e67	21	#include <linux/irq.h>
1da177e4 LT	22
	23	#include <asm/i8259.h>
	24	#include <asm/io.h>
	25
1da177e4 LT	26	/*
	27	* This is the 'legacy' 8259A Programmable Interrupt Controller,
	28	* present in the majority of PC/AT boxes.
	29	* plus some generic x86 specific things if generic specifics makes
	30	* any sense at all.
	31	* this file should become arch/i386/kernel/irq.c when the old irq.c
	32	* moves to arch independent land
	33	*/
	34
a0be2f79	35	static int i8259A_auto_eoi = -1;
89650870	36	DEFINE_RAW_SPINLOCK(i8259A_lock);
7c8d948f TG	37	static void disable_8259A_irq(struct irq_data *d);
	38	static void enable_8259A_irq(struct irq_data *d);
	39	static void mask_and_ack_8259A(struct irq_data *d);
d80c1c0b	40	static void init_8259A(int auto_eoi);
19afc3d2	41	static int (*i8259_poll)(void) = i8259_irq;
1da177e4	42
2cafe978	43	static struct irq_chip i8259A_chip = {
7c8d948f TG	44	.name = "XT-PIC",
	45	.irq_mask = disable_8259A_irq,
	46	.irq_disable = disable_8259A_irq,
	47	.irq_unmask = enable_8259A_irq,
	48	.irq_mask_ack = mask_and_ack_8259A,
1da177e4 LT	49	};
	50
	51	/*
	52	* 8259A PIC functions to handle ISA devices:
	53	*/
	54
19afc3d2 PB	55	void i8259_set_poll(int (*poll)(void))
	56	{
	57	i8259_poll = poll;
	58	}
	59
1da177e4 LT	60	/*
	61	* This contains the irq mask for both 8259A irq controllers,
	62	*/
	63	static unsigned int cached_irq_mask = 0xffff;
	64
2cafe978 AN	65	#define cached_master_mask (cached_irq_mask)
2cafe978 AN	66	#define cached_slave_mask (cached_irq_mask >> 8)
1da177e4	67
7c8d948f	68	static void disable_8259A_irq(struct irq_data *d)
1da177e4	69	{
7c8d948f	70	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	71	unsigned long flags;
1da177e4 LT	72
2fa7937b	73	mask = 1 << irq;
89650870	74	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	75	cached_irq_mask \|= mask;
1da177e4 LT	76	if (irq & 8)
2cafe978	77	outb(cached_slave_mask, PIC_SLAVE_IMR);
1da177e4	78	else
2cafe978	79	outb(cached_master_mask, PIC_MASTER_IMR);
89650870	80	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	81	}
1da177e4 LT	82
7c8d948f	83	static void enable_8259A_irq(struct irq_data *d)
1da177e4	84	{
7c8d948f	85	unsigned int mask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	86	unsigned long flags;
1da177e4 LT	87
2fa7937b	88	mask = ~(1 << irq);
89650870	89	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4 LT	90	cached_irq_mask &= mask;
1da177e4 LT	91	if (irq & 8)
2cafe978	92	outb(cached_slave_mask, PIC_SLAVE_IMR);
1da177e4	93	else
2cafe978	94	outb(cached_master_mask, PIC_MASTER_IMR);
89650870	95	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	96	}
1da177e4 LT	97
1da177e4 LT	98	void make_8259A_irq(unsigned int irq)
	99	{
	100	disable_irq_nosync(irq);
e4ec7989	101	irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
1da177e4 LT	102	enable_irq(irq);
	103	}
	104
	105	/*
	106	* This function assumes to be called rarely. Switching between
	107	* 8259A registers is slow.
	108	* This has to be protected by the irq controller spinlock
	109	* before being called.
	110	*/
	111	static inline int i8259A_irq_real(unsigned int irq)
	112	{
	113	int value;
	114	int irqmask = 1 << irq;
	115
	116	if (irq < 8) {
21a151d8	117	outb(0x0B, PIC_MASTER_CMD); /* ISR register */
2cafe978	118	value = inb(PIC_MASTER_CMD) & irqmask;
21a151d8	119	outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
1da177e4 LT	120	return value;
1da177e4 LT	121	}
21a151d8	122	outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
2cafe978	123	value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
21a151d8	124	outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
1da177e4 LT	125	return value;
	126	}
	127
	128	/*
	129	* Careful! The 8259A is a fragile beast, it pretty
	130	* much _has_ to be done exactly like this (mask it
	131	* first, _then_ send the EOI, and the order of EOI
	132	* to the two 8259s is important!
	133	*/
7c8d948f	134	static void mask_and_ack_8259A(struct irq_data *d)
1da177e4	135	{
7c8d948f	136	unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE;
1da177e4 LT	137	unsigned long flags;
1da177e4 LT	138
2fa7937b	139	irqmask = 1 << irq;
89650870	140	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4	141	/*
2cafe978 AN	142	* Lightweight spurious IRQ detection. We do not want
	143	* to overdo spurious IRQ handling - it's usually a sign
	144	* of hardware problems, so we only do the checks we can
	145	* do without slowing down good hardware unnecessarily.
1da177e4	146	*
2cafe978 AN	147	* Note that IRQ7 and IRQ15 (the two spurious IRQs
	148	* usually resulting from the 8259A-1\|2 PICs) occur
	149	* even if the IRQ is masked in the 8259A. Thus we
	150	* can check spurious 8259A IRQs without doing the
	151	* quite slow i8259A_irq_real() call for every IRQ.
	152	* This does not cover 100% of spurious interrupts,
	153	* but should be enough to warn the user that there
	154	* is something bad going on ...
1da177e4 LT	155	*/
	156	if (cached_irq_mask & irqmask)
	157	goto spurious_8259A_irq;
	158	cached_irq_mask \|= irqmask;
	159
	160	handle_real_irq:
	161	if (irq & 8) {
2cafe978 AN	162	inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
2cafe978 AN	163	outb(cached_slave_mask, PIC_SLAVE_IMR);
21a151d8 RB	164	outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
21a151d8 RB	165	outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
1da177e4	166	} else {
2cafe978 AN	167	inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
2cafe978 AN	168	outb(cached_master_mask, PIC_MASTER_IMR);
70342287	169	outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
1da177e4	170	}
89650870	171	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	172	return;
	173
	174	spurious_8259A_irq:
	175	/*
	176	* this is the slow path - should happen rarely.
	177	*/
	178	if (i8259A_irq_real(irq))
	179	/*
	180	* oops, the IRQ _is_ in service according to the
	181	* 8259A - not spurious, go handle it.
	182	*/
	183	goto handle_real_irq;
	184
	185	{
2cafe978	186	static int spurious_irq_mask;
1da177e4 LT	187	/*
	188	* At this point we can be sure the IRQ is spurious,
	189	* lets ACK and report it. [once per IRQ]
	190	*/
	191	if (!(spurious_irq_mask & irqmask)) {
	192	printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
	193	spurious_irq_mask \|= irqmask;
	194	}
	195	atomic_inc(&irq_err_count);
	196	/*
	197	* Theoretically we do not have to handle this IRQ,
	198	* but in Linux this does not cause problems and is
	199	* simpler for us.
	200	*/
	201	goto handle_real_irq;
	202	}
	203	}
	204
84652e83	205	static void i8259A_resume(void)
1da177e4	206	{
a0be2f79 AN	207	if (i8259A_auto_eoi >= 0)
a0be2f79 AN	208	init_8259A(i8259A_auto_eoi);
2cafe978 AN	209	}
2cafe978 AN	210
84652e83	211	static void i8259A_shutdown(void)
2cafe978 AN	212	{
	213	/* Put the i8259A into a quiescent state that
	214	* the kernel initialization code can get it
	215	* out of.
	216	*/
a0be2f79 AN	217	if (i8259A_auto_eoi >= 0) {
a0be2f79 AN	218	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
fe0b030c	219	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
a0be2f79	220	}
1da177e4 LT	221	}
1da177e4 LT	222
84652e83	223	static struct syscore_ops i8259_syscore_ops = {
1da177e4	224	.resume = i8259A_resume,
2cafe978	225	.shutdown = i8259A_shutdown,
1da177e4 LT	226	};
1da177e4 LT	227
1da177e4 LT	228	static int __init i8259A_init_sysfs(void)
1da177e4 LT	229	{
84652e83 RW	230	register_syscore_ops(&i8259_syscore_ops);
84652e83 RW	231	return 0;
1da177e4 LT	232	}
	233
	234	device_initcall(i8259A_init_sysfs);
	235
d80c1c0b	236	static void init_8259A(int auto_eoi)
1da177e4 LT	237	{
	238	unsigned long flags;
	239
2cafe978 AN	240	i8259A_auto_eoi = auto_eoi;
2cafe978 AN	241
89650870	242	raw_spin_lock_irqsave(&i8259A_lock, flags);
1da177e4	243
2cafe978 AN	244	outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
2cafe978 AN	245	outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
1da177e4 LT	246
	247	/*
	248	* outb_p - this has to work on a wide range of PC hardware.
	249	*/
2cafe978 AN	250	outb_p(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
	251	outb_p(I8259A_IRQ_BASE + 0, PIC_MASTER_IMR); /* ICW2: 8259A-1 IR0 mapped to I8259A_IRQ_BASE + 0x00 */
	252	outb_p(1U << PIC_CASCADE_IR, PIC_MASTER_IMR); /* 8259A-1 (the master) has a slave on IR2 */
	253	if (auto_eoi) /* master does Auto EOI */
	254	outb_p(MASTER_ICW4_DEFAULT \| PIC_ICW4_AEOI, PIC_MASTER_IMR);
	255	else /* master expects normal EOI */
	256	outb_p(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
	257
	258	outb_p(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
	259	outb_p(I8259A_IRQ_BASE + 8, PIC_SLAVE_IMR); /* ICW2: 8259A-2 IR0 mapped to I8259A_IRQ_BASE + 0x08 */
	260	outb_p(PIC_CASCADE_IR, PIC_SLAVE_IMR); /* 8259A-2 is a slave on master's IR2 */
	261	outb_p(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR); /* (slave's support for AEOI in flat mode is to be investigated) */
1da177e4 LT	262	if (auto_eoi)
1da177e4 LT	263	/*
2cafe978	264	* In AEOI mode we just have to mask the interrupt
1da177e4 LT	265	* when acking.
1da177e4 LT	266	*/
7c8d948f	267	i8259A_chip.irq_mask_ack = disable_8259A_irq;
1da177e4	268	else
7c8d948f	269	i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
1da177e4 LT	270
	271	udelay(100); /* wait for 8259A to initialize */
	272
2cafe978 AN	273	outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
2cafe978 AN	274	outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
1da177e4	275
89650870	276	raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1da177e4 LT	277	}
	278
	279	/*
	280	* IRQ2 is cascade interrupt to second interrupt controller
	281	*/
	282	static struct irqaction irq2 = {
4e45171c	283	.handler = no_action,
4e45171c	284	.name = "cascade",
5c22cd40	285	.flags = IRQF_NO_THREAD,
1da177e4 LT	286	};
	287
	288	static struct resource pic1_io_resource = {
2cafe978 AN	289	.name = "pic1",
	290	.start = PIC_MASTER_CMD,
	291	.end = PIC_MASTER_IMR,
	292	.flags = IORESOURCE_BUSY
1da177e4 LT	293	};
	294
	295	static struct resource pic2_io_resource = {
2cafe978 AN	296	.name = "pic2",
	297	.start = PIC_SLAVE_CMD,
	298	.end = PIC_SLAVE_IMR,
	299	.flags = IORESOURCE_BUSY
1da177e4 LT	300	};
1da177e4 LT	301
079a4601 AB	302	static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq,
	303	irq_hw_number_t hw)
	304	{
	305	irq_set_chip_and_handler(virq, &i8259A_chip, handle_level_irq);
	306	irq_set_probe(virq);
	307	return 0;
	308	}
	309
53ccf331	310	static const struct irq_domain_ops i8259A_ops = {
079a4601 AB	311	.map = i8259A_irq_domain_map,
	312	.xlate = irq_domain_xlate_onecell,
	313	};
	314
1da177e4 LT	315	/*
1da177e4 LT	316	* On systems with i8259-style interrupt controllers we assume for
28a7879d	317	* driver compatibility reasons interrupts 0 - 15 to be the i8259
1da177e4 LT	318	* interrupts even if the hardware uses a different interrupt numbering.
1da177e4 LT	319	*/
5f93ef5c	320	struct irq_domain * __init __init_i8259_irqs(struct device_node *node)
1da177e4	321	{
079a4601	322	struct irq_domain *domain;
1da177e4	323
639702bd TB	324	insert_resource(&ioport_resource, &pic1_io_resource);
639702bd TB	325	insert_resource(&ioport_resource, &pic2_io_resource);
1da177e4 LT	326
	327	init_8259A(0);
	328
5f93ef5c	329	domain = irq_domain_add_legacy(node, 16, I8259A_IRQ_BASE, 0,
079a4601 AB	330	&i8259A_ops, NULL);
	331	if (!domain)
	332	panic("Failed to add i8259 IRQ domain");
1da177e4	333
2fa7937b	334	setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
5f93ef5c PB	335	return domain;
	336	}
	337
	338	void __init init_i8259_irqs(void)
	339	{
	340	__init_i8259_irqs(NULL);
	341	}
	342
bd0b9ac4	343	static void i8259_irq_dispatch(struct irq_desc *desc)
5f93ef5c	344	{
4ba37501	345	struct irq_domain *domain = irq_desc_get_handler_data(desc);
19afc3d2	346	int hwirq = i8259_poll();
4ba37501	347	unsigned int irq;
5f93ef5c PB	348
	349	if (hwirq < 0)
	350	return;
	351
	352	irq = irq_linear_revmap(domain, hwirq);
	353	generic_handle_irq(irq);
	354	}
	355
	356	int __init i8259_of_init(struct device_node node, struct device_node parent)
	357	{
	358	struct irq_domain *domain;
	359	unsigned int parent_irq;
	360
690803ac PB	361	domain = __init_i8259_irqs(node);
690803ac PB	362
5f93ef5c PB	363	parent_irq = irq_of_parse_and_map(node, 0);
	364	if (!parent_irq) {
	365	pr_err("Failed to map i8259 parent IRQ\n");
690803ac	366	irq_domain_remove(domain);
5f93ef5c PB	367	return -ENODEV;
	368	}
	369
a51e80d0 AL	370	irq_set_chained_handler_and_data(parent_irq, i8259_irq_dispatch,
a51e80d0 AL	371	domain);
5f93ef5c	372	return 0;
1da177e4	373	}
5f93ef5c	374	IRQCHIP_DECLARE(i8259, "intel,i8259", i8259_of_init);