]> Git Repo - f1c200s-dev-board.git/blob - f1c200s.pro
second rev of crap board
[f1c200s-dev-board.git] / f1c200s.pro
1 update=7/10/2020 2:54:31 PM
2 version=1
3 last_client=kicad
4 [general]
5 version=1
6 RootSch=
7 BoardNm=
8 [cvpcb]
9 version=1
10 NetIExt=net
11 [eeschema]
12 version=1
13 LibDir=
14 [eeschema/libraries]
15 [schematic_editor]
16 version=1
17 PageLayoutDescrFile=
18 PlotDirectoryName=
19 SubpartIdSeparator=0
20 SubpartFirstId=65
21 NetFmtName=Pcbnew
22 SpiceAjustPassiveValues=0
23 LabSize=50
24 ERC_TestSimilarLabels=1
25 [pcbnew]
26 version=1
27 PageLayoutDescrFile=
28 LastNetListRead=f1c200s.net
29 CopperLayerCount=2
30 BoardThickness=1.6
31 AllowMicroVias=0
32 AllowBlindVias=0
33 RequireCourtyardDefinitions=0
34 ProhibitOverlappingCourtyards=1
35 MinTrackWidth=0.09999999999999999
36 MinViaDiameter=0.3
37 MinViaDrill=0.3
38 MinMicroViaDiameter=0.2
39 MinMicroViaDrill=0.09999999999999999
40 MinHoleToHole=0.25
41 TrackWidth1=0.25
42 TrackWidth2=0.125
43 TrackWidth3=0.15
44 TrackWidth4=0.2
45 TrackWidth5=0.35
46 TrackWidth6=0.6
47 TrackWidth7=0.8
48 ViaDiameter1=0.8
49 ViaDrill1=0.4
50 ViaDiameter2=0.6
51 ViaDrill2=0.3
52 dPairWidth1=0.2
53 dPairGap1=0.25
54 dPairViaGap1=0.25
55 SilkLineWidth=0.15
56 SilkTextSizeV=1
57 SilkTextSizeH=1
58 SilkTextSizeThickness=0.15
59 SilkTextItalic=0
60 SilkTextUpright=1
61 CopperLineWidth=0.2
62 CopperTextSizeV=1.5
63 CopperTextSizeH=1.5
64 CopperTextThickness=0.3
65 CopperTextItalic=0
66 CopperTextUpright=1
67 EdgeCutLineWidth=0.15
68 CourtyardLineWidth=0.05
69 OthersLineWidth=0.15
70 OthersTextSizeV=1
71 OthersTextSizeH=1
72 OthersTextSizeThickness=0.15
73 OthersTextItalic=0
74 OthersTextUpright=1
75 SolderMaskClearance=0.051
76 SolderMaskMinWidth=0.25
77 SolderPasteClearance=0
78 SolderPasteRatio=-0
79 [pcbnew/Layer.F.Cu]
80 Name=F.Cu
81 Type=0
82 Enabled=1
83 [pcbnew/Layer.In1.Cu]
84 Name=In1.Cu
85 Type=0
86 Enabled=0
87 [pcbnew/Layer.In2.Cu]
88 Name=In2.Cu
89 Type=0
90 Enabled=0
91 [pcbnew/Layer.In3.Cu]
92 Name=In3.Cu
93 Type=0
94 Enabled=0
95 [pcbnew/Layer.In4.Cu]
96 Name=In4.Cu
97 Type=0
98 Enabled=0
99 [pcbnew/Layer.In5.Cu]
100 Name=In5.Cu
101 Type=0
102 Enabled=0
103 [pcbnew/Layer.In6.Cu]
104 Name=In6.Cu
105 Type=0
106 Enabled=0
107 [pcbnew/Layer.In7.Cu]
108 Name=In7.Cu
109 Type=0
110 Enabled=0
111 [pcbnew/Layer.In8.Cu]
112 Name=In8.Cu
113 Type=0
114 Enabled=0
115 [pcbnew/Layer.In9.Cu]
116 Name=In9.Cu
117 Type=0
118 Enabled=0
119 [pcbnew/Layer.In10.Cu]
120 Name=In10.Cu
121 Type=0
122 Enabled=0
123 [pcbnew/Layer.In11.Cu]
124 Name=In11.Cu
125 Type=0
126 Enabled=0
127 [pcbnew/Layer.In12.Cu]
128 Name=In12.Cu
129 Type=0
130 Enabled=0
131 [pcbnew/Layer.In13.Cu]
132 Name=In13.Cu
133 Type=0
134 Enabled=0
135 [pcbnew/Layer.In14.Cu]
136 Name=In14.Cu
137 Type=0
138 Enabled=0
139 [pcbnew/Layer.In15.Cu]
140 Name=In15.Cu
141 Type=0
142 Enabled=0
143 [pcbnew/Layer.In16.Cu]
144 Name=In16.Cu
145 Type=0
146 Enabled=0
147 [pcbnew/Layer.In17.Cu]
148 Name=In17.Cu
149 Type=0
150 Enabled=0
151 [pcbnew/Layer.In18.Cu]
152 Name=In18.Cu
153 Type=0
154 Enabled=0
155 [pcbnew/Layer.In19.Cu]
156 Name=In19.Cu
157 Type=0
158 Enabled=0
159 [pcbnew/Layer.In20.Cu]
160 Name=In20.Cu
161 Type=0
162 Enabled=0
163 [pcbnew/Layer.In21.Cu]
164 Name=In21.Cu
165 Type=0
166 Enabled=0
167 [pcbnew/Layer.In22.Cu]
168 Name=In22.Cu
169 Type=0
170 Enabled=0
171 [pcbnew/Layer.In23.Cu]
172 Name=In23.Cu
173 Type=0
174 Enabled=0
175 [pcbnew/Layer.In24.Cu]
176 Name=In24.Cu
177 Type=0
178 Enabled=0
179 [pcbnew/Layer.In25.Cu]
180 Name=In25.Cu
181 Type=0
182 Enabled=0
183 [pcbnew/Layer.In26.Cu]
184 Name=In26.Cu
185 Type=0
186 Enabled=0
187 [pcbnew/Layer.In27.Cu]
188 Name=In27.Cu
189 Type=0
190 Enabled=0
191 [pcbnew/Layer.In28.Cu]
192 Name=In28.Cu
193 Type=0
194 Enabled=0
195 [pcbnew/Layer.In29.Cu]
196 Name=In29.Cu
197 Type=0
198 Enabled=0
199 [pcbnew/Layer.In30.Cu]
200 Name=In30.Cu
201 Type=0
202 Enabled=0
203 [pcbnew/Layer.B.Cu]
204 Name=B.Cu
205 Type=0
206 Enabled=1
207 [pcbnew/Layer.B.Adhes]
208 Enabled=1
209 [pcbnew/Layer.F.Adhes]
210 Enabled=1
211 [pcbnew/Layer.B.Paste]
212 Enabled=1
213 [pcbnew/Layer.F.Paste]
214 Enabled=1
215 [pcbnew/Layer.B.SilkS]
216 Enabled=1
217 [pcbnew/Layer.F.SilkS]
218 Enabled=1
219 [pcbnew/Layer.B.Mask]
220 Enabled=1
221 [pcbnew/Layer.F.Mask]
222 Enabled=1
223 [pcbnew/Layer.Dwgs.User]
224 Enabled=1
225 [pcbnew/Layer.Cmts.User]
226 Enabled=1
227 [pcbnew/Layer.Eco1.User]
228 Enabled=1
229 [pcbnew/Layer.Eco2.User]
230 Enabled=1
231 [pcbnew/Layer.Edge.Cuts]
232 Enabled=1
233 [pcbnew/Layer.Margin]
234 Enabled=1
235 [pcbnew/Layer.B.CrtYd]
236 Enabled=1
237 [pcbnew/Layer.F.CrtYd]
238 Enabled=1
239 [pcbnew/Layer.B.Fab]
240 Enabled=1
241 [pcbnew/Layer.F.Fab]
242 Enabled=1
243 [pcbnew/Layer.Rescue]
244 Enabled=0
245 [pcbnew/Netclasses]
246 [pcbnew/Netclasses/Default]
247 Name=Default
248 Clearance=0.1
249 TrackWidth=0.25
250 ViaDiameter=0.8
251 ViaDrill=0.4
252 uViaDiameter=0.3
253 uViaDrill=0.1
254 dPairWidth=0.2
255 dPairGap=0.25
256 dPairViaGap=0.25
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