board/zynqmp/zcu102/pm_cfg_obj.c

   1 /******************************************************************************
   2 * Copyright (c) 2017 - 2021 Xilinx, Inc.  All rights reserved.
   3 * SPDX-License-Identifier: MIT
   4 ******************************************************************************/
   5
   6 #include "xil_types.h"
   7 #include "pm_defs.h"
   8
   9 #define PM_CONFIG_MASTER_SECTION_ID     0x101U
  10 #define PM_CONFIG_SLAVE_SECTION_ID      0x102U
  11 #define PM_CONFIG_PREALLOC_SECTION_ID   0x103U
  12 #define PM_CONFIG_POWER_SECTION_ID      0x104U
  13 #define PM_CONFIG_RESET_SECTION_ID      0x105U
  14 #define PM_CONFIG_SHUTDOWN_SECTION_ID   0x106U
  15 #define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
  16 #define PM_CONFIG_GPO_SECTION_ID        0x108U
  17
  18 #define PM_SLAVE_FLAG_IS_SHAREABLE      0x1U
  19 #define PM_MASTER_USING_SLAVE_MASK      0x2U
  20
  21 #define PM_CONFIG_GPO1_MIO_PIN_34_MAP   (1U << 10U)
  22 #define PM_CONFIG_GPO1_MIO_PIN_35_MAP   (1U << 11U)
  23 #define PM_CONFIG_GPO1_MIO_PIN_36_MAP   (1U << 12U)
  24 #define PM_CONFIG_GPO1_MIO_PIN_37_MAP   (1U << 13U)
  25
  26 #define PM_CONFIG_GPO1_BIT_2_MASK       (1U << 2U)
  27 #define PM_CONFIG_GPO1_BIT_3_MASK       (1U << 3U)
  28 #define PM_CONFIG_GPO1_BIT_4_MASK       (1U << 4U)
  29 #define PM_CONFIG_GPO1_BIT_5_MASK       (1U << 5U)
  30
  31 #define SUSPEND_TIMEOUT 0xFFFFFFFFU
  32
  33 #define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK    0x00000001
  34 #define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK    0x00000100
  35 #define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK    0x00000200
  36
  37
  38
  39 #if defined (__ICCARM__)
  40 #pragma language=save
  41 #pragma language=extended
  42 #endif
  43 #if defined (__GNUC__)
  44     const u32 XPm_ConfigObject[] __attribute__((used, section(".sys_cfg_data"))) =
  45 #elif defined (__ICCARM__)
  46 #pragma location = ".sys_cfg_data"
  47 __root const u32 XPm_ConfigObject[] =
  48 #endif
  49 {
  50         /**********************************************************************/
  51         /* HEADER */
  52         2,      /* Number of remaining words in the header */
  53         8,      /* Number of sections included in config object */
  54         1U,     /* Type of config object as base */
  55         /**********************************************************************/
  56         /* MASTER SECTION */
  57         PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
  58         3U, /* No. of Masters*/
  59
  60         NODE_APU, /* Master Node ID */
  61         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask of this master */
  62         SUSPEND_TIMEOUT, /* Suspend timeout */
  63         PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
  64         PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
  65
  66         NODE_RPU_0, /* Master Node ID */
  67         PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask of this master */
  68         SUSPEND_TIMEOUT, /* Suspend timeout */
  69         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Suspend permissions */
  70         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Wake permissions */
  71
  72         NODE_RPU_1, /* Master Node ID */
  73         PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask of this master */
  74         SUSPEND_TIMEOUT, /* Suspend timeout */
  75         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Suspend permissions */
  76         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* Wake permissions */
  77
  78
  79         /**********************************************************************/
  80         /* SLAVE SECTION */
  81
  82
  83         PM_CONFIG_SLAVE_SECTION_ID,     /* Section ID */
  84         49,                             /* Number of slaves */
  85
  86         NODE_OCM_BANK_0,
  87         PM_SLAVE_FLAG_IS_SHAREABLE,
  88         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
  89
  90         NODE_OCM_BANK_1,
  91         PM_SLAVE_FLAG_IS_SHAREABLE,
  92         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
  93
  94         NODE_OCM_BANK_2,
  95         PM_SLAVE_FLAG_IS_SHAREABLE,
  96         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
  97
  98         NODE_OCM_BANK_3,
  99         PM_SLAVE_FLAG_IS_SHAREABLE,
 100         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 101
 102         NODE_TCM_0_A,
 103         PM_SLAVE_FLAG_IS_SHAREABLE,
 104         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
 105
 106         NODE_TCM_0_B,
 107         PM_SLAVE_FLAG_IS_SHAREABLE,
 108         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
 109
 110         NODE_TCM_1_A,
 111         PM_SLAVE_FLAG_IS_SHAREABLE,
 112         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 113
 114         NODE_TCM_1_B,
 115         PM_SLAVE_FLAG_IS_SHAREABLE,
 116         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 117
 118         NODE_L2,
 119         PM_SLAVE_FLAG_IS_SHAREABLE,
 120         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 121
 122         NODE_GPU_PP_0,
 123         PM_SLAVE_FLAG_IS_SHAREABLE,
 124         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 125
 126         NODE_GPU_PP_1,
 127         PM_SLAVE_FLAG_IS_SHAREABLE,
 128         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 129
 130         NODE_USB_0,
 131         PM_SLAVE_FLAG_IS_SHAREABLE,
 132         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 133
 134         NODE_USB_1,
 135         PM_SLAVE_FLAG_IS_SHAREABLE,
 136         0U, /* IPI Mask */
 137
 138         NODE_TTC_0,
 139         PM_SLAVE_FLAG_IS_SHAREABLE,
 140         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 141
 142         NODE_TTC_1,
 143         PM_SLAVE_FLAG_IS_SHAREABLE,
 144         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 145
 146         NODE_TTC_2,
 147         PM_SLAVE_FLAG_IS_SHAREABLE,
 148         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 149
 150         NODE_TTC_3,
 151         PM_SLAVE_FLAG_IS_SHAREABLE,
 152         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 153
 154         NODE_SATA,
 155         PM_SLAVE_FLAG_IS_SHAREABLE,
 156         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 157
 158         NODE_ETH_0,
 159         PM_SLAVE_FLAG_IS_SHAREABLE,
 160         0U, /* IPI Mask */
 161
 162         NODE_ETH_1,
 163         PM_SLAVE_FLAG_IS_SHAREABLE,
 164         0U, /* IPI Mask */
 165
 166         NODE_ETH_2,
 167         PM_SLAVE_FLAG_IS_SHAREABLE,
 168         0U, /* IPI Mask */
 169
 170         NODE_ETH_3,
 171         PM_SLAVE_FLAG_IS_SHAREABLE,
 172         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 173
 174         NODE_UART_0,
 175         PM_SLAVE_FLAG_IS_SHAREABLE,
 176         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 177
 178         NODE_UART_1,
 179         PM_SLAVE_FLAG_IS_SHAREABLE,
 180         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 181
 182         NODE_SPI_0,
 183         PM_SLAVE_FLAG_IS_SHAREABLE,
 184         0U, /* IPI Mask */
 185
 186         NODE_SPI_1,
 187         PM_SLAVE_FLAG_IS_SHAREABLE,
 188         0U, /* IPI Mask */
 189
 190         NODE_I2C_0,
 191         PM_SLAVE_FLAG_IS_SHAREABLE,
 192         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 193
 194         NODE_I2C_1,
 195         PM_SLAVE_FLAG_IS_SHAREABLE,
 196         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 197
 198         NODE_SD_0,
 199         PM_SLAVE_FLAG_IS_SHAREABLE,
 200         0U, /* IPI Mask */
 201
 202         NODE_SD_1,
 203         PM_SLAVE_FLAG_IS_SHAREABLE,
 204         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 205
 206         NODE_DP,
 207         PM_SLAVE_FLAG_IS_SHAREABLE,
 208         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 209
 210         NODE_GDMA,
 211         PM_SLAVE_FLAG_IS_SHAREABLE,
 212         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 213
 214         NODE_ADMA,
 215         PM_SLAVE_FLAG_IS_SHAREABLE,
 216         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 217
 218         NODE_NAND,
 219         PM_SLAVE_FLAG_IS_SHAREABLE,
 220         0U, /* IPI Mask */
 221
 222         NODE_QSPI,
 223         PM_SLAVE_FLAG_IS_SHAREABLE,
 224         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 225
 226         NODE_GPIO,
 227         PM_SLAVE_FLAG_IS_SHAREABLE,
 228         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 229
 230         NODE_CAN_0,
 231         PM_SLAVE_FLAG_IS_SHAREABLE,
 232         0U, /* IPI Mask */
 233
 234         NODE_CAN_1,
 235         PM_SLAVE_FLAG_IS_SHAREABLE,
 236         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 237
 238         NODE_EXTERN,
 239         PM_SLAVE_FLAG_IS_SHAREABLE,
 240         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 241
 242         NODE_DDR,
 243         PM_SLAVE_FLAG_IS_SHAREABLE,
 244         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK| PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 245
 246         NODE_IPI_APU,
 247         0U,
 248         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK, /* IPI Mask */
 249
 250         NODE_IPI_RPU_0,
 251         0U,
 252         PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK, /* IPI Mask */
 253
 254         NODE_IPI_RPU_1,
 255         0U,
 256         PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 257
 258         NODE_GPU,
 259         PM_SLAVE_FLAG_IS_SHAREABLE,
 260         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 261
 262         NODE_PCIE,
 263         PM_SLAVE_FLAG_IS_SHAREABLE,
 264         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 265
 266         NODE_PCAP,
 267         PM_SLAVE_FLAG_IS_SHAREABLE,
 268         0U, /* IPI Mask */
 269
 270         NODE_RTC,
 271         PM_SLAVE_FLAG_IS_SHAREABLE,
 272         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 273
 274         NODE_VCU,
 275         PM_SLAVE_FLAG_IS_SHAREABLE,
 276         0U, /* IPI Mask */
 277
 278         NODE_PL,
 279         PM_SLAVE_FLAG_IS_SHAREABLE,
 280         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
 281
 282
 283         /**********************************************************************/
 284         /* PREALLOC SECTION */
 285
 286         PM_CONFIG_PREALLOC_SECTION_ID, /* Preallaoc SectionID */
 287         3U, /* No. of Masters*/
 288
 289 /* Prealloc for psu_cortexa53_0 */
 290         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK,
 291         12,
 292         NODE_DDR,
 293         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 294         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 295         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 296
 297         NODE_L2,
 298         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 299         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 300         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 301
 302         NODE_OCM_BANK_0,
 303         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 304         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 305         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 306
 307         NODE_OCM_BANK_1,
 308         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 309         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 310         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 311
 312         NODE_OCM_BANK_2,
 313         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 314         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 315         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 316
 317         NODE_OCM_BANK_3,
 318         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 319         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 320         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 321
 322         NODE_I2C_0,
 323         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 324         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 325         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 326
 327         NODE_I2C_1,
 328         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 329         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 330         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 331
 332         NODE_SD_1,
 333         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 334         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 335         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 336
 337         NODE_QSPI,
 338         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 339         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 340         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 341
 342         NODE_PL,
 343         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 344         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 345         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 346
 347         NODE_IPI_APU,
 348         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 349         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 350         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 351
 352
 353         /* Prealloc for psu_cortexr5_0 */
 354         PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
 355         3,
 356         NODE_TCM_0_A,
 357         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 358         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 359         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 360
 361         NODE_TCM_0_B,
 362         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 363         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 364         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 365
 366         NODE_IPI_RPU_0,
 367         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 368         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 369         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 370
 371
 372         /* Prealloc for psu_cortexr5_1 */
 373         PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 374         3,
 375         NODE_TCM_1_A,
 376         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 377         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 378         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 379
 380         NODE_TCM_1_B,
 381         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 382         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 383         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 384
 385         NODE_IPI_RPU_1,
 386         PM_MASTER_USING_SLAVE_MASK, /* Master is using Slave */
 387         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Current Requirements */
 388         PM_CAP_ACCESS | PM_CAP_CONTEXT, /* Default Requirements */
 389
 390
 391
 392         /**********************************************************************/
 393         /* POWER SECTION */
 394
 395         PM_CONFIG_POWER_SECTION_ID, /* Power Section ID */
 396         4U, /* Number of power nodes */
 397
 398         NODE_APU, /* Power node ID */
 399         PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
 400
 401         NODE_RPU, /* Power node ID */
 402         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
 403
 404         NODE_FPD, /* Power node ID */
 405         PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
 406
 407         NODE_PLD, /* Power node ID */
 408         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* Force power down permissions */
 409
 410
 411         /**********************************************************************/
 412         /* RESET SECTION */
 413
 414         PM_CONFIG_RESET_SECTION_ID, /* Reset Section ID */
 415         120U, /* Number of resets */
 416
 417         XILPM_RESET_PCIE_CFG, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 418         XILPM_RESET_PCIE_BRIDGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 419         XILPM_RESET_PCIE_CTRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 420         XILPM_RESET_DP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 421         XILPM_RESET_SWDT_CRF, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 422         XILPM_RESET_AFI_FM5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 423         XILPM_RESET_AFI_FM4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 424         XILPM_RESET_AFI_FM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 425         XILPM_RESET_AFI_FM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 426         XILPM_RESET_AFI_FM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 427         XILPM_RESET_AFI_FM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 428         XILPM_RESET_GDMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 429         XILPM_RESET_GPU_PP1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 430         XILPM_RESET_GPU_PP0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 431         XILPM_RESET_GPU, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 432         XILPM_RESET_GT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 433         XILPM_RESET_SATA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 434         XILPM_RESET_ACPU3_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 435         XILPM_RESET_ACPU2_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 436         XILPM_RESET_ACPU1_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 437         XILPM_RESET_ACPU0_PWRON, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 438         XILPM_RESET_APU_L2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 439         XILPM_RESET_ACPU3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 440         XILPM_RESET_ACPU2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 441         XILPM_RESET_ACPU1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 442         XILPM_RESET_ACPU0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 443         XILPM_RESET_DDR, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 444         XILPM_RESET_APM_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 445         XILPM_RESET_SOFT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 446         XILPM_RESET_GEM0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 447         XILPM_RESET_GEM1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 448         XILPM_RESET_GEM2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 449         XILPM_RESET_GEM3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 450         XILPM_RESET_QSPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 451         XILPM_RESET_UART0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 452         XILPM_RESET_UART1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 453         XILPM_RESET_SPI0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 454         XILPM_RESET_SPI1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 455         XILPM_RESET_SDIO0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 456         XILPM_RESET_SDIO1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 457         XILPM_RESET_CAN0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 458         XILPM_RESET_CAN1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 459         XILPM_RESET_I2C0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 460         XILPM_RESET_I2C1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 461         XILPM_RESET_TTC0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 462         XILPM_RESET_TTC1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 463         XILPM_RESET_TTC2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 464         XILPM_RESET_TTC3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 465         XILPM_RESET_SWDT_CRL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 466         XILPM_RESET_NAND, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 467         XILPM_RESET_ADMA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 468         XILPM_RESET_GPIO, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 469         XILPM_RESET_IOU_CC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 470         XILPM_RESET_TIMESTAMP, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 471         XILPM_RESET_RPU_R50, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 472         XILPM_RESET_RPU_R51, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 473         XILPM_RESET_RPU_AMBA, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 474         XILPM_RESET_OCM, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 475         XILPM_RESET_RPU_PGE, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 476         XILPM_RESET_USB0_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 477         XILPM_RESET_USB1_CORERESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 478         XILPM_RESET_USB0_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 479         XILPM_RESET_USB1_HIBERRESET, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 480         XILPM_RESET_USB0_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 481         XILPM_RESET_USB1_APB, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 482         XILPM_RESET_IPI, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 483         XILPM_RESET_APM_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 484         XILPM_RESET_RTC, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 485         XILPM_RESET_SYSMON, 0,
 486         XILPM_RESET_AFI_FM6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 487         XILPM_RESET_LPD_SWDT, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 488         XILPM_RESET_FPD, PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK,
 489         XILPM_RESET_RPU_DBG1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 490         XILPM_RESET_RPU_DBG0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 491         XILPM_RESET_DBG_LPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 492         XILPM_RESET_DBG_FPD, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 493         XILPM_RESET_APLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 494         XILPM_RESET_DPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 495         XILPM_RESET_VPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 496         XILPM_RESET_IOPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 497         XILPM_RESET_RPLL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 498         XILPM_RESET_GPO3_PL_0, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 499         XILPM_RESET_GPO3_PL_1, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 500         XILPM_RESET_GPO3_PL_2, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 501         XILPM_RESET_GPO3_PL_3, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 502         XILPM_RESET_GPO3_PL_4, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 503         XILPM_RESET_GPO3_PL_5, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 504         XILPM_RESET_GPO3_PL_6, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 505         XILPM_RESET_GPO3_PL_7, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 506         XILPM_RESET_GPO3_PL_8, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 507         XILPM_RESET_GPO3_PL_9, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 508         XILPM_RESET_GPO3_PL_10, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 509         XILPM_RESET_GPO3_PL_11, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 510         XILPM_RESET_GPO3_PL_12, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 511         XILPM_RESET_GPO3_PL_13, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 512         XILPM_RESET_GPO3_PL_14, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 513         XILPM_RESET_GPO3_PL_15, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 514         XILPM_RESET_GPO3_PL_16, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 515         XILPM_RESET_GPO3_PL_17, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 516         XILPM_RESET_GPO3_PL_18, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 517         XILPM_RESET_GPO3_PL_19, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 518         XILPM_RESET_GPO3_PL_20, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 519         XILPM_RESET_GPO3_PL_21, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 520         XILPM_RESET_GPO3_PL_22, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 521         XILPM_RESET_GPO3_PL_23, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 522         XILPM_RESET_GPO3_PL_24, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 523         XILPM_RESET_GPO3_PL_25, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 524         XILPM_RESET_GPO3_PL_26, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 525         XILPM_RESET_GPO3_PL_27, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 526         XILPM_RESET_GPO3_PL_28, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 527         XILPM_RESET_GPO3_PL_29, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 528         XILPM_RESET_GPO3_PL_30, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 529         XILPM_RESET_GPO3_PL_31, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 530         XILPM_RESET_RPU_LS, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 531         XILPM_RESET_PS_ONLY, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 532         XILPM_RESET_PL, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 533         XILPM_RESET_GPIO5_EMIO_92, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 534         XILPM_RESET_GPIO5_EMIO_93, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 535         XILPM_RESET_GPIO5_EMIO_94, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 536         XILPM_RESET_GPIO5_EMIO_95, PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK,
 537
 538         /**********************************************************************/
 539         /* SET CONFIG SECTION */
 540         PM_CONFIG_SET_CONFIG_SECTION_ID,                /* Set Config Section ID */
 541         0U, /* Permissions to load base config object */
 542         0U, /* Permissions to load overlay config object */
 543
 544         /**********************************************************************/
 545         /* SHUTDOWN SECTION */
 546
 547         PM_CONFIG_SHUTDOWN_SECTION_ID, /* Shutdown Section ID */
 548         PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* System Shutdown/Restart Permission */
 549
 550         /**********************************************************************/
 551         /* GPO SECTION */
 552         PM_CONFIG_GPO_SECTION_ID,               /* GPO Section ID */
 553         PM_CONFIG_GPO1_BIT_2_MASK |
 554         PM_CONFIG_GPO1_MIO_PIN_34_MAP |
 555         PM_CONFIG_GPO1_MIO_PIN_35_MAP |
 556         PM_CONFIG_GPO1_MIO_PIN_36_MAP |
 557         PM_CONFIG_GPO1_MIO_PIN_37_MAP |
 558         0,                                      /* State of GPO pins */
 559 };
 560 #if defined (__ICCARM__)
 561 #pragma language=restore
 562 #endif
 563