arch/Config.in

   1 menu "Target options"
   2
   3 config BR2_ARCH_IS_64
   4         bool
   5
   6 config BR2_KERNEL_64_USERLAND_32
   7         bool
   8
   9 config BR2_SOFT_FLOAT
  10         bool
  11
  12 config BR2_ARCH_HAS_MMU_MANDATORY
  13         bool
  14
  15 config BR2_ARCH_HAS_MMU_OPTIONAL
  16         bool
  17
  18 choice
  19         prompt "Target Architecture"
  20         default BR2_i386
  21         help
  22           Select the target architecture family to build for.
  23
  24 config BR2_arcle
  25         bool "ARC (little endian)"
  26         select BR2_ARCH_HAS_MMU_MANDATORY
  27         help
  28           Synopsys' DesignWare ARC Processor Cores are a family of
  29           32-bit CPUs that can be used from deeply embedded to high
  30           performance host applications. Little endian.
  31
  32 config BR2_arceb
  33         bool "ARC (big endian)"
  34         select BR2_ARCH_HAS_MMU_MANDATORY
  35         help
  36           Synopsys' DesignWare ARC Processor Cores are a family of
  37           32-bit CPUs that can be used from deeply embedded to high
  38           performance host applications. Big endian.
  39
  40 config BR2_arm
  41         bool "ARM (little endian)"
  42         # MMU support is set by the subarchitecture file, arch/Config.in.arm
  43         help
  44           ARM is a 32-bit reduced instruction set computer (RISC)
  45           instruction set architecture (ISA) developed by ARM Holdings.
  46           Little endian.
  47           http://www.arm.com/
  48           http://en.wikipedia.org/wiki/ARM
  49
  50 config BR2_armeb
  51         bool "ARM (big endian)"
  52         # MMU support is set by the subarchitecture file, arch/Config.in.arm
  53         help
  54           ARM is a 32-bit reduced instruction set computer (RISC)
  55           instruction set architecture (ISA) developed by ARM Holdings.
  56           Big endian.
  57           http://www.arm.com/
  58           http://en.wikipedia.org/wiki/ARM
  59
  60 config BR2_aarch64
  61         bool "AArch64 (little endian)"
  62         select BR2_ARCH_IS_64
  63         select BR2_ARCH_HAS_MMU_MANDATORY
  64         help
  65           Aarch64 is a 64-bit architecture developed by ARM Holdings.
  66           http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  67           http://en.wikipedia.org/wiki/ARM
  68
  69 config BR2_aarch64_be
  70         bool "AArch64 (big endian)"
  71         select BR2_ARCH_IS_64
  72         select BR2_ARCH_HAS_MMU_MANDATORY
  73         help
  74           Aarch64 is a 64-bit architecture developed by ARM Holdings.
  75           http://www.arm.com/products/processors/instruction-set-architectures/armv8-architecture.php
  76           http://en.wikipedia.org/wiki/ARM
  77
  78 config BR2_csky
  79         bool "csky"
  80         select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
  81         select BR2_ARCH_HAS_MMU_MANDATORY
  82         help
  83           csky is processor IP from china.
  84           http://www.c-sky.com/
  85           http://www.github.com/c-sky
  86
  87 config BR2_i386
  88         bool "i386"
  89         select BR2_ARCH_HAS_MMU_MANDATORY
  90         help
  91           Intel i386 architecture compatible microprocessor
  92           http://en.wikipedia.org/wiki/I386
  93
  94 config BR2_m68k
  95         bool "m68k"
  96         # MMU support is set by the subarchitecture file, arch/Config.in.m68k
  97         help
  98           Motorola 68000 family microprocessor
  99           http://en.wikipedia.org/wiki/M68k
 100
 101 config BR2_microblazeel
 102         bool "Microblaze AXI (little endian)"
 103         select BR2_ARCH_HAS_MMU_MANDATORY
 104         help
 105           Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
 106           bus based architecture (little endian)
 107           http://www.xilinx.com
 108           http://en.wikipedia.org/wiki/Microblaze
 109
 110 config BR2_microblazebe
 111         bool "Microblaze non-AXI (big endian)"
 112         select BR2_ARCH_HAS_MMU_MANDATORY
 113         help
 114           Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
 115           bus based architecture (non-AXI, big endian)
 116           http://www.xilinx.com
 117           http://en.wikipedia.org/wiki/Microblaze
 118
 119 config BR2_mips
 120         bool "MIPS (big endian)"
 121         select BR2_ARCH_HAS_MMU_MANDATORY
 122         help
 123           MIPS is a RISC microprocessor from MIPS Technologies. Big
 124           endian.
 125           http://www.mips.com/
 126           http://en.wikipedia.org/wiki/MIPS_Technologies
 127
 128 config BR2_mipsel
 129         bool "MIPS (little endian)"
 130         select BR2_ARCH_HAS_MMU_MANDATORY
 131         help
 132           MIPS is a RISC microprocessor from MIPS Technologies. Little
 133           endian.
 134           http://www.mips.com/
 135           http://en.wikipedia.org/wiki/MIPS_Technologies
 136
 137 config BR2_mips64
 138         bool "MIPS64 (big endian)"
 139         select BR2_ARCH_IS_64
 140         select BR2_ARCH_HAS_MMU_MANDATORY
 141         help
 142           MIPS is a RISC microprocessor from MIPS Technologies. Big
 143           endian.
 144           http://www.mips.com/
 145           http://en.wikipedia.org/wiki/MIPS_Technologies
 146
 147 config BR2_mips64el
 148         bool "MIPS64 (little endian)"
 149         select BR2_ARCH_IS_64
 150         select BR2_ARCH_HAS_MMU_MANDATORY
 151         help
 152           MIPS is a RISC microprocessor from MIPS Technologies. Little
 153           endian.
 154           http://www.mips.com/
 155           http://en.wikipedia.org/wiki/MIPS_Technologies
 156
 157 config BR2_nds32
 158         bool "nds32"
 159         select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
 160         select BR2_ARCH_HAS_MMU_MANDATORY
 161         help
 162           nds32 is a 32-bit architecture developed by Andes Technology.
 163           https://en.wikipedia.org/wiki/Andes_Technology
 164
 165 config BR2_nios2
 166         bool "Nios II"
 167         select BR2_ARCH_HAS_MMU_MANDATORY
 168         help
 169           Nios II is a soft core processor from Altera Corporation.
 170           http://www.altera.com/
 171           http://en.wikipedia.org/wiki/Nios_II
 172
 173 config BR2_or1k
 174         bool "OpenRISC"
 175         select BR2_ARCH_HAS_MMU_MANDATORY
 176         help
 177           OpenRISC is a free and open processor for embedded system.
 178           http://openrisc.io
 179
 180 config BR2_powerpc
 181         bool "PowerPC"
 182         select BR2_ARCH_HAS_MMU_MANDATORY
 183         help
 184           PowerPC is a RISC architecture created by Apple-IBM-Motorola
 185           alliance. Big endian.
 186           http://www.power.org/
 187           http://en.wikipedia.org/wiki/Powerpc
 188
 189 config BR2_powerpc64
 190         bool "PowerPC64 (big endian)"
 191         select BR2_ARCH_IS_64
 192         select BR2_ARCH_HAS_MMU_MANDATORY
 193         help
 194           PowerPC is a RISC architecture created by Apple-IBM-Motorola
 195           alliance. Big endian.
 196           http://www.power.org/
 197           http://en.wikipedia.org/wiki/Powerpc
 198
 199 config BR2_powerpc64le
 200         bool "PowerPC64 (little endian)"
 201         select BR2_ARCH_IS_64
 202         select BR2_ARCH_HAS_MMU_MANDATORY
 203         help
 204           PowerPC is a RISC architecture created by Apple-IBM-Motorola
 205           alliance. Little endian.
 206           http://www.power.org/
 207           http://en.wikipedia.org/wiki/Powerpc
 208
 209 config BR2_riscv
 210         bool "RISCV"
 211         select BR2_ARCH_HAS_MMU_MANDATORY
 212         select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
 213         help
 214           RISC-V is an open, free Instruction Set Architecture created
 215           by the UC Berkeley Architecture Research group and supported
 216           and promoted by RISC-V Foundation.
 217           https://riscv.org/
 218           https://en.wikipedia.org/wiki/RISC-V
 219
 220 config BR2_sh
 221         bool "SuperH"
 222         select BR2_ARCH_HAS_MMU_OPTIONAL
 223         help
 224           SuperH (or SH) is a 32-bit reduced instruction set computer
 225           (RISC) instruction set architecture (ISA) developed by
 226           Hitachi.
 227           http://www.hitachi.com/
 228           http://en.wikipedia.org/wiki/SuperH
 229
 230 config BR2_sparc
 231         bool "SPARC"
 232         select BR2_ARCH_HAS_MMU_MANDATORY
 233         help
 234           SPARC (from Scalable Processor Architecture) is a RISC
 235           instruction set architecture (ISA) developed by Sun
 236           Microsystems.
 237           http://www.oracle.com/sun
 238           http://en.wikipedia.org/wiki/Sparc
 239
 240 config BR2_sparc64
 241         bool "SPARC64"
 242         select BR2_ARCH_IS_64
 243         select BR2_ARCH_HAS_MMU_MANDATORY
 244         help
 245           SPARC (from Scalable Processor Architecture) is a RISC
 246           instruction set architecture (ISA) developed by Sun
 247           Microsystems.
 248           http://www.oracle.com/sun
 249           http://en.wikipedia.org/wiki/Sparc
 250
 251 config BR2_x86_64
 252         bool "x86_64"
 253         select BR2_ARCH_IS_64
 254         select BR2_ARCH_HAS_MMU_MANDATORY
 255         help
 256           x86-64 is an extension of the x86 instruction set (Intel i386
 257           architecture compatible microprocessor).
 258           http://en.wikipedia.org/wiki/X86_64
 259
 260 config BR2_xtensa
 261         bool "Xtensa"
 262         # MMU support is set by the subarchitecture file, arch/Config.in.xtensa
 263         help
 264           Xtensa is a Tensilica processor IP architecture.
 265           http://en.wikipedia.org/wiki/Xtensa
 266           http://www.tensilica.com/
 267
 268 endchoice
 269
 270 # For some architectures or specific cores, our internal toolchain
 271 # backend is not suitable (like, missing support in upstream gcc, or
 272 # no ChipCo fork exists...)
 273 config BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
 274         bool
 275
 276 config BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT
 277         bool
 278         default y if !BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
 279
 280 # The following symbols are selected by the individual
 281 # Config.in.$ARCH files
 282 config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
 283         bool
 284
 285 config BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
 286         bool
 287         select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8
 288
 289 config BR2_ARCH_NEEDS_GCC_AT_LEAST_5
 290         bool
 291         select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
 292
 293 config BR2_ARCH_NEEDS_GCC_AT_LEAST_6
 294         bool
 295         select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
 296
 297 config BR2_ARCH_NEEDS_GCC_AT_LEAST_7
 298         bool
 299         select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
 300
 301 config BR2_ARCH_NEEDS_GCC_AT_LEAST_8
 302         bool
 303         select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
 304
 305 # The following string values are defined by the individual
 306 # Config.in.$ARCH files
 307 config BR2_ARCH
 308         string
 309
 310 config BR2_ENDIAN
 311         string
 312
 313 config BR2_GCC_TARGET_ARCH
 314         string
 315
 316 config BR2_GCC_TARGET_ABI
 317         string
 318
 319 config BR2_GCC_TARGET_NAN
 320         string
 321
 322 config BR2_GCC_TARGET_FP32_MODE
 323         string
 324
 325 config BR2_GCC_TARGET_CPU
 326         string
 327
 328 # The value of this option will be passed as --with-fpu=<value> when
 329 # building gcc (internal backend) or -mfpu=<value> in the toolchain
 330 # wrapper (external toolchain)
 331 config BR2_GCC_TARGET_FPU
 332         string
 333
 334 # The value of this option will be passed as --with-float=<value> when
 335 # building gcc (internal backend) or -mfloat-abi=<value> in the toolchain
 336 # wrapper (external toolchain)
 337 config BR2_GCC_TARGET_FLOAT_ABI
 338         string
 339
 340 # The value of this option will be passed as --with-mode=<value> when
 341 # building gcc (internal backend) or -m<value> in the toolchain
 342 # wrapper (external toolchain)
 343 config BR2_GCC_TARGET_MODE
 344         string
 345
 346 # Must be selected by binary formats that support shared libraries.
 347 config BR2_BINFMT_SUPPORTS_SHARED
 348         bool
 349
 350 # Must match the name of the architecture from readelf point of view,
 351 # i.e the "Machine:" field of readelf output. See get_machine_name()
 352 # in binutils/readelf.c for the list of possible values.
 353 config BR2_READELF_ARCH_NAME
 354         string
 355
 356 # Set up target binary format
 357 choice
 358         prompt "Target Binary Format"
 359         default BR2_BINFMT_ELF if BR2_USE_MMU
 360         default BR2_BINFMT_FLAT
 361
 362 config BR2_BINFMT_ELF
 363         bool "ELF"
 364         depends on BR2_USE_MMU
 365         select BR2_BINFMT_SUPPORTS_SHARED
 366         help
 367           ELF (Executable and Linkable Format) is a format for libraries
 368           and executables used across different architectures and
 369           operating systems.
 370
 371 config BR2_BINFMT_FLAT
 372         bool "FLAT"
 373         depends on !BR2_USE_MMU
 374         help
 375           FLAT binary is a relatively simple and lightweight executable
 376           format based on the original a.out format. It is widely used
 377           in environment where no MMU is available.
 378
 379 endchoice
 380
 381 # Set up flat binary type
 382 choice
 383         prompt "FLAT Binary type"
 384         default BR2_BINFMT_FLAT_ONE
 385         depends on BR2_BINFMT_FLAT
 386
 387 config BR2_BINFMT_FLAT_ONE
 388         bool "One memory region"
 389         help
 390           All segments are linked into one memory region.
 391
 392 config BR2_BINFMT_FLAT_SHARED
 393         bool "Shared binary"
 394         depends on BR2_m68k
 395         # Even though this really generates shared binaries, there is no libdl
 396         # and dlopen() cannot be used. So packages that require shared
 397         # libraries cannot be built. Therefore, we don't select
 398         # BR2_BINFMT_SUPPORTS_SHARED and therefore force BR2_STATIC_LIBS.
 399         # Although this adds -static to the compilation, that's not a problem
 400         # because the -mid-shared-library option overrides it.
 401         help
 402           Allow to load and link indiviual FLAT binaries at run time.
 403
 404 endchoice
 405
 406 if BR2_arcle || BR2_arceb
 407 source "arch/Config.in.arc"
 408 endif
 409
 410 if BR2_arm || BR2_armeb || BR2_aarch64 || BR2_aarch64_be
 411 source "arch/Config.in.arm"
 412 endif
 413
 414 if BR2_csky
 415 source "arch/Config.in.csky"
 416 endif
 417
 418 if BR2_m68k
 419 source "arch/Config.in.m68k"
 420 endif
 421
 422 if BR2_microblazeel || BR2_microblazebe
 423 source "arch/Config.in.microblaze"
 424 endif
 425
 426 if BR2_mips || BR2_mips64 || BR2_mipsel || BR2_mips64el
 427 source "arch/Config.in.mips"
 428 endif
 429
 430 if BR2_nds32
 431 source "arch/Config.in.nds32"
 432 endif
 433
 434 if BR2_nios2
 435 source "arch/Config.in.nios2"
 436 endif
 437
 438 if BR2_or1k
 439 source "arch/Config.in.or1k"
 440 endif
 441
 442 if BR2_powerpc || BR2_powerpc64 || BR2_powerpc64le
 443 source "arch/Config.in.powerpc"
 444 endif
 445
 446 if BR2_riscv
 447 source "arch/Config.in.riscv"
 448 endif
 449
 450 if BR2_sh
 451 source "arch/Config.in.sh"
 452 endif
 453
 454 if BR2_sparc || BR2_sparc64
 455 source "arch/Config.in.sparc"
 456 endif
 457
 458 if BR2_i386 || BR2_x86_64
 459 source "arch/Config.in.x86"
 460 endif
 461
 462 if BR2_xtensa
 463 source "arch/Config.in.xtensa"
 464 endif
 465
 466 endmenu # Target options