RISC-V: Fix disassemble for c.li, c.andi and c.addiw

ChangeLog

2017-05-03  Kito Cheng  <[email protected]>

        * riscv-dis.c (print_insn_args): Handle 'Co' operands.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 355a162b0ec5142e3c31d14513fcf007d7efb98c..ea0902fc1d4bfc318d5271800c41cedbb007d9ea 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-05-03  Kito Cheng  <[email protected]>
+
+       * riscv-dis.c (print_insn_args): Handle 'Co' operands.
+
 2017-05-01  Michael Clark  <[email protected]>
 
        * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d760d701d49a43eabeae1359794e508ce842c898..bb534633102c3274f1b3a2b0fdc14370497defea 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
            case 'i':
              print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
              break;
+           case 'o':
            case 'j':
              print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
              break;