add support for Blackfin bf504/bf506

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 981149990e8955703f5389a970fbc25122172064..1506913d0823c8eb12769401e9463eedc02466e8 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2010-03-10  Mike Frysinger  <[email protected]>
+
+       * doc/c-bfin.texi (-mcpu): Add bf504 and bf506.
+       * config/tc-bfin.c (bfin_cpu_type): Add BFIN_CPU_BF504 and
+       BFIN_CPU_BF506.
+       (bfin_cpus[]): Add 0.0 for bf504 and bf506.
+

 2010-03-10  Jie Zhang  <[email protected]>
 
        * doc/as.texinfo: Add Blackfin options.
 2010-03-10  Jie Zhang  <[email protected]>
 
        * doc/as.texinfo: Add Blackfin options.

diff --git a/gas/config/tc-bfin.c b/gas/config/tc-bfin.c
index 6680f22361aed4ef7eae1cd3b078be56152e06b4..7d4f1cdb814b6f39e77e196d08bc66904c504057 100644 (file)
--- a/gas/config/tc-bfin.c
+++ b/gas/config/tc-bfin.c
@@ -151,6 +151,8 @@ const char FLT_CHARS[] = "fFdDxX";
 typedef enum bfin_cpu_type
 {
   BFIN_CPU_UNKNOWN,
 typedef enum bfin_cpu_type
 {
   BFIN_CPU_UNKNOWN,

+  BFIN_CPU_BF504,
+  BFIN_CPU_BF506,

   BFIN_CPU_BF512,
   BFIN_CPU_BF514,
   BFIN_CPU_BF516,
   BFIN_CPU_BF512,
   BFIN_CPU_BF514,
   BFIN_CPU_BF516,


@@ -200,6 +202,10 @@ struct bfin_cpu
 
 struct bfin_cpu bfin_cpus[] =
 {
 
 struct bfin_cpu bfin_cpus[] =
 {

+  {"bf504", BFIN_CPU_BF504, 0x0000, AC_05000074},
+
+  {"bf506", BFIN_CPU_BF506, 0x0000, AC_05000074},
+

   {"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074},
   {"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074},
 
   {"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074},
   {"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074},
 

diff --git a/gas/doc/c-bfin.texi b/gas/doc/c-bfin.texi
index e2749d38752ddc64777385c64c1eb5962cffb6a3..60c3360e5266ed97f2921cb9046c57c5fdfd3bba 100644 (file)
--- a/gas/doc/c-bfin.texi
+++ b/gas/doc/c-bfin.texi
@@ -34,6 +34,8 @@ is not used in assembler.  It's here such that GCC can easily pass down its
 error message if an attempt is made to assemble an instruction which
 will not execute on the target processor.  The following processor names are
 recognized: 
 error message if an attempt is made to assemble an instruction which
 will not execute on the target processor.  The following processor names are
 recognized: 

+@code{bf504},
+@code{bf506},

 @code{bf512},
 @code{bf514},
 @code{bf516},
 @code{bf512},
 @code{bf514},
 @code{bf516},