sim: bfin: fix typos in large constants in tests

Truncate constants that are larger than 32bits but get loaded into 32bit
registers.  These high bits don't get used and don't really make sense.

diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog
index 849f2b2280e2cdf2cbad9d4133d8203cb50fb53d..6dbe3ee035b094c1593538c5259b99dd0156c88b 100644 (file)
--- a/sim/testsuite/sim/bfin/ChangeLog
+++ b/sim/testsuite/sim/bfin/ChangeLog
@@ -1,3 +1,11 @@
+2012-03-25  Mike Frysinger  <[email protected]>
+
+       * c_dsp32mac_dr_a1a0.s: Change 0x12efbc5569 to 0xefbc5569.
+       * c_dsp32mac_dr_a1a0_iutsh.s: Change 0x12efbc556 to 0x2efbc556.
+       * c_dsp32mac_dr_a1a0_m.s: Change 0x12efbc5569 to 0xefbc5569.
+       * c_dsp32shift_vmaxvmax.s: Change 0xa11002001 to 0x11002001.
+       * c_dsp32shiftim_af_s.s: Change 0x3a1230001 to 0xa1230001.
+
 2012-03-19  Mike Frysinger  <[email protected]>
 
        * se_all64bitg0opcodes.S, se_all64bitg1opcodes.S,

diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s
index 700cbdf4d307af59bf5606a5f4509d672929634c..e84f3d59030b2a90598dc49078d2838b8f801bc8 100644 (file)
--- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s
+++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0.s
@@ -14,7 +14,7 @@
        imm32 r1, 0xb2bcfec7;
        imm32 r2, 0xc1348679;
        imm32 r3, 0xd0049007;
-       imm32 r4, 0x12efbc5569;
+       imm32 r4, 0xefbc5569;
        imm32 r5, 0xcd35560b;
        imm32 r6, 0xe00c807d;
        imm32 r7, 0xf78e9008;

diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s
index 8d4232e3a03761d604ffcf6c6a8986d12f9a23a8..8f9e70c5ee92ff2af443f3b8d799cd80d80a7957 100644 (file)
--- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s
+++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_iutsh.s
@@ -14,7 +14,7 @@
        imm32 r1, 0xb2bcfec7;
        imm32 r2, 0xc1348679;
        imm32 r3, 0xd0049007;
-       imm32 r4, 0x12efbc556;
+       imm32 r4, 0x2efbc556;
        imm32 r5, 0xcd35560b;
        imm32 r6, 0xe00c807d;
        imm32 r7, 0xf78e9008;

diff --git a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s
index 75fcc43292fb74e057e95c3f6e0bf13670fff07e..2b6f741ac8aae7dbb5ca990d91f63fcf2aea7a90 100644 (file)
--- a/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s
+++ b/sim/testsuite/sim/bfin/c_dsp32mac_dr_a1a0_m.s
@@ -14,7 +14,7 @@
        imm32 r1, 0xb2bcfec7;
        imm32 r2, 0xc1348679;
        imm32 r3, 0xd0049007;
-       imm32 r4, 0x12efbc5569;
+       imm32 r4, 0xefbc5569;
        imm32 r5, 0xcd35560b;
        imm32 r6, 0xe00c807d;
        imm32 r7, 0xf78e9008;

diff --git a/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s b/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s
index 48e8d4bef52e34474cca6779680c912c05bb4a8a..0d4722ae60db5b4821a0cdc15848c1d635cb6c4c 100644 (file)
--- a/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s
+++ b/sim/testsuite/sim/bfin/c_dsp32shift_vmaxvmax.s
@@ -33,7 +33,7 @@ CHECKREG r5, 0x71004300;
 CHECKREG r6, 0x81007100;
 CHECKREG r7, 0x19008100;
 
-imm32 r0, 0xa11002001;
+imm32 r0, 0x11002001;
 imm32 r1, 0xd2001001;
 imm32 r2, 0x14301302;
 imm32 r3, 0x43001003;

diff --git a/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s b/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s
index 748d8c976343c9af32226c0e50f6f98273bfb5c5..5fdf02a0efc0da96f4ae2bbbe5c7faf5bca03531 100644 (file)
--- a/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s
+++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_af_s.s
@@ -33,7 +33,7 @@ CHECKREG r5, 0x80000000;
 CHECKREG r6, 0x80000000;
 CHECKREG r7, 0x80000000;
 
-imm32 r0, 0x3a1230001;
+imm32 r0, 0xa1230001;
 imm32 r1, 0x1e345678;
 imm32 r2, 0x23f56789;
 imm32 r3, 0x34db789a;