Fix cmov insn.

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 87870078d77da0fc80cf4e420f920452cc2b8007..647435526fa31c7b3a1fd90181e57fa0dec1f40a 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,12 @@
+Fri Sep 19 10:37:20 1997  Andrew Cagney  <[email protected]>
+
+       * simops.c (condition_met): Make global.
+       * sim-main.h (TRACE_ALU_INPUT3): Define.
+
+start-sanitize-v850e
+       * simops.c (OP_32007E0): Move "cmov" to v850.igen, fix.
+
+end-sanitize-v850e
 Wed Sep 17 16:21:08 1997  Andrew Cagney  <[email protected]>
 
        * simops.c: Move "mov", "reti", to v850.igen, fix tracing.

diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index a4c57af01050eae85878be748fca8e1b23ff59fa..2d1bf6a9a65943a2cdd69bb3f133347e1923420c 100644 (file)
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -224,6 +224,10 @@ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
                                PC, sim_core_write_map, (ADDR), (DATA))
 
 
+/* compare cccc field against PSW */
+unsigned int condition_met (unsigned code);
+
+
 /* Debug/tracing calls */
 
 enum op_types
@@ -310,6 +314,19 @@ do { \
   } \
 } while (0)
 
+#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \
+do { \
+  if (TRACE_ALU_P (CPU)) { \
+    trace_module = "alu"; \
+    trace_pc = cia; \
+    trace_name = itable[MY_INDEX].name; \
+    trace_values[0] = (IN0); \
+    trace_values[1] = (IN1); \
+    trace_values[2] = (IN2); \
+    trace_num_values = 3; \
+  } \
+} while (0)
+
 #define TRACE_ALU_RESULT(RESULT) \
 do { \
   if (TRACE_ALU_P (CPU)) { \

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 8a360a31bb47b4d62a1f1ce08b8ef460e3b8ab6d..b55b430218009a2d315bacb3bc9aa960580c46e9 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -305,7 +305,7 @@ trace_output (result)
 
 \f
 /* Returns 1 if the specific condition is met, returns 0 otherwise.  */
-static unsigned int
+unsigned int
 condition_met (unsigned code)
 {
   unsigned int psw = PSW;
@@ -2896,21 +2896,6 @@ OP_70 (void)
   return 2;
 }
 
-/* end-sanitize-v850e */
-/* start-sanitize-v850e */
-/* cmov reg1, reg2, reg3 */
-int
-OP_32007E0 (void)
-{
-  trace_input ("cmov", OP_REG_REG_REG, 0);
-
-  State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
-  
-  trace_output (OP_REG_REG_REG);
-
-  return 4;
-}
-
 /* end-sanitize-v850e */
 /* start-sanitize-v850e */
 /* mul reg1, reg2, reg3 */

diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index fd45a3057219b4913b1075b0cc2167fbaaf14ec6..192a302a29774c4df7b108a1640e381c392cde1d 100644 (file)
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -353,7 +353,9 @@ rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
 // end-sanitize-v850eq
 "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
 {
-  COMPAT_2 (OP_32007E0 ());
+  TRACE_ALU_INPUT3 (cccc, GR[reg1], GR[reg2]);
+  GR[reg3] = condition_met (cccc) ? GR[reg1] : GR[reg2];
+  TRACE_ALU_RESULT (GR[reg3]);
 }
 
 // end-sanitize-v850e