Emit error for unaligned instructions.

	* config/tc-ia64.c (emit_one_bundle): Check and set insn_addr.
	* config/tc-ia64.h (md_frag_check): Define.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f02d2a816d2f7f7387f76633c7e7736a23f78aa4..86101d4fd423c4d28773571c73aba4aee0d35afa 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2004-07-03  James E Wilson  <[email protected]>
+
+       * config/tc-ia64.c (emit_one_bundle): Check and set insn_addr.
+       * config/tc-ia64.h (md_frag_check): Define.
+
 2004-07-03  Aaron W. LaFramboise  <[email protected]>
 
        * config/obj-coff.c (obj_coff_weak): New .weak syntax for PE weak

diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c
index 3d153ae69761b706dad1077d62488060b218d195..74ee21512598512efd291f273546fe6a574278f4 100644 (file)
--- a/gas/config/tc-ia64.c
+++ b/gas/config/tc-ia64.c
@@ -6129,6 +6129,7 @@ emit_one_bundle ()
   char mnemonic[16];
   fixS *fix;
   char *f;
+  int addr_mod;
 
   first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
   know (first >= 0 & first < NUM_SLOTS);
@@ -6160,6 +6161,14 @@ emit_one_bundle ()
 
   f = frag_more (16);
 
+  /* Check to see if this bundle is at an offset that is a multiple of 16-bytes
+     from the start of the frag.  */
+  addr_mod = frag_now_fix () & 15;
+  if (frag_now->has_code && frag_now->insn_addr != addr_mod)
+    as_bad (_("instruction address is not a multiple of 16"));
+  frag_now->insn_addr = addr_mod;
+  frag_now->has_code = 1;
+
   /* now fill in slots with as many insns as possible:  */
   curr = first;
   idesc = md.slot[curr].idesc;

diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h
index dcc2c299602dcd28944479805f65beb673715caf..f626c4600f25a6cc0a927208eefa6cdef609a090 100644 (file)
--- a/gas/config/tc-ia64.h
+++ b/gas/config/tc-ia64.h
@@ -158,6 +158,14 @@ extern void ia64_convert_frag (fragS *);
 #define TC_FRAG_TYPE                   int
 #define TC_FRAG_INIT(FRAGP)            do {(FRAGP)->tc_frag_data = 0;}while (0)
 
+/* Give an error if a frag containing code is not aligned to a 16 byte
+   boundary.  */
+#define md_frag_check(FRAGP) \
+  if ((FRAGP)->has_code                                                        \
+      && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 15) != 0)       \
+     as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line,                 \
+                  _("instruction address is not a multiple of 16"));
+
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (15 + 16)
 
 #define WORKING_DOT_WORD       /* don't do broken word processing for now */