+
+ * gas/s390/zarch-z13.d: Fix tests for VFCE, VLDE, VFSQ, WFK, and
+ WFC.
+ * gas/s390/zarch-z13.s: Likewise.
+
* gas/arm/align64.d: Delete trailing padding NOPs.
.*: e7 f1 40 0c d6 e3 [ ]*vfa %v15,%v17,%v20,13,12
.*: e7 f1 40 00 36 e3 [ ]*vfadb %v15,%v17,%v20
.*: e7 f1 40 08 36 e3 [ ]*wfadb %v15,%v17,%v20
-.*: e7 f1 00 cd 04 cb [ ]*wfc %v15,%v17,13,12
+.*: e7 f1 00 0c d4 cb [ ]*wfc %v15,%v17,13,12
.*: e7 f1 00 00 34 cb [ ]*wfcdb %v15,%v17
-.*: e7 f1 00 cd 04 ca [ ]*wfk %v15,%v17,13,12
+.*: e7 f1 00 0c d4 ca [ ]*wfk %v15,%v17,13,12
.*: e7 f1 00 00 34 ca [ ]*wfkdb %v15,%v17
-.*: e7 f1 40 00 06 e8 [ ]*vfce %v15,%v17,%v20
+.*: e7 f1 40 bc d6 e8 [ ]*vfce %v15,%v17,%v20,13,12,11
.*: e7 f1 40 00 36 e8 [ ]*vfcedb %v15,%v17,%v20
.*: e7 f1 40 10 36 e8 [ ]*vfcedbs %v15,%v17,%v20
.*: e7 f1 40 08 36 e8 [ ]*wfcedb %v15,%v17,%v20
.*: e7 f1 00 bc d4 c7 [ ]*vfi %v15,%v17,13,12,11
.*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12
.*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12
-.*: e7 f1 00 cd 04 c4 [ ]*vlde %v15,%v17,13,12
+.*: e7 f1 00 0c d4 c4 [ ]*vlde %v15,%v17,13,12
.*: e7 f1 00 00 24 c4 [ ]*vldeb %v15,%v17
.*: e7 f1 00 08 24 c4 [ ]*wldeb %v15,%v17
.*: e7 f1 00 bc d4 c5 [ ]*vled %v15,%v17,13,12,11
.*: e7 f1 00 18 34 cc [ ]*wflndb %v15,%v17
.*: e7 f1 00 20 34 cc [ ]*vflpdb %v15,%v17
.*: e7 f1 00 28 34 cc [ ]*wflpdb %v15,%v17
-.*: e7 f1 00 cd 04 ce [ ]*vfsq %v15,%v17,13,12
+.*: e7 f1 00 0c d4 ce [ ]*vfsq %v15,%v17,13,12
.*: e7 f1 00 00 34 ce [ ]*vfsqdb %v15,%v17
.*: e7 f1 00 08 34 ce [ ]*wfsqdb %v15,%v17
.*: e7 f1 40 0c d6 e2 [ ]*vfs %v15,%v17,%v20,13,12
wfcdb %v15,%v17
wfk %v15,%v17,13,12
wfkdb %v15,%v17
- vfce %v15,%v17,%v20
+ vfce %v15,%v17,%v20,13,12,11
vfcedb %v15,%v17,%v20
vfcedbs %v15,%v17,%v20
wfcedb %v15,%v17,%v20
+
+ * s390-opc.c: New instruction type VV0UU2.
+ * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
+ and WFC.
+
* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
#define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */
#define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/
#define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */
+#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */
#define INSTR_VRR_VV0UU8 6, { V_8,V_12,U4_OR8_28,U4_24,0,0 } /* e.g. wcdgb */
#define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */
#define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */
#define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff }
#define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff }
#define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff }
+#define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff }
#define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff }
#define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff }
#define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff }
e700000000e3 vfa VRR_VVV0UU "vector fp add" z13 zarch
e700000030e3 vfadb VRR_VVV "vector fp add" z13 zarch
e700000830e3 wfadb VRR_VVV "vector fp add" z13 zarch
-e700000000cb wfc VRR_VV0UU "vector fp compare scalar" z13 zarch
+e700000000cb wfc VRR_VV0UU2 "vector fp compare scalar" z13 zarch
e700000030cb wfcdb VRR_VV "vector fp compare scalar" z13 zarch
-e700000000ca wfk VRR_VV0UU "vector fp compare and signal scalar" z13 zarch
+e700000000ca wfk VRR_VV0UU2 "vector fp compare and signal scalar" z13 zarch
e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar" z13 zarch
-e700000000e8 vfce VRR_VVV "vector fp compare equal" z13 zarch
+e700000000e8 vfce VRR_VVV0UUU "vector fp compare equal" z13 zarch
e700000030e8 vfcedb VRR_VVV "vector fp compare equal" z13 zarch
e700001030e8 vfcedbs VRR_VVV "vector fp compare equal" z13 zarch
e700000830e8 wfcedb VRR_VVV "vector fp compare equal" z13 zarch
e700000000c7 vfi VRR_VV0UUU "vector load fp integer" z13 zarch
e700000030c7 vfidb VRR_VV0UU "vector load fp integer" z13 zarch
e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer" z13 zarch
-e700000000c4 vlde VRR_VV0UU "vector fp load lengthened" z13 zarch
+e700000000c4 vlde VRR_VV0UU2 "vector fp load lengthened" z13 zarch
e700000020c4 vldeb VRR_VV "vector fp load lengthened" z13 zarch
e700000820c4 wldeb VRR_VV "vector fp load lengthened" z13 zarch
e700000000c5 vled VRR_VV0UUU "vector fp load rounded" z13 zarch
e700001830cc wflndb VRR_VV "vector fp perform sign operation" z13 zarch
e700002030cc vflpdb VRR_VV "vector fp perform sign operation" z13 zarch
e700002830cc wflpdb VRR_VV "vector fp perform sign operation" z13 zarch
-e700000000ce vfsq VRR_VV0UU "vector fp square root" z13 zarch
+e700000000ce vfsq VRR_VV0UU2 "vector fp square root" z13 zarch
e700000030ce vfsqdb VRR_VV "vector fp square root" z13 zarch
e700000830ce wfsqdb VRR_VV "vector fp square root" z13 zarch
e700000000e2 vfs VRR_VVV0UU "vector fp subtract" z13 zarch