sim/mips/m16.igen

   1 // -*- C -*-
   2 //
   3 //
   4 // MIPS Architecture:
   5 //
   6 //        CPU Instruction Set (mips16)
   7 //
   8
   9 // The instructions in this section are ordered according
  10 // to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
  11
  12
  13 // The MIPS16 codes registers in a special way, map from one to the other.
  14 // :<type>:<flags>:<models>:<typedef>:<name>:<field>:<expression>
  15 :compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
  16 :compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
  17 :compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
  18 :compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
  19
  20 :compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0)
  21
  22 :compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0))
  23 :compute:::int:R32:R32L,R32H:((R32H << 3) | R32L)
  24
  25 :compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0))
  26
  27 :compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0))
  28
  29 // FIXME:
  30 //
  31 // Only the `LB' instruction is implemented.  It should be used as a guideline
  32 // when implementing other instructions.
  33 //
  34 // How to handle delayslots (for jumps) and extended lwpc instructions
  35 // has not been resolved.
  36
  37
  38 // Load and Store Instructions
  39
  40
  41 10000,3.RX,3.RY,5.IMMED:RRI:16::LB
  42 "lb r<TRY>, <IMMED> (r<TRX>)"
  43 *mips16:
  44 // start-sanitize-tx19
  45 *tx19:
  46 // end-sanitize-tx19
  47 {
  48   GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
  49 }
  50
  51 11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB
  52 "lb r<TRY>, <IMMEDIATE> (r<TRX>)"
  53 *mips16:
  54 // start-sanitize-tx19
  55 *tx19:
  56 // end-sanitize-tx19
  57 {
  58   GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
  59 }
  60
  61
  62
  63 10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
  64 "lbu r<TRY>, <IMMED> (r<TRX>)"
  65 *mips16:
  66 // start-sanitize-tx19
  67 *tx19:
  68 // end-sanitize-tx19
  69 {
  70   GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
  71 }
  72
  73 11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU
  74 "lbu r<TRY>, <IMMEDIATE> (r<TRX>)"
  75 *mips16:
  76 // start-sanitize-tx19
  77 *tx19:
  78 // end-sanitize-tx19
  79 {
  80   GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
  81 }
  82
  83
  84
  85 10001,3.RX,3.RY,5.IMMED:RRI:16::LH
  86 "lh r<TRY>, <IMMED> (r<TRX>)"
  87 *mips16:
  88 // start-sanitize-tx19
  89 *tx19:
  90 // end-sanitize-tx19
  91 {
  92   GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
  93 }
  94
  95 11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH
  96 "lh r<TRY>, <IMMEDIATE> (r<TRX>)"
  97 *mips16:
  98 // start-sanitize-tx19
  99 *tx19:
 100 // end-sanitize-tx19
 101 {
 102   GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
 103 }
 104
 105
 106
 107 10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
 108 "lhu r<TRY>, <IMMED> (r<TRX>)"
 109 *mips16:
 110 // start-sanitize-tx19
 111 *tx19:
 112 // end-sanitize-tx19
 113 {
 114   GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
 115 }
 116
 117 11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU
 118 "lhu r<TRY>, <IMMEDIATE> (r<TRX>)"
 119 *mips16:
 120 // start-sanitize-tx19
 121 *tx19:
 122 // end-sanitize-tx19
 123 {
 124   GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
 125 }
 126
 127
 128
 129 10011,3.RX,3.RY,5.IMMED:RRI:16::LW
 130 "lw r<TRY>, <IMMED> (r<TRX>)"
 131 *mips16:
 132 // start-sanitize-tx19
 133 *tx19:
 134 // end-sanitize-tx19
 135 {
 136   GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
 137 }
 138
 139 11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW
 140 "lw r<TRY>, <IMMEDIATE> (r<TRX>)"
 141 *mips16:
 142 // start-sanitize-tx19
 143 *tx19:
 144 // end-sanitize-tx19
 145 {
 146   GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
 147 }
 148
 149
 150
 151 10110,3.RX,8.IMMED:RI:16::LWPC
 152 "lw r<TRX>, <IMMED> (PC)"
 153 *mips16:
 154 // start-sanitize-tx19
 155 *tx19:
 156 // end-sanitize-tx19
 157 {
 158   GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
 159                                 basepc (SD_) & ~3, IMMED << 2));
 160 }
 161
 162 11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC
 163 "lw r<TRX>, <IMMEDIATE> (PC)"
 164 *mips16:
 165 // start-sanitize-tx19
 166 *tx19:
 167 // end-sanitize-tx19
 168 {
 169   GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE)));
 170 }
 171
 172
 173
 174 10010,3.RX,8.IMMED:RI:16::LWSP
 175 "lw r<TRX>, <IMMED> (SP)"
 176 *mips16:
 177 // start-sanitize-tx19
 178 *tx19:
 179 // end-sanitize-tx19
 180 {
 181   GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
 182 }
 183
 184 11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP
 185 "lw r<TRX>, <IMMEDIATE> (SP)"
 186 *mips16:
 187 // start-sanitize-tx19
 188 *tx19:
 189 // end-sanitize-tx19
 190 {
 191   GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE)));
 192 }
 193
 194
 195
 196 10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
 197 "lwu r<TRY>, <IMMED> (r<TRX>)"
 198 *mips16:
 199 // start-sanitize-tx19
 200 *tx19:
 201 // end-sanitize-tx19
 202 {
 203   GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
 204 }
 205
 206 11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU
 207 "lwu r<TRY>, <IMMEDIATE> (r<TRX>)"
 208 *mips16:
 209 // start-sanitize-tx19
 210 *tx19:
 211 // end-sanitize-tx19
 212 {
 213   GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE));
 214 }
 215
 216
 217
 218 00111,3.RX,3.RY,5.IMMED:RRI:16,64::LD
 219 "ld r<TRY>, <IMMED> (r<TRX>)"
 220 *mips16:
 221 // start-sanitize-tx19
 222 *tx19:
 223 // end-sanitize-tx19
 224 {
 225   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
 226 }
 227
 228 11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16,64::LD
 229 "ld r<TRY>, <IMMED> (r<TRX>)"
 230 *mips16:
 231 // start-sanitize-tx19
 232 *tx19:
 233 // end-sanitize-tx19
 234 {
 235   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
 236 }
 237
 238
 239
 240 11111,100,3.RY,5.IMMED:RI64:16::LDPC
 241 "ld r<TRY>, <IMMED> (PC)"
 242 *mips16:
 243 // start-sanitize-tx19
 244 *tx19:
 245 // end-sanitize-tx19
 246 {
 247   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
 248                       basepc (SD_) & ~7, IMMED << 3);
 249 }
 250
 251 11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC
 252 "ld r<TRY>, <IMMEDIATE> (PC)"
 253 *mips16:
 254 // start-sanitize-tx19
 255 *tx19:
 256 // end-sanitize-tx19
 257 {
 258   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE));
 259 }
 260
 261
 262
 263 11111,000,3.RY,5.IMMED:RI64:16::LDSP
 264 "ld r<TRY>, <IMMED> (SP)"
 265 *mips16:
 266 // start-sanitize-tx19
 267 *tx19:
 268 // end-sanitize-tx19
 269 {
 270   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
 271 }
 272
 273 11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP
 274 "ld r<TRY>, <IMMEDIATE> (SP)"
 275 *mips16:
 276 // start-sanitize-tx19
 277 *tx19:
 278 // end-sanitize-tx19
 279 {
 280   GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE));
 281 }
 282
 283
 284
 285 11000,3.RX,3.RY,5.IMMED:RRI:16::SB
 286 "sb r<TRY>, <IMMED> (r<TRX>)"
 287 *mips16:
 288 // start-sanitize-tx19
 289 *tx19:
 290 // end-sanitize-tx19
 291 {
 292   do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
 293 }
 294
 295 11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB
 296 "sb r<TRY>, <IMMEDIATE> (r<TRX>)"
 297 *mips16:
 298 // start-sanitize-tx19
 299 *tx19:
 300 // end-sanitize-tx19
 301 {
 302   do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
 303 }
 304
 305
 306
 307 11001,3.RX,3.RY,5.IMMED:RRI:16::SH
 308 "sh r<TRY>, <IMMED> (r<TRX>)"
 309 *mips16:
 310 // start-sanitize-tx19
 311 *tx19:
 312 // end-sanitize-tx19
 313 {
 314   do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
 315 }
 316
 317 11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH
 318 "sh r<TRY>, <IMMEDIATE> (r<TRX>)"
 319 *mips16:
 320 // start-sanitize-tx19
 321 *tx19:
 322 // end-sanitize-tx19
 323 {
 324   do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
 325 }
 326
 327
 328
 329 11011,3.RX,3.RY,5.IMMED:RRI:16::SW
 330 "sw r<TRY>, <IMMED> (r<TRX>)"
 331 *mips16:
 332 // start-sanitize-tx19
 333 *tx19:
 334 // end-sanitize-tx19
 335 {
 336   do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
 337 }
 338
 339 11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW
 340 "sw r<TRY>, <IMMEDIATE> (r<TRX>)"
 341 *mips16:
 342 // start-sanitize-tx19
 343 *tx19:
 344 // end-sanitize-tx19
 345 {
 346   do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
 347 }
 348
 349
 350
 351 11010,3.RX,8.IMMED:RI:16::SWSP
 352 "sw r<TRX>, <IMMED> (SP)"
 353 *mips16:
 354 // start-sanitize-tx19
 355 *tx19:
 356 // end-sanitize-tx19
 357 {
 358   do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
 359 }
 360
 361 11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP
 362 "sw r<TRX>, <IMMEDIATE> (SP)"
 363 *mips16:
 364 // start-sanitize-tx19
 365 *tx19:
 366 // end-sanitize-tx19
 367 {
 368   do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]);
 369 }
 370
 371
 372
 373 01100,010,8.IMMED:I8:16::SWRASP
 374 "sw r<RAIDX>, <IMMED> (SP)"
 375 *mips16:
 376 // start-sanitize-tx19
 377 *tx19:
 378 // end-sanitize-tx19
 379 {
 380   do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
 381 }
 382
 383 11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP
 384 "sw r<RAIDX>, <IMMEDIATE> (SP)"
 385 *mips16:
 386 // start-sanitize-tx19
 387 *tx19:
 388 // end-sanitize-tx19
 389 {
 390   do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA);
 391 }
 392
 393
 394
 395 01111,3.RX,3.RY,5.IMMED:RRI:16::SD
 396 "sd r<TRY>, <IMMED> (r<TRX>)"
 397 *mips16:
 398 // start-sanitize-tx19
 399 *tx19:
 400 // end-sanitize-tx19
 401 {
 402   do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
 403 }
 404
 405 11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD
 406 "sd r<TRY>, <IMMEDIATE> (r<TRX>)"
 407 *mips16:
 408 // start-sanitize-tx19
 409 *tx19:
 410 // end-sanitize-tx19
 411 {
 412   do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
 413 }
 414
 415
 416
 417 11111,001,3.RY,5.IMMED:RI64:16::SDSP
 418 "sd r<TRY>, <IMMED> (SP)"
 419 *mips16:
 420 // start-sanitize-tx19
 421 *tx19:
 422 // end-sanitize-tx19
 423 {
 424   do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
 425 }
 426
 427 11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP
 428 "sd r<TRY>, <IMMEDIATE> (SP)"
 429 *mips16:
 430 // start-sanitize-tx19
 431 *tx19:
 432 // end-sanitize-tx19
 433 {
 434   do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]);
 435 }
 436
 437
 438
 439 11111,010,8.IMMED:I64:16::SDRASP
 440 "sd r<RAIDX>, <IMMED> (SP)"
 441 *mips16:
 442 // start-sanitize-tx19
 443 *tx19:
 444 // end-sanitize-tx19
 445 {
 446   do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
 447 }
 448
 449 11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP
 450 "sd r<RAIDX>, <IMMEDIATE> (SP)"
 451 *mips16:
 452 // start-sanitize-tx19
 453 *tx19:
 454 // end-sanitize-tx19
 455 {
 456   do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA);
 457 }
 458
 459
 460
 461 // ALU Immediate Instructions
 462
 463
 464 01101,3.RX,8.IMMED:RI:16::LI
 465 "li r<TRX>, <IMMED>"
 466 *mips16:
 467 // start-sanitize-tx19
 468 *tx19:
 469 // end-sanitize-tx19
 470 {
 471   do_ori (SD_, 0, TRX, IMMED);
 472 }
 473
 474 11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI
 475 "li r<TRX>, <IMMEDIATE>"
 476 *mips16:
 477 // start-sanitize-tx19
 478 *tx19:
 479 // end-sanitize-tx19
 480 {
 481   do_ori (SD_, 0, TRX, IMMEDIATE);
 482 }
 483
 484
 485
 486 01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU
 487 "addiu r<TRY>, r<TRX>, <IMMED>"
 488 *mips16:
 489 // start-sanitize-tx19
 490 *tx19:
 491 // end-sanitize-tx19
 492 {
 493   do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
 494 }
 495
 496 11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU
 497 "addiu r<TRY>, r<TRX>, <IMMEDIATE>"
 498 *mips16:
 499 // start-sanitize-tx19
 500 *tx19:
 501 // end-sanitize-tx19
 502 {
 503   do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
 504 }
 505
 506
 507
 508 01001,3.RX,8.IMMED:RI:16::ADDIU8
 509 "addiu r<TRX>, <IMMED>"
 510 *mips16:
 511 // start-sanitize-tx19
 512 *tx19:
 513 // end-sanitize-tx19
 514 {
 515   do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
 516 }
 517
 518 11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8
 519 "addiu r<TRX>, <IMMEDIATE>"
 520 *mips16:
 521 // start-sanitize-tx19
 522 *tx19:
 523 // end-sanitize-tx19
 524 {
 525   do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE));
 526 }
 527
 528
 529
 530 01100,011,8.IMMED:I8:16::ADJSP
 531 "addiu SP, <IMMED>"
 532 *mips16:
 533 // start-sanitize-tx19
 534 *tx19:
 535 // end-sanitize-tx19
 536 {
 537   do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
 538 }
 539
 540 11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP
 541 "addiu SP, <IMMEDIATE>"
 542 *mips16:
 543 // start-sanitize-tx19
 544 *tx19:
 545 // end-sanitize-tx19
 546 {
 547   do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
 548 }
 549
 550
 551
 552 00001,3.RX,8.IMMED:RI:16::ADDIUPC
 553 "addiu r<TRX>, PC, <IMMED>"
 554 *mips16:
 555 // start-sanitize-tx19
 556 *tx19:
 557 // end-sanitize-tx19
 558 {
 559   unsigned32 temp = (basepc (SD_) & ~3) + (EXTEND8 (IMMED) << 2);
 560   GPR[TRX] = EXTEND32 (temp);
 561 }
 562
 563 11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC
 564 "addiu r<TRX>, PC, <IMMEDIATE>"
 565 *mips16:
 566 // start-sanitize-tx19
 567 *tx19:
 568 // end-sanitize-tx19
 569 {
 570   unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
 571   GPR[TRX] = EXTEND32 (temp);
 572 }
 573
 574
 575
 576 00000,3.RX,8.IMMED:RI:16::ADDIUSP
 577 "addiu r<TRX>, SP, <IMMED>"
 578 *mips16:
 579 // start-sanitize-tx19
 580 *tx19:
 581 // end-sanitize-tx19
 582 {
 583   do_addiu (SD_, SPIDX, TRX, EXTEND8 (IMMED) << 2);
 584 }
 585
 586 11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP
 587 "addiu r<TRX>, SP, <IMMEDIATE>"
 588 *mips16:
 589 // start-sanitize-tx19
 590 *tx19:
 591 // end-sanitize-tx19
 592 {
 593   do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE));
 594 }
 595
 596
 597
 598 01000,3.RX,3.RY,1,4.IMMED:RRI-A:16,64::DADDIU
 599 "daddiu r<TRY>, r<TRX>, <IMMED>"
 600 *mips16:
 601 // start-sanitize-tx19
 602 *tx19:
 603 // end-sanitize-tx19
 604 {
 605   do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
 606 }
 607
 608 11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16,64::DADDIU
 609 "daddiu r<TRY>, r<TRX>, <IMMED>"
 610 *mips16:
 611 // start-sanitize-tx19
 612 *tx19:
 613 // end-sanitize-tx19
 614 {
 615   do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
 616 }
 617
 618
 619
 620 11111,101,3.RY,5.IMMED:RI64:16,64::DADDIU5
 621 "daddiu r<TRY>, <IMMED>"
 622 *mips16:
 623 // start-sanitize-tx19
 624 *tx19:
 625 // end-sanitize-tx19
 626 {
 627   do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
 628 }
 629
 630 11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16,64::DADDIU5
 631 "daddiu r<TRY>, <IMMED>"
 632 *mips16:
 633 // start-sanitize-tx19
 634 *tx19:
 635 // end-sanitize-tx19
 636 {
 637   do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMEDIATE));
 638 }
 639
 640
 641
 642 11111,011,8.IMMED:I64:16,64::DADJSP
 643 "daddiu SP, <IMMED>"
 644 *mips16:
 645 // start-sanitize-tx19
 646 *tx19:
 647 // end-sanitize-tx19
 648 {
 649   do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
 650 }
 651
 652 11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16,64::DADJSP
 653 "daddiu SP, <IMMED>"
 654 *mips16:
 655 // start-sanitize-tx19
 656 *tx19:
 657 // end-sanitize-tx19
 658 {
 659   do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
 660 }
 661
 662
 663
 664 11111,110,3.RY,5.IMMED:RI64:16,64::DADDIUPC
 665 "daddiu r<TRY>, PC, <IMMED>"
 666 *mips16:
 667 // start-sanitize-tx19
 668 *tx19:
 669 // end-sanitize-tx19
 670 {
 671   GPR[TRY] = (basepc (SD_) & ~3) + (EXTEND5 (IMMED) << 2);
 672 }
 673
 674 11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16,64::DADDIUPC
 675 "daddiu r<TRY>, PC, <IMMED>"
 676 *mips16:
 677 // start-sanitize-tx19
 678 *tx19:
 679 // end-sanitize-tx19
 680 {
 681   GPR[TRY] = (basepc (SD_) & ~3) + EXTEND5 (IMMED);
 682 }
 683
 684
 685
 686 11111,111,3.RY,5.IMMED:RI64:16,64::DADDIUSP
 687 "daddiu r<TRY>, SP, <IMMED>"
 688 *mips16:
 689 // start-sanitize-tx19
 690 *tx19:
 691 // end-sanitize-tx19
 692 {
 693   do_daddiu (SD_, SPIDX, TRY, EXTEND5 (IMMED) << 2);
 694 }
 695
 696 11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16,64::DADDIUSP
 697 "daddiu r<TRY>, SP, <IMMED>"
 698 *mips16:
 699 // start-sanitize-tx19
 700 *tx19:
 701 // end-sanitize-tx19
 702 {
 703   do_daddiu (SD_, SPIDX, TRY, EXTEND5 (IMMED));
 704 }
 705
 706
 707
 708 01010,3.RX,8.IMMED:RI:16::SLTI
 709 "slti r<TRX>, <IMMED>"
 710 *mips16:
 711 // start-sanitize-tx19
 712 *tx19:
 713 // end-sanitize-tx19
 714 {
 715   do_slti (SD_, TRX, T8IDX, IMMED);
 716 }
 717
 718 11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI
 719 "slti r<TRX>, <IMMEDIATE>"
 720 *mips16:
 721 // start-sanitize-tx19
 722 *tx19:
 723 // end-sanitize-tx19
 724 {
 725   do_slti (SD_, TRX, T8IDX, IMMEDIATE);
 726 }
 727
 728
 729
 730 01011,3.RX,8.IMMED:RI:16::SLTIU
 731 "sltiu r<TRX>, <IMMED>"
 732 *mips16:
 733 // start-sanitize-tx19
 734 *tx19:
 735 // end-sanitize-tx19
 736 {
 737   do_sltiu (SD_, TRX, T8IDX, IMMED);
 738 }
 739
 740 11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU
 741 "sltiu r<TRX>, <IMMEDIATE>"
 742 *mips16:
 743 // start-sanitize-tx19
 744 *tx19:
 745 // end-sanitize-tx19
 746 {
 747   do_sltiu (SD_, TRX, T8IDX, IMMEDIATE);
 748 }
 749
 750
 751
 752 11101,3.RX,3.RY,01010:RR:16::CMP
 753 "sltiu r<TRX>, r<TRY>"
 754 *mips16:
 755 // start-sanitize-tx19
 756 *tx19:
 757 // end-sanitize-tx19
 758 {
 759   do_xor (SD_, TRX, TRY, T8IDX);
 760 }
 761
 762
 763 01110,3.RX,8.IMMED:RI:16::CMPI
 764 "sltiu r<TRX>, <IMMED>"
 765 *mips16:
 766 // start-sanitize-tx19
 767 *tx19:
 768 // end-sanitize-tx19
 769 {
 770   do_xori (SD_, TRX, T8IDX, IMMED);
 771 }
 772
 773 11110,6.IMM_10_5,5.IMM_15_11 + 01110,3.RX,000,5.IMM_4_0:EXT-RI:16::CMPI
 774 "sltiu r<TRX>, <IMMEDIATE>"
 775 *mips16:
 776 // start-sanitize-tx19
 777 *tx19:
 778 // end-sanitize-tx19
 779 {
 780   do_xori (SD_, TRX, T8IDX, IMMEDIATE);
 781 }
 782
 783
 784
 785 // Two/Three Operand, Register-Type
 786
 787
 788
 789 11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
 790 "addu r<TRZ>, r<TRX>, r<TRY>"
 791 *mips16:
 792 // start-sanitize-tx19
 793 *tx19:
 794 // end-sanitize-tx19
 795 {
 796   do_addu (SD_, TRX, TRY, TRZ);
 797 }
 798
 799
 800
 801 11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
 802 "subu r<TRZ>, r<TRX>, r<TRY>"
 803 *mips16:
 804 // start-sanitize-tx19
 805 *tx19:
 806 // end-sanitize-tx19
 807 {
 808   do_subu (SD_, TRX, TRY, TRZ);
 809 }
 810
 811
 812
 813 11100,3.RX,3.RY,3.RZ,00:RRR:16,64::DADDU
 814 "daddu r<TRZ>, r<TRX>, r<TRY>"
 815 *mips16:
 816 // start-sanitize-tx19
 817 *tx19:
 818 // end-sanitize-tx19
 819 {
 820   do_daddu (SD_, TRX, TRY, TRZ);
 821 }
 822
 823
 824
 825 11100,3.RX,3.RY,3.RZ,10:RRR:16,64::DSUBU
 826 "dsubu r<TRZ>, r<TRX>, r<TRY>"
 827 *mips16:
 828 // start-sanitize-tx19
 829 *tx19:
 830 // end-sanitize-tx19
 831 {
 832   do_dsubu (SD_, TRX, TRY, TRZ);
 833 }
 834
 835
 836
 837 11101,3.RX,3.RY,00010:RR:16::SLT
 838 "slt r<TRX>, r<TRY>"
 839 *mips16:
 840 // start-sanitize-tx19
 841 *tx19:
 842 // end-sanitize-tx19
 843 {
 844   do_slt (SD_, TRX, TRY, T8IDX);
 845 }
 846
 847
 848
 849 11101,3.RX,3.RY,00011:RR:16::SLTU
 850 "sltu r<TRX>, r<TRY>"
 851 *mips16:
 852 // start-sanitize-tx19
 853 *tx19:
 854 // end-sanitize-tx19
 855 {
 856   do_sltu (SD_, TRX, TRY, T8IDX);
 857 }
 858
 859
 860
 861 11101,3.RX,3.RY,01011:RR:16::NEG
 862 "neg r<TRX>, r<TRY>"
 863 *mips16:
 864 // start-sanitize-tx19
 865 *tx19:
 866 // end-sanitize-tx19
 867 {
 868   do_subu (SD_, 0, TRY, TRX);
 869 }
 870
 871
 872
 873 11101,3.RX,3.RY,01100:RR:16::AND
 874 "and r<TRX>, r<TRY>"
 875 *mips16:
 876 // start-sanitize-tx19
 877 *tx19:
 878 // end-sanitize-tx19
 879 {
 880   do_and (SD_, TRX, TRY, TRX);
 881 }
 882
 883
 884
 885 11101,3.RX,3.RY,01101:RR:16::OR
 886 "or r<TRX>, r<TRY>"
 887 *mips16:
 888 // start-sanitize-tx19
 889 *tx19:
 890 // end-sanitize-tx19
 891 {
 892   do_or (SD_, TRX, TRY, TRX);
 893 }
 894
 895
 896
 897 11101,3.RX,3.RY,01110:RR:16::XOR
 898 "xor r<TRX>, r<TRY>"
 899 *mips16:
 900 // start-sanitize-tx19
 901 *tx19:
 902 // end-sanitize-tx19
 903 {
 904   do_xor (SD_, TRX, TRY, TRX);
 905 }
 906
 907
 908
 909 11101,3.RX,3.RY,01111:RR:16::NOT
 910 "not r<TRX>, r<TRY>"
 911 *mips16:
 912 // start-sanitize-tx19
 913 *tx19:
 914 // end-sanitize-tx19
 915 {
 916   do_nor (SD_, 0, TRY, TRX);
 917 }
 918
 919
 920
 921 01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
 922 "move r<TRY>, r<R32>"
 923 *mips16:
 924 // start-sanitize-tx19
 925 *tx19:
 926 // end-sanitize-tx19
 927 {
 928   do_or (SD_, R32, 0, TRY);
 929 }
 930
 931
 932
 933 01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
 934 "move r<R32>, r<TRZ>"
 935 *mips16:
 936 // start-sanitize-tx19
 937 *tx19:
 938 // end-sanitize-tx19
 939 {
 940   do_or (SD_, TRZ, 0, R32);
 941 }
 942
 943
 944
 945 00110,3.RX,3.RY,3.SHAMT,00:SHIFT:16::SLL
 946 "sll r<TRX>, r<TRY>, <SHIFT>"
 947 *mips16:
 948 // start-sanitize-tx19
 949 *tx19:
 950 // end-sanitize-tx19
 951 {
 952   do_sll (SD_, TRY, TRX, SHIFT);
 953 }
 954
 955 11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,00:EXT-SHIFT:16::SLL
 956 "sll r<TRX>, r<TRY>, <SHIFT>"
 957 *mips16:
 958 // start-sanitize-tx19
 959 *tx19:
 960 // end-sanitize-tx19
 961 {
 962   do_sll (SD_, TRY, TRX, SHAMT);
 963 }
 964
 965
 966
 967 00110,3.RX,3.RY,3.SHAMT,10:SHIFT:16::SRL
 968 "srl r<TRX>, r<TRY>, <SHIFT>"
 969 *mips16:
 970 // start-sanitize-tx19
 971 *tx19:
 972 // end-sanitize-tx19
 973 {
 974   do_srl (SD_, TRY, TRX, SHIFT);
 975 }
 976
 977 11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,10:EXT-SHIFT:16::SRL
 978 "srl r<TRX>, r<TRY>, <SHIFT>"
 979 *mips16:
 980 // start-sanitize-tx19
 981 *tx19:
 982 // end-sanitize-tx19
 983 {
 984   do_srl (SD_, TRY, TRX, SHAMT);
 985 }
 986
 987
 988
 989 00110,3.RX,3.RY,3.SHAMT,11:SHIFT:16::SRA
 990 "sra r<TRX>, r<TRY>, <SHIFT>"
 991 *mips16:
 992 // start-sanitize-tx19
 993 *tx19:
 994 // end-sanitize-tx19
 995 {
 996   do_sra (SD_, TRY, TRX, SHIFT);
 997 }
 998
 999 11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,11:EXT-SHIFT:16::SRA
1000 "sra r<TRX>, r<TRY>, <SHIFT>"
1001 *mips16:
1002 // start-sanitize-tx19
1003 *tx19:
1004 // end-sanitize-tx19
1005 {
1006   do_sra (SD_, TRY, TRX, SHAMT);
1007 }
1008
1009
1010
1011 11101,3.RX,3.RY,00100:RR:16::SLLV
1012 "sllv r<TRY>, r<TRX>"
1013 *mips16:
1014 // start-sanitize-tx19
1015 *tx19:
1016 // end-sanitize-tx19
1017 {
1018   do_sllv (SD_, TRX, TRY, TRY);
1019 }
1020
1021
1022 11101,3.RX,3.RY,00110:RR:16::SRLV
1023 "srlv r<TRY>, r<TRX>"
1024 *mips16:
1025 // start-sanitize-tx19
1026 *tx19:
1027 // end-sanitize-tx19
1028 {
1029   do_srlv (SD_, TRX, TRY, TRY);
1030 }
1031
1032
1033 11101,3.RX,3.RY,00111:RR:16::SRAV
1034 "srav r<TRY>, r<TRX>"
1035 *mips16:
1036 // start-sanitize-tx19
1037 *tx19:
1038 // end-sanitize-tx19
1039 {
1040   do_srav (SD_, TRX, TRY, TRY);
1041 }
1042
1043
1044 00110,3.RX,3.RY,3.SHAMT,01:SHIFT:16,64::DSLL
1045 "dsll r<TRY>, r<TRX>, <SHIFT>"
1046 *mips16:
1047 // start-sanitize-tx19
1048 *tx19:
1049 // end-sanitize-tx19
1050 {
1051   do_dsll (SD_, 0, TRY, TRX, SHIFT);
1052 }
1053
1054 11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16,64::DSLL
1055 "dsll r<TRY>, r<TRX>, <SHAMT>"
1056 *mips16:
1057 // start-sanitize-tx19
1058 *tx19:
1059 // end-sanitize-tx19
1060 {
1061   do_dsll (SD_, 0, TRY, TRX, SHAMT);
1062 }
1063
1064
1065
1066 11101,3.SHAMT,3.RY,01000:SHIFT64:16,64::DSRL
1067 "dsrl r<TRY>, <SHIFT>"
1068 *mips16:
1069 // start-sanitize-tx19
1070 *tx19:
1071 // end-sanitize-tx19
1072 {
1073   do_dsrl (SD_, 0, TRY, TRY, SHIFT);
1074 }
1075
1076 11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,01000:EXT-SHIFT64:16,64::DSRL
1077 "dsrl r<TRY>, <SHIFT>"
1078 *mips16:
1079 // start-sanitize-tx19
1080 *tx19:
1081 // end-sanitize-tx19
1082 {
1083   do_dsrl (SD_, 0, TRY, TRY, SHIFT);
1084 }
1085
1086
1087
1088 11101,3.SHAMT,3.RY,10011:SHIFT64:16,64::DSRA
1089 "dsra r<TRY>, <SHIFT>"
1090 *mips16:
1091 // start-sanitize-tx19
1092 *tx19:
1093 // end-sanitize-tx19
1094 {
1095   do_dsra (SD_, 0, TRY, TRY, SHIFT);
1096 }
1097
1098 11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,10011:EXT-SHIFT64:16,64::DSRA
1099 "dsra r<TRY>, <SHIFT>"
1100 *mips16:
1101 // start-sanitize-tx19
1102 *tx19:
1103 // end-sanitize-tx19
1104 {
1105   do_dsra (SD_, 0, TRY, TRY, SHIFT);
1106 }
1107
1108
1109
1110 11101,3.RX,3.RY,10100:RR:16,64::DSLLV
1111 "dsra r<TRY>, r<TRX>"
1112 *mips16:
1113 // start-sanitize-tx19
1114 *tx19:
1115 // end-sanitize-tx19
1116 {
1117   do_dsllv (SD_, TRX, TRY, TRY);
1118 }
1119
1120
1121 11101,3.RX,3.RY,10110:RR:16,64::DSRLV
1122 "dsrlv r<TRY>, r<TRX>"
1123 *mips16:
1124 // start-sanitize-tx19
1125 *tx19:
1126 // end-sanitize-tx19
1127 {
1128   do_dsrlv (SD_, TRX, TRY, TRY);
1129 }
1130
1131
1132 11101,3.RX,3.RY,10111:RR:16,64::DSRAV
1133 "dsrav r<TRY>, r<TRX>"
1134 *mips16:
1135 // start-sanitize-tx19
1136 *tx19:
1137 // end-sanitize-tx19
1138 {
1139   do_dsrav (SD_, TRX, TRY, TRY);
1140 }
1141
1142
1143 // Multiply /Divide Instructions
1144
1145
1146 11101,3.RX,3.RY,11000:RR:16::MULT
1147 "mult r<TRX>, r<TRY>"
1148 *mips16:
1149 // start-sanitize-tx19
1150 *tx19:
1151 // end-sanitize-tx19
1152 {
1153   do_mult (SD_, TRX, TRY, 0);
1154 }
1155
1156
1157 11101,3.RX,3.RY,11001:RR:16::MULTU
1158 "multu r<TRX>, r<TRY>"
1159 *mips16:
1160 // start-sanitize-tx19
1161 *tx19:
1162 // end-sanitize-tx19
1163 {
1164   do_multu (SD_, TRX, TRY, 0);
1165 }
1166
1167
1168 11101,3.RX,3.RY,11010:RR:16::DIV
1169 "div r<TRX>, r<TRY>"
1170 *mips16:
1171 // start-sanitize-tx19
1172 *tx19:
1173 // end-sanitize-tx19
1174 {
1175   do_div (SD_, TRX, TRY);
1176 }
1177
1178
1179 11101,3.RX,3.RY,11011:RR:16::DIVU
1180 "divu r<TRX>, r<TRY>"
1181 *mips16:
1182 // start-sanitize-tx19
1183 *tx19:
1184 // end-sanitize-tx19
1185 {
1186   do_divu (SD_, TRX, TRY);
1187 }
1188
1189
1190 11101,3.RX,000,10000:RR:16::MFHI
1191 "mfhi r<TRX>"
1192 *mips16:
1193 // start-sanitize-tx19
1194 *tx19:
1195 // end-sanitize-tx19
1196 {
1197   do_mfhi (SD_, TRX);
1198 }
1199
1200
1201 11101,3.RX,000,10010:RR:16::MFLO
1202 "mflo r<TRX>"
1203 *mips16:
1204 // start-sanitize-tx19
1205 *tx19:
1206 // end-sanitize-tx19
1207 {
1208   do_mflo (SD_, TRX);
1209 }
1210
1211
1212 11101,3.RX,3.RY,11100:RR:16,64::DMULT
1213 "dmult r<TRX>, r<TRY>"
1214 *mips16:
1215 // start-sanitize-tx19
1216 *tx19:
1217 // end-sanitize-tx19
1218 {
1219   do_dmult (SD_, TRX, TRY);
1220 }
1221
1222
1223 11101,3.RX,3.RY,11101:RR:16,64::DMULTU
1224 "dmultu r<TRX>, r<TRY>"
1225 *mips16:
1226 // start-sanitize-tx19
1227 *tx19:
1228 // end-sanitize-tx19
1229 {
1230   do_dmultu (SD_, TRX, TRY);
1231 }
1232
1233
1234 11101,3.RX,3.RY,11110:RR:16,64::DDIV
1235 "ddiv r<TRX>, r<TRY>"
1236 *mips16:
1237 // start-sanitize-tx19
1238 *tx19:
1239 // end-sanitize-tx19
1240 {
1241   do_ddiv (SD_, TRX, TRY);
1242 }
1243
1244
1245 11101,3.RX,3.RY,11111:RR:16,64::DDIVU
1246 "ddivu r<TRX>, r<TRY>"
1247 *mips16:
1248 // start-sanitize-tx19
1249 *tx19:
1250 // end-sanitize-tx19
1251 {
1252   do_ddivu (SD_, TRX, TRY);
1253 }
1254
1255
1256 // Jump and Branch Instructions
1257
1258
1259
1260 // Issue instruction in delay slot of branch
1261 :function:::address_word:delayslot16:address_word nia, address_word target
1262 {
1263   instruction_word delay_insn;
1264   sim_events_slip (SD, 1);
1265   DSPC = CIA; /* save current PC somewhere */
1266   STATE |= simDELAYSLOT;
1267   delay_insn = IMEM16 (nia); /* NOTE: mips16 */
1268   idecode_issue (CPU_, delay_insn, (nia));
1269   STATE &= ~simDELAYSLOT;
1270   return target;
1271 }
1272
1273 // compute basepc dependant on us being in a delay slot
1274 :function:::address_word:basepc:
1275 {
1276   if (STATE & simDELAYSLOT)
1277     {
1278       return DSPC; /* return saved address of preceeding jmp */
1279     }
1280   else
1281     {
1282       return CIA;
1283     }
1284 }
1285
1286
1287 // JAL
1288 00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JAL:16::JAL
1289 "jal <IMMEDIATE>"
1290 *mips16:
1291 // start-sanitize-tx19
1292 *tx19:
1293 // end-sanitize-tx19
1294 {
1295   address_word region = (NIA & MASK (63, 28));
1296   RA = NIA + 2; /* skip 16 bit delayslot insn */
1297   NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2))) | 1;
1298 }
1299
1300
1301
1302 // JALX - 32 and 16 bit versions.
1303
1304 011101,26.IMMED:JALX:32::JALX32
1305 "jalx <IMMED>"
1306 *r3900:
1307 // start-sanitize-tx19
1308 *tx19:
1309 // end-sanitize-tx19
1310 {
1311   address_word region = (NIA & MASK (63, 28));
1312   RA = NIA + 4; /* skip 32 bit delayslot insn */
1313   NIA = delayslot32 (SD_, (region | (IMMED << 2)) | 1);
1314 }
1315
1316 00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JALX:16::JALX16
1317 "jalx <IMMEDIATE>"
1318 *mips16:
1319 // start-sanitize-tx19
1320 *tx19:
1321 // end-sanitize-tx19
1322 {
1323   address_word region = (NIA & MASK (63, 28));
1324   RA = NIA + 2; /* 16 bit INSN */
1325   NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2)) & ~1);
1326 }
1327
1328
1329
1330 11101,3.RX,000,00000:RR:16::JR
1331 "jr r<TRX>"
1332 *mips16:
1333 // start-sanitize-tx19
1334 *tx19:
1335 // end-sanitize-tx19
1336 {
1337   NIA = delayslot16 (SD_, NIA, GPR[TRX]);
1338 }
1339
1340
1341 11101,000,001,00000:RR:16::JRRA
1342 "jrra"
1343 *mips16:
1344 // start-sanitize-tx19
1345 *tx19:
1346 // end-sanitize-tx19
1347 {
1348   NIA = delayslot16 (SD_, NIA, RA);
1349 }
1350
1351
1352
1353 11101,3.RX,010,00000:RR:16::JALR
1354 "jalr r<TRX>"
1355 *mips16:
1356 // start-sanitize-tx19
1357 *tx19:
1358 // end-sanitize-tx19
1359 {
1360   RA = NIA + 2;
1361   NIA = delayslot16 (SD_, NIA, GPR[TRX]);
1362 }
1363
1364
1365
1366 00100,3.RX,8.IMMED:RI:16::BEQZ
1367 "beqz r<TRX>, <IMMED>"
1368 *mips16:
1369 // start-sanitize-tx19
1370 *tx19:
1371 // end-sanitize-tx19
1372 {
1373   if (GPR[RX] == 0)
1374     NIA = (NIA + (EXTEND8 (IMMED) << 1));
1375 }
1376
1377 11110,6.IMM_10_5,5.IMM_15_11 + 00100,3.RX,000,5.IMM_4_0:EXT-RI:16::BEQZ
1378 "beqz r<TRX>, <IMMEDIATE>"
1379 *mips16:
1380 // start-sanitize-tx19
1381 *tx19:
1382 // end-sanitize-tx19
1383 {
1384   if (GPR[RX] == 0)
1385     NIA = (NIA + EXTEND16 (IMMEDIATE));
1386 }
1387
1388
1389
1390 00101,3.RX,8.IMMED:RI:16::BNEZ
1391 "bnez r<TRX>, <IMMED>"
1392 *mips16:
1393 // start-sanitize-tx19
1394 *tx19:
1395 // end-sanitize-tx19
1396 {
1397   if (GPR[RX] != 0)
1398     NIA = (NIA + (EXTEND8 (IMMED) << 1));
1399 }
1400
1401 11110,6.IMM_10_5,5.IMM_15_11 + 00101,3.RX,000,5.IMM_4_0:EXT-RI:16::BNEZ
1402 "bnez r<TRX>, <IMMEDIATE>"
1403 *mips16:
1404 // start-sanitize-tx19
1405 *tx19:
1406 // end-sanitize-tx19
1407 {
1408   if (GPR[RX] != 0)
1409     NIA = (NIA + EXTEND16 (IMMEDIATE));
1410 }
1411
1412
1413
1414 01100,000,8.IMMED:I8:16::BTEQZ
1415 "bteqz <IMMED>"
1416 *mips16:
1417 // start-sanitize-tx19
1418 *tx19:
1419 // end-sanitize-tx19
1420 {
1421   if (T8 == 0)
1422     NIA = (NIA + (EXTEND8 (IMMED) << 1));
1423 }
1424
1425 11110,6.IMM_10_5,5.IMM_15_11 + 01100,000,000,5.IMM_4_0:EXT-I8:16::BTEQZ
1426 "bteqz <IMMEDIATE>"
1427 *mips16:
1428 // start-sanitize-tx19
1429 *tx19:
1430 // end-sanitize-tx19
1431 {
1432   if (T8 == 0)
1433     NIA = (NIA + EXTEND16 (IMMEDIATE));
1434 }
1435
1436
1437
1438 01100,001,8.IMMED:I8:16::BTNEZ
1439 "btnez <IMMED>"
1440 *mips16:
1441 // start-sanitize-tx19
1442 *tx19:
1443 // end-sanitize-tx19
1444 {
1445   if (T8 != 0)
1446     NIA = (NIA + (EXTEND8 (IMMED) << 1));
1447 }
1448
1449 11110,6.IMM_10_5,5.IMM_15_11 + 01100,001,000,5.IMM_4_0:EXT-I8:16::BTNEZ
1450 "btnez <IMMEDIATE>"
1451 *mips16:
1452 // start-sanitize-tx19
1453 *tx19:
1454 // end-sanitize-tx19
1455 {
1456   if (T8 != 0)
1457     NIA = (NIA + EXTEND16 (IMMEDIATE));
1458 }
1459
1460
1461
1462 00010,11.IMMED:I:16::B
1463 "b <IMMED>"
1464 *mips16:
1465 // start-sanitize-tx19
1466 *tx19:
1467 // end-sanitize-tx19
1468 {
1469   NIA = (NIA + (EXTEND8 (IMMED) << 1));
1470 }
1471
1472 11110,6.IMM_10_5,5.IMM_15_11 + 00010,6.0,5.IMM_4_0:EXT-I:16::B
1473 "b <IMMEDIATE>"
1474 *mips16:
1475 // start-sanitize-tx19
1476 *tx19:
1477 // end-sanitize-tx19
1478 {
1479   NIA = (NIA + EXTEND16 (IMMEDIATE));
1480 }
1481
1482
1483
1484 // Special Instructions
1485
1486
1487 // See the front of the mips16 doc
1488 //     -> FIXME need this for most instructions
1489 //// 11110,eeeeeeeeeee:I:16::EXTEND
1490 //// *mips16:
1491 //// // start-sanitize-tx19
1492 //// *tx19:
1493 //// // end-sanitize-tx19
1494
1495
1496 // 11101,3.RX,3.RY,00101:RR:16::BREAK
1497 // *mips16:
1498 // // start-sanitize-tx19
1499 // *tx19:
1500 // // end-sanitize-tx19