3 * simops.c: Handle "satadd", "satsub", "satsubi", "satsubr".
5 * interp.c (do_format_5): Get operands correctly and
6 call the target function.
7 (sim_resume): Don't do a PC update for format 5 instructions.
8 * simops.c: Handle "jarl" and "jmp" instructions.
10 * simops.c: Fix minor typos. Handle "cmp", "setf", "tst"
11 "di", and "ei" instructions correctly.
13 * interp.c (do_format_3): Get operands correctly and call
15 * simops.c: Handle bCC instructions.
17 * simops.c: Add condition code handling to shift insns.
18 Fix minor typos in condition code handling for other insns.
20 * Makefile.in: Fix typo.
21 * simops.c: Add condition code handling to "sub" "subr" and
24 * interp.c (hash): Update to be more accurate.
25 (lookup_hash): Call hash rather than computing the hash
27 (do_format_1_2): Handle format 1 and format 2 instructions.
28 Get operands correctly and call the target function.
29 (do_format_6): Get operands correctly and call the target
31 (do_formats_9_10): Rough cut so shift ops will work.
32 (sim_resume): Tweak to deal with format 1 and format 2
33 handling in a single funtion. Don't update the PC
34 for format 3 insns. Fix typos.
35 * simops.c: Slightly reorganize. Add condition code handling
36 to "add", "addi", "and", "andi", "or", "ori", "xor", "xori"
37 and "not" instructions.
38 * v850_sim.h (reg_t): Registers are 32bits.
39 (_state): The V850 has 32 general registers. Add a 32bit
40 psw and pc register too. Add accessor macros
42 * Makefile.in, interp.c, v850_sim.h: Bring over endianness
43 changes from the d10v simulator.
45 * simops.c: Add shift support.
47 * simops.c: Add multiply & divide support. Abort for system
50 * simops.c: Add logicals, mov, movhi, movea, add, addi, sub
51 and subr. No condition codes yet.
55 * ChangeLog, Makefile.in, configure, configure.in, v850_sim.h,
56 gencode.c, interp.c, simops.c: Created.