1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2020 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
57 typedef arelent, howto manager, Relocations, Relocations
62 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
97 .typedef const struct reloc_howto_struct reloc_howto_type;
99 .typedef struct reloc_cache_entry
101 . {* A pointer into the canonical table of pointers. *}
102 . struct bfd_symbol **sym_ptr_ptr;
104 . {* offset in section. *}
105 . bfd_size_type address;
107 . {* addend for relocation value. *}
110 . {* Pointer to how to perform the required relocation. *}
111 . reloc_howto_type *howto;
121 Here is a description of each of the fields within an <<arelent>>:
125 The symbol table pointer points to a pointer to the symbol
126 associated with the relocation request. It is the pointer
127 into the table returned by the back end's
128 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
129 referenced through a pointer to a pointer so that tools like
130 the linker can fix up all the symbols of the same name by
131 modifying only one pointer. The relocation routine looks in
132 the symbol and uses the base of the section the symbol is
133 attached to and the value of the symbol as the initial
134 relocation offset. If the symbol pointer is zero, then the
135 section provided is looked up.
139 The <<address>> field gives the offset in bytes from the base of
140 the section data which owns the relocation record to the first
141 byte of relocatable information. The actual data relocated
142 will be relative to this point; for example, a relocation
143 type which modifies the bottom two bytes of a four byte word
144 would not touch the first byte pointed to in a big endian
149 The <<addend>> is a value provided by the back end to be added (!)
150 to the relocation offset. Its interpretation is dependent upon
151 the howto. For example, on the 68k the code:
156 | return foo[0x12345678];
159 Could be compiled into:
162 | moveb @@#12345678,d0
167 This could create a reloc pointing to <<foo>>, but leave the
168 offset in the data, something like:
170 |RELOCATION RECORDS FOR [.text]:
174 |00000000 4e56 fffc ; linkw fp,#-4
175 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
176 |0000000a 49c0 ; extbl d0
177 |0000000c 4e5e ; unlk fp
180 Using coff and an 88k, some instructions don't have enough
181 space in them to represent the full address range, and
182 pointers have to be loaded in two parts. So you'd get something like:
184 | or.u r13,r0,hi16(_foo+0x12345678)
185 | ld.b r2,r13,lo16(_foo+0x12345678)
188 This should create two relocs, both pointing to <<_foo>>, and with
189 0x12340000 in their addend field. The data would consist of:
191 |RELOCATION RECORDS FOR [.text]:
193 |00000002 HVRT16 _foo+0x12340000
194 |00000006 LVRT16 _foo+0x12340000
196 |00000000 5da05678 ; or.u r13,r0,0x5678
197 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
198 |00000008 f400c001 ; jmp r1
200 The relocation routine digs out the value from the data, adds
201 it to the addend to get the original offset, and then adds the
202 value of <<_foo>>. Note that all 32 bits have to be kept around
203 somewhere, to cope with carry from bit 15 to bit 16.
205 One further example is the sparc and the a.out format. The
206 sparc has a similar problem to the 88k, in that some
207 instructions don't have room for an entire offset, but on the
208 sparc the parts are created in odd sized lumps. The designers of
209 the a.out format chose to not use the data within the section
210 for storing part of the offset; all the offset is kept within
211 the reloc. Anything in the data should be ignored.
214 | sethi %hi(_foo+0x12345678),%g2
215 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
219 Both relocs contain a pointer to <<foo>>, and the offsets
222 |RELOCATION RECORDS FOR [.text]:
224 |00000004 HI22 _foo+0x12345678
225 |00000008 LO10 _foo+0x12345678
227 |00000000 9de3bf90 ; save %sp,-112,%sp
228 |00000004 05000000 ; sethi %hi(_foo+0),%g2
229 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
230 |0000000c 81c7e008 ; ret
231 |00000010 81e80000 ; restore
235 The <<howto>> field can be imagined as a
236 relocation instruction. It is a pointer to a structure which
237 contains information on what to do with all of the other
238 information in the reloc record and data section. A back end
239 would normally have a relocation instruction set and turn
240 relocations into pointers to the correct structure on input -
241 but it would be possible to create each howto field on demand.
247 <<enum complain_overflow>>
249 Indicates what sort of overflow checking should be done when
250 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's idea of
287 . an external reloc number is stored in this field. *}
290 . {* The encoded size of the item to be relocated. This is *not* a
291 . power-of-two measure. Use bfd_get_reloc_size to find the size
292 . of the item in bytes. *}
293 . unsigned int size:3;
295 . {* The number of bits in the field to be relocated. This is used
296 . when doing overflow checking. *}
297 . unsigned int bitsize:7;
299 . {* The value the final relocation is shifted right by. This drops
300 . unwanted data from the relocation. *}
301 . unsigned int rightshift:6;
303 . {* The bit position of the reloc value in the destination.
304 . The relocated value is left shifted by this amount. *}
305 . unsigned int bitpos:6;
307 . {* What type of overflow error should be checked for when
309 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
311 . {* The relocation value should be negated before applying. *}
312 . unsigned int negate:1;
314 . {* The relocation is relative to the item being relocated. *}
315 . unsigned int pc_relative:1;
317 . {* Some formats record a relocation addend in the section contents
318 . rather than with the relocation. For ELF formats this is the
319 . distinction between USE_REL and USE_RELA (though the code checks
320 . for USE_REL == 1/0). The value of this field is TRUE if the
321 . addend is recorded with the section contents; when performing a
322 . partial link (ld -r) the section contents (the data) will be
323 . modified. The value of this field is FALSE if addends are
324 . recorded with the relocation (in arelent.addend); when performing
325 . a partial link the relocation will be modified.
326 . All relocations for all ELF USE_RELA targets should set this field
327 . to FALSE (values of TRUE should be looked on with suspicion).
328 . However, the converse is not true: not all relocations of all ELF
329 . USE_REL targets set this field to TRUE. Why this is so is peculiar
330 . to each particular target. For relocs that aren't used in partial
331 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
332 . unsigned int partial_inplace:1;
334 . {* When some formats create PC relative instructions, they leave
335 . the value of the pc of the place being relocated in the offset
336 . slot of the instruction, so that a PC relative relocation can
337 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
338 . Some formats leave the displacement part of an instruction
339 . empty (e.g., ELF); this flag signals the fact. *}
340 . unsigned int pcrel_offset:1;
342 . {* src_mask selects the part of the instruction (or data) to be used
343 . in the relocation sum. If the target relocations don't have an
344 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
345 . dst_mask to extract the addend from the section contents. If
346 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
347 . field should normally be zero. Non-zero values for ELF USE_RELA
348 . targets should be viewed with suspicion as normally the value in
349 . the dst_mask part of the section contents should be ignored. *}
352 . {* dst_mask selects which parts of the instruction (or data) are
353 . replaced with a relocated value. *}
356 . {* If this field is non null, then the supplied function is
357 . called rather than the normal function. This allows really
358 . strange relocation methods to be accommodated. *}
359 . bfd_reloc_status_type (*special_function)
360 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
363 . {* The textual name of the relocation type. *}
374 The HOWTO macro fills in a reloc_howto_type (a typedef for
375 const struct reloc_howto_struct).
377 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
378 . inplace, src_mask, dst_mask, pcrel_off) \
379 . { (unsigned) type, size < 0 ? -size : size, bits, right, left, ovf, \
380 . size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name }
383 This is used to fill in an empty howto entry in an array.
385 .#define EMPTY_HOWTO(C) \
386 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
387 . NULL, FALSE, 0, 0, FALSE)
396 unsigned int bfd_get_reloc_size (reloc_howto_type *);
399 For a reloc_howto_type that operates on a fixed number of bytes,
400 this returns the number of bytes operated on.
404 bfd_get_reloc_size (reloc_howto_type *howto)
424 How relocs are tied together in an <<asection>>:
426 .typedef struct relent_chain
429 . struct relent_chain *next;
435 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
436 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
443 bfd_reloc_status_type bfd_check_overflow
444 (enum complain_overflow how,
445 unsigned int bitsize,
446 unsigned int rightshift,
447 unsigned int addrsize,
451 Perform overflow checking on @var{relocation} which has
452 @var{bitsize} significant bits and will be shifted right by
453 @var{rightshift} bits, on a machine with addresses containing
454 @var{addrsize} significant bits. The result is either of
455 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
459 bfd_reloc_status_type
460 bfd_check_overflow (enum complain_overflow how,
461 unsigned int bitsize,
462 unsigned int rightshift,
463 unsigned int addrsize,
466 bfd_vma fieldmask, addrmask, signmask, ss, a;
467 bfd_reloc_status_type flag = bfd_reloc_ok;
472 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
473 we'll be permissive: extra bits in the field mask will
474 automatically extend the address mask for purposes of the
476 fieldmask = N_ONES (bitsize);
477 signmask = ~fieldmask;
478 addrmask = N_ONES (addrsize) | (fieldmask << rightshift);
479 a = (relocation & addrmask) >> rightshift;
483 case complain_overflow_dont:
486 case complain_overflow_signed:
487 /* If any sign bits are set, all sign bits must be set. That
488 is, A must be a valid negative address after shifting. */
489 signmask = ~ (fieldmask >> 1);
492 case complain_overflow_bitfield:
493 /* Bitfields are sometimes signed, sometimes unsigned. We
494 explicitly allow an address wrap too, which means a bitfield
495 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
496 if the value has some, but not all, bits set outside the
499 if (ss != 0 && ss != ((addrmask >> rightshift) & signmask))
500 flag = bfd_reloc_overflow;
503 case complain_overflow_unsigned:
504 /* We have an overflow if the address does not fit in the field. */
505 if ((a & signmask) != 0)
506 flag = bfd_reloc_overflow;
518 bfd_reloc_offset_in_range
521 bfd_boolean bfd_reloc_offset_in_range
522 (reloc_howto_type *howto,
525 bfd_size_type offset);
528 Returns TRUE if the reloc described by @var{HOWTO} can be
529 applied at @var{OFFSET} octets in @var{SECTION}.
533 /* HOWTO describes a relocation, at offset OCTET. Return whether the
534 relocation field is within SECTION of ABFD. */
537 bfd_reloc_offset_in_range (reloc_howto_type *howto,
542 bfd_size_type octet_end = bfd_get_section_limit_octets (abfd, section);
543 bfd_size_type reloc_size = bfd_get_reloc_size (howto);
545 /* The reloc field must be contained entirely within the section.
546 Allow zero length fields (marker relocs or NONE relocs where no
547 relocation will be performed) at the end of the section. */
548 return octet <= octet_end && octet + reloc_size <= octet_end;
551 /* Read and return the section contents at DATA converted to a host
552 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
555 read_reloc (bfd *abfd, bfd_byte *data, reloc_howto_type *howto)
560 return bfd_get_8 (abfd, data);
563 return bfd_get_16 (abfd, data);
566 return bfd_get_32 (abfd, data);
573 return bfd_get_64 (abfd, data);
577 return bfd_get_24 (abfd, data);
585 /* Convert VAL to target format and write to DATA. The number of
586 bytes written is given by the HOWTO. */
589 write_reloc (bfd *abfd, bfd_vma val, bfd_byte *data, reloc_howto_type *howto)
594 bfd_put_8 (abfd, val, data);
598 bfd_put_16 (abfd, val, data);
602 bfd_put_32 (abfd, val, data);
610 bfd_put_64 (abfd, val, data);
615 bfd_put_24 (abfd, val, data);
623 /* Apply RELOCATION value to target bytes at DATA, according to
627 apply_reloc (bfd *abfd, bfd_byte *data, reloc_howto_type *howto,
630 bfd_vma val = read_reloc (abfd, data, howto);
633 relocation = -relocation;
635 val = ((val & ~howto->dst_mask)
636 | (((val & howto->src_mask) + relocation) & howto->dst_mask));
638 write_reloc (abfd, val, data, howto);
643 bfd_perform_relocation
646 bfd_reloc_status_type bfd_perform_relocation
648 arelent *reloc_entry,
650 asection *input_section,
652 char **error_message);
655 If @var{output_bfd} is supplied to this function, the
656 generated image will be relocatable; the relocations are
657 copied to the output file after they have been changed to
658 reflect the new state of the world. There are two ways of
659 reflecting the results of partial linkage in an output file:
660 by modifying the output data in place, and by modifying the
661 relocation record. Some native formats (e.g., basic a.out and
662 basic coff) have no way of specifying an addend in the
663 relocation type, so the addend has to go in the output data.
664 This is no big deal since in these formats the output data
665 slot will always be big enough for the addend. Complex reloc
666 types with addends were invented to solve just this problem.
667 The @var{error_message} argument is set to an error message if
668 this return @code{bfd_reloc_dangerous}.
672 bfd_reloc_status_type
673 bfd_perform_relocation (bfd *abfd,
674 arelent *reloc_entry,
676 asection *input_section,
678 char **error_message)
681 bfd_reloc_status_type flag = bfd_reloc_ok;
682 bfd_size_type octets;
683 bfd_vma output_base = 0;
684 reloc_howto_type *howto = reloc_entry->howto;
685 asection *reloc_target_output_section;
688 symbol = *(reloc_entry->sym_ptr_ptr);
690 /* If we are not producing relocatable output, return an error if
691 the symbol is not defined. An undefined weak symbol is
692 considered to have a value of zero (SVR4 ABI, p. 4-27). */
693 if (bfd_is_und_section (symbol->section)
694 && (symbol->flags & BSF_WEAK) == 0
695 && output_bfd == NULL)
696 flag = bfd_reloc_undefined;
698 /* If there is a function supplied to handle this relocation type,
699 call it. It'll return `bfd_reloc_continue' if further processing
701 if (howto && howto->special_function)
703 bfd_reloc_status_type cont;
705 /* Note - we do not call bfd_reloc_offset_in_range here as the
706 reloc_entry->address field might actually be valid for the
707 backend concerned. It is up to the special_function itself
708 to call bfd_reloc_offset_in_range if needed. */
709 cont = howto->special_function (abfd, reloc_entry, symbol, data,
710 input_section, output_bfd,
712 if (cont != bfd_reloc_continue)
716 if (bfd_is_abs_section (symbol->section)
717 && output_bfd != NULL)
719 reloc_entry->address += input_section->output_offset;
723 /* PR 17512: file: 0f67f69d. */
725 return bfd_reloc_undefined;
727 /* Is the address of the relocation really within the section? */
728 octets = reloc_entry->address * bfd_octets_per_byte (abfd, input_section);
729 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
730 return bfd_reloc_outofrange;
732 /* Work out which section the relocation is targeted at and the
733 initial relocation command value. */
735 /* Get symbol value. (Common symbols are special.) */
736 if (bfd_is_com_section (symbol->section))
739 relocation = symbol->value;
741 reloc_target_output_section = symbol->section->output_section;
743 /* Convert input-section-relative symbol value to absolute. */
744 if ((output_bfd && ! howto->partial_inplace)
745 || reloc_target_output_section == NULL)
748 output_base = reloc_target_output_section->vma;
750 output_base += symbol->section->output_offset;
752 /* If symbol addresses are in octets, convert to bytes. */
753 if (bfd_get_flavour (abfd) == bfd_target_elf_flavour
754 && (symbol->section->flags & SEC_ELF_OCTETS))
755 output_base *= bfd_octets_per_byte (abfd, input_section);
757 relocation += output_base;
759 /* Add in supplied addend. */
760 relocation += reloc_entry->addend;
762 /* Here the variable relocation holds the final address of the
763 symbol we are relocating against, plus any addend. */
765 if (howto->pc_relative)
767 /* This is a PC relative relocation. We want to set RELOCATION
768 to the distance between the address of the symbol and the
769 location. RELOCATION is already the address of the symbol.
771 We start by subtracting the address of the section containing
774 If pcrel_offset is set, we must further subtract the position
775 of the location within the section. Some targets arrange for
776 the addend to be the negative of the position of the location
777 within the section; for example, i386-aout does this. For
778 i386-aout, pcrel_offset is FALSE. Some other targets do not
779 include the position of the location; for example, ELF.
780 For those targets, pcrel_offset is TRUE.
782 If we are producing relocatable output, then we must ensure
783 that this reloc will be correctly computed when the final
784 relocation is done. If pcrel_offset is FALSE we want to wind
785 up with the negative of the location within the section,
786 which means we must adjust the existing addend by the change
787 in the location within the section. If pcrel_offset is TRUE
788 we do not want to adjust the existing addend at all.
790 FIXME: This seems logical to me, but for the case of
791 producing relocatable output it is not what the code
792 actually does. I don't want to change it, because it seems
793 far too likely that something will break. */
796 input_section->output_section->vma + input_section->output_offset;
798 if (howto->pcrel_offset)
799 relocation -= reloc_entry->address;
802 if (output_bfd != NULL)
804 if (! howto->partial_inplace)
806 /* This is a partial relocation, and we want to apply the relocation
807 to the reloc entry rather than the raw data. Modify the reloc
808 inplace to reflect what we now know. */
809 reloc_entry->addend = relocation;
810 reloc_entry->address += input_section->output_offset;
815 /* This is a partial relocation, but inplace, so modify the
818 If we've relocated with a symbol with a section, change
819 into a ref to the section belonging to the symbol. */
821 reloc_entry->address += input_section->output_offset;
824 if (abfd->xvec->flavour == bfd_target_coff_flavour
825 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
826 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
828 /* For m68k-coff, the addend was being subtracted twice during
829 relocation with -r. Removing the line below this comment
830 fixes that problem; see PR 2953.
832 However, Ian wrote the following, regarding removing the line below,
833 which explains why it is still enabled: --djm
835 If you put a patch like that into BFD you need to check all the COFF
836 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
837 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
838 problem in a different way. There may very well be a reason that the
839 code works as it does.
841 Hmmm. The first obvious point is that bfd_perform_relocation should
842 not have any tests that depend upon the flavour. It's seem like
843 entirely the wrong place for such a thing. The second obvious point
844 is that the current code ignores the reloc addend when producing
845 relocatable output for COFF. That's peculiar. In fact, I really
846 have no idea what the point of the line you want to remove is.
848 A typical COFF reloc subtracts the old value of the symbol and adds in
849 the new value to the location in the object file (if it's a pc
850 relative reloc it adds the difference between the symbol value and the
851 location). When relocating we need to preserve that property.
853 BFD handles this by setting the addend to the negative of the old
854 value of the symbol. Unfortunately it handles common symbols in a
855 non-standard way (it doesn't subtract the old value) but that's a
856 different story (we can't change it without losing backward
857 compatibility with old object files) (coff-i386 does subtract the old
858 value, to be compatible with existing coff-i386 targets, like SCO).
860 So everything works fine when not producing relocatable output. When
861 we are producing relocatable output, logically we should do exactly
862 what we do when not producing relocatable output. Therefore, your
863 patch is correct. In fact, it should probably always just set
864 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
865 add the value into the object file. This won't hurt the COFF code,
866 which doesn't use the addend; I'm not sure what it will do to other
867 formats (the thing to check for would be whether any formats both use
868 the addend and set partial_inplace).
870 When I wanted to make coff-i386 produce relocatable output, I ran
871 into the problem that you are running into: I wanted to remove that
872 line. Rather than risk it, I made the coff-i386 relocs use a special
873 function; it's coff_i386_reloc in coff-i386.c. The function
874 specifically adds the addend field into the object file, knowing that
875 bfd_perform_relocation is not going to. If you remove that line, then
876 coff-i386.c will wind up adding the addend field in twice. It's
877 trivial to fix; it just needs to be done.
879 The problem with removing the line is just that it may break some
880 working code. With BFD it's hard to be sure of anything. The right
881 way to deal with this is simply to build and test at least all the
882 supported COFF targets. It should be straightforward if time and disk
883 space consuming. For each target:
885 2) generate some executable, and link it using -r (I would
886 probably use paranoia.o and link against newlib/libc.a, which
887 for all the supported targets would be available in
888 /usr/cygnus/progressive/H-host/target/lib/libc.a).
889 3) make the change to reloc.c
890 4) rebuild the linker
892 6) if the resulting object files are the same, you have at least
894 7) if they are different you have to figure out which version is
897 relocation -= reloc_entry->addend;
898 reloc_entry->addend = 0;
902 reloc_entry->addend = relocation;
907 /* FIXME: This overflow checking is incomplete, because the value
908 might have overflowed before we get here. For a correct check we
909 need to compute the value in a size larger than bitsize, but we
910 can't reasonably do that for a reloc the same size as a host
912 FIXME: We should also do overflow checking on the result after
913 adding in the value contained in the object file. */
914 if (howto->complain_on_overflow != complain_overflow_dont
915 && flag == bfd_reloc_ok)
916 flag = bfd_check_overflow (howto->complain_on_overflow,
919 bfd_arch_bits_per_address (abfd),
922 /* Either we are relocating all the way, or we don't want to apply
923 the relocation to the reloc entry (probably because there isn't
924 any room in the output format to describe addends to relocs). */
926 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
927 (OSF version 1.3, compiler version 3.11). It miscompiles the
941 x <<= (unsigned long) s.i0;
945 printf ("succeeded (%lx)\n", x);
949 relocation >>= (bfd_vma) howto->rightshift;
951 /* Shift everything up to where it's going to be used. */
952 relocation <<= (bfd_vma) howto->bitpos;
954 /* Wait for the day when all have the mask in them. */
957 i instruction to be left alone
958 o offset within instruction
959 r relocation offset to apply
968 (( i i i i i o o o o o from bfd_get<size>
969 and S S S S S) to get the size offset we want
970 + r r r r r r r r r r) to get the final value to place
971 and D D D D D to chop to right size
972 -----------------------
975 ( i i i i i o o o o o from bfd_get<size>
976 and N N N N N ) get instruction
977 -----------------------
983 -----------------------
984 = R R R R R R R R R R put into bfd_put<size>
987 data = (bfd_byte *) data + octets;
988 apply_reloc (abfd, data, howto, relocation);
994 bfd_install_relocation
997 bfd_reloc_status_type bfd_install_relocation
999 arelent *reloc_entry,
1000 void *data, bfd_vma data_start,
1001 asection *input_section,
1002 char **error_message);
1005 This looks remarkably like <<bfd_perform_relocation>>, except it
1006 does not expect that the section contents have been filled in.
1007 I.e., it's suitable for use when creating, rather than applying
1010 For now, this function should be considered reserved for the
1014 bfd_reloc_status_type
1015 bfd_install_relocation (bfd *abfd,
1016 arelent *reloc_entry,
1018 bfd_vma data_start_offset,
1019 asection *input_section,
1020 char **error_message)
1023 bfd_reloc_status_type flag = bfd_reloc_ok;
1024 bfd_size_type octets;
1025 bfd_vma output_base = 0;
1026 reloc_howto_type *howto = reloc_entry->howto;
1027 asection *reloc_target_output_section;
1031 symbol = *(reloc_entry->sym_ptr_ptr);
1033 /* If there is a function supplied to handle this relocation type,
1034 call it. It'll return `bfd_reloc_continue' if further processing
1036 if (howto && howto->special_function)
1038 bfd_reloc_status_type cont;
1040 /* Note - we do not call bfd_reloc_offset_in_range here as the
1041 reloc_entry->address field might actually be valid for the
1042 backend concerned. It is up to the special_function itself
1043 to call bfd_reloc_offset_in_range if needed. */
1044 /* XXX - The special_function calls haven't been fixed up to deal
1045 with creating new relocations and section contents. */
1046 cont = howto->special_function (abfd, reloc_entry, symbol,
1047 /* XXX - Non-portable! */
1048 ((bfd_byte *) data_start
1049 - data_start_offset),
1050 input_section, abfd, error_message);
1051 if (cont != bfd_reloc_continue)
1055 if (bfd_is_abs_section (symbol->section))
1057 reloc_entry->address += input_section->output_offset;
1058 return bfd_reloc_ok;
1061 /* No need to check for howto != NULL if !bfd_is_abs_section as
1062 it will have been checked in `bfd_perform_relocation already'. */
1064 /* Is the address of the relocation really within the section? */
1065 octets = reloc_entry->address * bfd_octets_per_byte (abfd, input_section);
1066 if (!bfd_reloc_offset_in_range (howto, abfd, input_section, octets))
1067 return bfd_reloc_outofrange;
1069 /* Work out which section the relocation is targeted at and the
1070 initial relocation command value. */
1072 /* Get symbol value. (Common symbols are special.) */
1073 if (bfd_is_com_section (symbol->section))
1076 relocation = symbol->value;
1078 reloc_target_output_section = symbol->section->output_section;
1080 /* Convert input-section-relative symbol value to absolute. */
1081 if (! howto->partial_inplace)
1084 output_base = reloc_target_output_section->vma;
1086 output_base += symbol->section->output_offset;
1088 /* If symbol addresses are in octets, convert to bytes. */
1089 if (bfd_get_flavour (abfd) == bfd_target_elf_flavour
1090 && (symbol->section->flags & SEC_ELF_OCTETS))
1091 output_base *= bfd_octets_per_byte (abfd, input_section);
1093 relocation += output_base;
1095 /* Add in supplied addend. */
1096 relocation += reloc_entry->addend;
1098 /* Here the variable relocation holds the final address of the
1099 symbol we are relocating against, plus any addend. */
1101 if (howto->pc_relative)
1103 /* This is a PC relative relocation. We want to set RELOCATION
1104 to the distance between the address of the symbol and the
1105 location. RELOCATION is already the address of the symbol.
1107 We start by subtracting the address of the section containing
1110 If pcrel_offset is set, we must further subtract the position
1111 of the location within the section. Some targets arrange for
1112 the addend to be the negative of the position of the location
1113 within the section; for example, i386-aout does this. For
1114 i386-aout, pcrel_offset is FALSE. Some other targets do not
1115 include the position of the location; for example, ELF.
1116 For those targets, pcrel_offset is TRUE.
1118 If we are producing relocatable output, then we must ensure
1119 that this reloc will be correctly computed when the final
1120 relocation is done. If pcrel_offset is FALSE we want to wind
1121 up with the negative of the location within the section,
1122 which means we must adjust the existing addend by the change
1123 in the location within the section. If pcrel_offset is TRUE
1124 we do not want to adjust the existing addend at all.
1126 FIXME: This seems logical to me, but for the case of
1127 producing relocatable output it is not what the code
1128 actually does. I don't want to change it, because it seems
1129 far too likely that something will break. */
1132 input_section->output_section->vma + input_section->output_offset;
1134 if (howto->pcrel_offset && howto->partial_inplace)
1135 relocation -= reloc_entry->address;
1138 if (! howto->partial_inplace)
1140 /* This is a partial relocation, and we want to apply the relocation
1141 to the reloc entry rather than the raw data. Modify the reloc
1142 inplace to reflect what we now know. */
1143 reloc_entry->addend = relocation;
1144 reloc_entry->address += input_section->output_offset;
1149 /* This is a partial relocation, but inplace, so modify the
1152 If we've relocated with a symbol with a section, change
1153 into a ref to the section belonging to the symbol. */
1154 reloc_entry->address += input_section->output_offset;
1157 if (abfd->xvec->flavour == bfd_target_coff_flavour
1158 && strcmp (abfd->xvec->name, "coff-Intel-little") != 0
1159 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0)
1162 /* For m68k-coff, the addend was being subtracted twice during
1163 relocation with -r. Removing the line below this comment
1164 fixes that problem; see PR 2953.
1166 However, Ian wrote the following, regarding removing the line below,
1167 which explains why it is still enabled: --djm
1169 If you put a patch like that into BFD you need to check all the COFF
1170 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1171 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1172 problem in a different way. There may very well be a reason that the
1173 code works as it does.
1175 Hmmm. The first obvious point is that bfd_install_relocation should
1176 not have any tests that depend upon the flavour. It's seem like
1177 entirely the wrong place for such a thing. The second obvious point
1178 is that the current code ignores the reloc addend when producing
1179 relocatable output for COFF. That's peculiar. In fact, I really
1180 have no idea what the point of the line you want to remove is.
1182 A typical COFF reloc subtracts the old value of the symbol and adds in
1183 the new value to the location in the object file (if it's a pc
1184 relative reloc it adds the difference between the symbol value and the
1185 location). When relocating we need to preserve that property.
1187 BFD handles this by setting the addend to the negative of the old
1188 value of the symbol. Unfortunately it handles common symbols in a
1189 non-standard way (it doesn't subtract the old value) but that's a
1190 different story (we can't change it without losing backward
1191 compatibility with old object files) (coff-i386 does subtract the old
1192 value, to be compatible with existing coff-i386 targets, like SCO).
1194 So everything works fine when not producing relocatable output. When
1195 we are producing relocatable output, logically we should do exactly
1196 what we do when not producing relocatable output. Therefore, your
1197 patch is correct. In fact, it should probably always just set
1198 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1199 add the value into the object file. This won't hurt the COFF code,
1200 which doesn't use the addend; I'm not sure what it will do to other
1201 formats (the thing to check for would be whether any formats both use
1202 the addend and set partial_inplace).
1204 When I wanted to make coff-i386 produce relocatable output, I ran
1205 into the problem that you are running into: I wanted to remove that
1206 line. Rather than risk it, I made the coff-i386 relocs use a special
1207 function; it's coff_i386_reloc in coff-i386.c. The function
1208 specifically adds the addend field into the object file, knowing that
1209 bfd_install_relocation is not going to. If you remove that line, then
1210 coff-i386.c will wind up adding the addend field in twice. It's
1211 trivial to fix; it just needs to be done.
1213 The problem with removing the line is just that it may break some
1214 working code. With BFD it's hard to be sure of anything. The right
1215 way to deal with this is simply to build and test at least all the
1216 supported COFF targets. It should be straightforward if time and disk
1217 space consuming. For each target:
1219 2) generate some executable, and link it using -r (I would
1220 probably use paranoia.o and link against newlib/libc.a, which
1221 for all the supported targets would be available in
1222 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1223 3) make the change to reloc.c
1224 4) rebuild the linker
1226 6) if the resulting object files are the same, you have at least
1228 7) if they are different you have to figure out which version is
1230 relocation -= reloc_entry->addend;
1231 /* FIXME: There should be no target specific code here... */
1232 if (strcmp (abfd->xvec->name, "coff-z8k") != 0)
1233 reloc_entry->addend = 0;
1237 reloc_entry->addend = relocation;
1241 /* FIXME: This overflow checking is incomplete, because the value
1242 might have overflowed before we get here. For a correct check we
1243 need to compute the value in a size larger than bitsize, but we
1244 can't reasonably do that for a reloc the same size as a host
1246 FIXME: We should also do overflow checking on the result after
1247 adding in the value contained in the object file. */
1248 if (howto->complain_on_overflow != complain_overflow_dont)
1249 flag = bfd_check_overflow (howto->complain_on_overflow,
1252 bfd_arch_bits_per_address (abfd),
1255 /* Either we are relocating all the way, or we don't want to apply
1256 the relocation to the reloc entry (probably because there isn't
1257 any room in the output format to describe addends to relocs). */
1259 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1260 (OSF version 1.3, compiler version 3.11). It miscompiles the
1274 x <<= (unsigned long) s.i0;
1276 printf ("failed\n");
1278 printf ("succeeded (%lx)\n", x);
1282 relocation >>= (bfd_vma) howto->rightshift;
1284 /* Shift everything up to where it's going to be used. */
1285 relocation <<= (bfd_vma) howto->bitpos;
1287 /* Wait for the day when all have the mask in them. */
1290 i instruction to be left alone
1291 o offset within instruction
1292 r relocation offset to apply
1301 (( i i i i i o o o o o from bfd_get<size>
1302 and S S S S S) to get the size offset we want
1303 + r r r r r r r r r r) to get the final value to place
1304 and D D D D D to chop to right size
1305 -----------------------
1308 ( i i i i i o o o o o from bfd_get<size>
1309 and N N N N N ) get instruction
1310 -----------------------
1316 -----------------------
1317 = R R R R R R R R R R put into bfd_put<size>
1320 data = (bfd_byte *) data_start + (octets - data_start_offset);
1321 apply_reloc (abfd, data, howto, relocation);
1325 /* This relocation routine is used by some of the backend linkers.
1326 They do not construct asymbol or arelent structures, so there is no
1327 reason for them to use bfd_perform_relocation. Also,
1328 bfd_perform_relocation is so hacked up it is easier to write a new
1329 function than to try to deal with it.
1331 This routine does a final relocation. Whether it is useful for a
1332 relocatable link depends upon how the object format defines
1335 FIXME: This routine ignores any special_function in the HOWTO,
1336 since the existing special_function values have been written for
1337 bfd_perform_relocation.
1339 HOWTO is the reloc howto information.
1340 INPUT_BFD is the BFD which the reloc applies to.
1341 INPUT_SECTION is the section which the reloc applies to.
1342 CONTENTS is the contents of the section.
1343 ADDRESS is the address of the reloc within INPUT_SECTION.
1344 VALUE is the value of the symbol the reloc refers to.
1345 ADDEND is the addend of the reloc. */
1347 bfd_reloc_status_type
1348 _bfd_final_link_relocate (reloc_howto_type *howto,
1350 asection *input_section,
1357 bfd_size_type octets = (address
1358 * bfd_octets_per_byte (input_bfd, input_section));
1360 /* Sanity check the address. */
1361 if (!bfd_reloc_offset_in_range (howto, input_bfd, input_section, octets))
1362 return bfd_reloc_outofrange;
1364 /* This function assumes that we are dealing with a basic relocation
1365 against a symbol. We want to compute the value of the symbol to
1366 relocate to. This is just VALUE, the value of the symbol, plus
1367 ADDEND, any addend associated with the reloc. */
1368 relocation = value + addend;
1370 /* If the relocation is PC relative, we want to set RELOCATION to
1371 the distance between the symbol (currently in RELOCATION) and the
1372 location we are relocating. Some targets (e.g., i386-aout)
1373 arrange for the contents of the section to be the negative of the
1374 offset of the location within the section; for such targets
1375 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1376 the contents of the section as zero; for such targets
1377 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1378 subtract out the offset of the location within the section (which
1379 is just ADDRESS). */
1380 if (howto->pc_relative)
1382 relocation -= (input_section->output_section->vma
1383 + input_section->output_offset);
1384 if (howto->pcrel_offset)
1385 relocation -= address;
1388 return _bfd_relocate_contents (howto, input_bfd, relocation,
1392 /* Relocate a given location using a given value and howto. */
1394 bfd_reloc_status_type
1395 _bfd_relocate_contents (reloc_howto_type *howto,
1401 bfd_reloc_status_type flag;
1402 unsigned int rightshift = howto->rightshift;
1403 unsigned int bitpos = howto->bitpos;
1406 relocation = -relocation;
1408 /* Get the value we are going to relocate. */
1409 x = read_reloc (input_bfd, location, howto);
1411 /* Check for overflow. FIXME: We may drop bits during the addition
1412 which we don't check for. We must either check at every single
1413 operation, which would be tedious, or we must do the computations
1414 in a type larger than bfd_vma, which would be inefficient. */
1415 flag = bfd_reloc_ok;
1416 if (howto->complain_on_overflow != complain_overflow_dont)
1418 bfd_vma addrmask, fieldmask, signmask, ss;
1421 /* Get the values to be added together. For signed and unsigned
1422 relocations, we assume that all values should be truncated to
1423 the size of an address. For bitfields, all the bits matter.
1424 See also bfd_check_overflow. */
1425 fieldmask = N_ONES (howto->bitsize);
1426 signmask = ~fieldmask;
1427 addrmask = (N_ONES (bfd_arch_bits_per_address (input_bfd))
1428 | (fieldmask << rightshift));
1429 a = (relocation & addrmask) >> rightshift;
1430 b = (x & howto->src_mask & addrmask) >> bitpos;
1431 addrmask >>= rightshift;
1433 switch (howto->complain_on_overflow)
1435 case complain_overflow_signed:
1436 /* If any sign bits are set, all sign bits must be set.
1437 That is, A must be a valid negative address after
1439 signmask = ~(fieldmask >> 1);
1442 case complain_overflow_bitfield:
1443 /* Much like the signed check, but for a field one bit
1444 wider. We allow a bitfield to represent numbers in the
1445 range -2**n to 2**n-1, where n is the number of bits in the
1446 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1447 can't overflow, which is exactly what we want. */
1449 if (ss != 0 && ss != (addrmask & signmask))
1450 flag = bfd_reloc_overflow;
1452 /* We only need this next bit of code if the sign bit of B
1453 is below the sign bit of A. This would only happen if
1454 SRC_MASK had fewer bits than BITSIZE. Note that if
1455 SRC_MASK has more bits than BITSIZE, we can get into
1456 trouble; we would need to verify that B is in range, as
1457 we do for A above. */
1458 ss = ((~howto->src_mask) >> 1) & howto->src_mask;
1461 /* Set all the bits above the sign bit. */
1464 /* Now we can do the addition. */
1467 /* See if the result has the correct sign. Bits above the
1468 sign bit are junk now; ignore them. If the sum is
1469 positive, make sure we did not have all negative inputs;
1470 if the sum is negative, make sure we did not have all
1471 positive inputs. The test below looks only at the sign
1472 bits, and it really just
1473 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1475 We mask with addrmask here to explicitly allow an address
1476 wrap-around. The Linux kernel relies on it, and it is
1477 the only way to write assembler code which can run when
1478 loaded at a location 0x80000000 away from the location at
1479 which it is linked. */
1480 if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask)
1481 flag = bfd_reloc_overflow;
1484 case complain_overflow_unsigned:
1485 /* Checking for an unsigned overflow is relatively easy:
1486 trim the addresses and add, and trim the result as well.
1487 Overflow is normally indicated when the result does not
1488 fit in the field. However, we also need to consider the
1489 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1490 input is 0x80000000, and bfd_vma is only 32 bits; then we
1491 will get sum == 0, but there is an overflow, since the
1492 inputs did not fit in the field. Instead of doing a
1493 separate test, we can check for this by or-ing in the
1494 operands when testing for the sum overflowing its final
1496 sum = (a + b) & addrmask;
1497 if ((a | b | sum) & signmask)
1498 flag = bfd_reloc_overflow;
1506 /* Put RELOCATION in the right bits. */
1507 relocation >>= (bfd_vma) rightshift;
1508 relocation <<= (bfd_vma) bitpos;
1510 /* Add RELOCATION to the right bits of X. */
1511 x = ((x & ~howto->dst_mask)
1512 | (((x & howto->src_mask) + relocation) & howto->dst_mask));
1514 /* Put the relocated value back in the object file. */
1515 write_reloc (input_bfd, x, location, howto);
1519 /* Clear a given location using a given howto, by applying a fixed relocation
1520 value and discarding any in-place addend. This is used for fixed-up
1521 relocations against discarded symbols, to make ignorable debug or unwind
1522 information more obvious. */
1524 bfd_reloc_status_type
1525 _bfd_clear_contents (reloc_howto_type *howto,
1527 asection *input_section,
1534 if (!bfd_reloc_offset_in_range (howto, input_bfd, input_section, off))
1535 return bfd_reloc_outofrange;
1537 /* Get the value we are going to relocate. */
1538 location = buf + off;
1539 x = read_reloc (input_bfd, location, howto);
1541 /* Zero out the unwanted bits of X. */
1542 x &= ~howto->dst_mask;
1544 /* For a range list, use 1 instead of 0 as placeholder. 0
1545 would terminate the list, hiding any later entries. */
1546 if (strcmp (bfd_section_name (input_section), ".debug_ranges") == 0
1547 && (howto->dst_mask & 1) != 0)
1550 /* Put the relocated value back in the object file. */
1551 write_reloc (input_bfd, x, location, howto);
1552 return bfd_reloc_ok;
1558 howto manager, , typedef arelent, Relocations
1563 When an application wants to create a relocation, but doesn't
1564 know what the target machine might call it, it can find out by
1565 using this bit of code.
1574 The insides of a reloc code. The idea is that, eventually, there
1575 will be one enumerator for every type of relocation we ever do.
1576 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1577 return a howto pointer.
1579 This does mean that the application must determine the correct
1580 enumerator value; you can't get a howto pointer from a random set
1601 Basic absolute relocations of N bits.
1616 PC-relative relocations. Sometimes these are relative to the address
1617 of the relocation itself; sometimes they are relative to the start of
1618 the section containing the relocation. It depends on the specific target.
1623 Section relative relocations. Some targets need this for DWARF2.
1626 BFD_RELOC_32_GOT_PCREL
1628 BFD_RELOC_16_GOT_PCREL
1630 BFD_RELOC_8_GOT_PCREL
1636 BFD_RELOC_LO16_GOTOFF
1638 BFD_RELOC_HI16_GOTOFF
1640 BFD_RELOC_HI16_S_GOTOFF
1644 BFD_RELOC_64_PLT_PCREL
1646 BFD_RELOC_32_PLT_PCREL
1648 BFD_RELOC_24_PLT_PCREL
1650 BFD_RELOC_16_PLT_PCREL
1652 BFD_RELOC_8_PLT_PCREL
1660 BFD_RELOC_LO16_PLTOFF
1662 BFD_RELOC_HI16_PLTOFF
1664 BFD_RELOC_HI16_S_PLTOFF
1678 BFD_RELOC_68K_GLOB_DAT
1680 BFD_RELOC_68K_JMP_SLOT
1682 BFD_RELOC_68K_RELATIVE
1684 BFD_RELOC_68K_TLS_GD32
1686 BFD_RELOC_68K_TLS_GD16
1688 BFD_RELOC_68K_TLS_GD8
1690 BFD_RELOC_68K_TLS_LDM32
1692 BFD_RELOC_68K_TLS_LDM16
1694 BFD_RELOC_68K_TLS_LDM8
1696 BFD_RELOC_68K_TLS_LDO32
1698 BFD_RELOC_68K_TLS_LDO16
1700 BFD_RELOC_68K_TLS_LDO8
1702 BFD_RELOC_68K_TLS_IE32
1704 BFD_RELOC_68K_TLS_IE16
1706 BFD_RELOC_68K_TLS_IE8
1708 BFD_RELOC_68K_TLS_LE32
1710 BFD_RELOC_68K_TLS_LE16
1712 BFD_RELOC_68K_TLS_LE8
1714 Relocations used by 68K ELF.
1717 BFD_RELOC_32_BASEREL
1719 BFD_RELOC_16_BASEREL
1721 BFD_RELOC_LO16_BASEREL
1723 BFD_RELOC_HI16_BASEREL
1725 BFD_RELOC_HI16_S_BASEREL
1731 Linkage-table relative.
1736 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1739 BFD_RELOC_32_PCREL_S2
1741 BFD_RELOC_16_PCREL_S2
1743 BFD_RELOC_23_PCREL_S2
1745 These PC-relative relocations are stored as word displacements --
1746 i.e., byte displacements shifted right two bits. The 30-bit word
1747 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1748 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1749 signed 16-bit displacement is used on the MIPS, and the 23-bit
1750 displacement is used on the Alpha.
1757 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1758 the target word. These are used on the SPARC.
1765 For systems that allocate a Global Pointer register, these are
1766 displacements off that register. These relocation types are
1767 handled specially, because the value the register will have is
1768 decided relatively late.
1773 BFD_RELOC_SPARC_WDISP22
1779 BFD_RELOC_SPARC_GOT10
1781 BFD_RELOC_SPARC_GOT13
1783 BFD_RELOC_SPARC_GOT22
1785 BFD_RELOC_SPARC_PC10
1787 BFD_RELOC_SPARC_PC22
1789 BFD_RELOC_SPARC_WPLT30
1791 BFD_RELOC_SPARC_COPY
1793 BFD_RELOC_SPARC_GLOB_DAT
1795 BFD_RELOC_SPARC_JMP_SLOT
1797 BFD_RELOC_SPARC_RELATIVE
1799 BFD_RELOC_SPARC_UA16
1801 BFD_RELOC_SPARC_UA32
1803 BFD_RELOC_SPARC_UA64
1805 BFD_RELOC_SPARC_GOTDATA_HIX22
1807 BFD_RELOC_SPARC_GOTDATA_LOX10
1809 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1811 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1813 BFD_RELOC_SPARC_GOTDATA_OP
1815 BFD_RELOC_SPARC_JMP_IREL
1817 BFD_RELOC_SPARC_IRELATIVE
1819 SPARC ELF relocations. There is probably some overlap with other
1820 relocation types already defined.
1823 BFD_RELOC_SPARC_BASE13
1825 BFD_RELOC_SPARC_BASE22
1827 I think these are specific to SPARC a.out (e.g., Sun 4).
1837 BFD_RELOC_SPARC_OLO10
1839 BFD_RELOC_SPARC_HH22
1841 BFD_RELOC_SPARC_HM10
1843 BFD_RELOC_SPARC_LM22
1845 BFD_RELOC_SPARC_PC_HH22
1847 BFD_RELOC_SPARC_PC_HM10
1849 BFD_RELOC_SPARC_PC_LM22
1851 BFD_RELOC_SPARC_WDISP16
1853 BFD_RELOC_SPARC_WDISP19
1861 BFD_RELOC_SPARC_DISP64
1864 BFD_RELOC_SPARC_PLT32
1866 BFD_RELOC_SPARC_PLT64
1868 BFD_RELOC_SPARC_HIX22
1870 BFD_RELOC_SPARC_LOX10
1878 BFD_RELOC_SPARC_REGISTER
1882 BFD_RELOC_SPARC_SIZE32
1884 BFD_RELOC_SPARC_SIZE64
1886 BFD_RELOC_SPARC_WDISP10
1891 BFD_RELOC_SPARC_REV32
1893 SPARC little endian relocation
1895 BFD_RELOC_SPARC_TLS_GD_HI22
1897 BFD_RELOC_SPARC_TLS_GD_LO10
1899 BFD_RELOC_SPARC_TLS_GD_ADD
1901 BFD_RELOC_SPARC_TLS_GD_CALL
1903 BFD_RELOC_SPARC_TLS_LDM_HI22
1905 BFD_RELOC_SPARC_TLS_LDM_LO10
1907 BFD_RELOC_SPARC_TLS_LDM_ADD
1909 BFD_RELOC_SPARC_TLS_LDM_CALL
1911 BFD_RELOC_SPARC_TLS_LDO_HIX22
1913 BFD_RELOC_SPARC_TLS_LDO_LOX10
1915 BFD_RELOC_SPARC_TLS_LDO_ADD
1917 BFD_RELOC_SPARC_TLS_IE_HI22
1919 BFD_RELOC_SPARC_TLS_IE_LO10
1921 BFD_RELOC_SPARC_TLS_IE_LD
1923 BFD_RELOC_SPARC_TLS_IE_LDX
1925 BFD_RELOC_SPARC_TLS_IE_ADD
1927 BFD_RELOC_SPARC_TLS_LE_HIX22
1929 BFD_RELOC_SPARC_TLS_LE_LOX10
1931 BFD_RELOC_SPARC_TLS_DTPMOD32
1933 BFD_RELOC_SPARC_TLS_DTPMOD64
1935 BFD_RELOC_SPARC_TLS_DTPOFF32
1937 BFD_RELOC_SPARC_TLS_DTPOFF64
1939 BFD_RELOC_SPARC_TLS_TPOFF32
1941 BFD_RELOC_SPARC_TLS_TPOFF64
1943 SPARC TLS relocations
1952 BFD_RELOC_SPU_IMM10W
1956 BFD_RELOC_SPU_IMM16W
1960 BFD_RELOC_SPU_PCREL9a
1962 BFD_RELOC_SPU_PCREL9b
1964 BFD_RELOC_SPU_PCREL16
1974 BFD_RELOC_SPU_ADD_PIC
1979 BFD_RELOC_ALPHA_GPDISP_HI16
1981 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1982 "addend" in some special way.
1983 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1984 writing; when reading, it will be the absolute section symbol. The
1985 addend is the displacement in bytes of the "lda" instruction from
1986 the "ldah" instruction (which is at the address of this reloc).
1988 BFD_RELOC_ALPHA_GPDISP_LO16
1990 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1991 with GPDISP_HI16 relocs. The addend is ignored when writing the
1992 relocations out, and is filled in with the file's GP value on
1993 reading, for convenience.
1996 BFD_RELOC_ALPHA_GPDISP
1998 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
1999 relocation except that there is no accompanying GPDISP_LO16
2003 BFD_RELOC_ALPHA_LITERAL
2005 BFD_RELOC_ALPHA_ELF_LITERAL
2007 BFD_RELOC_ALPHA_LITUSE
2009 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2010 the assembler turns it into a LDQ instruction to load the address of
2011 the symbol, and then fills in a register in the real instruction.
2013 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2014 section symbol. The addend is ignored when writing, but is filled
2015 in with the file's GP value on reading, for convenience, as with the
2018 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2019 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2020 but it generates output not based on the position within the .got
2021 section, but relative to the GP value chosen for the file during the
2024 The LITUSE reloc, on the instruction using the loaded address, gives
2025 information to the linker that it might be able to use to optimize
2026 away some literal section references. The symbol is ignored (read
2027 as the absolute section symbol), and the "addend" indicates the type
2028 of instruction using the register:
2029 1 - "memory" fmt insn
2030 2 - byte-manipulation (byte offset reg)
2031 3 - jsr (target of branch)
2034 BFD_RELOC_ALPHA_HINT
2036 The HINT relocation indicates a value that should be filled into the
2037 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2038 prediction logic which may be provided on some processors.
2041 BFD_RELOC_ALPHA_LINKAGE
2043 The LINKAGE relocation outputs a linkage pair in the object file,
2044 which is filled by the linker.
2047 BFD_RELOC_ALPHA_CODEADDR
2049 The CODEADDR relocation outputs a STO_CA in the object file,
2050 which is filled by the linker.
2053 BFD_RELOC_ALPHA_GPREL_HI16
2055 BFD_RELOC_ALPHA_GPREL_LO16
2057 The GPREL_HI/LO relocations together form a 32-bit offset from the
2061 BFD_RELOC_ALPHA_BRSGP
2063 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2064 share a common GP, and the target address is adjusted for
2065 STO_ALPHA_STD_GPLOAD.
2070 The NOP relocation outputs a NOP if the longword displacement
2071 between two procedure entry points is < 2^21.
2076 The BSR relocation outputs a BSR if the longword displacement
2077 between two procedure entry points is < 2^21.
2082 The LDA relocation outputs a LDA if the longword displacement
2083 between two procedure entry points is < 2^16.
2088 The BOH relocation outputs a BSR if the longword displacement
2089 between two procedure entry points is < 2^21, or else a hint.
2092 BFD_RELOC_ALPHA_TLSGD
2094 BFD_RELOC_ALPHA_TLSLDM
2096 BFD_RELOC_ALPHA_DTPMOD64
2098 BFD_RELOC_ALPHA_GOTDTPREL16
2100 BFD_RELOC_ALPHA_DTPREL64
2102 BFD_RELOC_ALPHA_DTPREL_HI16
2104 BFD_RELOC_ALPHA_DTPREL_LO16
2106 BFD_RELOC_ALPHA_DTPREL16
2108 BFD_RELOC_ALPHA_GOTTPREL16
2110 BFD_RELOC_ALPHA_TPREL64
2112 BFD_RELOC_ALPHA_TPREL_HI16
2114 BFD_RELOC_ALPHA_TPREL_LO16
2116 BFD_RELOC_ALPHA_TPREL16
2118 Alpha thread-local storage relocations.
2123 BFD_RELOC_MICROMIPS_JMP
2125 The MIPS jump instruction.
2128 BFD_RELOC_MIPS16_JMP
2130 The MIPS16 jump instruction.
2133 BFD_RELOC_MIPS16_GPREL
2135 MIPS16 GP relative reloc.
2140 High 16 bits of 32-bit value; simple reloc.
2145 High 16 bits of 32-bit value but the low 16 bits will be sign
2146 extended and added to form the final result. If the low 16
2147 bits form a negative number, we need to add one to the high value
2148 to compensate for the borrow when the low bits are added.
2156 BFD_RELOC_HI16_PCREL
2158 High 16 bits of 32-bit pc-relative value
2160 BFD_RELOC_HI16_S_PCREL
2162 High 16 bits of 32-bit pc-relative value, adjusted
2164 BFD_RELOC_LO16_PCREL
2166 Low 16 bits of pc-relative value
2169 BFD_RELOC_MIPS16_GOT16
2171 BFD_RELOC_MIPS16_CALL16
2173 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2174 16-bit immediate fields
2176 BFD_RELOC_MIPS16_HI16
2178 MIPS16 high 16 bits of 32-bit value.
2180 BFD_RELOC_MIPS16_HI16_S
2182 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2183 extended and added to form the final result. If the low 16
2184 bits form a negative number, we need to add one to the high value
2185 to compensate for the borrow when the low bits are added.
2187 BFD_RELOC_MIPS16_LO16
2192 BFD_RELOC_MIPS16_TLS_GD
2194 BFD_RELOC_MIPS16_TLS_LDM
2196 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2198 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2200 BFD_RELOC_MIPS16_TLS_GOTTPREL
2202 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2204 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2206 MIPS16 TLS relocations
2209 BFD_RELOC_MIPS_LITERAL
2211 BFD_RELOC_MICROMIPS_LITERAL
2213 Relocation against a MIPS literal section.
2216 BFD_RELOC_MICROMIPS_7_PCREL_S1
2218 BFD_RELOC_MICROMIPS_10_PCREL_S1
2220 BFD_RELOC_MICROMIPS_16_PCREL_S1
2222 microMIPS PC-relative relocations.
2225 BFD_RELOC_MIPS16_16_PCREL_S1
2227 MIPS16 PC-relative relocation.
2230 BFD_RELOC_MIPS_21_PCREL_S2
2232 BFD_RELOC_MIPS_26_PCREL_S2
2234 BFD_RELOC_MIPS_18_PCREL_S3
2236 BFD_RELOC_MIPS_19_PCREL_S2
2238 MIPS PC-relative relocations.
2241 BFD_RELOC_MICROMIPS_GPREL16
2243 BFD_RELOC_MICROMIPS_HI16
2245 BFD_RELOC_MICROMIPS_HI16_S
2247 BFD_RELOC_MICROMIPS_LO16
2249 microMIPS versions of generic BFD relocs.
2252 BFD_RELOC_MIPS_GOT16
2254 BFD_RELOC_MICROMIPS_GOT16
2256 BFD_RELOC_MIPS_CALL16
2258 BFD_RELOC_MICROMIPS_CALL16
2260 BFD_RELOC_MIPS_GOT_HI16
2262 BFD_RELOC_MICROMIPS_GOT_HI16
2264 BFD_RELOC_MIPS_GOT_LO16
2266 BFD_RELOC_MICROMIPS_GOT_LO16
2268 BFD_RELOC_MIPS_CALL_HI16
2270 BFD_RELOC_MICROMIPS_CALL_HI16
2272 BFD_RELOC_MIPS_CALL_LO16
2274 BFD_RELOC_MICROMIPS_CALL_LO16
2278 BFD_RELOC_MICROMIPS_SUB
2280 BFD_RELOC_MIPS_GOT_PAGE
2282 BFD_RELOC_MICROMIPS_GOT_PAGE
2284 BFD_RELOC_MIPS_GOT_OFST
2286 BFD_RELOC_MICROMIPS_GOT_OFST
2288 BFD_RELOC_MIPS_GOT_DISP
2290 BFD_RELOC_MICROMIPS_GOT_DISP
2292 BFD_RELOC_MIPS_SHIFT5
2294 BFD_RELOC_MIPS_SHIFT6
2296 BFD_RELOC_MIPS_INSERT_A
2298 BFD_RELOC_MIPS_INSERT_B
2300 BFD_RELOC_MIPS_DELETE
2302 BFD_RELOC_MIPS_HIGHEST
2304 BFD_RELOC_MICROMIPS_HIGHEST
2306 BFD_RELOC_MIPS_HIGHER
2308 BFD_RELOC_MICROMIPS_HIGHER
2310 BFD_RELOC_MIPS_SCN_DISP
2312 BFD_RELOC_MICROMIPS_SCN_DISP
2314 BFD_RELOC_MIPS_REL16
2316 BFD_RELOC_MIPS_RELGOT
2320 BFD_RELOC_MICROMIPS_JALR
2322 BFD_RELOC_MIPS_TLS_DTPMOD32
2324 BFD_RELOC_MIPS_TLS_DTPREL32
2326 BFD_RELOC_MIPS_TLS_DTPMOD64
2328 BFD_RELOC_MIPS_TLS_DTPREL64
2330 BFD_RELOC_MIPS_TLS_GD
2332 BFD_RELOC_MICROMIPS_TLS_GD
2334 BFD_RELOC_MIPS_TLS_LDM
2336 BFD_RELOC_MICROMIPS_TLS_LDM
2338 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2340 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2342 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2344 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2346 BFD_RELOC_MIPS_TLS_GOTTPREL
2348 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2350 BFD_RELOC_MIPS_TLS_TPREL32
2352 BFD_RELOC_MIPS_TLS_TPREL64
2354 BFD_RELOC_MIPS_TLS_TPREL_HI16
2356 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2358 BFD_RELOC_MIPS_TLS_TPREL_LO16
2360 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2364 MIPS ELF relocations.
2370 BFD_RELOC_MIPS_JUMP_SLOT
2372 MIPS ELF relocations (VxWorks and PLT extensions).
2376 BFD_RELOC_MOXIE_10_PCREL
2378 Moxie ELF relocations.
2390 BFD_RELOC_FT32_RELAX
2398 BFD_RELOC_FT32_DIFF32
2400 FT32 ELF relocations.
2404 BFD_RELOC_FRV_LABEL16
2406 BFD_RELOC_FRV_LABEL24
2412 BFD_RELOC_FRV_GPREL12
2414 BFD_RELOC_FRV_GPRELU12
2416 BFD_RELOC_FRV_GPREL32
2418 BFD_RELOC_FRV_GPRELHI
2420 BFD_RELOC_FRV_GPRELLO
2428 BFD_RELOC_FRV_FUNCDESC
2430 BFD_RELOC_FRV_FUNCDESC_GOT12
2432 BFD_RELOC_FRV_FUNCDESC_GOTHI
2434 BFD_RELOC_FRV_FUNCDESC_GOTLO
2436 BFD_RELOC_FRV_FUNCDESC_VALUE
2438 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2440 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2442 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2444 BFD_RELOC_FRV_GOTOFF12
2446 BFD_RELOC_FRV_GOTOFFHI
2448 BFD_RELOC_FRV_GOTOFFLO
2450 BFD_RELOC_FRV_GETTLSOFF
2452 BFD_RELOC_FRV_TLSDESC_VALUE
2454 BFD_RELOC_FRV_GOTTLSDESC12
2456 BFD_RELOC_FRV_GOTTLSDESCHI
2458 BFD_RELOC_FRV_GOTTLSDESCLO
2460 BFD_RELOC_FRV_TLSMOFF12
2462 BFD_RELOC_FRV_TLSMOFFHI
2464 BFD_RELOC_FRV_TLSMOFFLO
2466 BFD_RELOC_FRV_GOTTLSOFF12
2468 BFD_RELOC_FRV_GOTTLSOFFHI
2470 BFD_RELOC_FRV_GOTTLSOFFLO
2472 BFD_RELOC_FRV_TLSOFF
2474 BFD_RELOC_FRV_TLSDESC_RELAX
2476 BFD_RELOC_FRV_GETTLSOFF_RELAX
2478 BFD_RELOC_FRV_TLSOFF_RELAX
2480 BFD_RELOC_FRV_TLSMOFF
2482 Fujitsu Frv Relocations.
2486 BFD_RELOC_MN10300_GOTOFF24
2488 This is a 24bit GOT-relative reloc for the mn10300.
2490 BFD_RELOC_MN10300_GOT32
2492 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2495 BFD_RELOC_MN10300_GOT24
2497 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2500 BFD_RELOC_MN10300_GOT16
2502 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2505 BFD_RELOC_MN10300_COPY
2507 Copy symbol at runtime.
2509 BFD_RELOC_MN10300_GLOB_DAT
2513 BFD_RELOC_MN10300_JMP_SLOT
2517 BFD_RELOC_MN10300_RELATIVE
2519 Adjust by program base.
2521 BFD_RELOC_MN10300_SYM_DIFF
2523 Together with another reloc targeted at the same location,
2524 allows for a value that is the difference of two symbols
2525 in the same section.
2527 BFD_RELOC_MN10300_ALIGN
2529 The addend of this reloc is an alignment power that must
2530 be honoured at the offset's location, regardless of linker
2533 BFD_RELOC_MN10300_TLS_GD
2535 BFD_RELOC_MN10300_TLS_LD
2537 BFD_RELOC_MN10300_TLS_LDO
2539 BFD_RELOC_MN10300_TLS_GOTIE
2541 BFD_RELOC_MN10300_TLS_IE
2543 BFD_RELOC_MN10300_TLS_LE
2545 BFD_RELOC_MN10300_TLS_DTPMOD
2547 BFD_RELOC_MN10300_TLS_DTPOFF
2549 BFD_RELOC_MN10300_TLS_TPOFF
2551 Various TLS-related relocations.
2553 BFD_RELOC_MN10300_32_PCREL
2555 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2558 BFD_RELOC_MN10300_16_PCREL
2560 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2571 BFD_RELOC_386_GLOB_DAT
2573 BFD_RELOC_386_JUMP_SLOT
2575 BFD_RELOC_386_RELATIVE
2577 BFD_RELOC_386_GOTOFF
2581 BFD_RELOC_386_TLS_TPOFF
2583 BFD_RELOC_386_TLS_IE
2585 BFD_RELOC_386_TLS_GOTIE
2587 BFD_RELOC_386_TLS_LE
2589 BFD_RELOC_386_TLS_GD
2591 BFD_RELOC_386_TLS_LDM
2593 BFD_RELOC_386_TLS_LDO_32
2595 BFD_RELOC_386_TLS_IE_32
2597 BFD_RELOC_386_TLS_LE_32
2599 BFD_RELOC_386_TLS_DTPMOD32
2601 BFD_RELOC_386_TLS_DTPOFF32
2603 BFD_RELOC_386_TLS_TPOFF32
2605 BFD_RELOC_386_TLS_GOTDESC
2607 BFD_RELOC_386_TLS_DESC_CALL
2609 BFD_RELOC_386_TLS_DESC
2611 BFD_RELOC_386_IRELATIVE
2613 BFD_RELOC_386_GOT32X
2615 i386/elf relocations
2618 BFD_RELOC_X86_64_GOT32
2620 BFD_RELOC_X86_64_PLT32
2622 BFD_RELOC_X86_64_COPY
2624 BFD_RELOC_X86_64_GLOB_DAT
2626 BFD_RELOC_X86_64_JUMP_SLOT
2628 BFD_RELOC_X86_64_RELATIVE
2630 BFD_RELOC_X86_64_GOTPCREL
2632 BFD_RELOC_X86_64_32S
2634 BFD_RELOC_X86_64_DTPMOD64
2636 BFD_RELOC_X86_64_DTPOFF64
2638 BFD_RELOC_X86_64_TPOFF64
2640 BFD_RELOC_X86_64_TLSGD
2642 BFD_RELOC_X86_64_TLSLD
2644 BFD_RELOC_X86_64_DTPOFF32
2646 BFD_RELOC_X86_64_GOTTPOFF
2648 BFD_RELOC_X86_64_TPOFF32
2650 BFD_RELOC_X86_64_GOTOFF64
2652 BFD_RELOC_X86_64_GOTPC32
2654 BFD_RELOC_X86_64_GOT64
2656 BFD_RELOC_X86_64_GOTPCREL64
2658 BFD_RELOC_X86_64_GOTPC64
2660 BFD_RELOC_X86_64_GOTPLT64
2662 BFD_RELOC_X86_64_PLTOFF64
2664 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2666 BFD_RELOC_X86_64_TLSDESC_CALL
2668 BFD_RELOC_X86_64_TLSDESC
2670 BFD_RELOC_X86_64_IRELATIVE
2672 BFD_RELOC_X86_64_PC32_BND
2674 BFD_RELOC_X86_64_PLT32_BND
2676 BFD_RELOC_X86_64_GOTPCRELX
2678 BFD_RELOC_X86_64_REX_GOTPCRELX
2680 x86-64/elf relocations
2683 BFD_RELOC_NS32K_IMM_8
2685 BFD_RELOC_NS32K_IMM_16
2687 BFD_RELOC_NS32K_IMM_32
2689 BFD_RELOC_NS32K_IMM_8_PCREL
2691 BFD_RELOC_NS32K_IMM_16_PCREL
2693 BFD_RELOC_NS32K_IMM_32_PCREL
2695 BFD_RELOC_NS32K_DISP_8
2697 BFD_RELOC_NS32K_DISP_16
2699 BFD_RELOC_NS32K_DISP_32
2701 BFD_RELOC_NS32K_DISP_8_PCREL
2703 BFD_RELOC_NS32K_DISP_16_PCREL
2705 BFD_RELOC_NS32K_DISP_32_PCREL
2710 BFD_RELOC_PDP11_DISP_8_PCREL
2712 BFD_RELOC_PDP11_DISP_6_PCREL
2717 BFD_RELOC_PJ_CODE_HI16
2719 BFD_RELOC_PJ_CODE_LO16
2721 BFD_RELOC_PJ_CODE_DIR16
2723 BFD_RELOC_PJ_CODE_DIR32
2725 BFD_RELOC_PJ_CODE_REL16
2727 BFD_RELOC_PJ_CODE_REL32
2729 Picojava relocs. Not all of these appear in object files.
2740 BFD_RELOC_PPC_B16_BRTAKEN
2742 BFD_RELOC_PPC_B16_BRNTAKEN
2746 BFD_RELOC_PPC_BA16_BRTAKEN
2748 BFD_RELOC_PPC_BA16_BRNTAKEN
2752 BFD_RELOC_PPC_GLOB_DAT
2754 BFD_RELOC_PPC_JMP_SLOT
2756 BFD_RELOC_PPC_RELATIVE
2758 BFD_RELOC_PPC_LOCAL24PC
2760 BFD_RELOC_PPC_EMB_NADDR32
2762 BFD_RELOC_PPC_EMB_NADDR16
2764 BFD_RELOC_PPC_EMB_NADDR16_LO
2766 BFD_RELOC_PPC_EMB_NADDR16_HI
2768 BFD_RELOC_PPC_EMB_NADDR16_HA
2770 BFD_RELOC_PPC_EMB_SDAI16
2772 BFD_RELOC_PPC_EMB_SDA2I16
2774 BFD_RELOC_PPC_EMB_SDA2REL
2776 BFD_RELOC_PPC_EMB_SDA21
2778 BFD_RELOC_PPC_EMB_MRKREF
2780 BFD_RELOC_PPC_EMB_RELSEC16
2782 BFD_RELOC_PPC_EMB_RELST_LO
2784 BFD_RELOC_PPC_EMB_RELST_HI
2786 BFD_RELOC_PPC_EMB_RELST_HA
2788 BFD_RELOC_PPC_EMB_BIT_FLD
2790 BFD_RELOC_PPC_EMB_RELSDA
2792 BFD_RELOC_PPC_VLE_REL8
2794 BFD_RELOC_PPC_VLE_REL15
2796 BFD_RELOC_PPC_VLE_REL24
2798 BFD_RELOC_PPC_VLE_LO16A
2800 BFD_RELOC_PPC_VLE_LO16D
2802 BFD_RELOC_PPC_VLE_HI16A
2804 BFD_RELOC_PPC_VLE_HI16D
2806 BFD_RELOC_PPC_VLE_HA16A
2808 BFD_RELOC_PPC_VLE_HA16D
2810 BFD_RELOC_PPC_VLE_SDA21
2812 BFD_RELOC_PPC_VLE_SDA21_LO
2814 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2816 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2818 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2820 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2822 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2824 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2826 BFD_RELOC_PPC_16DX_HA
2828 BFD_RELOC_PPC_REL16DX_HA
2830 BFD_RELOC_PPC64_HIGHER
2832 BFD_RELOC_PPC64_HIGHER_S
2834 BFD_RELOC_PPC64_HIGHEST
2836 BFD_RELOC_PPC64_HIGHEST_S
2838 BFD_RELOC_PPC64_TOC16_LO
2840 BFD_RELOC_PPC64_TOC16_HI
2842 BFD_RELOC_PPC64_TOC16_HA
2846 BFD_RELOC_PPC64_PLTGOT16
2848 BFD_RELOC_PPC64_PLTGOT16_LO
2850 BFD_RELOC_PPC64_PLTGOT16_HI
2852 BFD_RELOC_PPC64_PLTGOT16_HA
2854 BFD_RELOC_PPC64_ADDR16_DS
2856 BFD_RELOC_PPC64_ADDR16_LO_DS
2858 BFD_RELOC_PPC64_GOT16_DS
2860 BFD_RELOC_PPC64_GOT16_LO_DS
2862 BFD_RELOC_PPC64_PLT16_LO_DS
2864 BFD_RELOC_PPC64_SECTOFF_DS
2866 BFD_RELOC_PPC64_SECTOFF_LO_DS
2868 BFD_RELOC_PPC64_TOC16_DS
2870 BFD_RELOC_PPC64_TOC16_LO_DS
2872 BFD_RELOC_PPC64_PLTGOT16_DS
2874 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2876 BFD_RELOC_PPC64_ADDR16_HIGH
2878 BFD_RELOC_PPC64_ADDR16_HIGHA
2880 BFD_RELOC_PPC64_REL16_HIGH
2882 BFD_RELOC_PPC64_REL16_HIGHA
2884 BFD_RELOC_PPC64_REL16_HIGHER
2886 BFD_RELOC_PPC64_REL16_HIGHERA
2888 BFD_RELOC_PPC64_REL16_HIGHEST
2890 BFD_RELOC_PPC64_REL16_HIGHESTA
2892 BFD_RELOC_PPC64_ADDR64_LOCAL
2894 BFD_RELOC_PPC64_ENTRY
2896 BFD_RELOC_PPC64_REL24_NOTOC
2900 BFD_RELOC_PPC64_D34_LO
2902 BFD_RELOC_PPC64_D34_HI30
2904 BFD_RELOC_PPC64_D34_HA30
2906 BFD_RELOC_PPC64_PCREL34
2908 BFD_RELOC_PPC64_GOT_PCREL34
2910 BFD_RELOC_PPC64_PLT_PCREL34
2912 BFD_RELOC_PPC64_ADDR16_HIGHER34
2914 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2916 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2918 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2920 BFD_RELOC_PPC64_REL16_HIGHER34
2922 BFD_RELOC_PPC64_REL16_HIGHERA34
2924 BFD_RELOC_PPC64_REL16_HIGHEST34
2926 BFD_RELOC_PPC64_REL16_HIGHESTA34
2930 BFD_RELOC_PPC64_PCREL28
2932 Power(rs6000) and PowerPC relocations.
2941 BFD_RELOC_PPC_DTPMOD
2943 BFD_RELOC_PPC_TPREL16
2945 BFD_RELOC_PPC_TPREL16_LO
2947 BFD_RELOC_PPC_TPREL16_HI
2949 BFD_RELOC_PPC_TPREL16_HA
2953 BFD_RELOC_PPC_DTPREL16
2955 BFD_RELOC_PPC_DTPREL16_LO
2957 BFD_RELOC_PPC_DTPREL16_HI
2959 BFD_RELOC_PPC_DTPREL16_HA
2961 BFD_RELOC_PPC_DTPREL
2963 BFD_RELOC_PPC_GOT_TLSGD16
2965 BFD_RELOC_PPC_GOT_TLSGD16_LO
2967 BFD_RELOC_PPC_GOT_TLSGD16_HI
2969 BFD_RELOC_PPC_GOT_TLSGD16_HA
2971 BFD_RELOC_PPC_GOT_TLSLD16
2973 BFD_RELOC_PPC_GOT_TLSLD16_LO
2975 BFD_RELOC_PPC_GOT_TLSLD16_HI
2977 BFD_RELOC_PPC_GOT_TLSLD16_HA
2979 BFD_RELOC_PPC_GOT_TPREL16
2981 BFD_RELOC_PPC_GOT_TPREL16_LO
2983 BFD_RELOC_PPC_GOT_TPREL16_HI
2985 BFD_RELOC_PPC_GOT_TPREL16_HA
2987 BFD_RELOC_PPC_GOT_DTPREL16
2989 BFD_RELOC_PPC_GOT_DTPREL16_LO
2991 BFD_RELOC_PPC_GOT_DTPREL16_HI
2993 BFD_RELOC_PPC_GOT_DTPREL16_HA
2995 BFD_RELOC_PPC64_TPREL16_DS
2997 BFD_RELOC_PPC64_TPREL16_LO_DS
2999 BFD_RELOC_PPC64_TPREL16_HIGH
3001 BFD_RELOC_PPC64_TPREL16_HIGHA
3003 BFD_RELOC_PPC64_TPREL16_HIGHER
3005 BFD_RELOC_PPC64_TPREL16_HIGHERA
3007 BFD_RELOC_PPC64_TPREL16_HIGHEST
3009 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3011 BFD_RELOC_PPC64_DTPREL16_DS
3013 BFD_RELOC_PPC64_DTPREL16_LO_DS
3015 BFD_RELOC_PPC64_DTPREL16_HIGH
3017 BFD_RELOC_PPC64_DTPREL16_HIGHA
3019 BFD_RELOC_PPC64_DTPREL16_HIGHER
3021 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3023 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3025 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3027 BFD_RELOC_PPC64_TPREL34
3029 BFD_RELOC_PPC64_DTPREL34
3031 BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
3033 BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
3035 BFD_RELOC_PPC64_GOT_TPREL_PCREL34
3037 BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
3039 BFD_RELOC_PPC64_TLS_PCREL
3041 PowerPC and PowerPC64 thread-local storage relocations.
3046 IBM 370/390 relocations
3051 The type of reloc used to build a constructor table - at the moment
3052 probably a 32 bit wide absolute relocation, but the target can choose.
3053 It generally does map to one of the other relocation types.
3056 BFD_RELOC_ARM_PCREL_BRANCH
3058 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3059 not stored in the instruction.
3061 BFD_RELOC_ARM_PCREL_BLX
3063 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3064 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3065 field in the instruction.
3067 BFD_RELOC_THUMB_PCREL_BLX
3069 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3070 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3071 field in the instruction.
3073 BFD_RELOC_ARM_PCREL_CALL
3075 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3077 BFD_RELOC_ARM_PCREL_JUMP
3079 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3082 BFD_RELOC_THUMB_PCREL_BRANCH5
3084 ARM 5-bit pc-relative branch for Branch Future instructions.
3087 BFD_RELOC_THUMB_PCREL_BFCSEL
3089 ARM 6-bit pc-relative branch for BFCSEL instruction.
3092 BFD_RELOC_ARM_THUMB_BF17
3094 ARM 17-bit pc-relative branch for Branch Future instructions.
3097 BFD_RELOC_ARM_THUMB_BF13
3099 ARM 13-bit pc-relative branch for BFCSEL instruction.
3102 BFD_RELOC_ARM_THUMB_BF19
3104 ARM 19-bit pc-relative branch for Branch Future Link instruction.
3107 BFD_RELOC_ARM_THUMB_LOOP12
3109 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
3112 BFD_RELOC_THUMB_PCREL_BRANCH7
3114 BFD_RELOC_THUMB_PCREL_BRANCH9
3116 BFD_RELOC_THUMB_PCREL_BRANCH12
3118 BFD_RELOC_THUMB_PCREL_BRANCH20
3120 BFD_RELOC_THUMB_PCREL_BRANCH23
3122 BFD_RELOC_THUMB_PCREL_BRANCH25
3124 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3125 The lowest bit must be zero and is not stored in the instruction.
3126 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3127 "nn" one smaller in all cases. Note further that BRANCH23
3128 corresponds to R_ARM_THM_CALL.
3131 BFD_RELOC_ARM_OFFSET_IMM
3133 12-bit immediate offset, used in ARM-format ldr and str instructions.
3136 BFD_RELOC_ARM_THUMB_OFFSET
3138 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3141 BFD_RELOC_ARM_TARGET1
3143 Pc-relative or absolute relocation depending on target. Used for
3144 entries in .init_array sections.
3146 BFD_RELOC_ARM_ROSEGREL32
3148 Read-only segment base relative address.
3150 BFD_RELOC_ARM_SBREL32
3152 Data segment base relative address.
3154 BFD_RELOC_ARM_TARGET2
3156 This reloc is used for references to RTTI data from exception handling
3157 tables. The actual definition depends on the target. It may be a
3158 pc-relative or some form of GOT-indirect relocation.
3160 BFD_RELOC_ARM_PREL31
3162 31-bit PC relative address.
3168 BFD_RELOC_ARM_MOVW_PCREL
3170 BFD_RELOC_ARM_MOVT_PCREL
3172 BFD_RELOC_ARM_THUMB_MOVW
3174 BFD_RELOC_ARM_THUMB_MOVT
3176 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3178 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3180 Low and High halfword relocations for MOVW and MOVT instructions.
3183 BFD_RELOC_ARM_GOTFUNCDESC
3185 BFD_RELOC_ARM_GOTOFFFUNCDESC
3187 BFD_RELOC_ARM_FUNCDESC
3189 BFD_RELOC_ARM_FUNCDESC_VALUE
3191 BFD_RELOC_ARM_TLS_GD32_FDPIC
3193 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3195 BFD_RELOC_ARM_TLS_IE32_FDPIC
3197 ARM FDPIC specific relocations.
3200 BFD_RELOC_ARM_JUMP_SLOT
3202 BFD_RELOC_ARM_GLOB_DAT
3208 BFD_RELOC_ARM_RELATIVE
3210 BFD_RELOC_ARM_GOTOFF
3214 BFD_RELOC_ARM_GOT_PREL
3216 Relocations for setting up GOTs and PLTs for shared libraries.
3219 BFD_RELOC_ARM_TLS_GD32
3221 BFD_RELOC_ARM_TLS_LDO32
3223 BFD_RELOC_ARM_TLS_LDM32
3225 BFD_RELOC_ARM_TLS_DTPOFF32
3227 BFD_RELOC_ARM_TLS_DTPMOD32
3229 BFD_RELOC_ARM_TLS_TPOFF32
3231 BFD_RELOC_ARM_TLS_IE32
3233 BFD_RELOC_ARM_TLS_LE32
3235 BFD_RELOC_ARM_TLS_GOTDESC
3237 BFD_RELOC_ARM_TLS_CALL
3239 BFD_RELOC_ARM_THM_TLS_CALL
3241 BFD_RELOC_ARM_TLS_DESCSEQ
3243 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3245 BFD_RELOC_ARM_TLS_DESC
3247 ARM thread-local storage relocations.
3250 BFD_RELOC_ARM_ALU_PC_G0_NC
3252 BFD_RELOC_ARM_ALU_PC_G0
3254 BFD_RELOC_ARM_ALU_PC_G1_NC
3256 BFD_RELOC_ARM_ALU_PC_G1
3258 BFD_RELOC_ARM_ALU_PC_G2
3260 BFD_RELOC_ARM_LDR_PC_G0
3262 BFD_RELOC_ARM_LDR_PC_G1
3264 BFD_RELOC_ARM_LDR_PC_G2
3266 BFD_RELOC_ARM_LDRS_PC_G0
3268 BFD_RELOC_ARM_LDRS_PC_G1
3270 BFD_RELOC_ARM_LDRS_PC_G2
3272 BFD_RELOC_ARM_LDC_PC_G0
3274 BFD_RELOC_ARM_LDC_PC_G1
3276 BFD_RELOC_ARM_LDC_PC_G2
3278 BFD_RELOC_ARM_ALU_SB_G0_NC
3280 BFD_RELOC_ARM_ALU_SB_G0
3282 BFD_RELOC_ARM_ALU_SB_G1_NC
3284 BFD_RELOC_ARM_ALU_SB_G1
3286 BFD_RELOC_ARM_ALU_SB_G2
3288 BFD_RELOC_ARM_LDR_SB_G0
3290 BFD_RELOC_ARM_LDR_SB_G1
3292 BFD_RELOC_ARM_LDR_SB_G2
3294 BFD_RELOC_ARM_LDRS_SB_G0
3296 BFD_RELOC_ARM_LDRS_SB_G1
3298 BFD_RELOC_ARM_LDRS_SB_G2
3300 BFD_RELOC_ARM_LDC_SB_G0
3302 BFD_RELOC_ARM_LDC_SB_G1
3304 BFD_RELOC_ARM_LDC_SB_G2
3306 ARM group relocations.
3311 Annotation of BX instructions.
3314 BFD_RELOC_ARM_IRELATIVE
3316 ARM support for STT_GNU_IFUNC.
3319 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3321 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3323 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3325 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3327 Thumb1 relocations to support execute-only code.
3330 BFD_RELOC_ARM_IMMEDIATE
3332 BFD_RELOC_ARM_ADRL_IMMEDIATE
3334 BFD_RELOC_ARM_T32_IMMEDIATE
3336 BFD_RELOC_ARM_T32_ADD_IMM
3338 BFD_RELOC_ARM_T32_IMM12
3340 BFD_RELOC_ARM_T32_ADD_PC12
3342 BFD_RELOC_ARM_SHIFT_IMM
3352 BFD_RELOC_ARM_CP_OFF_IMM
3354 BFD_RELOC_ARM_CP_OFF_IMM_S2
3356 BFD_RELOC_ARM_T32_CP_OFF_IMM
3358 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3360 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3362 BFD_RELOC_ARM_ADR_IMM
3364 BFD_RELOC_ARM_LDR_IMM
3366 BFD_RELOC_ARM_LITERAL
3368 BFD_RELOC_ARM_IN_POOL
3370 BFD_RELOC_ARM_OFFSET_IMM8
3372 BFD_RELOC_ARM_T32_OFFSET_U8
3374 BFD_RELOC_ARM_T32_OFFSET_IMM
3376 BFD_RELOC_ARM_HWLITERAL
3378 BFD_RELOC_ARM_THUMB_ADD
3380 BFD_RELOC_ARM_THUMB_IMM
3382 BFD_RELOC_ARM_THUMB_SHIFT
3384 These relocs are only used within the ARM assembler. They are not
3385 (at present) written to any object files.
3388 BFD_RELOC_SH_PCDISP8BY2
3390 BFD_RELOC_SH_PCDISP12BY2
3398 BFD_RELOC_SH_DISP12BY2
3400 BFD_RELOC_SH_DISP12BY4
3402 BFD_RELOC_SH_DISP12BY8
3406 BFD_RELOC_SH_DISP20BY8
3410 BFD_RELOC_SH_IMM4BY2
3412 BFD_RELOC_SH_IMM4BY4
3416 BFD_RELOC_SH_IMM8BY2
3418 BFD_RELOC_SH_IMM8BY4
3420 BFD_RELOC_SH_PCRELIMM8BY2
3422 BFD_RELOC_SH_PCRELIMM8BY4
3424 BFD_RELOC_SH_SWITCH16
3426 BFD_RELOC_SH_SWITCH32
3440 BFD_RELOC_SH_LOOP_START
3442 BFD_RELOC_SH_LOOP_END
3446 BFD_RELOC_SH_GLOB_DAT
3448 BFD_RELOC_SH_JMP_SLOT
3450 BFD_RELOC_SH_RELATIVE
3454 BFD_RELOC_SH_GOT_LOW16
3456 BFD_RELOC_SH_GOT_MEDLOW16
3458 BFD_RELOC_SH_GOT_MEDHI16
3460 BFD_RELOC_SH_GOT_HI16
3462 BFD_RELOC_SH_GOTPLT_LOW16
3464 BFD_RELOC_SH_GOTPLT_MEDLOW16
3466 BFD_RELOC_SH_GOTPLT_MEDHI16
3468 BFD_RELOC_SH_GOTPLT_HI16
3470 BFD_RELOC_SH_PLT_LOW16
3472 BFD_RELOC_SH_PLT_MEDLOW16
3474 BFD_RELOC_SH_PLT_MEDHI16
3476 BFD_RELOC_SH_PLT_HI16
3478 BFD_RELOC_SH_GOTOFF_LOW16
3480 BFD_RELOC_SH_GOTOFF_MEDLOW16
3482 BFD_RELOC_SH_GOTOFF_MEDHI16
3484 BFD_RELOC_SH_GOTOFF_HI16
3486 BFD_RELOC_SH_GOTPC_LOW16
3488 BFD_RELOC_SH_GOTPC_MEDLOW16
3490 BFD_RELOC_SH_GOTPC_MEDHI16
3492 BFD_RELOC_SH_GOTPC_HI16
3496 BFD_RELOC_SH_GLOB_DAT64
3498 BFD_RELOC_SH_JMP_SLOT64
3500 BFD_RELOC_SH_RELATIVE64
3502 BFD_RELOC_SH_GOT10BY4
3504 BFD_RELOC_SH_GOT10BY8
3506 BFD_RELOC_SH_GOTPLT10BY4
3508 BFD_RELOC_SH_GOTPLT10BY8
3510 BFD_RELOC_SH_GOTPLT32
3512 BFD_RELOC_SH_SHMEDIA_CODE
3518 BFD_RELOC_SH_IMMS6BY32
3524 BFD_RELOC_SH_IMMS10BY2
3526 BFD_RELOC_SH_IMMS10BY4
3528 BFD_RELOC_SH_IMMS10BY8
3534 BFD_RELOC_SH_IMM_LOW16
3536 BFD_RELOC_SH_IMM_LOW16_PCREL
3538 BFD_RELOC_SH_IMM_MEDLOW16
3540 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3542 BFD_RELOC_SH_IMM_MEDHI16
3544 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3546 BFD_RELOC_SH_IMM_HI16
3548 BFD_RELOC_SH_IMM_HI16_PCREL
3552 BFD_RELOC_SH_TLS_GD_32
3554 BFD_RELOC_SH_TLS_LD_32
3556 BFD_RELOC_SH_TLS_LDO_32
3558 BFD_RELOC_SH_TLS_IE_32
3560 BFD_RELOC_SH_TLS_LE_32
3562 BFD_RELOC_SH_TLS_DTPMOD32
3564 BFD_RELOC_SH_TLS_DTPOFF32
3566 BFD_RELOC_SH_TLS_TPOFF32
3570 BFD_RELOC_SH_GOTOFF20
3572 BFD_RELOC_SH_GOTFUNCDESC
3574 BFD_RELOC_SH_GOTFUNCDESC20
3576 BFD_RELOC_SH_GOTOFFFUNCDESC
3578 BFD_RELOC_SH_GOTOFFFUNCDESC20
3580 BFD_RELOC_SH_FUNCDESC
3582 Renesas / SuperH SH relocs. Not all of these appear in object files.
3605 BFD_RELOC_ARC_SECTOFF
3607 BFD_RELOC_ARC_S21H_PCREL
3609 BFD_RELOC_ARC_S21W_PCREL
3611 BFD_RELOC_ARC_S25H_PCREL
3613 BFD_RELOC_ARC_S25W_PCREL
3617 BFD_RELOC_ARC_SDA_LDST
3619 BFD_RELOC_ARC_SDA_LDST1
3621 BFD_RELOC_ARC_SDA_LDST2
3623 BFD_RELOC_ARC_SDA16_LD
3625 BFD_RELOC_ARC_SDA16_LD1
3627 BFD_RELOC_ARC_SDA16_LD2
3629 BFD_RELOC_ARC_S13_PCREL
3635 BFD_RELOC_ARC_32_ME_S
3637 BFD_RELOC_ARC_N32_ME
3639 BFD_RELOC_ARC_SECTOFF_ME
3641 BFD_RELOC_ARC_SDA32_ME
3645 BFD_RELOC_AC_SECTOFF_U8
3647 BFD_RELOC_AC_SECTOFF_U8_1
3649 BFD_RELOC_AC_SECTOFF_U8_2
3651 BFD_RELOC_AC_SECTOFF_S9
3653 BFD_RELOC_AC_SECTOFF_S9_1
3655 BFD_RELOC_AC_SECTOFF_S9_2
3657 BFD_RELOC_ARC_SECTOFF_ME_1
3659 BFD_RELOC_ARC_SECTOFF_ME_2
3661 BFD_RELOC_ARC_SECTOFF_1
3663 BFD_RELOC_ARC_SECTOFF_2
3665 BFD_RELOC_ARC_SDA_12
3667 BFD_RELOC_ARC_SDA16_ST2
3669 BFD_RELOC_ARC_32_PCREL
3675 BFD_RELOC_ARC_GOTPC32
3681 BFD_RELOC_ARC_GLOB_DAT
3683 BFD_RELOC_ARC_JMP_SLOT
3685 BFD_RELOC_ARC_RELATIVE
3687 BFD_RELOC_ARC_GOTOFF
3691 BFD_RELOC_ARC_S21W_PCREL_PLT
3693 BFD_RELOC_ARC_S25H_PCREL_PLT
3695 BFD_RELOC_ARC_TLS_DTPMOD
3697 BFD_RELOC_ARC_TLS_TPOFF
3699 BFD_RELOC_ARC_TLS_GD_GOT
3701 BFD_RELOC_ARC_TLS_GD_LD
3703 BFD_RELOC_ARC_TLS_GD_CALL
3705 BFD_RELOC_ARC_TLS_IE_GOT
3707 BFD_RELOC_ARC_TLS_DTPOFF
3709 BFD_RELOC_ARC_TLS_DTPOFF_S9
3711 BFD_RELOC_ARC_TLS_LE_S9
3713 BFD_RELOC_ARC_TLS_LE_32
3715 BFD_RELOC_ARC_S25W_PCREL_PLT
3717 BFD_RELOC_ARC_S21H_PCREL_PLT
3719 BFD_RELOC_ARC_NPS_CMEM16
3721 BFD_RELOC_ARC_JLI_SECTOFF
3726 BFD_RELOC_BFIN_16_IMM
3728 ADI Blackfin 16 bit immediate absolute reloc.
3730 BFD_RELOC_BFIN_16_HIGH
3732 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3734 BFD_RELOC_BFIN_4_PCREL
3736 ADI Blackfin 'a' part of LSETUP.
3738 BFD_RELOC_BFIN_5_PCREL
3742 BFD_RELOC_BFIN_16_LOW
3744 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3746 BFD_RELOC_BFIN_10_PCREL
3750 BFD_RELOC_BFIN_11_PCREL
3752 ADI Blackfin 'b' part of LSETUP.
3754 BFD_RELOC_BFIN_12_PCREL_JUMP
3758 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3760 ADI Blackfin Short jump, pcrel.
3762 BFD_RELOC_BFIN_24_PCREL_CALL_X
3764 ADI Blackfin Call.x not implemented.
3766 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3768 ADI Blackfin Long Jump pcrel.
3770 BFD_RELOC_BFIN_GOT17M4
3772 BFD_RELOC_BFIN_GOTHI
3774 BFD_RELOC_BFIN_GOTLO
3776 BFD_RELOC_BFIN_FUNCDESC
3778 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3780 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3782 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3784 BFD_RELOC_BFIN_FUNCDESC_VALUE
3786 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3788 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3790 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3792 BFD_RELOC_BFIN_GOTOFF17M4
3794 BFD_RELOC_BFIN_GOTOFFHI
3796 BFD_RELOC_BFIN_GOTOFFLO
3798 ADI Blackfin FD-PIC relocations.
3802 ADI Blackfin GOT relocation.
3804 BFD_RELOC_BFIN_PLTPC
3806 ADI Blackfin PLTPC relocation.
3808 BFD_ARELOC_BFIN_PUSH
3810 ADI Blackfin arithmetic relocation.
3812 BFD_ARELOC_BFIN_CONST
3814 ADI Blackfin arithmetic relocation.
3818 ADI Blackfin arithmetic relocation.
3822 ADI Blackfin arithmetic relocation.
3824 BFD_ARELOC_BFIN_MULT
3826 ADI Blackfin arithmetic relocation.
3830 ADI Blackfin arithmetic relocation.
3834 ADI Blackfin arithmetic relocation.
3836 BFD_ARELOC_BFIN_LSHIFT
3838 ADI Blackfin arithmetic relocation.
3840 BFD_ARELOC_BFIN_RSHIFT
3842 ADI Blackfin arithmetic relocation.
3846 ADI Blackfin arithmetic relocation.
3850 ADI Blackfin arithmetic relocation.
3854 ADI Blackfin arithmetic relocation.
3856 BFD_ARELOC_BFIN_LAND
3858 ADI Blackfin arithmetic relocation.
3862 ADI Blackfin arithmetic relocation.
3866 ADI Blackfin arithmetic relocation.
3870 ADI Blackfin arithmetic relocation.
3872 BFD_ARELOC_BFIN_COMP
3874 ADI Blackfin arithmetic relocation.
3876 BFD_ARELOC_BFIN_PAGE
3878 ADI Blackfin arithmetic relocation.
3880 BFD_ARELOC_BFIN_HWPAGE
3882 ADI Blackfin arithmetic relocation.
3884 BFD_ARELOC_BFIN_ADDR
3886 ADI Blackfin arithmetic relocation.
3889 BFD_RELOC_D10V_10_PCREL_R
3891 Mitsubishi D10V relocs.
3892 This is a 10-bit reloc with the right 2 bits
3895 BFD_RELOC_D10V_10_PCREL_L
3897 Mitsubishi D10V relocs.
3898 This is a 10-bit reloc with the right 2 bits
3899 assumed to be 0. This is the same as the previous reloc
3900 except it is in the left container, i.e.,
3901 shifted left 15 bits.
3905 This is an 18-bit reloc with the right 2 bits
3908 BFD_RELOC_D10V_18_PCREL
3910 This is an 18-bit reloc with the right 2 bits
3916 Mitsubishi D30V relocs.
3917 This is a 6-bit absolute reloc.
3919 BFD_RELOC_D30V_9_PCREL
3921 This is a 6-bit pc-relative reloc with
3922 the right 3 bits assumed to be 0.
3924 BFD_RELOC_D30V_9_PCREL_R
3926 This is a 6-bit pc-relative reloc with
3927 the right 3 bits assumed to be 0. Same
3928 as the previous reloc but on the right side
3933 This is a 12-bit absolute reloc with the
3934 right 3 bitsassumed to be 0.
3936 BFD_RELOC_D30V_15_PCREL
3938 This is a 12-bit pc-relative reloc with
3939 the right 3 bits assumed to be 0.
3941 BFD_RELOC_D30V_15_PCREL_R
3943 This is a 12-bit pc-relative reloc with
3944 the right 3 bits assumed to be 0. Same
3945 as the previous reloc but on the right side
3950 This is an 18-bit absolute reloc with
3951 the right 3 bits assumed to be 0.
3953 BFD_RELOC_D30V_21_PCREL
3955 This is an 18-bit pc-relative reloc with
3956 the right 3 bits assumed to be 0.
3958 BFD_RELOC_D30V_21_PCREL_R
3960 This is an 18-bit pc-relative reloc with
3961 the right 3 bits assumed to be 0. Same
3962 as the previous reloc but on the right side
3967 This is a 32-bit absolute reloc.
3969 BFD_RELOC_D30V_32_PCREL
3971 This is a 32-bit pc-relative reloc.
3974 BFD_RELOC_DLX_HI16_S
3989 BFD_RELOC_M32C_RL_JUMP
3991 BFD_RELOC_M32C_RL_1ADDR
3993 BFD_RELOC_M32C_RL_2ADDR
3995 Renesas M16C/M32C Relocations.
4000 Renesas M32R (formerly Mitsubishi M32R) relocs.
4001 This is a 24 bit absolute address.
4003 BFD_RELOC_M32R_10_PCREL
4005 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4007 BFD_RELOC_M32R_18_PCREL
4009 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4011 BFD_RELOC_M32R_26_PCREL
4013 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4015 BFD_RELOC_M32R_HI16_ULO
4017 This is a 16-bit reloc containing the high 16 bits of an address
4018 used when the lower 16 bits are treated as unsigned.
4020 BFD_RELOC_M32R_HI16_SLO
4022 This is a 16-bit reloc containing the high 16 bits of an address
4023 used when the lower 16 bits are treated as signed.
4027 This is a 16-bit reloc containing the lower 16 bits of an address.
4029 BFD_RELOC_M32R_SDA16
4031 This is a 16-bit reloc containing the small data area offset for use in
4032 add3, load, and store instructions.
4034 BFD_RELOC_M32R_GOT24
4036 BFD_RELOC_M32R_26_PLTREL
4040 BFD_RELOC_M32R_GLOB_DAT
4042 BFD_RELOC_M32R_JMP_SLOT
4044 BFD_RELOC_M32R_RELATIVE
4046 BFD_RELOC_M32R_GOTOFF
4048 BFD_RELOC_M32R_GOTOFF_HI_ULO
4050 BFD_RELOC_M32R_GOTOFF_HI_SLO
4052 BFD_RELOC_M32R_GOTOFF_LO
4054 BFD_RELOC_M32R_GOTPC24
4056 BFD_RELOC_M32R_GOT16_HI_ULO
4058 BFD_RELOC_M32R_GOT16_HI_SLO
4060 BFD_RELOC_M32R_GOT16_LO
4062 BFD_RELOC_M32R_GOTPC_HI_ULO
4064 BFD_RELOC_M32R_GOTPC_HI_SLO
4066 BFD_RELOC_M32R_GOTPC_LO
4075 This is a 20 bit absolute address.
4077 BFD_RELOC_NDS32_9_PCREL
4079 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4081 BFD_RELOC_NDS32_WORD_9_PCREL
4083 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4085 BFD_RELOC_NDS32_15_PCREL
4087 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4089 BFD_RELOC_NDS32_17_PCREL
4091 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4093 BFD_RELOC_NDS32_25_PCREL
4095 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4097 BFD_RELOC_NDS32_HI20
4099 This is a 20-bit reloc containing the high 20 bits of an address
4100 used with the lower 12 bits
4102 BFD_RELOC_NDS32_LO12S3
4104 This is a 12-bit reloc containing the lower 12 bits of an address
4105 then shift right by 3. This is used with ldi,sdi...
4107 BFD_RELOC_NDS32_LO12S2
4109 This is a 12-bit reloc containing the lower 12 bits of an address
4110 then shift left by 2. This is used with lwi,swi...
4112 BFD_RELOC_NDS32_LO12S1
4114 This is a 12-bit reloc containing the lower 12 bits of an address
4115 then shift left by 1. This is used with lhi,shi...
4117 BFD_RELOC_NDS32_LO12S0
4119 This is a 12-bit reloc containing the lower 12 bits of an address
4120 then shift left by 0. This is used with lbisbi...
4122 BFD_RELOC_NDS32_LO12S0_ORI
4124 This is a 12-bit reloc containing the lower 12 bits of an address
4125 then shift left by 0. This is only used with branch relaxations
4127 BFD_RELOC_NDS32_SDA15S3
4129 This is a 15-bit reloc containing the small data area 18-bit signed offset
4130 and shift left by 3 for use in ldi, sdi...
4132 BFD_RELOC_NDS32_SDA15S2
4134 This is a 15-bit reloc containing the small data area 17-bit signed offset
4135 and shift left by 2 for use in lwi, swi...
4137 BFD_RELOC_NDS32_SDA15S1
4139 This is a 15-bit reloc containing the small data area 16-bit signed offset
4140 and shift left by 1 for use in lhi, shi...
4142 BFD_RELOC_NDS32_SDA15S0
4144 This is a 15-bit reloc containing the small data area 15-bit signed offset
4145 and shift left by 0 for use in lbi, sbi...
4147 BFD_RELOC_NDS32_SDA16S3
4149 This is a 16-bit reloc containing the small data area 16-bit signed offset
4152 BFD_RELOC_NDS32_SDA17S2
4154 This is a 17-bit reloc containing the small data area 17-bit signed offset
4155 and shift left by 2 for use in lwi.gp, swi.gp...
4157 BFD_RELOC_NDS32_SDA18S1
4159 This is a 18-bit reloc containing the small data area 18-bit signed offset
4160 and shift left by 1 for use in lhi.gp, shi.gp...
4162 BFD_RELOC_NDS32_SDA19S0
4164 This is a 19-bit reloc containing the small data area 19-bit signed offset
4165 and shift left by 0 for use in lbi.gp, sbi.gp...
4167 BFD_RELOC_NDS32_GOT20
4169 BFD_RELOC_NDS32_9_PLTREL
4171 BFD_RELOC_NDS32_25_PLTREL
4173 BFD_RELOC_NDS32_COPY
4175 BFD_RELOC_NDS32_GLOB_DAT
4177 BFD_RELOC_NDS32_JMP_SLOT
4179 BFD_RELOC_NDS32_RELATIVE
4181 BFD_RELOC_NDS32_GOTOFF
4183 BFD_RELOC_NDS32_GOTOFF_HI20
4185 BFD_RELOC_NDS32_GOTOFF_LO12
4187 BFD_RELOC_NDS32_GOTPC20
4189 BFD_RELOC_NDS32_GOT_HI20
4191 BFD_RELOC_NDS32_GOT_LO12
4193 BFD_RELOC_NDS32_GOTPC_HI20
4195 BFD_RELOC_NDS32_GOTPC_LO12
4199 BFD_RELOC_NDS32_INSN16
4201 BFD_RELOC_NDS32_LABEL
4203 BFD_RELOC_NDS32_LONGCALL1
4205 BFD_RELOC_NDS32_LONGCALL2
4207 BFD_RELOC_NDS32_LONGCALL3
4209 BFD_RELOC_NDS32_LONGJUMP1
4211 BFD_RELOC_NDS32_LONGJUMP2
4213 BFD_RELOC_NDS32_LONGJUMP3
4215 BFD_RELOC_NDS32_LOADSTORE
4217 BFD_RELOC_NDS32_9_FIXED
4219 BFD_RELOC_NDS32_15_FIXED
4221 BFD_RELOC_NDS32_17_FIXED
4223 BFD_RELOC_NDS32_25_FIXED
4225 BFD_RELOC_NDS32_LONGCALL4
4227 BFD_RELOC_NDS32_LONGCALL5
4229 BFD_RELOC_NDS32_LONGCALL6
4231 BFD_RELOC_NDS32_LONGJUMP4
4233 BFD_RELOC_NDS32_LONGJUMP5
4235 BFD_RELOC_NDS32_LONGJUMP6
4237 BFD_RELOC_NDS32_LONGJUMP7
4241 BFD_RELOC_NDS32_PLTREL_HI20
4243 BFD_RELOC_NDS32_PLTREL_LO12
4245 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4247 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4251 BFD_RELOC_NDS32_SDA12S2_DP
4253 BFD_RELOC_NDS32_SDA12S2_SP
4255 BFD_RELOC_NDS32_LO12S2_DP
4257 BFD_RELOC_NDS32_LO12S2_SP
4261 BFD_RELOC_NDS32_DWARF2_OP1
4263 BFD_RELOC_NDS32_DWARF2_OP2
4265 BFD_RELOC_NDS32_DWARF2_LEB
4267 for dwarf2 debug_line.
4269 BFD_RELOC_NDS32_UPDATE_TA
4271 for eliminate 16-bit instructions
4273 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4275 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4277 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4279 BFD_RELOC_NDS32_GOT_LO15
4281 BFD_RELOC_NDS32_GOT_LO19
4283 BFD_RELOC_NDS32_GOTOFF_LO15
4285 BFD_RELOC_NDS32_GOTOFF_LO19
4287 BFD_RELOC_NDS32_GOT15S2
4289 BFD_RELOC_NDS32_GOT17S2
4291 for PIC object relaxation
4296 This is a 5 bit absolute address.
4298 BFD_RELOC_NDS32_10_UPCREL
4300 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4302 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4304 If fp were omitted, fp can used as another gp.
4306 BFD_RELOC_NDS32_RELAX_ENTRY
4308 BFD_RELOC_NDS32_GOT_SUFF
4310 BFD_RELOC_NDS32_GOTOFF_SUFF
4312 BFD_RELOC_NDS32_PLT_GOT_SUFF
4314 BFD_RELOC_NDS32_MULCALL_SUFF
4318 BFD_RELOC_NDS32_PTR_COUNT
4320 BFD_RELOC_NDS32_PTR_RESOLVED
4322 BFD_RELOC_NDS32_PLTBLOCK
4324 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4326 BFD_RELOC_NDS32_RELAX_REGION_END
4328 BFD_RELOC_NDS32_MINUEND
4330 BFD_RELOC_NDS32_SUBTRAHEND
4332 BFD_RELOC_NDS32_DIFF8
4334 BFD_RELOC_NDS32_DIFF16
4336 BFD_RELOC_NDS32_DIFF32
4338 BFD_RELOC_NDS32_DIFF_ULEB128
4340 BFD_RELOC_NDS32_EMPTY
4342 relaxation relative relocation types
4344 BFD_RELOC_NDS32_25_ABS
4346 This is a 25 bit absolute address.
4348 BFD_RELOC_NDS32_DATA
4350 BFD_RELOC_NDS32_TRAN
4352 BFD_RELOC_NDS32_17IFC_PCREL
4354 BFD_RELOC_NDS32_10IFCU_PCREL
4356 For ex9 and ifc using.
4358 BFD_RELOC_NDS32_TPOFF
4360 BFD_RELOC_NDS32_GOTTPOFF
4362 BFD_RELOC_NDS32_TLS_LE_HI20
4364 BFD_RELOC_NDS32_TLS_LE_LO12
4366 BFD_RELOC_NDS32_TLS_LE_20
4368 BFD_RELOC_NDS32_TLS_LE_15S0
4370 BFD_RELOC_NDS32_TLS_LE_15S1
4372 BFD_RELOC_NDS32_TLS_LE_15S2
4374 BFD_RELOC_NDS32_TLS_LE_ADD
4376 BFD_RELOC_NDS32_TLS_LE_LS
4378 BFD_RELOC_NDS32_TLS_IE_HI20
4380 BFD_RELOC_NDS32_TLS_IE_LO12
4382 BFD_RELOC_NDS32_TLS_IE_LO12S2
4384 BFD_RELOC_NDS32_TLS_IEGP_HI20
4386 BFD_RELOC_NDS32_TLS_IEGP_LO12
4388 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4390 BFD_RELOC_NDS32_TLS_IEGP_LW
4392 BFD_RELOC_NDS32_TLS_DESC
4394 BFD_RELOC_NDS32_TLS_DESC_HI20
4396 BFD_RELOC_NDS32_TLS_DESC_LO12
4398 BFD_RELOC_NDS32_TLS_DESC_20
4400 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4402 BFD_RELOC_NDS32_TLS_DESC_ADD
4404 BFD_RELOC_NDS32_TLS_DESC_FUNC
4406 BFD_RELOC_NDS32_TLS_DESC_CALL
4408 BFD_RELOC_NDS32_TLS_DESC_MEM
4410 BFD_RELOC_NDS32_REMOVE
4412 BFD_RELOC_NDS32_GROUP
4418 For floating load store relaxation.
4422 BFD_RELOC_V850_9_PCREL
4424 This is a 9-bit reloc
4426 BFD_RELOC_V850_22_PCREL
4428 This is a 22-bit reloc
4431 BFD_RELOC_V850_SDA_16_16_OFFSET
4433 This is a 16 bit offset from the short data area pointer.
4435 BFD_RELOC_V850_SDA_15_16_OFFSET
4437 This is a 16 bit offset (of which only 15 bits are used) from the
4438 short data area pointer.
4440 BFD_RELOC_V850_ZDA_16_16_OFFSET
4442 This is a 16 bit offset from the zero data area pointer.
4444 BFD_RELOC_V850_ZDA_15_16_OFFSET
4446 This is a 16 bit offset (of which only 15 bits are used) from the
4447 zero data area pointer.
4449 BFD_RELOC_V850_TDA_6_8_OFFSET
4451 This is an 8 bit offset (of which only 6 bits are used) from the
4452 tiny data area pointer.
4454 BFD_RELOC_V850_TDA_7_8_OFFSET
4456 This is an 8bit offset (of which only 7 bits are used) from the tiny
4459 BFD_RELOC_V850_TDA_7_7_OFFSET
4461 This is a 7 bit offset from the tiny data area pointer.
4463 BFD_RELOC_V850_TDA_16_16_OFFSET
4465 This is a 16 bit offset from the tiny data area pointer.
4468 BFD_RELOC_V850_TDA_4_5_OFFSET
4470 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4473 BFD_RELOC_V850_TDA_4_4_OFFSET
4475 This is a 4 bit offset from the tiny data area pointer.
4477 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4479 This is a 16 bit offset from the short data area pointer, with the
4480 bits placed non-contiguously in the instruction.
4482 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4484 This is a 16 bit offset from the zero data area pointer, with the
4485 bits placed non-contiguously in the instruction.
4487 BFD_RELOC_V850_CALLT_6_7_OFFSET
4489 This is a 6 bit offset from the call table base pointer.
4491 BFD_RELOC_V850_CALLT_16_16_OFFSET
4493 This is a 16 bit offset from the call table base pointer.
4495 BFD_RELOC_V850_LONGCALL
4497 Used for relaxing indirect function calls.
4499 BFD_RELOC_V850_LONGJUMP
4501 Used for relaxing indirect jumps.
4503 BFD_RELOC_V850_ALIGN
4505 Used to maintain alignment whilst relaxing.
4507 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4509 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4512 BFD_RELOC_V850_16_PCREL
4514 This is a 16-bit reloc.
4516 BFD_RELOC_V850_17_PCREL
4518 This is a 17-bit reloc.
4522 This is a 23-bit reloc.
4524 BFD_RELOC_V850_32_PCREL
4526 This is a 32-bit reloc.
4528 BFD_RELOC_V850_32_ABS
4530 This is a 32-bit reloc.
4532 BFD_RELOC_V850_16_SPLIT_OFFSET
4534 This is a 16-bit reloc.
4536 BFD_RELOC_V850_16_S1
4538 This is a 16-bit reloc.
4540 BFD_RELOC_V850_LO16_S1
4542 Low 16 bits. 16 bit shifted by 1.
4544 BFD_RELOC_V850_CALLT_15_16_OFFSET
4546 This is a 16 bit offset from the call table base pointer.
4548 BFD_RELOC_V850_32_GOTPCREL
4552 BFD_RELOC_V850_16_GOT
4556 BFD_RELOC_V850_32_GOT
4560 BFD_RELOC_V850_22_PLT_PCREL
4564 BFD_RELOC_V850_32_PLT_PCREL
4572 BFD_RELOC_V850_GLOB_DAT
4576 BFD_RELOC_V850_JMP_SLOT
4580 BFD_RELOC_V850_RELATIVE
4584 BFD_RELOC_V850_16_GOTOFF
4588 BFD_RELOC_V850_32_GOTOFF
4603 This is a 8bit DP reloc for the tms320c30, where the most
4604 significant 8 bits of a 24 bit word are placed into the least
4605 significant 8 bits of the opcode.
4608 BFD_RELOC_TIC54X_PARTLS7
4610 This is a 7bit reloc for the tms320c54x, where the least
4611 significant 7 bits of a 16 bit word are placed into the least
4612 significant 7 bits of the opcode.
4615 BFD_RELOC_TIC54X_PARTMS9
4617 This is a 9bit DP reloc for the tms320c54x, where the most
4618 significant 9 bits of a 16 bit word are placed into the least
4619 significant 9 bits of the opcode.
4624 This is an extended address 23-bit reloc for the tms320c54x.
4627 BFD_RELOC_TIC54X_16_OF_23
4629 This is a 16-bit reloc for the tms320c54x, where the least
4630 significant 16 bits of a 23-bit extended address are placed into
4634 BFD_RELOC_TIC54X_MS7_OF_23
4636 This is a reloc for the tms320c54x, where the most
4637 significant 7 bits of a 23-bit extended address are placed into
4641 BFD_RELOC_C6000_PCR_S21
4643 BFD_RELOC_C6000_PCR_S12
4645 BFD_RELOC_C6000_PCR_S10
4647 BFD_RELOC_C6000_PCR_S7
4649 BFD_RELOC_C6000_ABS_S16
4651 BFD_RELOC_C6000_ABS_L16
4653 BFD_RELOC_C6000_ABS_H16
4655 BFD_RELOC_C6000_SBR_U15_B
4657 BFD_RELOC_C6000_SBR_U15_H
4659 BFD_RELOC_C6000_SBR_U15_W
4661 BFD_RELOC_C6000_SBR_S16
4663 BFD_RELOC_C6000_SBR_L16_B
4665 BFD_RELOC_C6000_SBR_L16_H
4667 BFD_RELOC_C6000_SBR_L16_W
4669 BFD_RELOC_C6000_SBR_H16_B
4671 BFD_RELOC_C6000_SBR_H16_H
4673 BFD_RELOC_C6000_SBR_H16_W
4675 BFD_RELOC_C6000_SBR_GOT_U15_W
4677 BFD_RELOC_C6000_SBR_GOT_L16_W
4679 BFD_RELOC_C6000_SBR_GOT_H16_W
4681 BFD_RELOC_C6000_DSBT_INDEX
4683 BFD_RELOC_C6000_PREL31
4685 BFD_RELOC_C6000_COPY
4687 BFD_RELOC_C6000_JUMP_SLOT
4689 BFD_RELOC_C6000_EHTYPE
4691 BFD_RELOC_C6000_PCR_H16
4693 BFD_RELOC_C6000_PCR_L16
4695 BFD_RELOC_C6000_ALIGN
4697 BFD_RELOC_C6000_FPHEAD
4699 BFD_RELOC_C6000_NOCMP
4701 TMS320C6000 relocations.
4706 This is a 48 bit reloc for the FR30 that stores 32 bits.
4710 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4713 BFD_RELOC_FR30_6_IN_4
4715 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4718 BFD_RELOC_FR30_8_IN_8
4720 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4723 BFD_RELOC_FR30_9_IN_8
4725 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4728 BFD_RELOC_FR30_10_IN_8
4730 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4733 BFD_RELOC_FR30_9_PCREL
4735 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4736 short offset into 8 bits.
4738 BFD_RELOC_FR30_12_PCREL
4740 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4741 short offset into 11 bits.
4744 BFD_RELOC_MCORE_PCREL_IMM8BY4
4746 BFD_RELOC_MCORE_PCREL_IMM11BY2
4748 BFD_RELOC_MCORE_PCREL_IMM4BY2
4750 BFD_RELOC_MCORE_PCREL_32
4752 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4756 Motorola Mcore relocations.
4765 BFD_RELOC_MEP_PCREL8A2
4767 BFD_RELOC_MEP_PCREL12A2
4769 BFD_RELOC_MEP_PCREL17A2
4771 BFD_RELOC_MEP_PCREL24A2
4773 BFD_RELOC_MEP_PCABS24A2
4785 BFD_RELOC_MEP_TPREL7
4787 BFD_RELOC_MEP_TPREL7A2
4789 BFD_RELOC_MEP_TPREL7A4
4791 BFD_RELOC_MEP_UIMM24
4793 BFD_RELOC_MEP_ADDR24A4
4795 BFD_RELOC_MEP_GNU_VTINHERIT
4797 BFD_RELOC_MEP_GNU_VTENTRY
4799 Toshiba Media Processor Relocations.
4803 BFD_RELOC_METAG_HIADDR16
4805 BFD_RELOC_METAG_LOADDR16
4807 BFD_RELOC_METAG_RELBRANCH
4809 BFD_RELOC_METAG_GETSETOFF
4811 BFD_RELOC_METAG_HIOG
4813 BFD_RELOC_METAG_LOOG
4815 BFD_RELOC_METAG_REL8
4817 BFD_RELOC_METAG_REL16
4819 BFD_RELOC_METAG_HI16_GOTOFF
4821 BFD_RELOC_METAG_LO16_GOTOFF
4823 BFD_RELOC_METAG_GETSET_GOTOFF
4825 BFD_RELOC_METAG_GETSET_GOT
4827 BFD_RELOC_METAG_HI16_GOTPC
4829 BFD_RELOC_METAG_LO16_GOTPC
4831 BFD_RELOC_METAG_HI16_PLT
4833 BFD_RELOC_METAG_LO16_PLT
4835 BFD_RELOC_METAG_RELBRANCH_PLT
4837 BFD_RELOC_METAG_GOTOFF
4841 BFD_RELOC_METAG_COPY
4843 BFD_RELOC_METAG_JMP_SLOT
4845 BFD_RELOC_METAG_RELATIVE
4847 BFD_RELOC_METAG_GLOB_DAT
4849 BFD_RELOC_METAG_TLS_GD
4851 BFD_RELOC_METAG_TLS_LDM
4853 BFD_RELOC_METAG_TLS_LDO_HI16
4855 BFD_RELOC_METAG_TLS_LDO_LO16
4857 BFD_RELOC_METAG_TLS_LDO
4859 BFD_RELOC_METAG_TLS_IE
4861 BFD_RELOC_METAG_TLS_IENONPIC
4863 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4865 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4867 BFD_RELOC_METAG_TLS_TPOFF
4869 BFD_RELOC_METAG_TLS_DTPMOD
4871 BFD_RELOC_METAG_TLS_DTPOFF
4873 BFD_RELOC_METAG_TLS_LE
4875 BFD_RELOC_METAG_TLS_LE_HI16
4877 BFD_RELOC_METAG_TLS_LE_LO16
4879 Imagination Technologies Meta relocations.
4884 BFD_RELOC_MMIX_GETA_1
4886 BFD_RELOC_MMIX_GETA_2
4888 BFD_RELOC_MMIX_GETA_3
4890 These are relocations for the GETA instruction.
4892 BFD_RELOC_MMIX_CBRANCH
4894 BFD_RELOC_MMIX_CBRANCH_J
4896 BFD_RELOC_MMIX_CBRANCH_1
4898 BFD_RELOC_MMIX_CBRANCH_2
4900 BFD_RELOC_MMIX_CBRANCH_3
4902 These are relocations for a conditional branch instruction.
4904 BFD_RELOC_MMIX_PUSHJ
4906 BFD_RELOC_MMIX_PUSHJ_1
4908 BFD_RELOC_MMIX_PUSHJ_2
4910 BFD_RELOC_MMIX_PUSHJ_3
4912 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4914 These are relocations for the PUSHJ instruction.
4918 BFD_RELOC_MMIX_JMP_1
4920 BFD_RELOC_MMIX_JMP_2
4922 BFD_RELOC_MMIX_JMP_3
4924 These are relocations for the JMP instruction.
4926 BFD_RELOC_MMIX_ADDR19
4928 This is a relocation for a relative address as in a GETA instruction or
4931 BFD_RELOC_MMIX_ADDR27
4933 This is a relocation for a relative address as in a JMP instruction.
4935 BFD_RELOC_MMIX_REG_OR_BYTE
4937 This is a relocation for an instruction field that may be a general
4938 register or a value 0..255.
4942 This is a relocation for an instruction field that may be a general
4945 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4947 This is a relocation for two instruction fields holding a register and
4948 an offset, the equivalent of the relocation.
4950 BFD_RELOC_MMIX_LOCAL
4952 This relocation is an assertion that the expression is not allocated as
4953 a global register. It does not modify contents.
4956 BFD_RELOC_AVR_7_PCREL
4958 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4959 short offset into 7 bits.
4961 BFD_RELOC_AVR_13_PCREL
4963 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4964 short offset into 12 bits.
4968 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4969 program memory address) into 16 bits.
4971 BFD_RELOC_AVR_LO8_LDI
4973 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4974 data memory address) into 8 bit immediate value of LDI insn.
4976 BFD_RELOC_AVR_HI8_LDI
4978 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4979 of data memory address) into 8 bit immediate value of LDI insn.
4981 BFD_RELOC_AVR_HH8_LDI
4983 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4984 of program memory address) into 8 bit immediate value of LDI insn.
4986 BFD_RELOC_AVR_MS8_LDI
4988 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4989 of 32 bit value) into 8 bit immediate value of LDI insn.
4991 BFD_RELOC_AVR_LO8_LDI_NEG
4993 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4994 (usually data memory address) into 8 bit immediate value of SUBI insn.
4996 BFD_RELOC_AVR_HI8_LDI_NEG
4998 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4999 (high 8 bit of data memory address) into 8 bit immediate value of
5002 BFD_RELOC_AVR_HH8_LDI_NEG
5004 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5005 (most high 8 bit of program memory address) into 8 bit immediate value
5006 of LDI or SUBI insn.
5008 BFD_RELOC_AVR_MS8_LDI_NEG
5010 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
5011 of 32 bit value) into 8 bit immediate value of LDI insn.
5013 BFD_RELOC_AVR_LO8_LDI_PM
5015 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5016 command address) into 8 bit immediate value of LDI insn.
5018 BFD_RELOC_AVR_LO8_LDI_GS
5020 This is a 16 bit reloc for the AVR that stores 8 bit value
5021 (command address) into 8 bit immediate value of LDI insn. If the address
5022 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5025 BFD_RELOC_AVR_HI8_LDI_PM
5027 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5028 of command address) into 8 bit immediate value of LDI insn.
5030 BFD_RELOC_AVR_HI8_LDI_GS
5032 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5033 of command address) into 8 bit immediate value of LDI insn. If the address
5034 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5037 BFD_RELOC_AVR_HH8_LDI_PM
5039 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5040 of command address) into 8 bit immediate value of LDI insn.
5042 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5044 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5045 (usually command address) into 8 bit immediate value of SUBI insn.
5047 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5049 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5050 (high 8 bit of 16 bit command address) into 8 bit immediate value
5053 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5055 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5056 (high 6 bit of 22 bit command address) into 8 bit immediate
5061 This is a 32 bit reloc for the AVR that stores 23 bit value
5066 This is a 16 bit reloc for the AVR that stores all needed bits
5067 for absolute addressing with ldi with overflow check to linktime
5071 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5074 BFD_RELOC_AVR_6_ADIW
5076 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5081 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5082 in .byte lo8(symbol)
5086 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5087 in .byte hi8(symbol)
5091 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5092 in .byte hlo8(symbol)
5096 BFD_RELOC_AVR_DIFF16
5098 BFD_RELOC_AVR_DIFF32
5100 AVR relocations to mark the difference of two local symbols.
5101 These are only needed to support linker relaxation and can be ignored
5102 when not relaxing. The field is set to the value of the difference
5103 assuming no relaxation. The relocation encodes the position of the
5104 second symbol so the linker can determine whether to adjust the field
5107 BFD_RELOC_AVR_LDS_STS_16
5109 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5110 lds and sts instructions supported only tiny core.
5114 This is a 6 bit reloc for the AVR that stores an I/O register
5115 number for the IN and OUT instructions
5119 This is a 5 bit reloc for the AVR that stores an I/O register
5120 number for the SBIC, SBIS, SBI and CBI instructions
5123 BFD_RELOC_RISCV_HI20
5125 BFD_RELOC_RISCV_PCREL_HI20
5127 BFD_RELOC_RISCV_PCREL_LO12_I
5129 BFD_RELOC_RISCV_PCREL_LO12_S
5131 BFD_RELOC_RISCV_LO12_I
5133 BFD_RELOC_RISCV_LO12_S
5135 BFD_RELOC_RISCV_GPREL12_I
5137 BFD_RELOC_RISCV_GPREL12_S
5139 BFD_RELOC_RISCV_TPREL_HI20
5141 BFD_RELOC_RISCV_TPREL_LO12_I
5143 BFD_RELOC_RISCV_TPREL_LO12_S
5145 BFD_RELOC_RISCV_TPREL_ADD
5147 BFD_RELOC_RISCV_CALL
5149 BFD_RELOC_RISCV_CALL_PLT
5151 BFD_RELOC_RISCV_ADD8
5153 BFD_RELOC_RISCV_ADD16
5155 BFD_RELOC_RISCV_ADD32
5157 BFD_RELOC_RISCV_ADD64
5159 BFD_RELOC_RISCV_SUB8
5161 BFD_RELOC_RISCV_SUB16
5163 BFD_RELOC_RISCV_SUB32
5165 BFD_RELOC_RISCV_SUB64
5167 BFD_RELOC_RISCV_GOT_HI20
5169 BFD_RELOC_RISCV_TLS_GOT_HI20
5171 BFD_RELOC_RISCV_TLS_GD_HI20
5175 BFD_RELOC_RISCV_TLS_DTPMOD32
5177 BFD_RELOC_RISCV_TLS_DTPREL32
5179 BFD_RELOC_RISCV_TLS_DTPMOD64
5181 BFD_RELOC_RISCV_TLS_DTPREL64
5183 BFD_RELOC_RISCV_TLS_TPREL32
5185 BFD_RELOC_RISCV_TLS_TPREL64
5187 BFD_RELOC_RISCV_ALIGN
5189 BFD_RELOC_RISCV_RVC_BRANCH
5191 BFD_RELOC_RISCV_RVC_JUMP
5193 BFD_RELOC_RISCV_RVC_LUI
5195 BFD_RELOC_RISCV_GPREL_I
5197 BFD_RELOC_RISCV_GPREL_S
5199 BFD_RELOC_RISCV_TPREL_I
5201 BFD_RELOC_RISCV_TPREL_S
5203 BFD_RELOC_RISCV_RELAX
5207 BFD_RELOC_RISCV_SUB6
5209 BFD_RELOC_RISCV_SET6
5211 BFD_RELOC_RISCV_SET8
5213 BFD_RELOC_RISCV_SET16
5215 BFD_RELOC_RISCV_SET32
5217 BFD_RELOC_RISCV_32_PCREL
5224 BFD_RELOC_RL78_NEG16
5226 BFD_RELOC_RL78_NEG24
5228 BFD_RELOC_RL78_NEG32
5230 BFD_RELOC_RL78_16_OP
5232 BFD_RELOC_RL78_24_OP
5234 BFD_RELOC_RL78_32_OP
5242 BFD_RELOC_RL78_DIR3U_PCREL
5246 BFD_RELOC_RL78_GPRELB
5248 BFD_RELOC_RL78_GPRELW
5250 BFD_RELOC_RL78_GPRELL
5254 BFD_RELOC_RL78_OP_SUBTRACT
5256 BFD_RELOC_RL78_OP_NEG
5258 BFD_RELOC_RL78_OP_AND
5260 BFD_RELOC_RL78_OP_SHRA
5264 BFD_RELOC_RL78_ABS16
5266 BFD_RELOC_RL78_ABS16_REV
5268 BFD_RELOC_RL78_ABS32
5270 BFD_RELOC_RL78_ABS32_REV
5272 BFD_RELOC_RL78_ABS16U
5274 BFD_RELOC_RL78_ABS16UW
5276 BFD_RELOC_RL78_ABS16UL
5278 BFD_RELOC_RL78_RELAX
5288 BFD_RELOC_RL78_SADDR
5290 Renesas RL78 Relocations.
5313 BFD_RELOC_RX_DIR3U_PCREL
5325 BFD_RELOC_RX_OP_SUBTRACT
5333 BFD_RELOC_RX_ABS16_REV
5337 BFD_RELOC_RX_ABS32_REV
5341 BFD_RELOC_RX_ABS16UW
5343 BFD_RELOC_RX_ABS16UL
5347 Renesas RX Relocations.
5360 32 bit PC relative PLT address.
5364 Copy symbol at runtime.
5366 BFD_RELOC_390_GLOB_DAT
5370 BFD_RELOC_390_JMP_SLOT
5374 BFD_RELOC_390_RELATIVE
5376 Adjust by program base.
5380 32 bit PC relative offset to GOT.
5386 BFD_RELOC_390_PC12DBL
5388 PC relative 12 bit shifted by 1.
5390 BFD_RELOC_390_PLT12DBL
5392 12 bit PC rel. PLT shifted by 1.
5394 BFD_RELOC_390_PC16DBL
5396 PC relative 16 bit shifted by 1.
5398 BFD_RELOC_390_PLT16DBL
5400 16 bit PC rel. PLT shifted by 1.
5402 BFD_RELOC_390_PC24DBL
5404 PC relative 24 bit shifted by 1.
5406 BFD_RELOC_390_PLT24DBL
5408 24 bit PC rel. PLT shifted by 1.
5410 BFD_RELOC_390_PC32DBL
5412 PC relative 32 bit shifted by 1.
5414 BFD_RELOC_390_PLT32DBL
5416 32 bit PC rel. PLT shifted by 1.
5418 BFD_RELOC_390_GOTPCDBL
5420 32 bit PC rel. GOT shifted by 1.
5428 64 bit PC relative PLT address.
5430 BFD_RELOC_390_GOTENT
5432 32 bit rel. offset to GOT entry.
5434 BFD_RELOC_390_GOTOFF64
5436 64 bit offset to GOT.
5438 BFD_RELOC_390_GOTPLT12
5440 12-bit offset to symbol-entry within GOT, with PLT handling.
5442 BFD_RELOC_390_GOTPLT16
5444 16-bit offset to symbol-entry within GOT, with PLT handling.
5446 BFD_RELOC_390_GOTPLT32
5448 32-bit offset to symbol-entry within GOT, with PLT handling.
5450 BFD_RELOC_390_GOTPLT64
5452 64-bit offset to symbol-entry within GOT, with PLT handling.
5454 BFD_RELOC_390_GOTPLTENT
5456 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5458 BFD_RELOC_390_PLTOFF16
5460 16-bit rel. offset from the GOT to a PLT entry.
5462 BFD_RELOC_390_PLTOFF32
5464 32-bit rel. offset from the GOT to a PLT entry.
5466 BFD_RELOC_390_PLTOFF64
5468 64-bit rel. offset from the GOT to a PLT entry.
5471 BFD_RELOC_390_TLS_LOAD
5473 BFD_RELOC_390_TLS_GDCALL
5475 BFD_RELOC_390_TLS_LDCALL
5477 BFD_RELOC_390_TLS_GD32
5479 BFD_RELOC_390_TLS_GD64
5481 BFD_RELOC_390_TLS_GOTIE12
5483 BFD_RELOC_390_TLS_GOTIE32
5485 BFD_RELOC_390_TLS_GOTIE64
5487 BFD_RELOC_390_TLS_LDM32
5489 BFD_RELOC_390_TLS_LDM64
5491 BFD_RELOC_390_TLS_IE32
5493 BFD_RELOC_390_TLS_IE64
5495 BFD_RELOC_390_TLS_IEENT
5497 BFD_RELOC_390_TLS_LE32
5499 BFD_RELOC_390_TLS_LE64
5501 BFD_RELOC_390_TLS_LDO32
5503 BFD_RELOC_390_TLS_LDO64
5505 BFD_RELOC_390_TLS_DTPMOD
5507 BFD_RELOC_390_TLS_DTPOFF
5509 BFD_RELOC_390_TLS_TPOFF
5511 s390 tls relocations.
5518 BFD_RELOC_390_GOTPLT20
5520 BFD_RELOC_390_TLS_GOTIE20
5522 Long displacement extension.
5525 BFD_RELOC_390_IRELATIVE
5527 STT_GNU_IFUNC relocation.
5530 BFD_RELOC_SCORE_GPREL15
5533 Low 16 bit for load/store
5535 BFD_RELOC_SCORE_DUMMY2
5539 This is a 24-bit reloc with the right 1 bit assumed to be 0
5541 BFD_RELOC_SCORE_BRANCH
5543 This is a 19-bit reloc with the right 1 bit assumed to be 0
5545 BFD_RELOC_SCORE_IMM30
5547 This is a 32-bit reloc for 48-bit instructions.
5549 BFD_RELOC_SCORE_IMM32
5551 This is a 32-bit reloc for 48-bit instructions.
5553 BFD_RELOC_SCORE16_JMP
5555 This is a 11-bit reloc with the right 1 bit assumed to be 0
5557 BFD_RELOC_SCORE16_BRANCH
5559 This is a 8-bit reloc with the right 1 bit assumed to be 0
5561 BFD_RELOC_SCORE_BCMP
5563 This is a 9-bit reloc with the right 1 bit assumed to be 0
5565 BFD_RELOC_SCORE_GOT15
5567 BFD_RELOC_SCORE_GOT_LO16
5569 BFD_RELOC_SCORE_CALL15
5571 BFD_RELOC_SCORE_DUMMY_HI16
5573 Undocumented Score relocs
5578 Scenix IP2K - 9-bit register number / data address
5582 Scenix IP2K - 4-bit register/data bank number
5584 BFD_RELOC_IP2K_ADDR16CJP
5586 Scenix IP2K - low 13 bits of instruction word address
5588 BFD_RELOC_IP2K_PAGE3
5590 Scenix IP2K - high 3 bits of instruction word address
5592 BFD_RELOC_IP2K_LO8DATA
5594 BFD_RELOC_IP2K_HI8DATA
5596 BFD_RELOC_IP2K_EX8DATA
5598 Scenix IP2K - ext/low/high 8 bits of data address
5600 BFD_RELOC_IP2K_LO8INSN
5602 BFD_RELOC_IP2K_HI8INSN
5604 Scenix IP2K - low/high 8 bits of instruction word address
5606 BFD_RELOC_IP2K_PC_SKIP
5608 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5612 Scenix IP2K - 16 bit word address in text section.
5614 BFD_RELOC_IP2K_FR_OFFSET
5616 Scenix IP2K - 7-bit sp or dp offset
5618 BFD_RELOC_VPE4KMATH_DATA
5620 BFD_RELOC_VPE4KMATH_INSN
5622 Scenix VPE4K coprocessor - data/insn-space addressing
5625 BFD_RELOC_VTABLE_INHERIT
5627 BFD_RELOC_VTABLE_ENTRY
5629 These two relocations are used by the linker to determine which of
5630 the entries in a C++ virtual function table are actually used. When
5631 the --gc-sections option is given, the linker will zero out the entries
5632 that are not used, so that the code for those functions need not be
5633 included in the output.
5635 VTABLE_INHERIT is a zero-space relocation used to describe to the
5636 linker the inheritance tree of a C++ virtual function table. The
5637 relocation's symbol should be the parent class' vtable, and the
5638 relocation should be located at the child vtable.
5640 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5641 virtual function table entry. The reloc's symbol should refer to the
5642 table of the class mentioned in the code. Off of that base, an offset
5643 describes the entry that is being used. For Rela hosts, this offset
5644 is stored in the reloc's addend. For Rel hosts, we are forced to put
5645 this offset in the reloc's section offset.
5648 BFD_RELOC_IA64_IMM14
5650 BFD_RELOC_IA64_IMM22
5652 BFD_RELOC_IA64_IMM64
5654 BFD_RELOC_IA64_DIR32MSB
5656 BFD_RELOC_IA64_DIR32LSB
5658 BFD_RELOC_IA64_DIR64MSB
5660 BFD_RELOC_IA64_DIR64LSB
5662 BFD_RELOC_IA64_GPREL22
5664 BFD_RELOC_IA64_GPREL64I
5666 BFD_RELOC_IA64_GPREL32MSB
5668 BFD_RELOC_IA64_GPREL32LSB
5670 BFD_RELOC_IA64_GPREL64MSB
5672 BFD_RELOC_IA64_GPREL64LSB
5674 BFD_RELOC_IA64_LTOFF22
5676 BFD_RELOC_IA64_LTOFF64I
5678 BFD_RELOC_IA64_PLTOFF22
5680 BFD_RELOC_IA64_PLTOFF64I
5682 BFD_RELOC_IA64_PLTOFF64MSB
5684 BFD_RELOC_IA64_PLTOFF64LSB
5686 BFD_RELOC_IA64_FPTR64I
5688 BFD_RELOC_IA64_FPTR32MSB
5690 BFD_RELOC_IA64_FPTR32LSB
5692 BFD_RELOC_IA64_FPTR64MSB
5694 BFD_RELOC_IA64_FPTR64LSB
5696 BFD_RELOC_IA64_PCREL21B
5698 BFD_RELOC_IA64_PCREL21BI
5700 BFD_RELOC_IA64_PCREL21M
5702 BFD_RELOC_IA64_PCREL21F
5704 BFD_RELOC_IA64_PCREL22
5706 BFD_RELOC_IA64_PCREL60B
5708 BFD_RELOC_IA64_PCREL64I
5710 BFD_RELOC_IA64_PCREL32MSB
5712 BFD_RELOC_IA64_PCREL32LSB
5714 BFD_RELOC_IA64_PCREL64MSB
5716 BFD_RELOC_IA64_PCREL64LSB
5718 BFD_RELOC_IA64_LTOFF_FPTR22
5720 BFD_RELOC_IA64_LTOFF_FPTR64I
5722 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5724 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5726 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5728 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5730 BFD_RELOC_IA64_SEGREL32MSB
5732 BFD_RELOC_IA64_SEGREL32LSB
5734 BFD_RELOC_IA64_SEGREL64MSB
5736 BFD_RELOC_IA64_SEGREL64LSB
5738 BFD_RELOC_IA64_SECREL32MSB
5740 BFD_RELOC_IA64_SECREL32LSB
5742 BFD_RELOC_IA64_SECREL64MSB
5744 BFD_RELOC_IA64_SECREL64LSB
5746 BFD_RELOC_IA64_REL32MSB
5748 BFD_RELOC_IA64_REL32LSB
5750 BFD_RELOC_IA64_REL64MSB
5752 BFD_RELOC_IA64_REL64LSB
5754 BFD_RELOC_IA64_LTV32MSB
5756 BFD_RELOC_IA64_LTV32LSB
5758 BFD_RELOC_IA64_LTV64MSB
5760 BFD_RELOC_IA64_LTV64LSB
5762 BFD_RELOC_IA64_IPLTMSB
5764 BFD_RELOC_IA64_IPLTLSB
5768 BFD_RELOC_IA64_LTOFF22X
5770 BFD_RELOC_IA64_LDXMOV
5772 BFD_RELOC_IA64_TPREL14
5774 BFD_RELOC_IA64_TPREL22
5776 BFD_RELOC_IA64_TPREL64I
5778 BFD_RELOC_IA64_TPREL64MSB
5780 BFD_RELOC_IA64_TPREL64LSB
5782 BFD_RELOC_IA64_LTOFF_TPREL22
5784 BFD_RELOC_IA64_DTPMOD64MSB
5786 BFD_RELOC_IA64_DTPMOD64LSB
5788 BFD_RELOC_IA64_LTOFF_DTPMOD22
5790 BFD_RELOC_IA64_DTPREL14
5792 BFD_RELOC_IA64_DTPREL22
5794 BFD_RELOC_IA64_DTPREL64I
5796 BFD_RELOC_IA64_DTPREL32MSB
5798 BFD_RELOC_IA64_DTPREL32LSB
5800 BFD_RELOC_IA64_DTPREL64MSB
5802 BFD_RELOC_IA64_DTPREL64LSB
5804 BFD_RELOC_IA64_LTOFF_DTPREL22
5806 Intel IA64 Relocations.
5809 BFD_RELOC_M68HC11_HI8
5811 Motorola 68HC11 reloc.
5812 This is the 8 bit high part of an absolute address.
5814 BFD_RELOC_M68HC11_LO8
5816 Motorola 68HC11 reloc.
5817 This is the 8 bit low part of an absolute address.
5819 BFD_RELOC_M68HC11_3B
5821 Motorola 68HC11 reloc.
5822 This is the 3 bit of a value.
5824 BFD_RELOC_M68HC11_RL_JUMP
5826 Motorola 68HC11 reloc.
5827 This reloc marks the beginning of a jump/call instruction.
5828 It is used for linker relaxation to correctly identify beginning
5829 of instruction and change some branches to use PC-relative
5832 BFD_RELOC_M68HC11_RL_GROUP
5834 Motorola 68HC11 reloc.
5835 This reloc marks a group of several instructions that gcc generates
5836 and for which the linker relaxation pass can modify and/or remove
5839 BFD_RELOC_M68HC11_LO16
5841 Motorola 68HC11 reloc.
5842 This is the 16-bit lower part of an address. It is used for 'call'
5843 instruction to specify the symbol address without any special
5844 transformation (due to memory bank window).
5846 BFD_RELOC_M68HC11_PAGE
5848 Motorola 68HC11 reloc.
5849 This is a 8-bit reloc that specifies the page number of an address.
5850 It is used by 'call' instruction to specify the page number of
5853 BFD_RELOC_M68HC11_24
5855 Motorola 68HC11 reloc.
5856 This is a 24-bit reloc that represents the address with a 16-bit
5857 value and a 8-bit page number. The symbol address is transformed
5858 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5860 BFD_RELOC_M68HC12_5B
5862 Motorola 68HC12 reloc.
5863 This is the 5 bits of a value.
5865 BFD_RELOC_XGATE_RL_JUMP
5867 Freescale XGATE reloc.
5868 This reloc marks the beginning of a bra/jal instruction.
5870 BFD_RELOC_XGATE_RL_GROUP
5872 Freescale XGATE reloc.
5873 This reloc marks a group of several instructions that gcc generates
5874 and for which the linker relaxation pass can modify and/or remove
5877 BFD_RELOC_XGATE_LO16
5879 Freescale XGATE reloc.
5880 This is the 16-bit lower part of an address. It is used for the '16-bit'
5883 BFD_RELOC_XGATE_GPAGE
5885 Freescale XGATE reloc.
5889 Freescale XGATE reloc.
5891 BFD_RELOC_XGATE_PCREL_9
5893 Freescale XGATE reloc.
5894 This is a 9-bit pc-relative reloc.
5896 BFD_RELOC_XGATE_PCREL_10
5898 Freescale XGATE reloc.
5899 This is a 10-bit pc-relative reloc.
5901 BFD_RELOC_XGATE_IMM8_LO
5903 Freescale XGATE reloc.
5904 This is the 16-bit lower part of an address. It is used for the '16-bit'
5907 BFD_RELOC_XGATE_IMM8_HI
5909 Freescale XGATE reloc.
5910 This is the 16-bit higher part of an address. It is used for the '16-bit'
5913 BFD_RELOC_XGATE_IMM3
5915 Freescale XGATE reloc.
5916 This is a 3-bit pc-relative reloc.
5918 BFD_RELOC_XGATE_IMM4
5920 Freescale XGATE reloc.
5921 This is a 4-bit pc-relative reloc.
5923 BFD_RELOC_XGATE_IMM5
5925 Freescale XGATE reloc.
5926 This is a 5-bit pc-relative reloc.
5928 BFD_RELOC_M68HC12_9B
5930 Motorola 68HC12 reloc.
5931 This is the 9 bits of a value.
5933 BFD_RELOC_M68HC12_16B
5935 Motorola 68HC12 reloc.
5936 This is the 16 bits of a value.
5938 BFD_RELOC_M68HC12_9_PCREL
5940 Motorola 68HC12/XGATE reloc.
5941 This is a PCREL9 branch.
5943 BFD_RELOC_M68HC12_10_PCREL
5945 Motorola 68HC12/XGATE reloc.
5946 This is a PCREL10 branch.
5948 BFD_RELOC_M68HC12_LO8XG
5950 Motorola 68HC12/XGATE reloc.
5951 This is the 8 bit low part of an absolute address and immediately precedes
5952 a matching HI8XG part.
5954 BFD_RELOC_M68HC12_HI8XG
5956 Motorola 68HC12/XGATE reloc.
5957 This is the 8 bit high part of an absolute address and immediately follows
5958 a matching LO8XG part.
5960 BFD_RELOC_S12Z_15_PCREL
5962 Freescale S12Z reloc.
5963 This is a 15 bit relative address. If the most significant bits are all zero
5964 then it may be truncated to 8 bits.
5969 BFD_RELOC_CR16_NUM16
5971 BFD_RELOC_CR16_NUM32
5973 BFD_RELOC_CR16_NUM32a
5975 BFD_RELOC_CR16_REGREL0
5977 BFD_RELOC_CR16_REGREL4
5979 BFD_RELOC_CR16_REGREL4a
5981 BFD_RELOC_CR16_REGREL14
5983 BFD_RELOC_CR16_REGREL14a
5985 BFD_RELOC_CR16_REGREL16
5987 BFD_RELOC_CR16_REGREL20
5989 BFD_RELOC_CR16_REGREL20a
5991 BFD_RELOC_CR16_ABS20
5993 BFD_RELOC_CR16_ABS24
5999 BFD_RELOC_CR16_IMM16
6001 BFD_RELOC_CR16_IMM20
6003 BFD_RELOC_CR16_IMM24
6005 BFD_RELOC_CR16_IMM32
6007 BFD_RELOC_CR16_IMM32a
6009 BFD_RELOC_CR16_DISP4
6011 BFD_RELOC_CR16_DISP8
6013 BFD_RELOC_CR16_DISP16
6015 BFD_RELOC_CR16_DISP20
6017 BFD_RELOC_CR16_DISP24
6019 BFD_RELOC_CR16_DISP24a
6021 BFD_RELOC_CR16_SWITCH8
6023 BFD_RELOC_CR16_SWITCH16
6025 BFD_RELOC_CR16_SWITCH32
6027 BFD_RELOC_CR16_GOT_REGREL20
6029 BFD_RELOC_CR16_GOTC_REGREL20
6031 BFD_RELOC_CR16_GLOB_DAT
6033 NS CR16 Relocations.
6040 BFD_RELOC_CRX_REL8_CMP
6048 BFD_RELOC_CRX_REGREL12
6050 BFD_RELOC_CRX_REGREL22
6052 BFD_RELOC_CRX_REGREL28
6054 BFD_RELOC_CRX_REGREL32
6070 BFD_RELOC_CRX_SWITCH8
6072 BFD_RELOC_CRX_SWITCH16
6074 BFD_RELOC_CRX_SWITCH32
6079 BFD_RELOC_CRIS_BDISP8
6081 BFD_RELOC_CRIS_UNSIGNED_5
6083 BFD_RELOC_CRIS_SIGNED_6
6085 BFD_RELOC_CRIS_UNSIGNED_6
6087 BFD_RELOC_CRIS_SIGNED_8
6089 BFD_RELOC_CRIS_UNSIGNED_8
6091 BFD_RELOC_CRIS_SIGNED_16
6093 BFD_RELOC_CRIS_UNSIGNED_16
6095 BFD_RELOC_CRIS_LAPCQ_OFFSET
6097 BFD_RELOC_CRIS_UNSIGNED_4
6099 These relocs are only used within the CRIS assembler. They are not
6100 (at present) written to any object files.
6104 BFD_RELOC_CRIS_GLOB_DAT
6106 BFD_RELOC_CRIS_JUMP_SLOT
6108 BFD_RELOC_CRIS_RELATIVE
6110 Relocs used in ELF shared libraries for CRIS.
6112 BFD_RELOC_CRIS_32_GOT
6114 32-bit offset to symbol-entry within GOT.
6116 BFD_RELOC_CRIS_16_GOT
6118 16-bit offset to symbol-entry within GOT.
6120 BFD_RELOC_CRIS_32_GOTPLT
6122 32-bit offset to symbol-entry within GOT, with PLT handling.
6124 BFD_RELOC_CRIS_16_GOTPLT
6126 16-bit offset to symbol-entry within GOT, with PLT handling.
6128 BFD_RELOC_CRIS_32_GOTREL
6130 32-bit offset to symbol, relative to GOT.
6132 BFD_RELOC_CRIS_32_PLT_GOTREL
6134 32-bit offset to symbol with PLT entry, relative to GOT.
6136 BFD_RELOC_CRIS_32_PLT_PCREL
6138 32-bit offset to symbol with PLT entry, relative to this relocation.
6141 BFD_RELOC_CRIS_32_GOT_GD
6143 BFD_RELOC_CRIS_16_GOT_GD
6145 BFD_RELOC_CRIS_32_GD
6149 BFD_RELOC_CRIS_32_DTPREL
6151 BFD_RELOC_CRIS_16_DTPREL
6153 BFD_RELOC_CRIS_32_GOT_TPREL
6155 BFD_RELOC_CRIS_16_GOT_TPREL
6157 BFD_RELOC_CRIS_32_TPREL
6159 BFD_RELOC_CRIS_16_TPREL
6161 BFD_RELOC_CRIS_DTPMOD
6163 BFD_RELOC_CRIS_32_IE
6165 Relocs used in TLS code for CRIS.
6168 BFD_RELOC_OR1K_REL_26
6170 BFD_RELOC_OR1K_SLO16
6172 BFD_RELOC_OR1K_PCREL_PG21
6176 BFD_RELOC_OR1K_SLO13
6178 BFD_RELOC_OR1K_GOTPC_HI16
6180 BFD_RELOC_OR1K_GOTPC_LO16
6182 BFD_RELOC_OR1K_GOT16
6184 BFD_RELOC_OR1K_GOT_PG21
6186 BFD_RELOC_OR1K_GOT_LO13
6188 BFD_RELOC_OR1K_PLT26
6190 BFD_RELOC_OR1K_PLTA26
6192 BFD_RELOC_OR1K_GOTOFF_SLO16
6196 BFD_RELOC_OR1K_GLOB_DAT
6198 BFD_RELOC_OR1K_JMP_SLOT
6200 BFD_RELOC_OR1K_RELATIVE
6202 BFD_RELOC_OR1K_TLS_GD_HI16
6204 BFD_RELOC_OR1K_TLS_GD_LO16
6206 BFD_RELOC_OR1K_TLS_GD_PG21
6208 BFD_RELOC_OR1K_TLS_GD_LO13
6210 BFD_RELOC_OR1K_TLS_LDM_HI16
6212 BFD_RELOC_OR1K_TLS_LDM_LO16
6214 BFD_RELOC_OR1K_TLS_LDM_PG21
6216 BFD_RELOC_OR1K_TLS_LDM_LO13
6218 BFD_RELOC_OR1K_TLS_LDO_HI16
6220 BFD_RELOC_OR1K_TLS_LDO_LO16
6222 BFD_RELOC_OR1K_TLS_IE_HI16
6224 BFD_RELOC_OR1K_TLS_IE_AHI16
6226 BFD_RELOC_OR1K_TLS_IE_LO16
6228 BFD_RELOC_OR1K_TLS_IE_PG21
6230 BFD_RELOC_OR1K_TLS_IE_LO13
6232 BFD_RELOC_OR1K_TLS_LE_HI16
6234 BFD_RELOC_OR1K_TLS_LE_AHI16
6236 BFD_RELOC_OR1K_TLS_LE_LO16
6238 BFD_RELOC_OR1K_TLS_LE_SLO16
6240 BFD_RELOC_OR1K_TLS_TPOFF
6242 BFD_RELOC_OR1K_TLS_DTPOFF
6244 BFD_RELOC_OR1K_TLS_DTPMOD
6246 OpenRISC 1000 Relocations.
6249 BFD_RELOC_H8_DIR16A8
6251 BFD_RELOC_H8_DIR16R8
6253 BFD_RELOC_H8_DIR24A8
6255 BFD_RELOC_H8_DIR24R8
6257 BFD_RELOC_H8_DIR32A16
6259 BFD_RELOC_H8_DISP32A16
6264 BFD_RELOC_XSTORMY16_REL_12
6266 BFD_RELOC_XSTORMY16_12
6268 BFD_RELOC_XSTORMY16_24
6270 BFD_RELOC_XSTORMY16_FPTR16
6272 Sony Xstormy16 Relocations.
6277 Self-describing complex relocations.
6289 Infineon Relocations.
6292 BFD_RELOC_VAX_GLOB_DAT
6294 BFD_RELOC_VAX_JMP_SLOT
6296 BFD_RELOC_VAX_RELATIVE
6298 Relocations used by VAX ELF.
6303 Morpho MT - 16 bit immediate relocation.
6307 Morpho MT - Hi 16 bits of an address.
6311 Morpho MT - Low 16 bits of an address.
6313 BFD_RELOC_MT_GNU_VTINHERIT
6315 Morpho MT - Used to tell the linker which vtable entries are used.
6317 BFD_RELOC_MT_GNU_VTENTRY
6319 Morpho MT - Used to tell the linker which vtable entries are used.
6321 BFD_RELOC_MT_PCINSN8
6323 Morpho MT - 8 bit immediate relocation.
6326 BFD_RELOC_MSP430_10_PCREL
6328 BFD_RELOC_MSP430_16_PCREL
6332 BFD_RELOC_MSP430_16_PCREL_BYTE
6334 BFD_RELOC_MSP430_16_BYTE
6336 BFD_RELOC_MSP430_2X_PCREL
6338 BFD_RELOC_MSP430_RL_PCREL
6340 BFD_RELOC_MSP430_ABS8
6342 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6344 BFD_RELOC_MSP430X_PCR20_EXT_DST
6346 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6348 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6350 BFD_RELOC_MSP430X_ABS20_EXT_DST
6352 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6354 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6356 BFD_RELOC_MSP430X_ABS20_ADR_DST
6358 BFD_RELOC_MSP430X_PCR16
6360 BFD_RELOC_MSP430X_PCR20_CALL
6362 BFD_RELOC_MSP430X_ABS16
6364 BFD_RELOC_MSP430_ABS_HI16
6366 BFD_RELOC_MSP430_PREL31
6368 BFD_RELOC_MSP430_SYM_DIFF
6370 msp430 specific relocation codes
6377 BFD_RELOC_NIOS2_CALL26
6379 BFD_RELOC_NIOS2_IMM5
6381 BFD_RELOC_NIOS2_CACHE_OPX
6383 BFD_RELOC_NIOS2_IMM6
6385 BFD_RELOC_NIOS2_IMM8
6387 BFD_RELOC_NIOS2_HI16
6389 BFD_RELOC_NIOS2_LO16
6391 BFD_RELOC_NIOS2_HIADJ16
6393 BFD_RELOC_NIOS2_GPREL
6395 BFD_RELOC_NIOS2_UJMP
6397 BFD_RELOC_NIOS2_CJMP
6399 BFD_RELOC_NIOS2_CALLR
6401 BFD_RELOC_NIOS2_ALIGN
6403 BFD_RELOC_NIOS2_GOT16
6405 BFD_RELOC_NIOS2_CALL16
6407 BFD_RELOC_NIOS2_GOTOFF_LO
6409 BFD_RELOC_NIOS2_GOTOFF_HA
6411 BFD_RELOC_NIOS2_PCREL_LO
6413 BFD_RELOC_NIOS2_PCREL_HA
6415 BFD_RELOC_NIOS2_TLS_GD16
6417 BFD_RELOC_NIOS2_TLS_LDM16
6419 BFD_RELOC_NIOS2_TLS_LDO16
6421 BFD_RELOC_NIOS2_TLS_IE16
6423 BFD_RELOC_NIOS2_TLS_LE16
6425 BFD_RELOC_NIOS2_TLS_DTPMOD
6427 BFD_RELOC_NIOS2_TLS_DTPREL
6429 BFD_RELOC_NIOS2_TLS_TPREL
6431 BFD_RELOC_NIOS2_COPY
6433 BFD_RELOC_NIOS2_GLOB_DAT
6435 BFD_RELOC_NIOS2_JUMP_SLOT
6437 BFD_RELOC_NIOS2_RELATIVE
6439 BFD_RELOC_NIOS2_GOTOFF
6441 BFD_RELOC_NIOS2_CALL26_NOAT
6443 BFD_RELOC_NIOS2_GOT_LO
6445 BFD_RELOC_NIOS2_GOT_HA
6447 BFD_RELOC_NIOS2_CALL_LO
6449 BFD_RELOC_NIOS2_CALL_HA
6451 BFD_RELOC_NIOS2_R2_S12
6453 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6455 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6457 BFD_RELOC_NIOS2_R2_T1I7_2
6459 BFD_RELOC_NIOS2_R2_T2I4
6461 BFD_RELOC_NIOS2_R2_T2I4_1
6463 BFD_RELOC_NIOS2_R2_T2I4_2
6465 BFD_RELOC_NIOS2_R2_X1I7_2
6467 BFD_RELOC_NIOS2_R2_X2L5
6469 BFD_RELOC_NIOS2_R2_F1I5_2
6471 BFD_RELOC_NIOS2_R2_L5I4X1
6473 BFD_RELOC_NIOS2_R2_T1X1I6
6475 BFD_RELOC_NIOS2_R2_T1X1I6_2
6477 Relocations used by the Altera Nios II core.
6482 PRU LDI 16-bit unsigned data-memory relocation.
6484 BFD_RELOC_PRU_U16_PMEMIMM
6486 PRU LDI 16-bit unsigned instruction-memory relocation.
6490 PRU relocation for two consecutive LDI load instructions that load a
6491 32 bit value into a register. If the higher bits are all zero, then
6492 the second instruction may be relaxed.
6494 BFD_RELOC_PRU_S10_PCREL
6496 PRU QBBx 10-bit signed PC-relative relocation.
6498 BFD_RELOC_PRU_U8_PCREL
6500 PRU 8-bit unsigned relocation used for the LOOP instruction.
6502 BFD_RELOC_PRU_32_PMEM
6504 BFD_RELOC_PRU_16_PMEM
6506 PRU Program Memory relocations. Used to convert from byte addressing to
6507 32-bit word addressing.
6509 BFD_RELOC_PRU_GNU_DIFF8
6511 BFD_RELOC_PRU_GNU_DIFF16
6513 BFD_RELOC_PRU_GNU_DIFF32
6515 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6517 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6519 PRU relocations to mark the difference of two local symbols.
6520 These are only needed to support linker relaxation and can be ignored
6521 when not relaxing. The field is set to the value of the difference
6522 assuming no relaxation. The relocation encodes the position of the
6523 second symbol so the linker can determine whether to adjust the field
6524 value. The PMEM variants encode the word difference, instead of byte
6525 difference between symbols.
6528 BFD_RELOC_IQ2000_OFFSET_16
6530 BFD_RELOC_IQ2000_OFFSET_21
6532 BFD_RELOC_IQ2000_UHI16
6537 BFD_RELOC_XTENSA_RTLD
6539 Special Xtensa relocation used only by PLT entries in ELF shared
6540 objects to indicate that the runtime linker should set the value
6541 to one of its own internal functions or data structures.
6543 BFD_RELOC_XTENSA_GLOB_DAT
6545 BFD_RELOC_XTENSA_JMP_SLOT
6547 BFD_RELOC_XTENSA_RELATIVE
6549 Xtensa relocations for ELF shared objects.
6551 BFD_RELOC_XTENSA_PLT
6553 Xtensa relocation used in ELF object files for symbols that may require
6554 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6556 BFD_RELOC_XTENSA_DIFF8
6558 BFD_RELOC_XTENSA_DIFF16
6560 BFD_RELOC_XTENSA_DIFF32
6562 Xtensa relocations for backward compatibility. These have been replaced
6563 by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF.
6564 Xtensa relocations to mark the difference of two local symbols.
6565 These are only needed to support linker relaxation and can be ignored
6566 when not relaxing. The field is set to the value of the difference
6567 assuming no relaxation. The relocation encodes the position of the
6568 first symbol so the linker can determine whether to adjust the field
6571 BFD_RELOC_XTENSA_SLOT0_OP
6573 BFD_RELOC_XTENSA_SLOT1_OP
6575 BFD_RELOC_XTENSA_SLOT2_OP
6577 BFD_RELOC_XTENSA_SLOT3_OP
6579 BFD_RELOC_XTENSA_SLOT4_OP
6581 BFD_RELOC_XTENSA_SLOT5_OP
6583 BFD_RELOC_XTENSA_SLOT6_OP
6585 BFD_RELOC_XTENSA_SLOT7_OP
6587 BFD_RELOC_XTENSA_SLOT8_OP
6589 BFD_RELOC_XTENSA_SLOT9_OP
6591 BFD_RELOC_XTENSA_SLOT10_OP
6593 BFD_RELOC_XTENSA_SLOT11_OP
6595 BFD_RELOC_XTENSA_SLOT12_OP
6597 BFD_RELOC_XTENSA_SLOT13_OP
6599 BFD_RELOC_XTENSA_SLOT14_OP
6601 Generic Xtensa relocations for instruction operands. Only the slot
6602 number is encoded in the relocation. The relocation applies to the
6603 last PC-relative immediate operand, or if there are no PC-relative
6604 immediates, to the last immediate operand.
6606 BFD_RELOC_XTENSA_SLOT0_ALT
6608 BFD_RELOC_XTENSA_SLOT1_ALT
6610 BFD_RELOC_XTENSA_SLOT2_ALT
6612 BFD_RELOC_XTENSA_SLOT3_ALT
6614 BFD_RELOC_XTENSA_SLOT4_ALT
6616 BFD_RELOC_XTENSA_SLOT5_ALT
6618 BFD_RELOC_XTENSA_SLOT6_ALT
6620 BFD_RELOC_XTENSA_SLOT7_ALT
6622 BFD_RELOC_XTENSA_SLOT8_ALT
6624 BFD_RELOC_XTENSA_SLOT9_ALT
6626 BFD_RELOC_XTENSA_SLOT10_ALT
6628 BFD_RELOC_XTENSA_SLOT11_ALT
6630 BFD_RELOC_XTENSA_SLOT12_ALT
6632 BFD_RELOC_XTENSA_SLOT13_ALT
6634 BFD_RELOC_XTENSA_SLOT14_ALT
6636 Alternate Xtensa relocations. Only the slot is encoded in the
6637 relocation. The meaning of these relocations is opcode-specific.
6639 BFD_RELOC_XTENSA_OP0
6641 BFD_RELOC_XTENSA_OP1
6643 BFD_RELOC_XTENSA_OP2
6645 Xtensa relocations for backward compatibility. These have all been
6646 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6648 BFD_RELOC_XTENSA_ASM_EXPAND
6650 Xtensa relocation to mark that the assembler expanded the
6651 instructions from an original target. The expansion size is
6652 encoded in the reloc size.
6654 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6656 Xtensa relocation to mark that the linker should simplify
6657 assembler-expanded instructions. This is commonly used
6658 internally by the linker after analysis of a
6659 BFD_RELOC_XTENSA_ASM_EXPAND.
6661 BFD_RELOC_XTENSA_TLSDESC_FN
6663 BFD_RELOC_XTENSA_TLSDESC_ARG
6665 BFD_RELOC_XTENSA_TLS_DTPOFF
6667 BFD_RELOC_XTENSA_TLS_TPOFF
6669 BFD_RELOC_XTENSA_TLS_FUNC
6671 BFD_RELOC_XTENSA_TLS_ARG
6673 BFD_RELOC_XTENSA_TLS_CALL
6675 Xtensa TLS relocations.
6677 BFD_RELOC_XTENSA_PDIFF8
6679 BFD_RELOC_XTENSA_PDIFF16
6681 BFD_RELOC_XTENSA_PDIFF32
6683 BFD_RELOC_XTENSA_NDIFF8
6685 BFD_RELOC_XTENSA_NDIFF16
6687 BFD_RELOC_XTENSA_NDIFF32
6689 Xtensa relocations to mark the difference of two local symbols.
6690 These are only needed to support linker relaxation and can be ignored
6691 when not relaxing. The field is set to the value of the difference
6692 assuming no relaxation. The relocation encodes the position of the
6693 subtracted symbol so the linker can determine whether to adjust the field
6694 value. PDIFF relocations are used for positive differences, NDIFF
6695 relocations are used for negative differences. The difference value
6696 is treated as unsigned with these relocation types, giving full
6702 8 bit signed offset in (ix+d) or (iy+d).
6706 First 8 bits of multibyte (32, 24 or 16 bit) value.
6710 Second 8 bits of multibyte (32, 24 or 16 bit) value.
6714 Third 8 bits of multibyte (32 or 24 bit) value.
6718 Fourth 8 bits of multibyte (32 bit) value.
6722 Lowest 16 bits of multibyte (32 or 24 bit) value.
6726 Highest 16 bits of multibyte (32 or 24 bit) value.
6730 Like BFD_RELOC_16 but big-endian.
6748 BFD_RELOC_LM32_BRANCH
6750 BFD_RELOC_LM32_16_GOT
6752 BFD_RELOC_LM32_GOTOFF_HI16
6754 BFD_RELOC_LM32_GOTOFF_LO16
6758 BFD_RELOC_LM32_GLOB_DAT
6760 BFD_RELOC_LM32_JMP_SLOT
6762 BFD_RELOC_LM32_RELATIVE
6764 Lattice Mico32 relocations.
6767 BFD_RELOC_MACH_O_SECTDIFF
6769 Difference between two section addreses. Must be followed by a
6770 BFD_RELOC_MACH_O_PAIR.
6772 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6774 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6776 BFD_RELOC_MACH_O_PAIR
6778 Pair of relocation. Contains the first symbol.
6780 BFD_RELOC_MACH_O_SUBTRACTOR32
6782 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6784 BFD_RELOC_MACH_O_SUBTRACTOR64
6786 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6789 BFD_RELOC_MACH_O_X86_64_BRANCH32
6791 BFD_RELOC_MACH_O_X86_64_BRANCH8
6793 PCREL relocations. They are marked as branch to create PLT entry if
6796 BFD_RELOC_MACH_O_X86_64_GOT
6798 Used when referencing a GOT entry.
6800 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6802 Used when loading a GOT entry with movq. It is specially marked so that
6803 the linker could optimize the movq to a leaq if possible.
6805 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6807 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6809 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6811 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6813 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6815 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6817 BFD_RELOC_MACH_O_X86_64_TLV
6819 Used when referencing a TLV entry.
6823 BFD_RELOC_MACH_O_ARM64_ADDEND
6825 Addend for PAGE or PAGEOFF.
6827 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6829 Relative offset to page of GOT slot.
6831 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6833 Relative offset within page of GOT slot.
6835 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6837 Address of a GOT entry.
6840 BFD_RELOC_MICROBLAZE_32_LO
6842 This is a 32 bit reloc for the microblaze that stores the
6843 low 16 bits of a value
6845 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6847 This is a 32 bit pc-relative reloc for the microblaze that
6848 stores the low 16 bits of a value
6850 BFD_RELOC_MICROBLAZE_32_ROSDA
6852 This is a 32 bit reloc for the microblaze that stores a
6853 value relative to the read-only small data area anchor
6855 BFD_RELOC_MICROBLAZE_32_RWSDA
6857 This is a 32 bit reloc for the microblaze that stores a
6858 value relative to the read-write small data area anchor
6860 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6862 This is a 32 bit reloc for the microblaze to handle
6863 expressions of the form "Symbol Op Symbol"
6865 BFD_RELOC_MICROBLAZE_64_NONE
6867 This is a 64 bit reloc that stores the 32 bit pc relative
6868 value in two words (with an imm instruction). No relocation is
6869 done here - only used for relaxing
6871 BFD_RELOC_MICROBLAZE_64_GOTPC
6873 This is a 64 bit reloc that stores the 32 bit pc relative
6874 value in two words (with an imm instruction). The relocation is
6875 PC-relative GOT offset
6877 BFD_RELOC_MICROBLAZE_64_GOT
6879 This is a 64 bit reloc that stores the 32 bit pc relative
6880 value in two words (with an imm instruction). The relocation is
6883 BFD_RELOC_MICROBLAZE_64_PLT
6885 This is a 64 bit reloc that stores the 32 bit pc relative
6886 value in two words (with an imm instruction). The relocation is
6887 PC-relative offset into PLT
6889 BFD_RELOC_MICROBLAZE_64_GOTOFF
6891 This is a 64 bit reloc that stores the 32 bit GOT relative
6892 value in two words (with an imm instruction). The relocation is
6893 relative offset from _GLOBAL_OFFSET_TABLE_
6895 BFD_RELOC_MICROBLAZE_32_GOTOFF
6897 This is a 32 bit reloc that stores the 32 bit GOT relative
6898 value in a word. The relocation is relative offset from
6899 _GLOBAL_OFFSET_TABLE_
6901 BFD_RELOC_MICROBLAZE_COPY
6903 This is used to tell the dynamic linker to copy the value out of
6904 the dynamic object into the runtime process image.
6906 BFD_RELOC_MICROBLAZE_64_TLS
6910 BFD_RELOC_MICROBLAZE_64_TLSGD
6912 This is a 64 bit reloc that stores the 32 bit GOT relative value
6913 of the GOT TLS GD info entry in two words (with an imm instruction). The
6914 relocation is GOT offset.
6916 BFD_RELOC_MICROBLAZE_64_TLSLD
6918 This is a 64 bit reloc that stores the 32 bit GOT relative value
6919 of the GOT TLS LD info entry in two words (with an imm instruction). The
6920 relocation is GOT offset.
6922 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6924 This is a 32 bit reloc that stores the Module ID to GOT(n).
6926 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6928 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6930 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6932 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6935 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6937 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6938 to two words (uses imm instruction).
6940 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6942 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6943 to two words (uses imm instruction).
6945 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6947 This is a 64 bit reloc that stores the 32 bit pc relative
6948 value in two words (with an imm instruction). The relocation is
6949 PC-relative offset from start of TEXT.
6951 BFD_RELOC_MICROBLAZE_64_TEXTREL
6953 This is a 64 bit reloc that stores the 32 bit offset
6954 value in two words (with an imm instruction). The relocation is
6955 relative offset from start of TEXT.
6958 BFD_RELOC_AARCH64_RELOC_START
6960 AArch64 pseudo relocation code to mark the start of the AArch64
6961 relocation enumerators. N.B. the order of the enumerators is
6962 important as several tables in the AArch64 bfd backend are indexed
6963 by these enumerators; make sure they are all synced.
6965 BFD_RELOC_AARCH64_NULL
6967 Deprecated AArch64 null relocation code.
6969 BFD_RELOC_AARCH64_NONE
6971 AArch64 null relocation code.
6973 BFD_RELOC_AARCH64_64
6975 BFD_RELOC_AARCH64_32
6977 BFD_RELOC_AARCH64_16
6979 Basic absolute relocations of N bits. These are equivalent to
6980 BFD_RELOC_N and they were added to assist the indexing of the howto
6983 BFD_RELOC_AARCH64_64_PCREL
6985 BFD_RELOC_AARCH64_32_PCREL
6987 BFD_RELOC_AARCH64_16_PCREL
6989 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6990 and they were added to assist the indexing of the howto table.
6992 BFD_RELOC_AARCH64_MOVW_G0
6994 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6995 of an unsigned address/value.
6997 BFD_RELOC_AARCH64_MOVW_G0_NC
6999 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7000 an address/value. No overflow checking.
7002 BFD_RELOC_AARCH64_MOVW_G1
7004 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7005 of an unsigned address/value.
7007 BFD_RELOC_AARCH64_MOVW_G1_NC
7009 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7010 of an address/value. No overflow checking.
7012 BFD_RELOC_AARCH64_MOVW_G2
7014 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7015 of an unsigned address/value.
7017 BFD_RELOC_AARCH64_MOVW_G2_NC
7019 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7020 of an address/value. No overflow checking.
7022 BFD_RELOC_AARCH64_MOVW_G3
7024 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7025 of a signed or unsigned address/value.
7027 BFD_RELOC_AARCH64_MOVW_G0_S
7029 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7030 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7033 BFD_RELOC_AARCH64_MOVW_G1_S
7035 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7036 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7039 BFD_RELOC_AARCH64_MOVW_G2_S
7041 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7042 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7045 BFD_RELOC_AARCH64_MOVW_PREL_G0
7047 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7048 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7051 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7053 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7054 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7057 BFD_RELOC_AARCH64_MOVW_PREL_G1
7059 AArch64 MOVK instruction with most significant bits 16 to 31
7062 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7064 AArch64 MOVK instruction with most significant bits 16 to 31
7067 BFD_RELOC_AARCH64_MOVW_PREL_G2
7069 AArch64 MOVK instruction with most significant bits 32 to 47
7072 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7074 AArch64 MOVK instruction with most significant bits 32 to 47
7077 BFD_RELOC_AARCH64_MOVW_PREL_G3
7079 AArch64 MOVK instruction with most significant bits 47 to 63
7082 BFD_RELOC_AARCH64_LD_LO19_PCREL
7084 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7085 offset. The lowest two bits must be zero and are not stored in the
7086 instruction, giving a 21 bit signed byte offset.
7088 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7090 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7092 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7094 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7095 offset, giving a 4KB aligned page base address.
7097 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7099 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7100 offset, giving a 4KB aligned page base address, but with no overflow
7103 BFD_RELOC_AARCH64_ADD_LO12
7105 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7106 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7108 BFD_RELOC_AARCH64_LDST8_LO12
7110 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7111 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7113 BFD_RELOC_AARCH64_TSTBR14
7115 AArch64 14 bit pc-relative test bit and branch.
7116 The lowest two bits must be zero and are not stored in the instruction,
7117 giving a 16 bit signed byte offset.
7119 BFD_RELOC_AARCH64_BRANCH19
7121 AArch64 19 bit pc-relative conditional branch and compare & branch.
7122 The lowest two bits must be zero and are not stored in the instruction,
7123 giving a 21 bit signed byte offset.
7125 BFD_RELOC_AARCH64_JUMP26
7127 AArch64 26 bit pc-relative unconditional branch.
7128 The lowest two bits must be zero and are not stored in the instruction,
7129 giving a 28 bit signed byte offset.
7131 BFD_RELOC_AARCH64_CALL26
7133 AArch64 26 bit pc-relative unconditional branch and link.
7134 The lowest two bits must be zero and are not stored in the instruction,
7135 giving a 28 bit signed byte offset.
7137 BFD_RELOC_AARCH64_LDST16_LO12
7139 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7140 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7142 BFD_RELOC_AARCH64_LDST32_LO12
7144 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7145 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7147 BFD_RELOC_AARCH64_LDST64_LO12
7149 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7150 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7152 BFD_RELOC_AARCH64_LDST128_LO12
7154 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7155 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7157 BFD_RELOC_AARCH64_GOT_LD_PREL19
7159 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7160 offset of the global offset table entry for a symbol. The lowest two
7161 bits must be zero and are not stored in the instruction, giving a 21
7162 bit signed byte offset. This relocation type requires signed overflow
7165 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7167 Get to the page base of the global offset table entry for a symbol as
7168 part of an ADRP instruction using a 21 bit PC relative value.Used in
7169 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7171 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7173 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7174 the GOT entry for this symbol. Used in conjunction with
7175 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7177 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7179 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7180 the GOT entry for this symbol. Used in conjunction with
7181 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7183 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7185 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7186 for this symbol. Valid in LP64 ABI only.
7188 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7190 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7191 for this symbol. Valid in LP64 ABI only.
7193 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7195 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7196 the GOT entry for this symbol. Valid in LP64 ABI only.
7198 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7200 Scaled 14 bit byte offset to the page base of the global offset table.
7202 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7204 Scaled 15 bit byte offset to the page base of the global offset table.
7206 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7208 Get to the page base of the global offset table entry for a symbols
7209 tls_index structure as part of an adrp instruction using a 21 bit PC
7210 relative value. Used in conjunction with
7211 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7213 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7215 AArch64 TLS General Dynamic
7217 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7219 Unsigned 12 bit byte offset to global offset table entry for a symbols
7220 tls_index structure. Used in conjunction with
7221 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7223 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7225 AArch64 TLS General Dynamic relocation.
7227 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7229 AArch64 TLS General Dynamic relocation.
7231 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7233 AArch64 TLS INITIAL EXEC relocation.
7235 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7237 AArch64 TLS INITIAL EXEC relocation.
7239 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7241 AArch64 TLS INITIAL EXEC relocation.
7243 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7245 AArch64 TLS INITIAL EXEC relocation.
7247 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7249 AArch64 TLS INITIAL EXEC relocation.
7251 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7253 AArch64 TLS INITIAL EXEC relocation.
7255 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7257 bit[23:12] of byte offset to module TLS base address.
7259 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7261 Unsigned 12 bit byte offset to module TLS base address.
7263 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7265 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7267 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7269 Unsigned 12 bit byte offset to global offset table entry for a symbols
7270 tls_index structure. Used in conjunction with
7271 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7273 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7275 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7278 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7280 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7282 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7284 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7287 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7289 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7291 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7293 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7296 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7298 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7300 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7302 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7305 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7307 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7309 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7311 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7314 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7316 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7318 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7320 bit[15:0] of byte offset to module TLS base address.
7322 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7324 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7326 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7328 bit[31:16] of byte offset to module TLS base address.
7330 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7332 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7334 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7336 bit[47:32] of byte offset to module TLS base address.
7338 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7340 AArch64 TLS LOCAL EXEC relocation.
7342 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7344 AArch64 TLS LOCAL EXEC relocation.
7346 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7348 AArch64 TLS LOCAL EXEC relocation.
7350 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7352 AArch64 TLS LOCAL EXEC relocation.
7354 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7356 AArch64 TLS LOCAL EXEC relocation.
7358 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7360 AArch64 TLS LOCAL EXEC relocation.
7362 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7364 AArch64 TLS LOCAL EXEC relocation.
7366 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7368 AArch64 TLS LOCAL EXEC relocation.
7370 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7372 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7375 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7377 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7379 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7381 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7384 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7386 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7388 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7390 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7393 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7395 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7397 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7399 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7402 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7404 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7406 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7408 AArch64 TLS DESC relocation.
7410 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7412 AArch64 TLS DESC relocation.
7414 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7416 AArch64 TLS DESC relocation.
7418 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7420 AArch64 TLS DESC relocation.
7422 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7424 AArch64 TLS DESC relocation.
7426 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7428 AArch64 TLS DESC relocation.
7430 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7432 AArch64 TLS DESC relocation.
7434 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7436 AArch64 TLS DESC relocation.
7438 BFD_RELOC_AARCH64_TLSDESC_LDR
7440 AArch64 TLS DESC relocation.
7442 BFD_RELOC_AARCH64_TLSDESC_ADD
7444 AArch64 TLS DESC relocation.
7446 BFD_RELOC_AARCH64_TLSDESC_CALL
7448 AArch64 TLS DESC relocation.
7450 BFD_RELOC_AARCH64_COPY
7452 AArch64 TLS relocation.
7454 BFD_RELOC_AARCH64_GLOB_DAT
7456 AArch64 TLS relocation.
7458 BFD_RELOC_AARCH64_JUMP_SLOT
7460 AArch64 TLS relocation.
7462 BFD_RELOC_AARCH64_RELATIVE
7464 AArch64 TLS relocation.
7466 BFD_RELOC_AARCH64_TLS_DTPMOD
7468 AArch64 TLS relocation.
7470 BFD_RELOC_AARCH64_TLS_DTPREL
7472 AArch64 TLS relocation.
7474 BFD_RELOC_AARCH64_TLS_TPREL
7476 AArch64 TLS relocation.
7478 BFD_RELOC_AARCH64_TLSDESC
7480 AArch64 TLS relocation.
7482 BFD_RELOC_AARCH64_IRELATIVE
7484 AArch64 support for STT_GNU_IFUNC.
7486 BFD_RELOC_AARCH64_RELOC_END
7488 AArch64 pseudo relocation code to mark the end of the AArch64
7489 relocation enumerators that have direct mapping to ELF reloc codes.
7490 There are a few more enumerators after this one; those are mainly
7491 used by the AArch64 assembler for the internal fixup or to select
7492 one of the above enumerators.
7494 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7496 AArch64 pseudo relocation code to be used internally by the AArch64
7497 assembler and not (currently) written to any object files.
7499 BFD_RELOC_AARCH64_LDST_LO12
7501 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7502 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7504 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7506 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7507 used internally by the AArch64 assembler and not (currently) written to
7510 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7512 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7514 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7516 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7517 used internally by the AArch64 assembler and not (currently) written to
7520 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7522 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7524 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7526 AArch64 pseudo relocation code to be used internally by the AArch64
7527 assembler and not (currently) written to any object files.
7529 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7531 AArch64 pseudo relocation code to be used internally by the AArch64
7532 assembler and not (currently) written to any object files.
7534 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7536 AArch64 pseudo relocation code to be used internally by the AArch64
7537 assembler and not (currently) written to any object files.
7539 BFD_RELOC_TILEPRO_COPY
7541 BFD_RELOC_TILEPRO_GLOB_DAT
7543 BFD_RELOC_TILEPRO_JMP_SLOT
7545 BFD_RELOC_TILEPRO_RELATIVE
7547 BFD_RELOC_TILEPRO_BROFF_X1
7549 BFD_RELOC_TILEPRO_JOFFLONG_X1
7551 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7553 BFD_RELOC_TILEPRO_IMM8_X0
7555 BFD_RELOC_TILEPRO_IMM8_Y0
7557 BFD_RELOC_TILEPRO_IMM8_X1
7559 BFD_RELOC_TILEPRO_IMM8_Y1
7561 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7563 BFD_RELOC_TILEPRO_MT_IMM15_X1
7565 BFD_RELOC_TILEPRO_MF_IMM15_X1
7567 BFD_RELOC_TILEPRO_IMM16_X0
7569 BFD_RELOC_TILEPRO_IMM16_X1
7571 BFD_RELOC_TILEPRO_IMM16_X0_LO
7573 BFD_RELOC_TILEPRO_IMM16_X1_LO
7575 BFD_RELOC_TILEPRO_IMM16_X0_HI
7577 BFD_RELOC_TILEPRO_IMM16_X1_HI
7579 BFD_RELOC_TILEPRO_IMM16_X0_HA
7581 BFD_RELOC_TILEPRO_IMM16_X1_HA
7583 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7585 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7587 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7589 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7591 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7593 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7595 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7597 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7599 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7601 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7603 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7605 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7607 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7609 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7611 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7613 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7615 BFD_RELOC_TILEPRO_MMSTART_X0
7617 BFD_RELOC_TILEPRO_MMEND_X0
7619 BFD_RELOC_TILEPRO_MMSTART_X1
7621 BFD_RELOC_TILEPRO_MMEND_X1
7623 BFD_RELOC_TILEPRO_SHAMT_X0
7625 BFD_RELOC_TILEPRO_SHAMT_X1
7627 BFD_RELOC_TILEPRO_SHAMT_Y0
7629 BFD_RELOC_TILEPRO_SHAMT_Y1
7631 BFD_RELOC_TILEPRO_TLS_GD_CALL
7633 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7635 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7637 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7639 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7641 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7643 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7645 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7647 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7649 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7651 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7653 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7655 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7657 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7659 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7661 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7663 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7665 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7667 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7669 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7671 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7673 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7675 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7677 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7679 BFD_RELOC_TILEPRO_TLS_TPOFF32
7681 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7683 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7685 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7687 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7689 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7691 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7693 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7695 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7697 Tilera TILEPro Relocations.
7699 BFD_RELOC_TILEGX_HW0
7701 BFD_RELOC_TILEGX_HW1
7703 BFD_RELOC_TILEGX_HW2
7705 BFD_RELOC_TILEGX_HW3
7707 BFD_RELOC_TILEGX_HW0_LAST
7709 BFD_RELOC_TILEGX_HW1_LAST
7711 BFD_RELOC_TILEGX_HW2_LAST
7713 BFD_RELOC_TILEGX_COPY
7715 BFD_RELOC_TILEGX_GLOB_DAT
7717 BFD_RELOC_TILEGX_JMP_SLOT
7719 BFD_RELOC_TILEGX_RELATIVE
7721 BFD_RELOC_TILEGX_BROFF_X1
7723 BFD_RELOC_TILEGX_JUMPOFF_X1
7725 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7727 BFD_RELOC_TILEGX_IMM8_X0
7729 BFD_RELOC_TILEGX_IMM8_Y0
7731 BFD_RELOC_TILEGX_IMM8_X1
7733 BFD_RELOC_TILEGX_IMM8_Y1
7735 BFD_RELOC_TILEGX_DEST_IMM8_X1
7737 BFD_RELOC_TILEGX_MT_IMM14_X1
7739 BFD_RELOC_TILEGX_MF_IMM14_X1
7741 BFD_RELOC_TILEGX_MMSTART_X0
7743 BFD_RELOC_TILEGX_MMEND_X0
7745 BFD_RELOC_TILEGX_SHAMT_X0
7747 BFD_RELOC_TILEGX_SHAMT_X1
7749 BFD_RELOC_TILEGX_SHAMT_Y0
7751 BFD_RELOC_TILEGX_SHAMT_Y1
7753 BFD_RELOC_TILEGX_IMM16_X0_HW0
7755 BFD_RELOC_TILEGX_IMM16_X1_HW0
7757 BFD_RELOC_TILEGX_IMM16_X0_HW1
7759 BFD_RELOC_TILEGX_IMM16_X1_HW1
7761 BFD_RELOC_TILEGX_IMM16_X0_HW2
7763 BFD_RELOC_TILEGX_IMM16_X1_HW2
7765 BFD_RELOC_TILEGX_IMM16_X0_HW3
7767 BFD_RELOC_TILEGX_IMM16_X1_HW3
7769 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7771 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7773 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7775 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7777 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7779 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7781 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7783 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7785 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7787 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7789 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7791 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7793 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7795 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7797 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7799 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7801 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7803 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7805 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7807 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7809 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7811 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7813 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7815 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7817 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7819 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7821 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7823 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7825 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7827 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7829 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7831 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7833 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7835 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7837 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7839 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7841 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7843 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7845 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7847 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7849 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7851 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7853 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7855 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7857 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7859 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7861 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7863 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7865 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7867 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7869 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7871 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7873 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7875 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7877 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7879 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7881 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7883 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7885 BFD_RELOC_TILEGX_TLS_DTPMOD64
7887 BFD_RELOC_TILEGX_TLS_DTPOFF64
7889 BFD_RELOC_TILEGX_TLS_TPOFF64
7891 BFD_RELOC_TILEGX_TLS_DTPMOD32
7893 BFD_RELOC_TILEGX_TLS_DTPOFF32
7895 BFD_RELOC_TILEGX_TLS_TPOFF32
7897 BFD_RELOC_TILEGX_TLS_GD_CALL
7899 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7901 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7903 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7905 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7907 BFD_RELOC_TILEGX_TLS_IE_LOAD
7909 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7911 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7913 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7915 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7917 Tilera TILE-Gx Relocations.
7926 BFD_RELOC_BPF_DISP16
7928 BFD_RELOC_BPF_DISP32
7930 Linux eBPF relocations.
7933 BFD_RELOC_EPIPHANY_SIMM8
7935 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7937 BFD_RELOC_EPIPHANY_SIMM24
7939 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7941 BFD_RELOC_EPIPHANY_HIGH
7943 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7945 BFD_RELOC_EPIPHANY_LOW
7947 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7949 BFD_RELOC_EPIPHANY_SIMM11
7951 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7953 BFD_RELOC_EPIPHANY_IMM11
7955 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7957 BFD_RELOC_EPIPHANY_IMM8
7959 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7962 BFD_RELOC_VISIUM_HI16
7964 BFD_RELOC_VISIUM_LO16
7966 BFD_RELOC_VISIUM_IM16
7968 BFD_RELOC_VISIUM_REL16
7970 BFD_RELOC_VISIUM_HI16_PCREL
7972 BFD_RELOC_VISIUM_LO16_PCREL
7974 BFD_RELOC_VISIUM_IM16_PCREL
7979 BFD_RELOC_WASM32_LEB128
7981 BFD_RELOC_WASM32_LEB128_GOT
7983 BFD_RELOC_WASM32_LEB128_GOT_CODE
7985 BFD_RELOC_WASM32_LEB128_PLT
7987 BFD_RELOC_WASM32_PLT_INDEX
7989 BFD_RELOC_WASM32_ABS32_CODE
7991 BFD_RELOC_WASM32_COPY
7993 BFD_RELOC_WASM32_CODE_POINTER
7995 BFD_RELOC_WASM32_INDEX
7997 BFD_RELOC_WASM32_PLT_SIG
7999 WebAssembly relocations.
8002 BFD_RELOC_CKCORE_NONE
8004 BFD_RELOC_CKCORE_ADDR32
8006 BFD_RELOC_CKCORE_PCREL_IMM8BY4
8008 BFD_RELOC_CKCORE_PCREL_IMM11BY2
8010 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8012 BFD_RELOC_CKCORE_PCREL32
8014 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8016 BFD_RELOC_CKCORE_GNU_VTINHERIT
8018 BFD_RELOC_CKCORE_GNU_VTENTRY
8020 BFD_RELOC_CKCORE_RELATIVE
8022 BFD_RELOC_CKCORE_COPY
8024 BFD_RELOC_CKCORE_GLOB_DAT
8026 BFD_RELOC_CKCORE_JUMP_SLOT
8028 BFD_RELOC_CKCORE_GOTOFF
8030 BFD_RELOC_CKCORE_GOTPC
8032 BFD_RELOC_CKCORE_GOT32
8034 BFD_RELOC_CKCORE_PLT32
8036 BFD_RELOC_CKCORE_ADDRGOT
8038 BFD_RELOC_CKCORE_ADDRPLT
8040 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8042 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8044 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8046 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8048 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8050 BFD_RELOC_CKCORE_ADDR_HI16
8052 BFD_RELOC_CKCORE_ADDR_LO16
8054 BFD_RELOC_CKCORE_GOTPC_HI16
8056 BFD_RELOC_CKCORE_GOTPC_LO16
8058 BFD_RELOC_CKCORE_GOTOFF_HI16
8060 BFD_RELOC_CKCORE_GOTOFF_LO16
8062 BFD_RELOC_CKCORE_GOT12
8064 BFD_RELOC_CKCORE_GOT_HI16
8066 BFD_RELOC_CKCORE_GOT_LO16
8068 BFD_RELOC_CKCORE_PLT12
8070 BFD_RELOC_CKCORE_PLT_HI16
8072 BFD_RELOC_CKCORE_PLT_LO16
8074 BFD_RELOC_CKCORE_ADDRGOT_HI16
8076 BFD_RELOC_CKCORE_ADDRGOT_LO16
8078 BFD_RELOC_CKCORE_ADDRPLT_HI16
8080 BFD_RELOC_CKCORE_ADDRPLT_LO16
8082 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8084 BFD_RELOC_CKCORE_TOFFSET_LO16
8086 BFD_RELOC_CKCORE_DOFFSET_LO16
8088 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8090 BFD_RELOC_CKCORE_DOFFSET_IMM18
8092 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8094 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8096 BFD_RELOC_CKCORE_GOTOFF_IMM18
8098 BFD_RELOC_CKCORE_GOT_IMM18BY4
8100 BFD_RELOC_CKCORE_PLT_IMM18BY4
8102 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8104 BFD_RELOC_CKCORE_TLS_LE32
8106 BFD_RELOC_CKCORE_TLS_IE32
8108 BFD_RELOC_CKCORE_TLS_GD32
8110 BFD_RELOC_CKCORE_TLS_LDM32
8112 BFD_RELOC_CKCORE_TLS_LDO32
8114 BFD_RELOC_CKCORE_TLS_DTPMOD32
8116 BFD_RELOC_CKCORE_TLS_DTPOFF32
8118 BFD_RELOC_CKCORE_TLS_TPOFF32
8120 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8122 BFD_RELOC_CKCORE_NOJSRI
8124 BFD_RELOC_CKCORE_CALLGRAPH
8126 BFD_RELOC_CKCORE_IRELATIVE
8128 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8130 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8143 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8148 bfd_reloc_type_lookup
8149 bfd_reloc_name_lookup
8152 reloc_howto_type *bfd_reloc_type_lookup
8153 (bfd *abfd, bfd_reloc_code_real_type code);
8154 reloc_howto_type *bfd_reloc_name_lookup
8155 (bfd *abfd, const char *reloc_name);
8158 Return a pointer to a howto structure which, when
8159 invoked, will perform the relocation @var{code} on data from the
8165 bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8167 return BFD_SEND (abfd, reloc_type_lookup, (abfd, code));
8171 bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name)
8173 return BFD_SEND (abfd, reloc_name_lookup, (abfd, reloc_name));
8176 static reloc_howto_type bfd_howto_32 =
8177 HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE);
8181 bfd_default_reloc_type_lookup
8184 reloc_howto_type *bfd_default_reloc_type_lookup
8185 (bfd *abfd, bfd_reloc_code_real_type code);
8188 Provides a default relocation lookup routine for any architecture.
8193 bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code)
8195 /* Very limited support is provided for relocs in generic targets
8196 such as elf32-little. FIXME: Should we always return NULL? */
8197 if (code == BFD_RELOC_CTOR
8198 && bfd_arch_bits_per_address (abfd) == 32)
8199 return &bfd_howto_32;
8205 bfd_get_reloc_code_name
8208 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8211 Provides a printable name for the supplied relocation code.
8212 Useful mainly for printing error messages.
8216 bfd_get_reloc_code_name (bfd_reloc_code_real_type code)
8218 if (code > BFD_RELOC_UNUSED)
8220 return bfd_reloc_code_real_names[code];
8225 bfd_generic_relax_section
8228 bfd_boolean bfd_generic_relax_section
8231 struct bfd_link_info *,
8235 Provides default handling for relaxing for back ends which
8240 bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED,
8241 asection *section ATTRIBUTE_UNUSED,
8242 struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
8245 if (bfd_link_relocatable (link_info))
8246 (*link_info->callbacks->einfo)
8247 (_("%P%F: --relax and -r may not be used together\n"));
8255 bfd_generic_gc_sections
8258 bfd_boolean bfd_generic_gc_sections
8259 (bfd *, struct bfd_link_info *);
8262 Provides default handling for relaxing for back ends which
8263 don't do section gc -- i.e., does nothing.
8267 bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED,
8268 struct bfd_link_info *info ATTRIBUTE_UNUSED)
8275 bfd_generic_lookup_section_flags
8278 bfd_boolean bfd_generic_lookup_section_flags
8279 (struct bfd_link_info *, struct flag_info *, asection *);
8282 Provides default handling for section flags lookup
8283 -- i.e., does nothing.
8284 Returns FALSE if the section should be omitted, otherwise TRUE.
8288 bfd_generic_lookup_section_flags (struct bfd_link_info *info ATTRIBUTE_UNUSED,
8289 struct flag_info *flaginfo,
8290 asection *section ATTRIBUTE_UNUSED)
8292 if (flaginfo != NULL)
8294 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8302 bfd_generic_merge_sections
8305 bfd_boolean bfd_generic_merge_sections
8306 (bfd *, struct bfd_link_info *);
8309 Provides default handling for SEC_MERGE section merging for back ends
8310 which don't have SEC_MERGE support -- i.e., does nothing.
8314 bfd_generic_merge_sections (bfd *abfd ATTRIBUTE_UNUSED,
8315 struct bfd_link_info *link_info ATTRIBUTE_UNUSED)
8322 bfd_generic_get_relocated_section_contents
8325 bfd_byte *bfd_generic_get_relocated_section_contents
8327 struct bfd_link_info *link_info,
8328 struct bfd_link_order *link_order,
8330 bfd_boolean relocatable,
8334 Provides default handling of relocation effort for back ends
8335 which can't be bothered to do it efficiently.
8340 bfd_generic_get_relocated_section_contents (bfd *abfd,
8341 struct bfd_link_info *link_info,
8342 struct bfd_link_order *link_order,
8344 bfd_boolean relocatable,
8347 bfd *input_bfd = link_order->u.indirect.section->owner;
8348 asection *input_section = link_order->u.indirect.section;
8350 arelent **reloc_vector;
8353 reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section);
8357 /* Read in the section. */
8358 if (!bfd_get_full_section_contents (input_bfd, input_section, &data))
8364 if (reloc_size == 0)
8367 reloc_vector = (arelent **) bfd_malloc (reloc_size);
8368 if (reloc_vector == NULL)
8371 reloc_count = bfd_canonicalize_reloc (input_bfd,
8375 if (reloc_count < 0)
8378 if (reloc_count > 0)
8382 for (parent = reloc_vector; *parent != NULL; parent++)
8384 char *error_message = NULL;
8386 bfd_reloc_status_type r;
8388 symbol = *(*parent)->sym_ptr_ptr;
8389 /* PR ld/19628: A specially crafted input file
8390 can result in a NULL symbol pointer here. */
8393 link_info->callbacks->einfo
8394 /* xgettext:c-format */
8395 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8396 abfd, input_section, (* parent)->address);
8400 /* Zap reloc field when the symbol is from a discarded
8401 section, ignoring any addend. Do the same when called
8402 from bfd_simple_get_relocated_section_contents for
8403 undefined symbols in debug sections. This is to keep
8404 debug info reasonably sane, in particular so that
8405 DW_FORM_ref_addr to another file's .debug_info isn't
8406 confused with an offset into the current file's
8408 if ((symbol->section != NULL && discarded_section (symbol->section))
8409 || (symbol->section == bfd_und_section_ptr
8410 && (input_section->flags & SEC_DEBUGGING) != 0
8411 && link_info->input_bfds == link_info->output_bfd))
8414 static reloc_howto_type none_howto
8415 = HOWTO (0, 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL,
8416 "unused", FALSE, 0, 0, FALSE);
8418 off = ((*parent)->address
8419 * bfd_octets_per_byte (input_bfd, input_section));
8420 _bfd_clear_contents ((*parent)->howto, input_bfd,
8421 input_section, data, off);
8422 (*parent)->sym_ptr_ptr = bfd_abs_section_ptr->symbol_ptr_ptr;
8423 (*parent)->addend = 0;
8424 (*parent)->howto = &none_howto;
8428 r = bfd_perform_relocation (input_bfd,
8432 relocatable ? abfd : NULL,
8437 asection *os = input_section->output_section;
8439 /* A partial link, so keep the relocs. */
8440 os->orelocation[os->reloc_count] = *parent;
8444 if (r != bfd_reloc_ok)
8448 case bfd_reloc_undefined:
8449 (*link_info->callbacks->undefined_symbol)
8450 (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8451 input_bfd, input_section, (*parent)->address, TRUE);
8453 case bfd_reloc_dangerous:
8454 BFD_ASSERT (error_message != NULL);
8455 (*link_info->callbacks->reloc_dangerous)
8456 (link_info, error_message,
8457 input_bfd, input_section, (*parent)->address);
8459 case bfd_reloc_overflow:
8460 (*link_info->callbacks->reloc_overflow)
8462 bfd_asymbol_name (*(*parent)->sym_ptr_ptr),
8463 (*parent)->howto->name, (*parent)->addend,
8464 input_bfd, input_section, (*parent)->address);
8466 case bfd_reloc_outofrange:
8468 This error can result when processing some partially
8469 complete binaries. Do not abort, but issue an error
8471 link_info->callbacks->einfo
8472 /* xgettext:c-format */
8473 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8474 abfd, input_section, * parent);
8477 case bfd_reloc_notsupported:
8479 This error can result when processing a corrupt binary.
8480 Do not abort. Issue an error message instead. */
8481 link_info->callbacks->einfo
8482 /* xgettext:c-format */
8483 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8484 abfd, input_section, * parent);
8488 /* PR 17512; file: 90c2a92e.
8489 Report unexpected results, without aborting. */
8490 link_info->callbacks->einfo
8491 /* xgettext:c-format */
8492 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8493 abfd, input_section, * parent, r);
8501 free (reloc_vector);
8505 free (reloc_vector);
8511 _bfd_generic_set_reloc
8514 void _bfd_generic_set_reloc
8518 unsigned int count);
8521 Installs a new set of internal relocations in SECTION.
8525 _bfd_generic_set_reloc (bfd *abfd ATTRIBUTE_UNUSED,
8530 section->orelocation = relptr;
8531 section->reloc_count = count;
8536 _bfd_unrecognized_reloc
8539 bfd_boolean _bfd_unrecognized_reloc
8542 unsigned int r_type);
8545 Reports an unrecognized reloc.
8546 Written as a function in order to reduce code duplication.
8547 Returns FALSE so that it can be called from a return statement.
8551 _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type)
8553 /* xgettext:c-format */
8554 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8555 abfd, r_type, section);
8557 /* PR 21803: Suggest the most likely cause of this error. */
8558 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8559 BFD_VERSION_STRING);
8561 bfd_set_error (bfd_error_bad_value);
8566 _bfd_norelocs_bfd_reloc_type_lookup
8568 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED)
8570 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8574 _bfd_norelocs_bfd_reloc_name_lookup (bfd *abfd,
8575 const char *reloc_name ATTRIBUTE_UNUSED)
8577 return (reloc_howto_type *) _bfd_ptr_bfd_null_error (abfd);
8581 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd *abfd,
8582 arelent **relp ATTRIBUTE_UNUSED,
8583 asymbol **symp ATTRIBUTE_UNUSED)
8585 return _bfd_long_bfd_n1_error (abfd);