3 * i386.h (fild, fistp): Change intel d_Suf form to fildd and
8 * cgen.h (cgen_cpu_desc): Rename field 'flags' to
9 'signed_overflow_ok_p'.
10 Delete prototypes for cgen_set_flags() and cgen_get_flags().
14 * cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
15 (CGEN_CPU_TABLE): flags: new field.
16 Add prototypes for new functions.
20 * i386.h: Add some more UNIXWARE_COMPAT comments.
28 * mips.h: (OPCODE_IS_MEMBER): Add comment.
32 * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines
33 whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit
38 * i386.h: Qualify intel mode far call and jmp with x_Suf.
42 * i386.h: Add JumpAbsolute qualifier to all non-intel mode
43 indirect jumps and calls. Add FF/3 call for intel mode.
47 * mn10300.h: Add new operand types. Add new instruction formats.
51 * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb"
56 * mips.h (INSN_ISA5): New.
60 * mips.h (OPCODE_IS_MEMBER): New.
64 * d30v.h (SHORT_AR): Define.
68 * alpha.h (alpha_num_opcodes): Convert to unsigned.
69 (alpha_num_operands): Ditto.
73 * hppa.h (pa_opcodes): Add load and store cache control to
74 instructions. Add ordered access load and store.
76 * hppa.h (pa_opcode): Add new entries for addb and addib.
78 * hppa.h (pa_opcodes): Fix cmpb and cmpib entries.
80 * hppa.h (pa_opcodes): Add entries for cmpb and cmpib.
84 * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands.
88 * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"
89 and "be" using completer prefixes.
91 * hppa.h (pa_opcodes): Add initializers to silence compiler.
93 * hppa.h: Update comments about character usage.
97 * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning
98 up the new fstw & bve instructions.
102 * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store
105 * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions.
107 * hppa.h (pa_opcodes): Add long offset double word load/store
110 * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and
113 * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns.
115 * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions.
117 * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions.
119 * hppa.h (pa_opcodes): Add new syntax "be" instructions.
121 * hppa.h (pa_opcodes): Note use of 'M' and 'L'.
123 * hppa.h (pa_opcodes): Add support for "b,l".
125 * hppa.h (pa_opcodes): Add support for "b,gate".
129 * hppa.h (pa_opcodes): Use 'fX' for first register operand
132 * hppa.h (pa_opcodes): Fix mask for probe and probei.
134 * hppa.h (pa_opcodes): Fix mask for depwi.
138 * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as
139 an explicit output argument.
143 * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores.
144 Add a few PA2.0 loads and store variants.
152 * i386.h (i386_regtab): Move %st to top of table, and split off
153 other fp reg entries.
154 (i386_float_regtab): To here.
158 * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args
161 * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi.
164 * hppa.h: Document new completers and args.
165 * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor,
166 uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0
167 extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions
170 * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl,
171 hshr, hsub, mixh, mixw, permh.
173 * hppa.h (pa_opcodes): Change completers in instructions to
176 * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg,
177 hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments.
179 * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg,
180 fnegabs to use 'I' instead of 'F'.
184 * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd.
185 Document pf2iw and pi2fw as athlon insns. Remove pswapw.
186 Alphabetically sort PIII insns.
190 * cgen.h (CGEN_INSN_MACH_HAS_P): New macro.
194 * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and,
195 and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr.
197 * hppa.h: Document 64 bit condition completers.
201 * hppa.h (pa_opcodes): Change condition args to use '?' prefix.
205 * i386.h (i386_optab): Add DefaultSize modifier to all insns
206 that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf,
207 sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table.
212 * hppa.h (pa_opcodes): Add "pushnom" and "pushbts".
214 * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT.
216 * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd,
217 and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'.
221 * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns.
225 * hppa.h (struct pa_opcode): Add new field "flags".
226 (FLAGS_STRICT): Define.
231 * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction.
233 * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions.
237 * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl,
238 lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP
239 flag to fcomi and friends.
243 * hppa.h (pa_opcodes): Move integer arithmetic instructions after
244 integer logical instructions.
248 * m68k.h: Document new formats `E', `G', `H' and new places `N',
251 * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u'
252 and new places `m', `M', `h'.
256 * hppa.h (pa_opcodes): Add several processor specific system
261 * hppa.h (pa_opcodes): Add second entry for "comb", "comib",
262 "addb", and "addib" to be used by the disassembler.
266 * i386.h (ReverseModrm): Remove all occurences.
267 (InvMem): Add to control/debug/test mov insns, movhlps, movlhps,
268 movmskps, pextrw, pmovmskb, maskmovq.
269 Change NoSuf to FP on all MMX, XMM and AMD insns as these all
270 ignore the data size prefix.
272 * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD.
277 * ppc.h (PPC_OPCODE_64_BRIDGE): New.
281 * cgen.h (CGEN_ATTR): Delete member num_nonbools.
282 (CGEN_ATTR_TYPE): Update.
283 (CGEN_ATTR_MASK): Number booleans starting at 0.
284 (CGEN_ATTR_VALUE): Update.
285 (CGEN_INSN_ATTR): Update.
289 * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0
294 * hppa.h (bb, bvb): Tweak opcode/mask.
299 * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs.
300 (struct cgen_cpu_desc): Rename member mach to machs. New member isas.
301 New members word_bitsize,default_insn_bitsize,base_insn-bitsize,
302 min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables.
303 Delete member max_insn_size.
304 (enum cgen_cpu_open_arg): New enum.
305 (cpu_open): Update prototype.
306 (cpu_open_1): Declare.
307 (cgen_set_cpu): Delete.
311 * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member.
312 (CGEN_OPERAND_NIL): New macro.
313 (CGEN_OPERAND): New member `type'.
314 (@arch@_cgen_operand_table): Delete decl.
315 (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete.
316 (CGEN_OPERAND_TABLE): New struct.
317 (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare.
318 (CGEN_OPINST): Pointer to operand table entry replaced with enum.
319 (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table',
320 now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to
321 {get,set}_{int,vma}_operand.
322 (@arch@_cgen_cpu_open): New arg `isa'.
323 (cgen_set_cpu): Ditto.
327 * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms.
331 * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE.
332 (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to
334 (CGEN_HW_TABLE): New struct.
335 (hw_table): Delete declaration.
336 (CGEN_OPERAND): Change member hw to hw_type, change type from pointer
337 to table entry to enum.
338 (CGEN_OPINST): Ditto.
339 (CGEN_CPU_TABLE): Change member hw_list to hw_table.
343 * alpha.h (AXP_OPCODE_EV6): New.
344 (AXP_OPCODE_NOPAL): Include it.
348 * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC.
349 All uses updated. New members int_insn_p, max_insn_size,
350 parse_operand,insert_operand,extract_operand,print_operand,
351 sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand,
352 get_vma_operand,set_vma_operand,parse_handlers,insert_handlers,
353 extract_handlers,print_handlers.
354 (CGEN_ATTR): Change type of num_nonbools to unsigned int.
355 (CGEN_ATTR_BOOL_OFFSET): New macro.
356 (CGEN_ATTR_MASK): Subtract it to compute bit number.
357 (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation.
358 (cgen_opcode_handler): Renamed from cgen_base.
359 (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated.
360 (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR,
362 (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global.
363 (enum cgen_opinst_type): Renamed from cgen_operand_instance_type.
364 (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated.
365 (CGEN_OPCODE,CGEN_IBASE): New types.
366 (CGEN_INSN): Rewrite.
367 (CGEN_{ASM,DIS}_HASH*): Delete.
368 (init_opcode_table,init_ibld_table): Declare.
369 (CGEN_INSN_ATTR): New type.
373 * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define.
374 (x_FP, d_FP, dls_FP, sldx_FP): Define.
375 Change *Suf definitions to include x and d suffixes.
376 (movsx): Use w_Suf and b_Suf.
378 (movs): Use bwld_Suf.
379 (fld): Change ordering. Use sld_FP.
380 (fild): Add Intel Syntax equivalent of fildq.
383 (fstp): Use sld_FP. Add x_FP version.
384 (fistp): LLongMem version for Intel Syntax.
385 (fcom, fcomp): Use sld_FP.
386 (fadd, fiadd, fsub): Use sld_FP.
388 (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP.
392 * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT,
397 * hppa.h (bv): Fix mask.
401 * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef.
403 (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto.
404 (CGEN_ATTR_TABLE): New member dfault.
408 * mips.h (MIPS16_INSN_BRANCH): New.
412 The following is part of a change made by Edith Epstein
414 changes by HP; HP did not create ChangeLog entries.
416 * hppa.h (completer_chars): list of chars to not put a space
421 * i386.h (i386_optab): Permit w suffix on processor control and
422 status word instructions.
426 * cgen.h (struct cgen_hw_entry): Delete const on attrs member.
427 (struct cgen_keyword_entry): Ditto.
428 (struct cgen_operand): Ditto.
429 (CGEN_IFLD): New typedef, with associated access macros.
430 (CGEN_IFMT): New typedef, with associated access macros.
431 (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'.
432 (CGEN_IVALUE): New typedef.
433 (struct cgen_insn): Delete const on syntax,attrs members.
434 `format' now points to format data. Type of `value' is now
436 (struct cgen_opcode_table): New member ifld_table.
440 * cgen.h (cgen_extract_fn): Update type of `base_insn' arg.
441 (CGEN_OPERAND_INSTANCE): New member `attrs'.
442 (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros.
443 (cgen_dis_lookup_insn): Update type of `base_insn' arg.
444 (cgen_opcode_table): Update type of dis_hash fn.
445 (extract_operand): Update type of `insn_value' arg.
449 * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete.
453 * mips.h (INSN_MULT): Added.
457 * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE.
461 * cgen.h (CGEN_INSN_INT): New typedef.
462 (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN.
463 (CGEN_INSN_BYTES): Renamed from cgen_insn_t.
464 (CGEN_INSN_BYTES_PTR): New typedef.
465 (CGEN_EXTRACT_INFO): New typedef.
466 (cgen_insert_fn,cgen_extract_fn): Update.
467 (cgen_opcode_table): New member `insn_endian'.
468 (assemble_insn,lookup_insn,lookup_get_insn_operands): Update.
469 (insert_operand,extract_operand): Update.
470 (cgen_get_insn_value,cgen_put_insn_value): Add prototypes.
474 * cgen.h (CGEN_ATTR_BOOLS): New macro.
475 (struct CGEN_HW_ENTRY): New member `attrs'.
476 (CGEN_HW_ATTR): New macro.
477 (struct CGEN_OPERAND_INSTANCE): New member `name'.
478 (CGEN_INSN_INVALID_P): New macro.
487 * i386.h (i386_optab): Add AMD 3DNow! instructions.
488 (AMD_3DNOW_OPCODE): Define.
492 * d30v.h (EITHER_BUT_PREFER_MU): Define.
496 * cgen.h (cgen_insn): #if 0 out element `cdx'.
500 Move all global state data into opcode table struct, and treat
501 opcode table as something that is "opened/closed".
502 * cgen.h (CGEN_OPCODE_DESC): New type.
503 (all fns): New first arg of opcode table descriptor.
504 (cgen_set_parse_operand_fn): Add prototype.
505 (cgen_current_machine,cgen_current_endian): Delete.
506 (CGEN_OPCODE_TABLE): New members mach,endian,operand_table,
507 parse_operand_fn,asm_hash_table,asm_hash_table_entries,
508 dis_hash_table,dis_hash_table_entries.
509 (opcode_open,opcode_close): Add prototypes.
511 * cgen.h (cgen_insn): New element `cdx'.
515 * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions.
519 * mn10300.h: Add "no_match_operands" field for instructions.
520 (MN10300_MAX_OPERANDS): Define.
524 * cgen.h (cgen_macro_insn_count): Declare.
528 * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define.
529 (cgen_insert_fn,cgen_extract_fn): New arg `pc'.
530 (get_operand,put_operand): Replaced with get_{int,vma}_operand,
531 set_{int,vma}_operand.
535 * mn10300.h: Add "machine" field for instructions.
536 (MN103, AM30): Define machine types.
540 * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor.
544 * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit.
548 * i386.h (i386_optab): Add general form of aad and aam. Add ud2a
550 (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just
551 those that happen to be implemented on pentiums.
555 * i386.h: Change occurences of Data16 to Size16, Data32 to Size32,
556 IgnoreDataSize to IgnoreSize. Flag address and data size prefixes
557 with Size16|IgnoreSize or Size32|IgnoreSize.
561 * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE.
562 (REPE): Rename to REPE_PREFIX_OPCODE.
563 (i386_regtab_end): Remove.
564 (i386_prefixtab, i386_prefixtab_end): Remove.
565 (i386_optab): Use NULL as sentinel rather than "" to suit rewrite
567 (MAX_OPCODE_SIZE): Define.
568 (i386_optab_end): Remove.
572 * i386.h (i386_optab): Allow 16 bit displacement for `mov
573 mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16
574 bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32,
575 data32, dword, and adword prefixes.
576 (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index
581 * i386.h (i386_regtab): Remove BaseIndex modifier from esp.
583 * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with
584 register operands, because this is a common idiom. Flag them with
585 a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp,
586 fdivrp because gcc erroneously generates them. Also flag with a
589 * i386.h: Add suffix modifiers to most insns, and tighter operand
590 checks in some cases. Fix a number of UnixWare compatibility
591 issues with float insns. Merge some floating point opcodes, using
592 new FloatMF modifier.
593 (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for
596 * i386.h: Change occurence of ShortformW to W|ShortForm. Add
597 IgnoreDataSize where appropriate.
601 * i386.h: (one_byte_segment_defaults): Remove.
602 (two_byte_segment_defaults): Remove.
603 (i386_regtab): Add BaseIndex to 32 bit regs reg_type.
607 * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup.
608 (cgen_hw_lookup_by_num): Declare.
612 * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower
613 ten bits of MIPS ISA1 "break" instruction, and for "sdbbp"
617 * cgen.h (cgen_asm_init_parse): Delete.
618 (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete.
619 (cgen_asm_record_register,cgen_asm_finish_insn): Delete.
623 * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses.
624 (cgen_asm_finish_insn): Update prototype.
625 (cgen_insn): New members num, data.
626 (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size,
627 dis_hash, dis_hash_table_size moved to ...
628 (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA.
629 All uses updated. New members asm_hash_p, dis_hash_p.
630 (CGEN_MINSN_EXPANSION): New struct.
631 (cgen_expand_macro_insn): Declare.
632 (cgen_macro_insn_count): Declare.
633 (get_insn_operands): Update prototype.
634 (lookup_get_insn_operands): Declare.
638 * i386.h (i386_optab): Change iclrKludge and imulKludge to
639 regKludge. Add operands types for string instructions.
643 * i386.h (X): Renamed from `Z_' to preserve formatting of opcode
648 * i386.h (Z_): Renamed from `_' to avoid clash with common alias
653 * i386.h: Remove NoModrm flag from all insns: it's never checked.
654 Add IsString flag to string instructions.
655 (IS_STRING): Don't define.
656 (LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define.
657 (ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define.
658 (SS_PREFIX_OPCODE): Define.
662 * i386.h: Revert March 24 patch; no more LinearAddress.
666 * i386.h (i386_optab): Remove fwait (9b) from all floating point
667 instructions, and instead add FWait opcode modifier. Add short
668 form of fldenv and fstenv.
669 (FWAIT_OPCODE): Define.
671 * i386.h (i386_optab): Change second operand constraint of `mov
672 sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to
673 allow legal instructions such as `movl %gs,%esi'
677 * h8300.h: Various changes to fully bracket initializers.
681 * i386.h: Set LinearAddress for lidt and lgdt.
685 * cgen.h (CGEN_BOOL_ATTR): New macro.
689 * d30v.h (FLAG_DELAY): New flag for delayed branches/jumps.
693 * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now.
694 (cgen_insn): Record syntax and format entries here, rather than
699 * cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro.
703 * cgen.h (cgen_insert_fn): Change type of result to const char *.
704 (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments.
705 (CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS.
709 * cgen.h (lookup_insn): New argument alias_p.
713 Fix rac to accept only a0:
714 * d10v.h (OPERAND_ACC): Split into:
715 (OPERAND_ACC0, OPERAND_ACC1) .
716 (OPERAND_GPR): Define.
720 * cgen.h (CGEN_FIELDS): Define here.
721 (CGEN_HW_ENTRY): New member `type'.
722 (hw_list): Delete decl.
723 (enum cgen_mode): Declare.
724 (CGEN_OPERAND): New member `hw'.
725 (enum cgen_operand_instance_type): Declare.
726 (CGEN_OPERAND_INSTANCE): New type.
727 (CGEN_INSN): New member `operands'.
728 (CGEN_OPCODE_DATA): Make hw_list const.
729 (get_insn_operands,lookup_insn): Add prototypes for.
733 * cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS.
734 (CGEN_HW_ENTRY): Move `next' entry to end of struct.
735 (CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS.
736 (CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS.
740 * cgen.h: Correct typo in comment end marker.
748 * cgen.h: Add prototypes for cgen_save_fixups(),
749 cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype
750 of cgen_asm_finish_insn() to return a char *.
754 * cgen.h: Formatting changes to improve readability.
758 * cgen.h (*): Clean up pass over `struct foo' usage.
759 (CGEN_ATTR): Make unsigned char.
760 (CGEN_ATTR_TYPE): Update.
761 (CGEN_ATTR_{ENTRY,TABLE}): New types.
762 (cgen_base): Move member `attrs' to cgen_insn.
763 (CGEN_KEYWORD): New member `null_entry'.
764 (CGEN_{SYNTAX,FORMAT}): New types.
765 (cgen_insn): Format and syntax separated from each other.
769 * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for
770 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make
771 flags_{used,set} long.
772 (d30v_operand): Make flags field long.
776 * m68k.h: Fix comment describing operand types.
780 * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move
781 everything else after down.
785 * d10v.h (OPERAND_FLAG): Split into:
786 (OPERAND_FFLAG, OPERAND_CFLAG) .
790 * mips.h (struct mips_opcode): Changed comments to reflect new
795 * mips.h: Added to comments a quick-ref list of all assigned
796 operand type characters.
797 (OP_{MASK,SH}_PERFREG): New macros.
801 * sparc.h: Add '_' and '/' for v9a asr's.
806 * h8300.h: Bit ops with absolute addresses not in the 8 bit
807 area are not available in the base model (H8/300).
811 * m68k.h: Remove documentation of ` operand specifier.
815 * m68k.h: Document q and v operand specifiers.
819 * v850.h (struct v850_opcode): Add processors field.
820 (PROCESSOR_V850, PROCESSOR_ALL): New bit constants.
821 (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants.
822 (PROCESSOR_V850EA): New bit constants.
826 Merge changes from Martin Hunt:
828 * d30v.h: Allow up to 64 control registers. Add
831 * d30v.h (LONG_Db): New form for delayed branches.
833 * d30v.h: (LONG_Db): New form for repeati.
835 * d30v.h (SHORT_D2B): New form.
837 * d30v.h (SHORT_A2): New form.
839 * d30v.h (OPERAND_2REG): Add new operand to indicate 2
840 registers are used. Needed for VLIW optimization.
844 * cgen.h: Move assembler interface section
845 up so cgen_parse_operand_result is defined for cgen_parse_address.
846 (cgen_parse_address): Update prototype.
850 * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed.
854 * i386.h (two_byte_segment_defaults): Correct base register 5 in
855 modes 1 and 2 to be ss rather than ds. From Gabriel Paubert
858 * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert
861 * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert
864 * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again).
865 (JUMP_ON_ECX_ZERO): Remove commented out macro.
869 * v850.h (V850_NOT_R0): New flag.
873 * v850.h (struct v850_opcode): Remove flags field.
877 * v850.h (struct v850_opcode): Add flags field.
878 (struct v850_operand): Extend meaning of 'bits' and 'shift'
880 (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags.
881 (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags.
889 * sparc.h (sparc_opcodes): Declare as const.
893 * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn
894 uses single or double precision floating point resources.
895 (INSN_NO_ISA, INSN_ISA1): Define.
896 (cpu specific INSN macros): Tweak into bitmasks outside the range
901 * i386.h: Fix pand opcode.
905 * mips.h: Widen INSN_ISA and move it to a more convenient
906 bit position. Add INSN_3900.
910 * mips.h (struct mips_opcode): added new field membership.
914 * i386.h (movd): only Reg32 is allowed.
916 * i386.h: add fcomp and ud2. From Wayne Scott
921 * i386.h: Add MMX instructions.
925 * i386.h: Remove W modifier from conditional move instructions.
929 * i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp
930 with no arguments to match that generated by the UnixWare
935 * cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg.
936 (cgen_parse_operand_fn): Declare.
937 (cgen_init_parse_operand): Declare.
938 (cgen_parse_operand): Renamed from cgen_asm_parse_operand,
940 (enum cgen_parse_operand_result): Renamed from cgen_asm_result.
941 (enum cgen_parse_operand_type): New enum.
945 * i386.h: Revert last patch for the NON_BROKEN_OPCODES cases.
953 * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and
958 * v850.h (extract): Make unsigned.
966 * i386.h: Change DW to W for cmpxchg and xadd, since they don't
967 take a direction bit.
971 * sparc.h (sparc_opcode_lookup_arch): Use full prototype.
975 * sparc.h: Include <ansidecl.h>. Update function declarations to
976 use prototypes, and to use const when appropriate.
980 * mn10300.h (MN10300_OPERAND_RELAX): Define.
984 * d10v.h: Change pre_defined_registers to
985 d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
989 * mips.h: Add macros for cop0, cop1 cop2 and cop3.
990 Change mips_opcodes from const array to a pointer,
991 and change bfd_mips_num_opcodes from const int to int,
992 so that we can increase the size of the mips opcodes table
997 * d30v.h (FLAG_X): Remove unused flag.
1005 * tic80.h (PDS_NAME): Macro to access name field of predefined symbols.
1006 (PDS_VALUE): Macro to access value field of predefined symbols.
1007 (tic80_next_predefined_symbol): Add prototype.
1011 * tic80.h (tic80_symbol_to_value): Change prototype to match
1012 change in function, added class parameter.
1016 * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80
1017 endmask fields, which are somewhat weird in that 0 and 32 are
1018 treated exactly the same.
1022 * tic80.h: Change all the OPERAND defines to use the form (1 << X)
1023 rather than a constant that is 2**X. Reorder them to put bits for
1024 operands that have symbolic names in the upper bits, so they can
1025 be packed into an int where the lower bits contain the value that
1026 corresponds to that symbolic name.
1027 (predefined_symbo): Add struct.
1028 (tic80_predefined_symbols): Declare array of translations.
1029 (tic80_num_predefined_symbols): Declare size of that array.
1030 (tic80_value_to_symbol): Declare function.
1031 (tic80_symbol_to_value): Declare function.
1035 * mn10200.h (MN10200_OPERAND_RELAX): Define.
1039 * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot
1040 be the destination register.
1044 * tic80.h (struct tic80_opcode): Change "format" field to "flags".
1045 (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete.
1046 (TIC80_VECTOR): Define a flag bit for the flags. This one means
1047 that the opcode can have two vector instructions in a single
1048 32 bit word and we have to encode/decode both.
1052 * tic80.h (TIC80_OPERAND_PCREL): Renamed from
1053 TIC80_OPERAND_RELATIVE for PC relative.
1054 (TIC80_OPERAND_BASEREL): New flag bit for register
1059 * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands.
1063 * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional
1064 ":s" modifier for scaling.
1068 * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m".
1069 (TIC80_OPERAND_M_LI): Ditto
1073 * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ.
1074 (TIC80_OPERAND_CC): New define for condition code operand.
1075 (TIC80_OPERAND_CR): New define for control register operand.
1079 * tic80.h (struct tic80_opcode): Name changed.
1080 (struct tic80_opcode): Remove format field.
1081 (struct tic80_operand): Add insertion and extraction functions.
1082 (TIC80_OPERAND_*): Remove old bogus values, start adding new
1088 * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust
1089 type IV instruction offsets.
1093 * tic80.h: New file.
1097 * mn10200.h (MN10200_OPERAND_NOCHECK): Define.
1101 * mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
1102 * mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
1103 * v850.h: Fix comment, v850_operand not powerpc_operand.
1107 * mn10200.h: Flesh out structures and definitions needed by
1108 the mn10200 assembler & disassembler.
1112 * mips.h: Add mips16 definitions.
1116 * m68k.h: Document new <, >, m, n, o and p operand specifiers.
1120 * mn10300.h (MN10300_OPERAND_PCREL): Define.
1121 (MN10300_OPERAND_MEMADDR): Define.
1125 * mn10300.h (MN10300_OPERAND_REG_LIST): Define.
1129 * mn10300.h (MN10300_OPERAND_SPLIT): Define.
1133 * mn10300.h (MN10300_OPERAND_EXTENDED): Define.
1137 * mn10300.h (MN10300_OPERAND_REPEATED): Define.
1141 * alpha.h: Don't include "bfd.h"; private relocation types are now
1142 negative to minimize problems with shared libraries. Organize
1143 instruction subsets by AMASK extensions and PALcode
1145 (struct alpha_operand): Move flags slot for better packing.
1149 * v850.h (V850_OPERAND_RELAX): New operand flag.
1153 * mn10300.h (FMT_*): Move operand format definitions
1158 * mn10300.h (MN10300_OPERAND_PAREN): Define.
1162 * mn10300.h (mn10300_opcode): Add "format" field.
1163 (MN10300_OPERAND_*): Define.
1167 * mn10x00.h: Delete.
1168 * mn10200.h, mn10300.h: New files.
1172 * mn10x00.h: New file.
1176 * v850.h: Add new flag to indicate this instruction uses a PC
1181 * h8300.h (stmac): Add missing instruction.
1185 * v850.h (v850_opcode): Remove "size" field. Add "memop"
1190 * v850.h (V850_OPERAND_EP): Define.
1192 * v850.h (v850_opcode): Add size field.
1196 * v850.h (v850_operands): Add insert and extract fields, pointers
1197 to functions used to handle unusual operand encoding.
1198 (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
1199 V850_OPERAND_SIGNED): Defined.
1203 * v850.h (v850_operands): Add flags field.
1204 (OPERAND_REG, OPERAND_NUM): Defined.
1212 * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
1213 OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC,
1214 OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT,
1215 OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE,
1216 OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT):
1221 * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept
1222 a 3 bit space id instead of a 2 bit space id.
1226 * d10v.h: Add some additional defines to support the
1227 assembler in determining which operations can be done in parallel.
1231 * h8300.h (SN): Define.
1232 (eepmov.b): Renamed from "eepmov"
1233 (nop, bpt, rte, rts, sleep, clrmac): These have no size associated
1238 * d10v.h (OPERAND_SHIFT): New operand flag.
1242 * d10v.h: Changes for divs, parallel-only instructions, and
1247 * d10v.h (pd_reg): Define. Putting the definition here allows
1248 the assembler and disassembler to share the same struct.
1252 * i960.h (i960_opcodes): "halt" takes an argument. From Stephen
1261 * h8300.h (band, bclr): Force high bit of immediate nibble to zero.
1265 * m68k.h (mcf5200): New macro.
1266 Document names of coldfire control registers.
1270 * h8300.h (SRC_IN_DST): Define.
1272 * h8300.h (UNOP3): Mark the register operand in this insn
1273 as a source operand, not a destination operand.
1274 (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references.
1275 (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark
1276 register operand with SRC_IN_DST.
1280 * alpha.h: New file.
1284 * rs6k.h: Remove obsolete file.
1288 * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp,
1289 fdivp, and fdivrp. Add ffreep.
1293 * h8300.h: Reorder various #defines for readability.
1294 (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define.
1295 (BITOP): Accept additional (unused) argument. All callers changed.
1298 (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes.
1300 * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define.
1301 (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define.
1302 (BITOP, EBITOP): Handle new H8/S addressing modes for
1304 (UNOP3): Handle new shift/rotate insns on the H8/S.
1305 (insns using exr): New instructions.
1306 (tas, mac, ldmac, clrmac, ldm, stm): New instructions.
1310 * h8300.h (add.l): Undo Apr 5th change. The manual I had
1315 * h8300.h (START): Remove.
1316 (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w
1317 and mov.l insns that can be relaxed.
1321 * i386.h: Remove Abs32 from lcall.
1325 * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro.
1326 (SLCPOP): New macro.
1327 Mark X,Y opcode letters as in use.
1331 * sparc.h (F_FLOAT, F_FBR): Define.
1335 * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV
1337 (ABS8SRC,ABS8DST): Add ABS8MEM.
1338 (add.l): Fix reg+reg variant.
1339 (eepmov.w): Renamed from eepmovw.
1340 (ldc,stc): Fix many cases.
1344 * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro.
1348 * sparc.h (O): Mark operand letter as in use.
1352 * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare.
1353 Mark operand letters uU as in use.
1357 * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET.
1358 (sparc_opcode_arch): Delete member `conflicts'. Add `supported'.
1359 (SPARC_OPCODE_SUPPORTED): New macro.
1360 (SPARC_OPCODE_CONFLICT_P): Rewrite.
1365 * sparc.h (sparc_opcode_lookup_arch) Make return type in
1366 declaration consistent with return type in definition.
1370 * i386.h (i386_optab): Remove Data32 from pushf and popf.
1374 * i386.h (i386_regtab): Add 80486 test registers.
1378 * i960.h (I_HX): Define.
1379 (i960_opcodes): Add HX instruction.
1383 * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw,
1388 * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture.
1389 (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P.
1390 (bfd_* defines): Delete.
1391 (sparc_opcode_archs): Replaces architecture_pname.
1392 (sparc_opcode_lookup_arch): Declare.
1393 (NUMOPCODES): Delete.
1397 * sparc.h (enum sparc_architecture): Add v9a.
1398 (ARCHITECTURES_CONFLICT_P): Update.
1402 * i386.h: Added Pentium Pro instructions.
1406 * m68k.h: Document new 'W' operand place.
1410 * hppa.h: Add lci and syncdma instructions.
1414 * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific
1419 * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for
1420 assembler's -mcom and -many switches.
1424 * i386.h: Fix cmpxchg8b extension opcode description.
1428 * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b,
1433 * m68k.h: Change comment: split type P into types 0, 1 and 2.
1437 * sparc.h (sparc_{encode,decode}_prefetch): Declare.
1441 * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare.
1445 * m68kmri.h: Remove.
1447 * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the
1448 declarations. Remove F_ALIAS and flag field of struct
1449 m68k_opcode. Change arch field of struct m68k_opcode to unsigned
1450 int. Make name and args fields of struct m68k_opcode const.
1454 * sparc.h (F_NOTV9): Define.
1458 * mips.h (INSN_4010): Define.
1462 * m68k.h (TBL1): Reverse sense of "round" argument in result.
1465 * m68k.h: Fix argument descriptions of coprocessor
1466 instructions to allow only alterable operands where appropriate.
1467 [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'.
1468 (m68k_opcode_aliases): Add more aliases.
1472 * m68k.h: Added explcitly short-sized conditional branches, and a
1473 bunch of aliases (fmov*, ftest*, tdivul) to support gcc's
1474 svr4-based configurations.
1479 * i386.h: added missing Data16/Data32 flags to a few instructions.
1483 * mips.h (OP_MASK_FR, OP_SH_FR): Define.
1484 (OP_MASK_BCC, OP_SH_BCC): Define.
1485 (OP_MASK_PREFX, OP_SH_PREFX): Define.
1486 (OP_MASK_CCC, OP_SH_CCC): Define.
1487 (INSN_READ_FPR_R): Define.
1492 * m68k.h (enum m68k_architecture): Deleted.
1493 (struct m68k_opcode_alias): New type.
1494 (m68k_opcodes): Now const. Deleted opcode aliases with exactly
1495 matching constraints, values and flags. As a side effect of this,
1496 the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far
1497 as I know were never used, now may need re-examining.
1498 (numopcodes): Now const.
1499 (m68k_opcode_aliases, numaliases): New variables.
1501 [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and
1502 m68k_opcode_aliases; update declaration of m68k_opcodes.
1506 * hppa.h (delay_type): Delete unused enumeration.
1507 (pa_opcode): Replace unused delayed field with an architecture
1509 (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1.
1513 * mips.h (INSN_ISA4): Define.
1517 * mips.h (M_DLA_AB, M_DLI): Define.
1521 * hppa.h (fstwx): Fix single-bit error.
1525 * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
1529 * i386.h: added cpuid instruction , and dr[0-7] aliases for the
1536 * i386.h (MOV_AX_DISP32): New macro.
1537 (i386_optab): Added Data16 and Data32 as needed. Added "w" forms
1538 of several call/return instructions.
1539 (ADDR_PREFIX_OPCODE): New macro.
1545 * ../include/opcode/vax.h (struct vot_wot, field `args'): make
1546 it pointer to const char;
1547 (struct vot, field `name'): ditto.
1551 * vax.h: Supply and properly group all values in end sentinel.
1555 * mips.h (INSN_ISA, INSN_4650): Define.
1559 * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On
1560 systems with a separate instruction and data cache, such as the
1561 29040, these instructions take an optional argument.
1565 * mips.h (INSN_STORE_MEMORY): Correct value to not conflict with
1570 * mips.h (INSN_STORE_MEMORY): Define.
1574 * sparc.h: Document new operand type 'x'.
1578 * i960.h (I_CX2): New instruction category. It includes
1579 instructions available on Cx and Jx processors.
1580 (I_JX): New instruction category, for JX-only instructions.
1581 (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added
1582 Jx-only instructions, in I_JX category.
1586 * ns32k.h (endop): Made pointer const too.
1590 * ns32k.h: Drop Q operand type as there is no correct use
1591 for it. Add I and Z operand types which allow better checking.
1595 * h8300.h (xor.l) :fix bit pattern.
1596 (L_2): New size of operand.
1601 * m68k.h: Move "trap" before "tpcc" to change disassembly.
1605 * sparc.h: Include v9 definitions.
1609 * m68k.h (m68060): Defined.
1610 (m68040up, mfloat, mmmu): Include it.
1611 (struct m68k_opcode): Widen `arch' field.
1612 (m68k_opcodes): Updated for M68060. Removed comments that were
1613 instructions commented out by "JF" years ago.
1617 * m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and
1618 add a one-bit `flags' field.
1619 (F_ALIAS): New macro.
1623 * h8300.h (dec, inc): Get encoding right.
1627 * ppc.h (struct powerpc_operand): Removed signedp field; just use
1629 (PPC_OPERAND_SIGNED): Define.
1630 (PPC_OPERAND_SIGNOPT): Define.
1634 * i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size
1639 * i386.h: Reverse last change. It'll be handled in gas instead.
1643 * i386.h (sar): Disabled the two-operand Imm1 form, since it was
1644 slower on the 486 and used the implicit shift count despite the
1645 explicit operand. The one-operand form is still available to get
1646 the shorter form with the implicit shift count.
1650 * hppa.h: Fix typo in fstws arg string.
1654 * ppc.h (struct powerpc_opcode): Make operands field unsigned.
1658 * ppc.h (PPC_OPCODE_601): Define.
1662 * hppa.h (addb): Use '@' for addb and addib pseudo ops.
1663 (so we can determine valid completers for both addb and addb[tf].)
1665 * hppa.h (xmpyu): No floating point format specifier for the
1670 * ppc.h (PPC_OPERAND_NEXT): Define.
1671 (PPC_OPERAND_NEGATIVE): Change value to make room for above.
1672 (struct powerpc_macro): Define.
1673 (powerpc_macros, powerpc_num_macros): Declare.
1677 * ppc.h: New file. Header file for PowerPC opcode table.
1681 * hppa.h: More minor template fixes for sfu and copr (to allow
1682 for easier disassembly).
1684 * hppa.h: Fix templates for all the sfu and copr instructions.
1688 * i386.h (push): Permit Imm16 operand too.
1692 * h8300.h (andc): Exists in base arch.
1697 * hppa.h: #undef NONE to avoid conflict with hiux include files.
1701 * hppa.h: Add FP quadword store instructions.
1705 * mips.h: (M_J_A): Added.
1710 * mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define. From Ted Lemon
1715 * hppa.h: Immediate field in probei instructions is unsigned,
1716 not low-sign extended.
1720 * m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00.
1724 * i386.h: Add "fxch" without operand.
1728 * mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added.
1732 * hppa.h: Add gfw and gfr to the opcode table.
1736 * m88k.h: extended to handle m88110.
1740 * hppa.h (be, ble): Use operand type 'z' to denote absolute branch
1745 * i960.h (i960_opcodes): Properly bracket initializers.
1749 * m88k.h (BOFLAG): rewrite to avoid nested comment.
1753 * m68k.h (two): Protect second argument with parentheses.
1757 * i386.h (i386_optab): Added new instruction "rsm" (for i386sl).
1758 Deleted old in/out instructions in "#if 0" section.
1762 * i386.h (i386_optab): Properly bracket initializers.
1766 * hppa.h (pa_opcode): Use '|' for movb and movib insns. (From
1771 * i386.h (lcall): Accept Imm32 operand also.
1775 * mips.h (M_ABSU): Removed (absolute value of unsigned number??).
1780 * mips.h (INSN_*): Changed values. Removed unused definitions.
1781 Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3. Split
1782 INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and
1783 INSN_LOAD_COPROC_DELAY. Split INSN_COPROC_DELAY into
1784 INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY.
1785 (M_*): Added new values for r6000 and r4000 macros.
1786 (ANY_DELAY): Removed.
1790 * mips.h: Added M_LI_S and M_LI_SS.
1794 * h8300.h: Get some rare mov.bs correct.
1798 * sparc.h: Don't define const ourself; rely on ansidecl.h having
1803 * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark
1804 jump instructions, for use in disassemblers.
1808 * m88k.h: Make bitfields just unsigned, not unsigned long or
1813 * hppa.h: New argument type 'y'. Use in various float instructions.
1817 * hppa.h (break): First immediate field is unsigned.
1819 * hppa.h: Add rfir instruction.
1823 * mips.h: Split the actual table out into ../../opcodes/mips-opc.c.
1827 * mips.h: Reworked the hazard information somewhat, and fixed some
1828 bugs in the instruction hazard descriptions.
1832 * m88k.h: Corrected a couple of opcodes.
1836 * mips.h: Replaced with version from Ralph Campbell and OSF. The
1837 new version includes instruction hazard information, but is
1838 otherwise reasonably similar.
1842 * h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l).
1847 * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage.
1848 Make the tables be the same for the following instructions:
1849 "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco",
1850 "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o",
1851 "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio",
1852 "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs",
1853 "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt",
1854 "fcmp", and "ftest".
1856 * hppa.h: Make new and old tables the same for "break", "mtctl",
1857 "mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub".
1858 Fix typo in last patch. Collapse several #ifdefs into a
1861 * hppa.h: Delete remaining OLD_TABLE code. Bring some
1862 of the comments up-to-date.
1864 * hppa.h: Update "free list" of letters and update
1865 comments describing each letter's function.
1869 * h8300.h: checkpoint, includes H8/300-H opcodes.
1874 * hppa.h: Rework single precision FP
1875 instructions so that they correctly disassemble code
1880 * i386.h (i386_optab, mov pattern): Remove Mem16 restriction from
1881 mov to allow instructions like mov ss,xyz(ecx) to assemble.
1885 * hppa.h: Use new version from Utah if OLD_TABLE isn't defined;
1886 gdb will define it for now.
1890 * sparc.h: Don't end enumerator list with comma.
1895 * mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define.
1896 ("bc2t"): Correct typo.
1897 ("[ls]wc[023]"): Use T rather than t.
1898 ("c[0123]"): Define general coprocessor instructions.
1902 * m68k.h: Move split point for gcc compilation more towards
1907 * rs6k.h: Clean up instructions for primary opcode 19 (many were
1908 simply wrong, ics, rfi, & rfsvc were missing).
1909 Add "a" to opr_ext for "bb". Doc fix.
1914 * mips.h: Add casts, to suppress warnings about shifting too much.
1915 * m68k.h: Document the placement code '9'.
1919 * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which
1920 allows callers to break up the large initialized struct full of
1921 opcodes into two half-sized ones. This permits GCC to compile
1922 this module, since it takes exponential space for initializers.
1923 (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs.
1927 * a29k.h: Remove RCS crud, update GPL to v2, update copyrights.
1928 * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all
1929 initialized structs in it.
1934 * m88k.h (PMEM): Avoid previous definition from <sys/param.h>.
1935 (AND): Change to AND_ to avoid ansidecl.h `AND' conflict.
1939 * mips.h: document "i" and "j" operands correctly.
1943 * mips.h: Removed endianness dependency.
1947 * h8300.h: include info on number of cycles per instruction.
1949 Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com)
1951 * hppa.h: Move handy aliases to the front. Fix masks for extract
1952 and deposit instructions.
1956 * i386.h: accept shld and shrd both with and without the shift
1957 count argument, which is always %cl.
1959 Fri Nov 27 17:13:18 1992 Ken Raeburn (raeburn at cygnus.com)
1961 * i386.h (i386_optab_end, i386_regtab_end): Now const.
1962 (one_byte_segment_defaults, two_byte_segment_defaults,
1963 i386_prefixtab_end): Ditto.
1967 * vax.h (bb*): Use "v" (bitfield type), not "a" (address operand)
1972 * m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions
1973 always use 16-bit offsets. Makes calculated-size jump tables
1978 * i386.h: Fix one-operand forms of in* and out* patterns.
1982 * m68k.h: Added CPU32 support.
1986 * mips.h (break): Disassemble the argument. Patch from
1991 * m68k.h: merged Motorola and MIT syntax.
1995 * m68k.h (pmove): make the tests less strict, the 68k book is
2000 * m68k.h (m68ec030): Defined as alias for 68030.
2001 (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t"
2002 for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use
2003 them. Tightened description of "fmovex" to distinguish it from
2004 some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned
2005 up descriptions that claimed versions were available for chips not
2006 supporting them. Added "pmovefd".
2010 * m68k.h: fix where the . goes in divull
2014 * m68k.h: the cas2 instruction is supposed to be written with
2015 indirection on the last two operands, which can be either data or
2016 address registers. Added a new operand type 'r' which accepts
2017 either register type. Added new cases for cas2l and cas2w which
2018 use them. Corrected masks for cas2 which failed to recognize use
2019 of address register.
2023 * m68k.h: Merged in patches (mostly m68040-specific) from
2026 * m68k.h: Merged m68kmri.h and m68k.h (using the former as a
2027 base). Also cleaned up duplicates, re-ordered instructions for
2028 the sake of dis-assembling (so aliases come after standard names).
2029 * m68kmri.h: Now just defines some macros, and #includes m68k.h.
2033 * m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in
2038 * sparc.h: Moved tables to BFD library.
2040 * i386.h (i386_optab): Add fildq, fistpq aliases used by gcc.
2044 * h8300.h: Finish filling in all the holes in the opcode table,
2045 so that the Lucid C compiler can digest this as well...
2047 Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com)
2049 * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases.
2050 Fix opcodes on various sizes of fild/fist instructions
2051 (16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix).
2052 Use tabs to indent for comments. Fixes suggested by Minh Tran-Le.
2054 Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com)
2056 * h8300.h: Fill in all the holes in the opcode table so that the
2057 losing HPUX C compiler can digest this...
2059 Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com)
2061 * mips.h: Fix decoding of coprocessor instructions, somewhat.
2066 * sparc.h: Add new architecture variant sparclite; add its scan
2067 and divscc opcodes. Define ARCHITECTURES_CONFLICT_P macro.
2071 * mips.h: Add some more opcode synonyms (from Frank Yellin,
2076 * rs6k.h: New version from IBM (Metin).
2080 * rs6k.h: Fix incorrect extended opcode for instructions `fm'
2083 Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com)
2085 * rs6k.h: Move from ../../gdb/rs6k-opcode.h.
2089 * m68k.h (one, two): Cast macro args to unsigned to suppress
2090 complaints from compiler and lint about integer overflow during
2093 Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com)
2095 * sparc.h (OP): Avoid signed overflow when shifting to high order bit.
2097 Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com)
2099 * mips.h: Make bitfield layout depend on the HOST compiler,
2100 not on the TARGET system.
2104 * i386.h: added inb, inw, outb, outw opcodes, added att syntax for
2105 scmp, slod, smov, ssca, ssto. Curtesy Minh Tran-Le
2108 Thu Jan 30 07:31:44 1992 Steve Chamberlain (sac at rtl.cygnus.com)
2110 * h8300.h: turned op_type enum into #define list
2112 Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com)
2114 * sparc.h: Remove "cypress" architecture. Remove "fitox" and
2115 similar instructions -- they've been renamed to "fitoq", etc.
2116 REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong
2117 number of arguments.
2118 * h8300.h: Remove extra ; which produces compiler warning.
2120 Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com)
2122 * sparc.h: fix opcode for tsubcctv.
2124 Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com)
2126 * sparc.h: fba and cba are now aliases for fb and cb respectively.
2128 Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com)
2130 * sparc.h (nop): Made the 'lose' field be even tighter,
2131 so only a standard 'nop' is disassembled as a nop.
2133 Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com)
2135 * sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is
2136 disassembled as a nop.
2138 Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com)
2140 * sparc.h: fix a typo.
2142 Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com)
2144 * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h,
2145 m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h,
2146 vax.h, ChangeLog: renamed from ../<foo>-opcode.h
2150 version-control: never