opcodes/arm-dis.c

   1 /* Instruction printing code for the ARM
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3    Contributed by Richard Earnshaw ([email protected])
   4    Modification by James G. Smith ([email protected])
   5
   6    This file is part of libopcodes.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #include "sysdep.h"
  24
  25 #include "disassemble.h"
  26 #include "opcode/arm.h"
  27 #include "opintl.h"
  28 #include "safe-ctype.h"
  29 #include "libiberty.h"
  30 #include "floatformat.h"
  31
  32 /* FIXME: This shouldn't be done here.  */
  33 #include "coff/internal.h"
  34 #include "libcoff.h"
  35 #include "elf-bfd.h"
  36 #include "elf/internal.h"
  37 #include "elf/arm.h"
  38 #include "mach-o.h"
  39
  40 /* FIXME: Belongs in global header.  */
  41 #ifndef strneq
  42 #define strneq(a,b,n)   (strncmp ((a), (b), (n)) == 0)
  43 #endif
  44
  45 /* Cached mapping symbol state.  */
  46 enum map_type
  47 {
  48   MAP_ARM,
  49   MAP_THUMB,
  50   MAP_DATA
  51 };
  52
  53 struct arm_private_data
  54 {
  55   /* The features to use when disassembling optional instructions.  */
  56   arm_feature_set features;
  57
  58   /* Whether any mapping symbols are present in the provided symbol
  59      table.  -1 if we do not know yet, otherwise 0 or 1.  */
  60   int has_mapping_symbols;
  61
  62   /* Track the last type (although this doesn't seem to be useful) */
  63   enum map_type last_type;
  64
  65   /* Tracking symbol table information */
  66   int last_mapping_sym;
  67   bfd_vma last_mapping_addr;
  68 };
  69
  70 struct opcode32
  71 {
  72   arm_feature_set arch;         /* Architecture defining this insn.  */
  73   unsigned long value;          /* If arch is 0 then value is a sentinel.  */
  74   unsigned long mask;           /* Recognise insn if (op & mask) == value.  */
  75   const char *  assembler;      /* How to disassemble this insn.  */
  76 };
  77
  78 struct opcode16
  79 {
  80   arm_feature_set arch;         /* Architecture defining this insn.  */
  81   unsigned short value, mask;   /* Recognise insn if (op & mask) == value.  */
  82   const char *assembler;        /* How to disassemble this insn.  */
  83 };
  84
  85 /* print_insn_coprocessor recognizes the following format control codes:
  86
  87    %%                   %
  88
  89    %c                   print condition code (always bits 28-31 in ARM mode)
  90    %q                   print shifter argument
  91    %u                   print condition code (unconditional in ARM mode,
  92                           UNPREDICTABLE if not AL in Thumb)
  93    %A                   print address for ldc/stc/ldf/stf instruction
  94    %B                   print vstm/vldm register list
  95    %I                   print cirrus signed shift immediate: bits 0..3|4..6
  96    %F                   print the COUNT field of a LFM/SFM instruction.
  97    %P                   print floating point precision in arithmetic insn
  98    %Q                   print floating point precision in ldf/stf insn
  99    %R                   print floating point rounding mode
 100
 101    %<bitfield>c         print as a condition code (for vsel)
 102    %<bitfield>r         print as an ARM register
 103    %<bitfield>R         as %<>r but r15 is UNPREDICTABLE
 104    %<bitfield>ru        as %<>r but each u register must be unique.
 105    %<bitfield>d         print the bitfield in decimal
 106    %<bitfield>k         print immediate for VFPv3 conversion instruction
 107    %<bitfield>x         print the bitfield in hex
 108    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
 109    %<bitfield>f         print a floating point constant if >7 else a
 110                         floating point register
 111    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
 112    %<bitfield>g         print as an iWMMXt 64-bit register
 113    %<bitfield>G         print as an iWMMXt general purpose or control register
 114    %<bitfield>D         print as a NEON D register
 115    %<bitfield>Q         print as a NEON Q register
 116    %<bitfield>V         print as a NEON D or Q register
 117    %<bitfield>E         print a quarter-float immediate value
 118
 119    %y<code>             print a single precision VFP reg.
 120                           Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
 121    %z<code>             print a double precision VFP reg
 122                           Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
 123
 124    %<bitfield>'c        print specified char iff bitfield is all ones
 125    %<bitfield>`c        print specified char iff bitfield is all zeroes
 126    %<bitfield>?ab...    select from array of values in big endian order
 127
 128    %L                   print as an iWMMXt N/M width field.
 129    %Z                   print the Immediate of a WSHUFH instruction.
 130    %l                   like 'A' except use byte offsets for 'B' & 'H'
 131                         versions.
 132    %i                   print 5-bit immediate in bits 8,3..0
 133                         (print "32" when 0)
 134    %r                   print register offset address for wldt/wstr instruction.  */
 135
 136 enum opcode_sentinel_enum
 137 {
 138   SENTINEL_IWMMXT_START = 1,
 139   SENTINEL_IWMMXT_END,
 140   SENTINEL_GENERIC_START
 141 } opcode_sentinels;
 142
 143 #define UNDEFINED_INSTRUCTION      "\t\t; <UNDEFINED> instruction: %0-31x"
 144 #define UNPREDICTABLE_INSTRUCTION  "\t; <UNPREDICTABLE>"
 145
 146 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
 147
 148 static const struct opcode32 coprocessor_opcodes[] =
 149 {
 150   /* XScale instructions.  */
 151   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 152     0x0e200010, 0x0fff0ff0,
 153     "mia%c\tacc0, %0-3r, %12-15r"},
 154   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 155     0x0e280010, 0x0fff0ff0,
 156     "miaph%c\tacc0, %0-3r, %12-15r"},
 157   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 158     0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
 159   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 160     0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
 161   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 162     0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
 163
 164   /* Intel Wireless MMX technology instructions.  */
 165   {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
 166   {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
 167     0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
 168   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 169     0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
 170   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 171     0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
 172   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 173     0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
 174   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 175     0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
 176   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 177     0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
 178   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 179     0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
 180   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 181     0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
 182   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 183     0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
 184   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 185     0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
 186   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 187     0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
 188   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 189     0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
 190   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 191     0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
 192   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 193     0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
 194   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 195     0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
 196   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 197     0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
 198   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 199     0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
 200   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 201     0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 202   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 203     0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
 204   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 205     0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
 206   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 207     0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
 208   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 209     0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
 210   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 211     0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
 212   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 213     0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
 214   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 215     0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
 216   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 217     0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 218   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 219     0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 220   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 221     0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
 222   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 223     0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
 224   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 225     0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
 226   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 227     0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
 228   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 229     0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
 230   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 231     0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
 232   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 233     0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 234   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 235     0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
 236   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 237     0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 238   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 239     0x0e800120, 0x0f800ff0,
 240     "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 241   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 242     0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 243   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 244     0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
 245   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 246     0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
 247   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 248     0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
 249   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 250     0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
 251   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 252     0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
 253   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 254     0x0e8000a0, 0x0f800ff0,
 255     "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
 256   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 257     0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 258   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 259     0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
 260   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 261     0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
 262   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 263     0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 264   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 265     0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
 266   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 267     0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 268   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 269     0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
 270   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 271     0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
 272   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 273     0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
 274   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 275     0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
 276   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 277     0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 278   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 279     0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 280   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 281     0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
 282   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 283     0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 284   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 285     0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 286   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 287     0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
 288   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 289     0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
 290   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 291     0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
 292   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 293     0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
 294   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 295     0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
 296   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 297     0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
 298   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 299     0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
 300   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 301     0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
 302   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 303     0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 304   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 305     0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
 306   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 307     0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
 308   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 309     0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
 310   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 311     0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
 312   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 313     0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 314   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 315     0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
 316   {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
 317     0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
 318   {ARM_FEATURE_CORE_LOW (0),
 319     SENTINEL_IWMMXT_END, 0, "" },
 320
 321   /* Floating point coprocessor (FPA) instructions.  */
 322   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 323     0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 324   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 325     0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 326   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 327     0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 328   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 329     0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 330   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 331     0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 332   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 333     0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 334   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 335     0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
 336   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 337     0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
 338   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 339     0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
 340   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 341     0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
 342   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 343     0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
 344   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 345     0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
 346   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 347     0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
 348   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 349     0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
 350   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 351     0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
 352   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 353     0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
 354   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 355     0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
 356   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 357     0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
 358   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 359     0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
 360   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 361     0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
 362   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 363     0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
 364   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 365     0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
 366   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 367     0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
 368   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 369     0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
 370   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 371     0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
 372   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 373     0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
 374   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 375     0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
 376   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 377     0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
 378   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 379     0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
 380   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 381     0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
 382   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 383     0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
 384   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 385     0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
 386   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 387     0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
 388   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 389     0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
 390   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 391     0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
 392   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 393     0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
 394   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 395     0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
 396   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 397     0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
 398   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 399     0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
 400   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 401     0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
 402   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
 403     0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
 404   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 405     0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
 406   {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
 407     0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
 408
 409   /* ARMv8-M Mainline Security Extensions instructions.  */
 410   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 411     0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
 412   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
 413     0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
 414
 415   /* Register load/store.  */
 416   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 417     0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
 418   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 419     0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
 420   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 421     0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
 422   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 423     0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
 424   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 425     0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
 426   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 427     0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
 428   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 429     0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
 430   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
 431     0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
 432   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 433     0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
 434   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 435     0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
 436   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 437     0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
 438   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 439     0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
 440   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 441     0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
 442   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 443     0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
 444   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 445     0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
 446   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 447     0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
 448
 449   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 450     0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 451   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 452     0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
 453   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 454     0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 455   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 456     0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
 457
 458   /* Data transfer between ARM and NEON registers.  */
 459   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 460     0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
 461   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 462     0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
 463   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 464     0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
 465   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 466     0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
 467   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 468     0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
 469   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 470     0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
 471   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 472     0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
 473   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 474     0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
 475   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 476     0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
 477   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 478     0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
 479   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 480     0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
 481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 482     0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
 483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 484     0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
 485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
 486     0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
 487   /* Half-precision conversion instructions.  */
 488   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 489     0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
 490   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 491     0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
 492   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 493     0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
 494   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
 495     0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
 496
 497   /* Floating point coprocessor (VFP) instructions.  */
 498   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 499     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
 500   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 501     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
 502   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 503     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
 504   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 505     0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
 506   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 507     0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
 508   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 509     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
 510   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 511     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
 512   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 513     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
 514   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 515     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
 516   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 517     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
 518   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 519     0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
 520   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 521     0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
 522   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 523     0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
 524   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 525     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
 526   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 527     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
 528   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 529     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
 530   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 531     0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
 532   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 533     0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
 534   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 535     0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
 536   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 537     0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
 538   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 539     0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
 540   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 541     0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
 542   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 543     0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
 544   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 545     0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
 546   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 547     0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
 548   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 549     0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
 550   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 551     0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
 552   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 553     0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
 554   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 555     0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
 556   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 557     0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
 558   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 559     0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
 560   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 561     0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
 562   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 563     0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
 564   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 565     0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
 566   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 567     0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
 568   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 569     0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
 570   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 571     0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
 572   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 573     0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 574   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 575     0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
 576   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 577     0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
 578   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 579     0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
 580   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 581     0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
 582   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 583     0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
 584   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 585     0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
 586   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
 587     0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
 588   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
 589     0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
 590   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 591     0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
 592   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 593     0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
 594   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
 595     0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
 596   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 597     0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
 598   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 599     0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
 600   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 601     0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
 602   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 603     0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
 604   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 605     0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
 606   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 607     0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
 608   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 609     0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
 610   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 611     0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
 612   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 613     0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
 614   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 615     0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
 616   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 617     0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
 618   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 619     0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
 620   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 621     0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
 622   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 623     0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
 624   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 625     0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
 626   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 627     0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
 628   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
 629     0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
 630   {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
 631     0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
 632
 633   /* Cirrus coprocessor instructions.  */
 634   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 635     0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 636   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 637     0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
 638   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 639     0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 640   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 641     0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
 642   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 643     0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 644   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 645     0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
 646   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 647     0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 648   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 649     0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
 650   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 651     0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 652   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 653     0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
 654   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 655     0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 656   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 657     0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
 658   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 659     0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 660   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 661     0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
 662   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 663     0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 664   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 665     0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
 666   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 667     0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
 668   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 669     0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
 670   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 671     0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
 672   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 673     0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
 674   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 675     0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
 676   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 677     0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
 678   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 679     0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
 680   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 681     0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
 682   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 683     0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
 684   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 685     0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
 686   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 687     0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
 688   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 689     0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
 690   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 691     0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
 692   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 693     0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
 694   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 695     0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
 696   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 697     0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
 698   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 699     0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
 700   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 701     0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
 702   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 703     0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
 704   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 705     0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
 706   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 707     0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
 708   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 709     0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
 710   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 711     0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
 712   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 713     0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
 714   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 715     0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
 716   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 717     0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
 718   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 719     0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
 720   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 721     0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
 722   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 723     0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
 724   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 725     0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
 726   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 727     0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
 728   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 729     0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
 730   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 731     0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
 732   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 733     0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
 734   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 735     0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
 736   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 737     0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
 738   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 739     0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
 740   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 741     0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
 742   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 743     0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
 744   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 745     0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
 746   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 747     0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
 748   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 749     0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
 750   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 751     0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
 752   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 753     0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
 754   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 755     0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
 756   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 757     0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
 758   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 759     0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 760   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 761     0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 762   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 763     0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 764   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 765     0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 766   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 767     0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
 768   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 769     0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
 770   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 771     0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
 772   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 773     0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
 774   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 775     0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
 776   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 777     0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
 778   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 779     0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 780   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 781     0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 782   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 783     0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 784   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 785     0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 786   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 787     0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 788   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 789     0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
 790   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 791     0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 792   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 793     0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 794   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 795     0x0e000600, 0x0ff00f10,
 796     "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 797   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 798     0x0e100600, 0x0ff00f10,
 799     "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
 800   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 801     0x0e200600, 0x0ff00f10,
 802     "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 803   {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
 804     0x0e300600, 0x0ff00f10,
 805     "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
 806
 807   /* VFP Fused multiply add instructions.  */
 808   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 809     0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
 810   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 811     0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
 812   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 813     0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
 814   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 815     0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
 816   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 817     0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
 818   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 819     0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
 820   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 821     0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
 822   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
 823     0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
 824
 825   /* FP v5.  */
 826   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 827     0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
 828   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 829     0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
 830   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 831     0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
 832   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 833     0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
 834   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 835     0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
 836   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 837     0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
 838   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 839     0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
 840   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 841     0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
 842   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 843     0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
 844   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 845     0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
 846   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 847     0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
 848   {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
 849     0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
 850
 851   /* Generic coprocessor instructions.  */
 852   {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
 853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 854     0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
 855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
 856     0x0c500000, 0x0ff00000,
 857     "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 858   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 859     0x0e000000, 0x0f000010,
 860     "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 862     0x0e10f010, 0x0f10f010,
 863     "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
 864   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 865     0x0e100010, 0x0f100010,
 866     "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 868     0x0e000010, 0x0f100010,
 869     "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 870   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 871     0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
 872   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
 873     0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
 874
 875   /* V6 coprocessor instructions.  */
 876   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 877     0xfc500000, 0xfff00000,
 878     "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
 879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
 880     0xfc400000, 0xfff00000,
 881     "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
 882
 883   /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8.  */
 884   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 885     0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 886   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 887     0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
 888   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 889     0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 890   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 891     0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 892   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 893     0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
 894   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 895     0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
 896   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 897     0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
 898   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 899     0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
 900   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 901     0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
 902   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
 903     0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
 904
 905   /* Dot Product instructions in the space of coprocessor 13.  */
 906   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 907     0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
 908   {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
 909     0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
 910
 911   /* V5 coprocessor instructions.  */
 912   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 913     0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 914   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 915     0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
 916   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 917     0xfe000000, 0xff000010,
 918     "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
 919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 920     0xfe000010, 0xff100010,
 921     "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
 922   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
 923     0xfe100010, 0xff100010,
 924     "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
 925
 926   /* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
 927      cp_num: bit <11:8> == 0b1001.
 928      cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE.  */
 929   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 930     0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
 931   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 932     0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
 933   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 934     0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
 935   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 936     0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
 937   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 938     0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
 939   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 940     0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
 941   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 942     0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
 943   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 944     0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
 945   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 946     0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
 947   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 948     0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
 949   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 950     0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
 951   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 952     0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
 953   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 954     0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
 955   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 956     0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
 957   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 958     0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
 959   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 960     0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
 961   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 962     0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
 963   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 964     0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
 965   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 966     0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
 967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 968     0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
 969   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 970     0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
 971   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 972     0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
 973   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 974     0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
 975   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 976     0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
 977   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 978     0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
 979   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 980     0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
 981   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 982     0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
 983   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 984     0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
 985   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 986     0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
 987   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 988     0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
 989   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 990     0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
 991   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 992     0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
 993   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 994     0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
 995   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 996     0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
 997   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
 998     0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
 999
1000   /* ARMv8.3 javascript conversion instruction.  */
1001   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
1002     0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
1003
1004   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
1005 };
1006
1007 /* Neon opcode table:  This does not encode the top byte -- that is
1008    checked by the print_insn_neon routine, as it depends on whether we are
1009    doing thumb32 or arm32 disassembly.  */
1010
1011 /* print_insn_neon recognizes the following format control codes:
1012
1013    %%                   %
1014
1015    %c                   print condition code
1016    %u                   print condition code (unconditional in ARM mode,
1017                           UNPREDICTABLE if not AL in Thumb)
1018    %A                   print v{st,ld}[1234] operands
1019    %B                   print v{st,ld}[1234] any one operands
1020    %C                   print v{st,ld}[1234] single->all operands
1021    %D                   print scalar
1022    %E                   print vmov, vmvn, vorr, vbic encoded constant
1023    %F                   print vtbl,vtbx register list
1024
1025    %<bitfield>r         print as an ARM register
1026    %<bitfield>d         print the bitfield in decimal
1027    %<bitfield>e         print the 2^N - bitfield in decimal
1028    %<bitfield>D         print as a NEON D register
1029    %<bitfield>Q         print as a NEON Q register
1030    %<bitfield>R         print as a NEON D or Q register
1031    %<bitfield>Sn        print byte scaled width limited by n
1032    %<bitfield>Tn        print short scaled width limited by n
1033    %<bitfield>Un        print long scaled width limited by n
1034
1035    %<bitfield>'c        print specified char iff bitfield is all ones
1036    %<bitfield>`c        print specified char iff bitfield is all zeroes
1037    %<bitfield>?ab...    select from array of values in big endian order.  */
1038
1039 static const struct opcode32 neon_opcodes[] =
1040 {
1041   /* Extract.  */
1042   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1043     0xf2b00840, 0xffb00850,
1044     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1045   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1046     0xf2b00000, 0xffb00810,
1047     "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
1048
1049   /* Move data element to all lanes.  */
1050   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1051     0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
1052   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1053     0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
1054   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1055     0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
1056
1057   /* Table lookup.  */
1058   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1059     0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
1060   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1061     0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
1062
1063   /* Half-precision conversions.  */
1064   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1065     0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
1066   {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
1067     0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
1068
1069   /* NEON fused multiply add instructions.  */
1070   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1071     0xf2000c10, 0xffb00f10, "vfma%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1072   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1073     0xf2100c10, 0xffb00f10, "vfma%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1074   {ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA),
1075     0xf2200c10, 0xffb00f10, "vfms%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1076   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1077     0xf2300c10, 0xffb00f10, "vfms%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1078
1079   /* Two registers, miscellaneous.  */
1080   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1081     0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
1082   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1083     0xf3b60400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f16\t%12-15,22R, %0-3,5R"},
1084   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1085     0xf3bb0000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us32.f32\t%12-15,22R, %0-3,5R"},
1086   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1087     0xf3b70000, 0xffbf0c10, "vcvt%8-9?mpna%u.%7?us16.f16\t%12-15,22R, %0-3,5R"},
1088   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1089     0xf3b00300, 0xffbf0fd0, "aese%u.8\t%12-15,22Q, %0-3,5Q"},
1090   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1091     0xf3b00340, 0xffbf0fd0, "aesd%u.8\t%12-15,22Q, %0-3,5Q"},
1092   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1093     0xf3b00380, 0xffbf0fd0, "aesmc%u.8\t%12-15,22Q, %0-3,5Q"},
1094   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1095     0xf3b003c0, 0xffbf0fd0, "aesimc%u.8\t%12-15,22Q, %0-3,5Q"},
1096   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1097     0xf3b902c0, 0xffbf0fd0, "sha1h%u.32\t%12-15,22Q, %0-3,5Q"},
1098   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1099     0xf3ba0380, 0xffbf0fd0, "sha1su1%u.32\t%12-15,22Q, %0-3,5Q"},
1100   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1101     0xf3ba03c0, 0xffbf0fd0, "sha256su0%u.32\t%12-15,22Q, %0-3,5Q"},
1102   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1103     0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
1104   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1105     0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
1106   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1107     0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
1108   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1109     0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
1110   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1111     0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
1112   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1113     0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
1114   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1115     0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
1116   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1117     0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1118   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1119     0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
1120   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1121     0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
1122   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1123     0xf3b20300, 0xffb30fd0,
1124     "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
1125   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1126     0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1127   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1128     0xf3b70400, 0xffbf0e90, "vrecpe%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1129   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1130     0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
1131   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1132     0xf3b70480, 0xffbf0e90, "vrsqrte%c.%8?fu16\t%12-15,22R, %0-3,5R"},
1133   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1134     0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1135   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1136     0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1137   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1138     0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1139   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1140     0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1141   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1142     0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
1143   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1144     0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1145   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1146     0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
1147   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1148     0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1149   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1150     0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1151   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1152     0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
1153   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1154     0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1155   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1156     0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1157   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1158     0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1159   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1160     0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1161   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1162     0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
1163   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1164     0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1165   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1166     0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
1167   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1168     0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1169   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1170     0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
1171   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1172     0xf3bb0600, 0xffbf0e10,
1173     "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
1174   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1175     0xf3b70600, 0xffbf0e10,
1176     "vcvt%c.%7-8?usff16.%7-8?ffus16\t%12-15,22R, %0-3,5R"},
1177
1178   /* Three registers of the same length.  */
1179   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1180     0xf2000c40, 0xffb00f50, "sha1c%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1181   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1182     0xf2100c40, 0xffb00f50, "sha1p%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1183   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1184     0xf2200c40, 0xffb00f50, "sha1m%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1185   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1186     0xf2300c40, 0xffb00f50, "sha1su0%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1187   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1188     0xf3000c40, 0xffb00f50, "sha256h%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1189   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1190     0xf3100c40, 0xffb00f50, "sha256h2%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1191   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1192     0xf3200c40, 0xffb00f50, "sha256su1%u.32\t%12-15,22Q, %16-19,7Q, %0-3,5Q"},
1193   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1194     0xf3000f10, 0xffb00f10, "vmaxnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1195   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1196     0xf3100f10, 0xffb00f10, "vmaxnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1197   {ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
1198     0xf3200f10, 0xffb00f10, "vminnm%u.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1199   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1200     0xf3300f10, 0xffb00f10, "vminnm%u.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1201   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1202     0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1203   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1204     0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1205   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1206     0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1207   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1208     0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1209   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1210     0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1211   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1212     0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1213   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1214     0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1215   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1216     0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
1217   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1218     0xf2000d00, 0xffb00f10, "vadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1219   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1220     0xf2100d00, 0xffb00f10, "vadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1221   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1222     0xf2000d10, 0xffb00f10, "vmla%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1223   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1224     0xf2100d10, 0xffb00f10, "vmla%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1225   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1226     0xf2000e00, 0xffb00f10, "vceq%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1227   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1228     0xf2100e00, 0xffb00f10, "vceq%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1229   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1230     0xf2000f00, 0xffb00f10, "vmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1231   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1232     0xf2100f00, 0xffb00f10, "vmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1233   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1234     0xf2000f10, 0xffb00f10, "vrecps%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1235   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1236     0xf2100f10, 0xffb00f10, "vrecps%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1237   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1238     0xf2200d00, 0xffb00f10, "vsub%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1239   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1240     0xf2300d00, 0xffb00f10, "vsub%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1241   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1242     0xf2200d10, 0xffb00f10, "vmls%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1243   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1244     0xf2300d10, 0xffb00f10, "vmls%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1245   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1246     0xf2200f00, 0xffb00f10, "vmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1247   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1248     0xf2300f00, 0xffb00f10, "vmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1249   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1250     0xf2200f10, 0xffb00f10, "vrsqrts%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1251   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1252     0xf2300f10, 0xffb00f10, "vrsqrts%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1253   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1254     0xf3000d00, 0xffb00f10, "vpadd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1255   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1256     0xf3100d00, 0xffb00f10, "vpadd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1257   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1258     0xf3000d10, 0xffb00f10, "vmul%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1259   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1260     0xf3100d10, 0xffb00f10, "vmul%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1261   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1262     0xf3000e00, 0xffb00f10, "vcge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1263   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1264     0xf3100e00, 0xffb00f10, "vcge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1265   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1266     0xf3000e10, 0xffb00f10, "vacge%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1267   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1268     0xf3100e10, 0xffb00f10, "vacge%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1269   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1270     0xf3000f00, 0xffb00f10, "vpmax%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1271   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1272     0xf3100f00, 0xffb00f10, "vpmax%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1273   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1274     0xf3200d00, 0xffb00f10, "vabd%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1275   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1276     0xf3300d00, 0xffb00f10, "vabd%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1277   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1278     0xf3200e00, 0xffb00f10, "vcgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1279   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1280     0xf3300e00, 0xffb00f10, "vcgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1281   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1282     0xf3200e10, 0xffb00f10, "vacgt%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1283   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1284     0xf3300e10, 0xffb00f10, "vacgt%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1285   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1286     0xf3200f00, 0xffb00f10, "vpmin%c.f32\t%12-15,22R, %16-19,7R, %0-3,5R"},
1287   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1288     0xf3300f00, 0xffb00f10, "vpmin%c.f16\t%12-15,22R, %16-19,7R, %0-3,5R"},
1289   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1290     0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1291   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1292     0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1293   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1294     0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1295   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1296     0xf2000b00, 0xff800f10,
1297     "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1298   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1299     0xf2000b10, 0xff800f10,
1300     "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1301   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1302     0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1303   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1304     0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1305   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1306     0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1307   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1308     0xf3000b00, 0xff800f10,
1309     "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1310   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1311     0xf2000000, 0xfe800f10,
1312     "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1313   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1314     0xf2000010, 0xfe800f10,
1315     "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1316   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1317     0xf2000100, 0xfe800f10,
1318     "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1319   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1320     0xf2000200, 0xfe800f10,
1321     "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1322   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1323     0xf2000210, 0xfe800f10,
1324     "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
1325   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1326     0xf2000300, 0xfe800f10,
1327     "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1328   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1329     0xf2000310, 0xfe800f10,
1330     "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1331   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1332     0xf2000400, 0xfe800f10,
1333     "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1334   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1335     0xf2000410, 0xfe800f10,
1336     "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1337   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1338     0xf2000500, 0xfe800f10,
1339     "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1340   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1341     0xf2000510, 0xfe800f10,
1342     "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
1343   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1344     0xf2000600, 0xfe800f10,
1345     "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1346   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1347     0xf2000610, 0xfe800f10,
1348     "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1349   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1350     0xf2000700, 0xfe800f10,
1351     "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1352   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1353     0xf2000710, 0xfe800f10,
1354     "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1355   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1356     0xf2000910, 0xfe800f10,
1357     "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1358   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1359     0xf2000a00, 0xfe800f10,
1360     "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1361   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1362     0xf2000a10, 0xfe800f10,
1363     "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
1364   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1365     0xf3000b10, 0xff800f10,
1366     "vqrdmlah%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1367   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1368     0xf3000c10, 0xff800f10,
1369     "vqrdmlsh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
1370
1371   /* One register and an immediate value.  */
1372   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1373     0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
1374   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1375     0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
1376   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1377     0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
1378   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1379     0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
1380   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1381     0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
1382   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1383     0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
1384   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1385     0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
1386   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1387     0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
1388   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1389     0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
1390   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1391     0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
1392   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1393     0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
1394   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1395     0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
1396   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1397     0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
1398
1399   /* Two registers and a shift amount.  */
1400   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1401     0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1402   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1403     0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1404   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1405     0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1406   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1407     0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1408   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1409     0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1410   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1411     0xf2880950, 0xfeb80fd0,
1412     "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
1413   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1414     0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22Q, %0-3,5D, #%16-18d"},
1415   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1416     0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1417   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1418     0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1419   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1420     0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1421   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1422     0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
1423   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1424     0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
1425   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1426     0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
1427   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1428     0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1429   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1430     0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1431   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1432     0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1433   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1434     0xf2900950, 0xfeb00fd0,
1435     "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
1436   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1437     0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22Q, %0-3,5D, #%16-19d"},
1438   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1439     0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1440   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1441     0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1442   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1443     0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1444   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1445     0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
1446   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1447     0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
1448   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1449     0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1450   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1451     0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1452   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1453     0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1454   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1455     0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
1456   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1457     0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
1458   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1459     0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
1460   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1461     0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22Q, %0-3,5D, #%16-20d"},
1462   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1463     0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1464   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1465     0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1466   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1467     0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1468   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1469     0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
1470   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1471     0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
1472   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1473     0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1474   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1475     0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1476   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1477     0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1478   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1479     0xf2a00950, 0xfea00fd0,
1480     "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
1481   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1482     0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1483   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1484     0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
1485   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1486     0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
1487   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1488     0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
1489   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1490     0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1491   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1492     0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1493   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1494     0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1495   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1496     0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
1497   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1498     0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
1499   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1500     0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1501   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1502     0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
1503   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1504     0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
1505   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1506     0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
1507   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1508     0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1509   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1510     0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1511   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1512     0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1513   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1514     0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
1515   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1516     0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
1517   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1518     0xf2a00e10, 0xfea00e90,
1519     "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
1520   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
1521     0xf2a00c10, 0xfea00e90,
1522     "vcvt%c.%24,8?usff16.%24,8?ffus16\t%12-15,22R, %0-3,5R, #%16-20e"},
1523
1524   /* Three registers of different lengths.  */
1525   {ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8),
1526     0xf2a00e00, 0xfeb00f50, "vmull%c.p64\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1527   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1528     0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1529   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1530     0xf2800400, 0xff800f50,
1531     "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1532   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1533     0xf2800600, 0xff800f50,
1534     "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1535   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1536     0xf2800900, 0xff800f50,
1537     "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1538   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1539     0xf2800b00, 0xff800f50,
1540     "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1541   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1542     0xf2800d00, 0xff800f50,
1543     "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1544   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1545     0xf3800400, 0xff800f50,
1546     "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1547   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1548     0xf3800600, 0xff800f50,
1549     "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
1550   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1551     0xf2800000, 0xfe800f50,
1552     "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1553   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1554     0xf2800100, 0xfe800f50,
1555     "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1556   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1557     0xf2800200, 0xfe800f50,
1558     "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1559   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1560     0xf2800300, 0xfe800f50,
1561     "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
1562   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1563     0xf2800500, 0xfe800f50,
1564     "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1565   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1566     0xf2800700, 0xfe800f50,
1567     "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1568   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1569     0xf2800800, 0xfe800f50,
1570     "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1571   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1572     0xf2800a00, 0xfe800f50,
1573     "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1574   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1575     0xf2800c00, 0xfe800f50,
1576     "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
1577
1578   /* Two registers and a scalar.  */
1579   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1580     0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1581   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1582     0xf2800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1583   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1584     0xf2900140, 0xffb00f50, "vmla%c.f16\t%12-15,22D, %16-19,7D, %D"},
1585   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1586     0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1587   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1588     0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1589   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1590     0xf2800540, 0xff900f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1591   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1592     0xf2900540, 0xffb00f50, "vmls%c.f16\t%12-15,22D, %16-19,7D, %D"},
1593   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1594     0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1595   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1596     0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1597   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1598     0xf2800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
1599   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1600     0xf2900940, 0xffb00f50, "vmul%c.f16\t%12-15,22D, %16-19,7D, %D"},
1601   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1602     0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1603   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1604     0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1605   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1606     0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1607   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1608     0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1609   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1610     0xf3800140, 0xff900f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1611   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1612     0xf3900140, 0xffb00f50, "vmla%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1613   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1614     0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1615   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1616     0xf3800540, 0xff900f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1617   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1618     0xf3900540, 0xffb00f50, "vmls%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1619   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1620     0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1621   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1622     0xf3800940, 0xff900f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
1623   {ARM_FEATURE_COPROC (ARM_EXT2_FP16_INST),
1624     0xf3900940, 0xffb00f50, "vmul%c.f16\t%12-15,22Q, %16-19,7Q, %D"},
1625   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1626     0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1627   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1628     0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1629   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1630     0xf2800240, 0xfe800f50,
1631     "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1632   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1633     0xf2800640, 0xfe800f50,
1634     "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1635   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1636     0xf2800a40, 0xfe800f50,
1637     "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
1638   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1639     0xf2800e40, 0xff800f50,
1640    "vqrdmlah%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1641   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1642     0xf2800f40, 0xff800f50,
1643    "vqrdmlsh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
1644   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1645     0xf3800e40, 0xff800f50,
1646    "vqrdmlah%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
1647   {ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA),
1648     0xf3800f40, 0xff800f50,
1649    "vqrdmlsh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"
1650   },
1651
1652   /* Element and structure load/store.  */
1653   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1654     0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
1655   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1656     0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
1657   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1658     0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
1659   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1660     0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
1661   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1662     0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
1663   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1664     0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1665   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1666     0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1667   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1668     0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1669   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1670     0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
1671   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1672     0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1673   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1674     0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1675   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1676     0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1677   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1678     0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
1679   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1680     0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
1681   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1682     0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
1683   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1684     0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
1685   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1686     0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
1687   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1688     0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
1689   {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
1690     0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
1691
1692   {ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
1693 };
1694
1695 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
1696    ordered: they must be searched linearly from the top to obtain a correct
1697    match.  */
1698
1699 /* print_insn_arm recognizes the following format control codes:
1700
1701    %%                   %
1702
1703    %a                   print address for ldr/str instruction
1704    %s                   print address for ldr/str halfword/signextend instruction
1705    %S                   like %s but allow UNPREDICTABLE addressing
1706    %b                   print branch destination
1707    %c                   print condition code (always bits 28-31)
1708    %m                   print register mask for ldm/stm instruction
1709    %o                   print operand2 (immediate or register + shift)
1710    %p                   print 'p' iff bits 12-15 are 15
1711    %t                   print 't' iff bit 21 set and bit 24 clear
1712    %B                   print arm BLX(1) destination
1713    %C                   print the PSR sub type.
1714    %U                   print barrier type.
1715    %P                   print address for pli instruction.
1716
1717    %<bitfield>r         print as an ARM register
1718    %<bitfield>T         print as an ARM register + 1
1719    %<bitfield>R         as %r but r15 is UNPREDICTABLE
1720    %<bitfield>{r|R}u    as %{r|R} but if matches the other %u field then is UNPREDICTABLE
1721    %<bitfield>{r|R}U    as %{r|R} but if matches the other %U field then is UNPREDICTABLE
1722    %<bitfield>d         print the bitfield in decimal
1723    %<bitfield>W         print the bitfield plus one in decimal
1724    %<bitfield>x         print the bitfield in hex
1725    %<bitfield>X         print the bitfield as 1 hex digit without leading "0x"
1726
1727    %<bitfield>'c        print specified char iff bitfield is all ones
1728    %<bitfield>`c        print specified char iff bitfield is all zeroes
1729    %<bitfield>?ab...    select from array of values in big endian order
1730
1731    %e                   print arm SMI operand (bits 0..7,8..19).
1732    %E                   print the LSB and WIDTH fields of a BFI or BFC instruction.
1733    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.
1734    %R                   print the SPSR/CPSR or banked register of an MRS.  */
1735
1736 static const struct opcode32 arm_opcodes[] =
1737 {
1738   /* ARM instructions.  */
1739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1740     0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
1741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
1742     0xe7f000f0, 0xfff000f0, "udf\t#%e"},
1743
1744   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5),
1745     0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
1746   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1747     0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
1748   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
1749     0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1750   {ARM_FEATURE_CORE_LOW (ARM_EXT_V2S),
1751     0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
1752   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1753     0x00800090, 0x0fa000f0,
1754     "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3M),
1756     0x00a00090, 0x0fa000f0,
1757     "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
1758
1759   /* V8.2 RAS extension instructions.  */
1760   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
1761     0xe320f010, 0xffffffff, "esb"},
1762
1763   /* V8 instructions.  */
1764   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1765     0x0320f005, 0x0fffffff, "sevl"},
1766   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1767     0xe1000070, 0xfff000f0, "hlt\t0x%16-19X%12-15X%8-11X%0-3X"},
1768   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS),
1769     0x01800e90, 0x0ff00ff0, "stlex%c\t%12-15r, %0-3r, [%16-19R]"},
1770   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1771     0x01900e9f, 0x0ff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
1772   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1773     0x01a00e90, 0x0ff00ff0, "stlexd%c\t%12-15r, %0-3r, %0-3T, [%16-19R]"},
1774   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
1775     0x01b00e9f, 0x0ff00fff, "ldaexd%c\t%12-15r, %12-15T, [%16-19R]"},
1776   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1777     0x01c00e90, 0x0ff00ff0, "stlexb%c\t%12-15r, %0-3r, [%16-19R]"},
1778   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1779     0x01d00e9f, 0x0ff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
1780   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1781     0x01e00e90, 0x0ff00ff0, "stlexh%c\t%12-15r, %0-3r, [%16-19R]"},
1782   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1783     0x01f00e9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
1784   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1785     0x0180fc90, 0x0ff0fff0, "stl%c\t%0-3r, [%16-19R]"},
1786   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1787     0x01900c9f, 0x0ff00fff, "lda%c\t%12-15r, [%16-19R]"},
1788   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1789     0x01c0fc90, 0x0ff0fff0, "stlb%c\t%0-3r, [%16-19R]"},
1790   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1791     0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
1792   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1793     0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
1794   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
1795     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
1796   /* CRC32 instructions.  */
1797   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1798     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
1799   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1800     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
1801   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1802     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
1803   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1804     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
1805   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1806     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
1807   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
1808     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
1809
1810   /* Privileged Access Never extension instructions.  */
1811   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
1812     0xf1100000, 0xfffffdff, "setpan\t#%9-9d"},
1813
1814   /* Virtualization Extension instructions.  */
1815   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x0160006e, 0x0fffffff, "eret%c"},
1816   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
1817
1818   /* Integer Divide Extension instructions.  */
1819   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1820     0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
1821   {ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
1822     0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
1823
1824   /* MP Extension instructions.  */
1825   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP), 0xf410f000, 0xfc70f000, "pldw\t%a"},
1826
1827   /* V7 instructions.  */
1828   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf450f000, 0xfd70f000, "pli\t%P"},
1829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
1830   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff051, 0xfffffff3, "dmb\t%U"},
1831   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf57ff041, 0xfffffff3, "dsb\t%U"},
1832   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"},
1833   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"},
1834   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"},
1835    {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
1836     0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"},
1837
1838   /* ARM V6T2 instructions.  */
1839   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1840     0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
1841   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1842     0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
1843   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1844     0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
1845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1846     0x002000b0, 0x0f3000f0, "strht%c\t%12-15R, %S"},
1847
1848   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1849     0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
1850   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1851     0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
1852
1853   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1854     0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
1855   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
1856     0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
1857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1858     0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
1859   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
1860     0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
1861
1862   /* ARM Security extension instructions.  */
1863   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
1864     0x01600070, 0x0ff000f0, "smc%c\t%e"},
1865
1866   /* ARM V6K instructions.  */
1867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1868     0xf57ff01f, 0xffffffff, "clrex"},
1869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1870     0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
1871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1872     0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
1873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1874     0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
1875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1876     0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
1877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1878     0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
1879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1880     0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
1881
1882   /* ARM V6K NOP hints.  */
1883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1884     0x0320f001, 0x0fffffff, "yield%c"},
1885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1886     0x0320f002, 0x0fffffff, "wfe%c"},
1887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1888     0x0320f003, 0x0fffffff, "wfi%c"},
1889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1890     0x0320f004, 0x0fffffff, "sev%c"},
1891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
1892     0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
1893
1894   /* ARM V6 instructions.  */
1895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1896     0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
1897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1898     0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
1899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1900     0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
1901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1902     0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
1903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1904     0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
1905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1906     0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
1907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1908     0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
1909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1910     0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
1911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1912     0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
1913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1914     0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
1915   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1916     0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
1917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1918     0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
1919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1920     0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
1921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1922     0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
1923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1924     0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
1925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1926     0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
1927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1928     0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
1929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1930     0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
1931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1932     0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
1933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1934     0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
1935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1936     0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
1937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1938     0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
1939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1940     0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
1941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1942     0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
1943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1944     0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
1945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1946     0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
1947   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1948     0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
1949   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1950     0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
1951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1952     0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
1953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1954     0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
1955   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1956     0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
1957   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1958     0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
1959   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1960     0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
1961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1962     0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
1963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1964     0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
1965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1966     0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
1967   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1968     0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
1969   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1970     0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
1971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1972     0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
1973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1974     0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
1975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1976     0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
1977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1978     0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
1979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1980     0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
1981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1982     0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
1983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1984     0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
1985   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1986     0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
1987   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1988     0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
1989   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1990     0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
1991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1992     0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
1993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1994     0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
1995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1996     0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
1997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
1998     0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
1999   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2000     0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
2001   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2002     0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
2003   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2004     0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
2005   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2006     0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
2007   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2008     0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
2009   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2010     0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
2011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2012     0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
2013   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2014     0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
2015   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2016     0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
2017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2018     0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
2019   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2020     0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
2021   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2022     0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
2023   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2024     0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
2025   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2026     0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
2027   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2028     0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
2029   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2030     0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
2031   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2032     0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
2033   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2034     0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
2035   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2036     0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
2037   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2038     0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
2039   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2040     0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
2041   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2042     0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
2043   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2044     0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
2045   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2046     0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2047   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2048     0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2050     0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2052     0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
2053   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2054     0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2056     0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2058     0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2060     0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
2061   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2062     0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2063   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2064     0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2066     0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2068     0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
2069   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2070     0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2071   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2072     0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2074     0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2075   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2076     0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
2077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2078     0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2079   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2080     0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2082     0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
2083   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2084     0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
2085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2086     0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
2087   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2088     0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
2089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2090     0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
2091   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2092     0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
2093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2094     0xf1010000, 0xfffffc00, "setend\t%9?ble"},
2095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2096     0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
2097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2098     0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
2099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2100     0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2102     0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2103   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2104     0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2105   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2106     0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2107   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2108     0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
2109   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2110     0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2112     0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2114     0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
2115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2116     0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
2117   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2118     0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
2119   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2120     0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
2121   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2122     0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
2123   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2124     0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
2125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2126     0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
2127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2128     0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
2129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2130     0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2132     0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
2133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2134     0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
2135   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2136     0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
2137   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
2138     0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
2139
2140   /* V5J instruction.  */
2141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5J),
2142     0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
2143
2144   /* V5 Instructions.  */
2145   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2146     0xe1200070, 0xfff000f0,
2147     "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
2148   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2149     0xfa000000, 0xfe000000, "blx\t%B"},
2150   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2151     0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
2152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
2153     0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
2154
2155   /* V5E "El Segundo" Instructions.  */
2156   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2157     0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
2158   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2159     0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
2160   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
2161     0xf450f000, 0xfc70f000, "pld\t%a"},
2162   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2163     0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2164   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2165     0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2166   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2167     0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2168   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2169     0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
2170
2171   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2172     0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
2173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2174     0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
2175
2176   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2177     0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2178   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2179     0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2180   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2181     0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2182   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2183     0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
2184
2185   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2186     0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
2187   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2188     0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
2189   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2190     0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
2191   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2192     0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
2193
2194   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2195     0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
2196   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2197     0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
2198
2199   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2200     0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15R, %0-3R, %16-19R"},
2201   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2202     0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
2203   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2204     0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15R, %0-3R, %16-19R"},
2205   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP),
2206     0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
2207
2208   /* ARM Instructions.  */
2209   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2210     0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
2211
2212   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2213     0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
2214   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2215     0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
2216   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2217     0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
2218   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2219     0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
2220   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2221     0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
2222   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2223     0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
2224
2225   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2226     0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
2227   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2228     0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
2229   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2230     0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
2231   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2232     0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
2233
2234   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2235     0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
2236   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2237     0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
2238   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2239     0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
2240   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2241     0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
2242
2243   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2244     0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
2245   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2246     0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
2247   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2248     0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
2249
2250   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2251     0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
2252   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2253     0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
2254   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2255     0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
2256
2257   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2258     0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
2259   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2260     0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
2261   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2262     0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
2263
2264   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2265     0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2266   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2267     0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
2268   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2269     0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
2270
2271   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2272     0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
2273   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2274     0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
2275   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2276     0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
2277
2278   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2279     0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
2280   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2281     0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
2282   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2283     0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
2284
2285   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2286     0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2287   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2288     0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
2289   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2290     0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
2291
2292   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2293     0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2294   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2295     0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
2296   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2297     0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
2298
2299   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
2300     0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
2301   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2302     0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
2303   {ARM_FEATURE_CORE_LOW (ARM_EXT_V3),
2304     0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
2305
2306   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2307     0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
2308   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2309     0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
2310   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2311     0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
2312
2313   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2314     0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"},
2315   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2316     0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
2317   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2318     0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
2319
2320   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2321     0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
2322   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2323     0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
2324   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2325     0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
2326
2327   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2328     0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
2329   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2330     0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
2331   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2332     0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
2333
2334   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2335     0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
2336   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2337     0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
2338   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2339     0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
2340
2341   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2342     0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
2343   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2344     0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
2345   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2346     0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
2347   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2348     0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
2349   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2350     0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
2351   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2352     0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
2353   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2354     0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
2355
2356   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2357     0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
2358   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2359     0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
2360   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2361     0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
2362
2363   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2364     0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
2365   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2366     0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
2367   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2368     0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
2369
2370   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2371     0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
2372   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2373     0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
2374
2375   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2376     0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
2377
2378   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2379     0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
2380   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2381     0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
2382
2383   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2384     0x092d0001, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2385   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2386     0x092d0002, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2387   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2388     0x092d0004, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2389   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2390     0x092d0008, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2391   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2392     0x092d0010, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2393   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2394     0x092d0020, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2395   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2396     0x092d0040, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2397   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2398     0x092d0080, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2399   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2400     0x092d0100, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2401   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2402     0x092d0200, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2403   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2404     0x092d0400, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2405   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2406     0x092d0800, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2407   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2408     0x092d1000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2409   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2410     0x092d2000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2411   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2412     0x092d4000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2413   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2414     0x092d8000, 0x0fffffff, "stmfd%c\t%16-19R!, %m"},
2415   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2416     0x092d0000, 0x0fff0000, "push%c\t%m"},
2417   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2418     0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
2419   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2420     0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2421
2422   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2423     0x08bd0001, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2424   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2425     0x08bd0002, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2426   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2427     0x08bd0004, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2428   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2429     0x08bd0008, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2430   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2431     0x08bd0010, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2432   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2433     0x08bd0020, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2434   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2435     0x08bd0040, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2436   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2437     0x08bd0080, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2438   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2439     0x08bd0100, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2440   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2441     0x08bd0200, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2442   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2443     0x08bd0400, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2444   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2445     0x08bd0800, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2446   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2447     0x08bd1000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2448   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2449     0x08bd2000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2450   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2451     0x08bd4000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2452   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2453     0x08bd8000, 0x0fffffff, "ldmfd%c\t%16-19R!, %m"},
2454   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2455     0x08bd0000, 0x0fff0000, "pop%c\t%m"},
2456   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2457     0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
2458   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2459     0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
2460
2461   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2462     0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
2463   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2464     0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
2465
2466   /* The rest.  */
2467   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7),
2468     0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION},
2469   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
2470     0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
2471   {ARM_FEATURE_CORE_LOW (0),
2472     0x00000000, 0x00000000, 0}
2473 };
2474
2475 /* print_insn_thumb16 recognizes the following format control codes:
2476
2477    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
2478    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
2479    %<bitfield>I         print bitfield as a signed decimal
2480                                 (top bit of range being the sign bit)
2481    %N                   print Thumb register mask (with LR)
2482    %O                   print Thumb register mask (with PC)
2483    %M                   print Thumb register mask
2484    %b                   print CZB's 6-bit unsigned branch destination
2485    %s                   print Thumb right-shift immediate (6..10; 0 == 32).
2486    %c                   print the condition code
2487    %C                   print the condition code, or "s" if not conditional
2488    %x                   print warning if conditional an not at end of IT block"
2489    %X                   print "\t; unpredictable <IT:code>" if conditional
2490    %I                   print IT instruction suffix and operands
2491    %W                   print Thumb Writeback indicator for LDMIA
2492    %<bitfield>r         print bitfield as an ARM register
2493    %<bitfield>d         print bitfield as a decimal
2494    %<bitfield>H         print (bitfield * 2) as a decimal
2495    %<bitfield>W         print (bitfield * 4) as a decimal
2496    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
2497    %<bitfield>B         print Thumb branch destination (signed displacement)
2498    %<bitfield>c         print bitfield as a condition code
2499    %<bitnum>'c          print specified char iff bit is one
2500    %<bitnum>?ab         print a if bit is one else print b.  */
2501
2502 static const struct opcode16 thumb_opcodes[] =
2503 {
2504   /* Thumb instructions.  */
2505
2506   /* ARMv8-M Security Extensions instructions.  */
2507   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
2508   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
2509
2510   /* ARM V8 instructions.  */
2511   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xbf50, 0xffff, "sevl%c"},
2512   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),  0xba80, 0xffc0, "hlt\t%0-5x"},
2513   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),  0xb610, 0xfff7, "setpan\t#%3-3d"},
2514
2515   /* ARM V6K no-argument instructions.  */
2516   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xffff, "nop%c"},
2517   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf10, 0xffff, "yield%c"},
2518   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf20, 0xffff, "wfe%c"},
2519   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf30, 0xffff, "wfi%c"},
2520   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf40, 0xffff, "sev%c"},
2521   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
2522
2523   /* ARM V6T2 instructions.  */
2524   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2525     0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
2526   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2527     0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
2528   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"},
2529
2530   /* ARM V6.  */
2531   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
2532   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
2533   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
2534   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
2535   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
2536   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
2537   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb650, 0xfff7, "setend\t%3?ble%X"},
2538   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
2539   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
2540   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
2541   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6), 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
2542
2543   /* ARM V5 ISA extends Thumb.  */
2544   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2545     0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
2546   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
2547   {ARM_FEATURE_CORE_LOW (ARM_EXT_V5T),
2548     0x4780, 0xff87, "blx%c\t%3-6r%x"},  /* note: 4 bit register number.  */
2549   /* ARM V4T ISA (Thumb v1).  */
2550   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2551     0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
2552   /* Format 4.  */
2553   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
2554   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
2555   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
2556   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
2557   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
2558   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
2559   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
2560   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
2561   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
2562   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
2563   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
2564   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
2565   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
2566   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
2567   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
2568   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
2569   /* format 13 */
2570   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
2571   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
2572   /* format 5 */
2573   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4700, 0xFF80, "bx%c\t%S%x"},
2574   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4400, 0xFF00, "add%c\t%D, %S"},
2575   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4500, 0xFF00, "cmp%c\t%D, %S"},
2576   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x4600, 0xFF00, "mov%c\t%D, %S"},
2577   /* format 14 */
2578   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xB400, 0xFE00, "push%c\t%N"},
2579   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xBC00, 0xFE00, "pop%c\t%O"},
2580   /* format 2 */
2581   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2582     0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
2583   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2584     0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
2585   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2586     0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
2587   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2588     0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
2589   /* format 8 */
2590   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2591     0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
2592   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2593     0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
2594   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2595     0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
2596   /* format 7 */
2597   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2598     0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2599   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2600     0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
2601   /* format 1 */
2602   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
2603   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2604     0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
2605   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
2606   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
2607   /* format 3 */
2608   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
2609   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
2610   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
2611   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
2612   /* format 6 */
2613   /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
2614   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2615     0x4800, 0xF800,
2616     "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"},
2617   /* format 9 */
2618   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2619     0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
2620   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2621     0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
2622   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2623     0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
2624   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2625     0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
2626   /* format 10 */
2627   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2628     0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
2629   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2630     0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
2631   /* format 11 */
2632   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2633     0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
2634   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2635     0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
2636   /* format 12 */
2637   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2638     0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
2639   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
2640     0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
2641   /* format 15 */
2642   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
2643   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
2644   /* format 17 */
2645   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDF00, 0xFF00, "svc%c\t%0-7d"},
2646   /* format 16 */
2647   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFF00, "udf%c\t#%0-7d"},
2648   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
2649   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
2650   /* format 18 */
2651   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T), 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
2652
2653   /* The E800 .. FFFF range is unconditionally redirected to the
2654      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
2655      are processed via that table.  Thus, we can never encounter a
2656      bare "second half of BL/BLX(1)" instruction here.  */
2657   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),  0x0000, 0x0000, UNDEFINED_INSTRUCTION},
2658   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
2659 };
2660
2661 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
2662    We adopt the convention that hw1 is the high 16 bits of .value and
2663    .mask, hw2 the low 16 bits.
2664
2665    print_insn_thumb32 recognizes the following format control codes:
2666
2667        %%               %
2668
2669        %I               print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
2670        %M               print a modified 12-bit immediate (same location)
2671        %J               print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
2672        %K               print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
2673        %H               print a 16-bit immediate from hw2[3:0],hw1[11:0]
2674        %S               print a possibly-shifted Rm
2675
2676        %L               print address for a ldrd/strd instruction
2677        %a               print the address of a plain load/store
2678        %w               print the width and signedness of a core load/store
2679        %m               print register mask for ldm/stm
2680
2681        %E               print the lsb and width fields of a bfc/bfi instruction
2682        %F               print the lsb and width fields of a sbfx/ubfx instruction
2683        %b               print a conditional branch offset
2684        %B               print an unconditional branch offset
2685        %s               print the shift field of an SSAT instruction
2686        %R               print the rotation field of an SXT instruction
2687        %U               print barrier type.
2688        %P               print address for pli instruction.
2689        %c               print the condition code
2690        %x               print warning if conditional an not at end of IT block"
2691        %X               print "\t; unpredictable <IT:code>" if conditional
2692
2693        %<bitfield>d     print bitfield in decimal
2694        %<bitfield>D     print bitfield plus one in decimal
2695        %<bitfield>W     print bitfield*4 in decimal
2696        %<bitfield>r     print bitfield as an ARM register
2697        %<bitfield>R     as %<>r but r15 is UNPREDICTABLE
2698        %<bitfield>S     as %<>R but r13 is UNPREDICTABLE
2699        %<bitfield>c     print bitfield as a condition code
2700
2701        %<bitfield>'c    print specified char iff bitfield is all ones
2702        %<bitfield>`c    print specified char iff bitfield is all zeroes
2703        %<bitfield>?ab... select from array of values in big endian order
2704
2705    With one exception at the bottom (done because BL and BLX(1) need
2706    to come dead last), this table was machine-sorted first in
2707    decreasing order of number of bits set in the mask, then in
2708    increasing numeric order of mask, then in increasing numeric order
2709    of opcode.  This order is not the clearest for a human reader, but
2710    is guaranteed never to catch a special-case bit pattern with a more
2711    general mask, which is important, because this instruction encoding
2712    makes heavy use of special-case bit patterns.  */
2713 static const struct opcode32 thumb32_opcodes[] =
2714 {
2715   /* ARMv8-M and ARMv8-M Security Extensions instructions.  */
2716   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
2717   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2718     0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
2719   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2720     0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
2721   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2722     0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
2723   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
2724     0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
2725
2726   /* ARM V8.2 RAS extension instructions.  */
2727   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
2728     0xf3af8010, 0xffffffff, "esb"},
2729
2730   /* V8 instructions.  */
2731   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2732     0xf3af8005, 0xffffffff, "sevl%c.w"},
2733   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2734     0xf78f8000, 0xfffffffc, "dcps%0-1d"},
2735   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2736     0xe8c00f8f, 0xfff00fff, "stlb%c\t%12-15r, [%16-19R]"},
2737   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2738     0xe8c00f9f, 0xfff00fff, "stlh%c\t%12-15r, [%16-19R]"},
2739   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2740     0xe8c00faf, 0xfff00fff, "stl%c\t%12-15r, [%16-19R]"},
2741   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2742     0xe8c00fc0, 0xfff00ff0, "stlexb%c\t%0-3r, %12-15r, [%16-19R]"},
2743   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2744     0xe8c00fd0, 0xfff00ff0, "stlexh%c\t%0-3r, %12-15r, [%16-19R]"},
2745   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2746     0xe8c00fe0, 0xfff00ff0, "stlex%c\t%0-3r, %12-15r, [%16-19R]"},
2747   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2748     0xe8c000f0, 0xfff000f0, "stlexd%c\t%0-3r, %12-15r, %8-11r, [%16-19R]"},
2749   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2750     0xe8d00f8f, 0xfff00fff, "ldab%c\t%12-15r, [%16-19R]"},
2751   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2752     0xe8d00f9f, 0xfff00fff, "ldah%c\t%12-15r, [%16-19R]"},
2753   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2754     0xe8d00faf, 0xfff00fff, "lda%c\t%12-15r, [%16-19R]"},
2755   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2756     0xe8d00fcf, 0xfff00fff, "ldaexb%c\t%12-15r, [%16-19R]"},
2757   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2758     0xe8d00fdf, 0xfff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
2759   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2760     0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
2761   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8),
2762     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
2763
2764   /* CRC32 instructions.  */
2765   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2766     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
2767   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2768     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
2769   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2770     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
2771   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2772     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
2773   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2774     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
2775   {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
2776     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
2777
2778   /* V7 instructions.  */
2779   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf910f000, 0xff70f000, "pli%c\t%a"},
2780   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
2781   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f51, 0xfffffff3, "dmb%c\t%U"},
2782   {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3bf8f41, 0xfffffff3, "dsb%c\t%U"},
2783   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
2784   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
2785   {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
2786   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2787     0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
2788   {ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
2789     0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
2790
2791   /* Virtualization Extension instructions.  */
2792   {ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT), 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
2793   /* We skip ERET as that is SUBS pc, lr, #0.  */
2794
2795   /* MP Extension instructions.  */
2796   {ARM_FEATURE_CORE_LOW (ARM_EXT_MP),   0xf830f000, 0xff70f000, "pldw%c\t%a"},
2797
2798   /* Security extension instructions.  */
2799   {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),  0xf7f08000, 0xfff0f000, "smc%c\t%K"},
2800
2801   /* Instructions defined in the basic V6T2 set.  */
2802   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"},
2803   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"},
2804   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8002, 0xffffffff, "wfe%c.w"},
2805   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8003, 0xffffffff, "wfi%c.w"},
2806   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8004, 0xffffffff, "sev%c.w"},
2807   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2808     0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
2809   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"},
2810
2811   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2812     0xf3bf8f2f, 0xffffffff, "clrex%c"},
2813   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2814     0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
2815   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2816     0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
2817   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2818     0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
2819   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2820     0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
2821   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2822     0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
2823   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2824     0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
2825   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2826     0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
2827   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2828     0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
2829   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2830     0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
2831   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2832     0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
2833   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2834     0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
2835   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2836     0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
2837   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2838     0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
2839   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2840     0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
2841   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2842     0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
2843   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2844     0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
2845   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2846     0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
2847   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2848     0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
2849   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2850     0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
2851   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2852     0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
2853   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2854     0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
2855   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2856     0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
2857   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2858     0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
2859   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2860     0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
2861   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2862     0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
2863   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2864     0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
2865   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2866     0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
2867   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2868     0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
2869   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2870     0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
2871   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2872     0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
2873   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2874     0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
2875   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2876     0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
2877   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2878     0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
2879   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2880     0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
2881   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2882     0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
2883   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2884     0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
2885   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2886     0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
2887   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2888     0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
2889   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2890     0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
2891   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2892     0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
2893   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2894     0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
2895   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2896     0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
2897   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2898     0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
2899   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2900     0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
2901   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2902     0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
2903   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2904     0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
2905   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2906     0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
2907   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2908     0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
2909   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2910     0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
2911   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2912     0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
2913   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2914     0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
2915   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2916     0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
2917   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2918     0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
2919   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2920     0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
2921   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2922     0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
2923   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2924     0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
2925   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2926     0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
2927   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2928     0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
2929   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2930     0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
2931   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2932     0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
2933   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2934     0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
2935   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2936     0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
2937   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2938     0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
2939   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2940     0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
2941   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2942     0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
2943   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2944     0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
2945   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2946     0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
2947   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2948     0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
2949   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2950     0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
2951   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2952     0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
2953   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2954     0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
2955   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2956     0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
2957   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2958     0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
2959   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2960     0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2961   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2962     0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2963   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2964     0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
2965   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2966     0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
2967   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
2968     0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
2969   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2970     0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"},
2971   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2972     0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
2973   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2974     0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
2975   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2976     0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2977   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2978     0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
2979   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2980     0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
2981   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2982     0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2983   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2984     0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
2985   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2986     0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2987   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2988     0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
2989   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2990     0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2991   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2992     0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
2993   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2994     0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
2995   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2996     0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
2997   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
2998     0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
2999   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3000     0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3001   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3002     0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3003   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3004     0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3005   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3006     0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3007   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3008     0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3009   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3010     0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3011   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3012     0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3013   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3014     0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3015   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3016     0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3017   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3018     0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3019   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3020     0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3021   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3022     0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3023   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3024     0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3025   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3026     0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3027   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3028     0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3029   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3030     0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3031   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3032     0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3033   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3034     0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3035   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3036     0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3037   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3038     0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3039   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3040     0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3041   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3042     0xf810f000, 0xff70f000, "pld%c\t%a"},
3043   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3044     0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3045   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3046     0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3047   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3048     0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3049   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3050     0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3051   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3052     0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3053   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3054     0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3055   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3056     0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3057   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3058     0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3059   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3060     0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3061   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3062     0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3063   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3064     0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3065   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3066     0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3067   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3068     0xfb100000, 0xfff000c0,
3069     "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3070   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3071     0xfbc00080, 0xfff000c0,
3072     "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3073   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3074     0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3075   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3076     0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3077   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3078     0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4D, %16-19r%s"},
3079   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3080     0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3081   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3082     0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3083   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3084     0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3085   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3086     0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3087   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3088     0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3089   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3090     0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3091   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3092     0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3093   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3094     0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3095   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3096     0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3097   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3098     0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3099   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3100     0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3101   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3102     0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3103   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3104     0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3105   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3106     0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3107   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3108     0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3109   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M),
3110     0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3111   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3112     0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3113   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3114     0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3115   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3116     0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3117   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3118     0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3119   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3120     0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3121   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3122     0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3123   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3124     0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3125   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3126     0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3127   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3128     0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3129   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3130     0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3131   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3132     0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3133   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3134     0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3135   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3136     0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3137   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3138     0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3139   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3140     0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3141   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3142     0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3143   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3144     0xe9400000, 0xff500000,
3145     "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3146   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3147     0xe9500000, 0xff500000,
3148     "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3149   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3150     0xe8600000, 0xff700000,
3151     "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3152   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3153     0xe8700000, 0xff700000,
3154     "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3155   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3156     0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3157   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3158     0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3159
3160   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
3161   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3162     0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3163   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3164     0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3165   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3166     0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3167   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2),
3168     0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3169
3170   /* These have been 32-bit since the invention of Thumb.  */
3171   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3172      0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3173   {ARM_FEATURE_CORE_LOW (ARM_EXT_V4T),
3174      0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3175
3176   /* Fallback.  */
3177   {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
3178       0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3179   {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
3180 };
3181
3182 static const char *const arm_conditional[] =
3183 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3184  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3185
3186 static const char *const arm_fp_const[] =
3187 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3188
3189 static const char *const arm_shift[] =
3190 {"lsl", "lsr", "asr", "ror"};
3191
3192 typedef struct
3193 {
3194   const char *name;
3195   const char *description;
3196   const char *reg_names[16];
3197 }
3198 arm_regname;
3199
3200 static const arm_regname regnames[] =
3201 {
3202   { "reg-names-raw", N_("Select raw register names"),
3203     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3204   { "reg-names-gcc", N_("Select register names used by GCC"),
3205     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3206   { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
3207     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
3208   { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
3209   { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
3210   { "reg-names-apcs", N_("Select register names used in the APCS"),
3211     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
3212   { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
3213     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
3214   { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
3215     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }}
3216 };
3217
3218 static const char *const iwmmxt_wwnames[] =
3219 {"b", "h", "w", "d"};
3220
3221 static const char *const iwmmxt_wwssnames[] =
3222 {"b", "bus", "bc", "bss",
3223  "h", "hus", "hc", "hss",
3224  "w", "wus", "wc", "wss",
3225  "d", "dus", "dc", "dss"
3226 };
3227
3228 static const char *const iwmmxt_regnames[] =
3229 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3230   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3231 };
3232
3233 static const char *const iwmmxt_cregnames[] =
3234 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3235   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3236 };
3237
3238 /* Default to GCC register name set.  */
3239 static unsigned int regname_selected = 1;
3240
3241 #define NUM_ARM_OPTIONS   ARRAY_SIZE (regnames)
3242 #define arm_regnames      regnames[regname_selected].reg_names
3243
3244 static bfd_boolean force_thumb = FALSE;
3245
3246 /* Current IT instruction state.  This contains the same state as the IT
3247    bits in the CPSR.  */
3248 static unsigned int ifthen_state;
3249 /* IT state for the next instruction.  */
3250 static unsigned int ifthen_next_state;
3251 /* The address of the insn for which the IT state is valid.  */
3252 static bfd_vma ifthen_address;
3253 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3254 /* Indicates that the current Conditional state is unconditional or outside
3255    an IT block.  */
3256 #define COND_UNCOND 16
3257
3258 \f
3259 /* Functions.  */
3260
3261 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3262    Returns pointer to following character of the format string and
3263    fills in *VALUEP and *WIDTHP with the extracted value and number of
3264    bits extracted.  WIDTHP can be NULL.  */
3265
3266 static const char *
3267 arm_decode_bitfield (const char *ptr,
3268                      unsigned long insn,
3269                      unsigned long *valuep,
3270                      int *widthp)
3271 {
3272   unsigned long value = 0;
3273   int width = 0;
3274
3275   do
3276     {
3277       int start, end;
3278       int bits;
3279
3280       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3281         start = start * 10 + *ptr - '0';
3282       if (*ptr == '-')
3283         for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3284           end = end * 10 + *ptr - '0';
3285       else
3286         end = start;
3287       bits = end - start;
3288       if (bits < 0)
3289         abort ();
3290       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3291       width += bits + 1;
3292     }
3293   while (*ptr++ == ',');
3294   *valuep = value;
3295   if (widthp)
3296     *widthp = width;
3297   return ptr - 1;
3298 }
3299
3300 static void
3301 arm_decode_shift (long given, fprintf_ftype func, void *stream,
3302                   bfd_boolean print_shift)
3303 {
3304   func (stream, "%s", arm_regnames[given & 0xf]);
3305
3306   if ((given & 0xff0) != 0)
3307     {
3308       if ((given & 0x10) == 0)
3309         {
3310           int amount = (given & 0xf80) >> 7;
3311           int shift = (given & 0x60) >> 5;
3312
3313           if (amount == 0)
3314             {
3315               if (shift == 3)
3316                 {
3317                   func (stream, ", rrx");
3318                   return;
3319                 }
3320
3321               amount = 32;
3322             }
3323
3324           if (print_shift)
3325             func (stream, ", %s #%d", arm_shift[shift], amount);
3326           else
3327             func (stream, ", #%d", amount);
3328         }
3329       else if ((given & 0x80) == 0x80)
3330         func (stream, "\t; <illegal shifter operand>");
3331       else if (print_shift)
3332         func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3333               arm_regnames[(given & 0xf00) >> 8]);
3334       else
3335         func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3336     }
3337 }
3338
3339 #define W_BIT 21
3340 #define I_BIT 22
3341 #define U_BIT 23
3342 #define P_BIT 24
3343
3344 #define WRITEBACK_BIT_SET   (given & (1 << W_BIT))
3345 #define IMMEDIATE_BIT_SET   (given & (1 << I_BIT))
3346 #define NEGATIVE_BIT_SET   ((given & (1 << U_BIT)) == 0)
3347 #define PRE_BIT_SET         (given & (1 << P_BIT))
3348
3349 /* Print one coprocessor instruction on INFO->STREAM.
3350    Return TRUE if the instuction matched, FALSE if this is not a
3351    recognised coprocessor instruction.  */
3352
3353 static bfd_boolean
3354 print_insn_coprocessor (bfd_vma pc,
3355                         struct disassemble_info *info,
3356                         long given,
3357                         bfd_boolean thumb)
3358 {
3359   const struct opcode32 *insn;
3360   void *stream = info->stream;
3361   fprintf_ftype func = info->fprintf_func;
3362   unsigned long mask;
3363   unsigned long value = 0;
3364   int cond;
3365   int cp_num;
3366   struct arm_private_data *private_data = info->private_data;
3367   arm_feature_set allowed_arches = ARM_ARCH_NONE;
3368
3369   ARM_FEATURE_COPY (allowed_arches, private_data->features);
3370
3371   for (insn = coprocessor_opcodes; insn->assembler; insn++)
3372     {
3373       unsigned long u_reg = 16;
3374       bfd_boolean is_unpredictable = FALSE;
3375       signed long value_in_comment = 0;
3376       const char *c;
3377
3378       if (ARM_FEATURE_ZERO (insn->arch))
3379         switch (insn->value)
3380           {
3381           case SENTINEL_IWMMXT_START:
3382             if (info->mach != bfd_mach_arm_XScale
3383                 && info->mach != bfd_mach_arm_iWMMXt
3384                 && info->mach != bfd_mach_arm_iWMMXt2)
3385               do
3386                 insn++;
3387               while ((! ARM_FEATURE_ZERO (insn->arch))
3388                      && insn->value != SENTINEL_IWMMXT_END);
3389             continue;
3390
3391           case SENTINEL_IWMMXT_END:
3392             continue;
3393
3394           case SENTINEL_GENERIC_START:
3395             ARM_FEATURE_COPY (allowed_arches, private_data->features);
3396             continue;
3397
3398           default:
3399             abort ();
3400           }
3401
3402       mask = insn->mask;
3403       value = insn->value;
3404       cp_num = (given >> 8) & 0xf;
3405
3406       if (thumb)
3407         {
3408           /* The high 4 bits are 0xe for Arm conditional instructions, and
3409              0xe for arm unconditional instructions.  The rest of the
3410              encoding is the same.  */
3411           mask |= 0xf0000000;
3412           value |= 0xe0000000;
3413           if (ifthen_state)
3414             cond = IFTHEN_COND;
3415           else
3416             cond = COND_UNCOND;
3417         }
3418       else
3419         {
3420           /* Only match unconditional instuctions against unconditional
3421              patterns.  */
3422           if ((given & 0xf0000000) == 0xf0000000)
3423             {
3424               mask |= 0xf0000000;
3425               cond = COND_UNCOND;
3426             }
3427           else
3428             {
3429               cond = (given >> 28) & 0xf;
3430               if (cond == 0xe)
3431                 cond = COND_UNCOND;
3432             }
3433         }
3434
3435       if ((given & mask) != value)
3436         continue;
3437
3438       if (! ARM_CPU_HAS_FEATURE (insn->arch, allowed_arches))
3439         continue;
3440
3441       if (insn->value == 0xfe000010     /* mcr2  */
3442           || insn->value == 0xfe100010  /* mrc2  */
3443           || insn->value == 0xfc100000  /* ldc2  */
3444           || insn->value == 0xfc000000) /* stc2  */
3445         {
3446           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3447             is_unpredictable = TRUE;
3448         }
3449       else if (insn->value == 0x0e000000     /* cdp  */
3450                || insn->value == 0xfe000000  /* cdp2  */
3451                || insn->value == 0x0e000010  /* mcr  */
3452                || insn->value == 0x0e100010  /* mrc  */
3453                || insn->value == 0x0c100000  /* ldc  */
3454                || insn->value == 0x0c000000) /* stc  */
3455         {
3456           /* Floating-point instructions.  */
3457           if (cp_num == 9 || cp_num == 10 || cp_num == 11)
3458             continue;
3459         }
3460
3461       for (c = insn->assembler; *c; c++)
3462         {
3463           if (*c == '%')
3464             {
3465               switch (*++c)
3466                 {
3467                 case '%':
3468                   func (stream, "%%");
3469                   break;
3470
3471                 case 'A':
3472                   {
3473                     int rn = (given >> 16) & 0xf;
3474                     bfd_vma offset = given & 0xff;
3475
3476                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3477
3478                     if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3479                       {
3480                         /* Not unindexed.  The offset is scaled.  */
3481                         if (cp_num == 9)
3482                           /* vldr.16/vstr.16 will shift the address
3483                              left by 1 bit only.  */
3484                           offset = offset * 2;
3485                         else
3486                           offset = offset * 4;
3487
3488                         if (NEGATIVE_BIT_SET)
3489                           offset = - offset;
3490                         if (rn != 15)
3491                           value_in_comment = offset;
3492                       }
3493
3494                     if (PRE_BIT_SET)
3495                       {
3496                         if (offset)
3497                           func (stream, ", #%d]%s",
3498                                 (int) offset,
3499                                 WRITEBACK_BIT_SET ? "!" : "");
3500                         else if (NEGATIVE_BIT_SET)
3501                           func (stream, ", #-0]");
3502                         else
3503                           func (stream, "]");
3504                       }
3505                     else
3506                       {
3507                         func (stream, "]");
3508
3509                         if (WRITEBACK_BIT_SET)
3510                           {
3511                             if (offset)
3512                               func (stream, ", #%d", (int) offset);
3513                             else if (NEGATIVE_BIT_SET)
3514                               func (stream, ", #-0");
3515                           }
3516                         else
3517                           {
3518                             func (stream, ", {%s%d}",
3519                                   (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3520                                   (int) offset);
3521                             value_in_comment = offset;
3522                           }
3523                       }
3524                     if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3525                       {
3526                         func (stream, "\t; ");
3527                         /* For unaligned PCs, apply off-by-alignment
3528                            correction.  */
3529                         info->print_address_func (offset + pc
3530                                                   + info->bytes_per_chunk * 2
3531                                                   - (pc & 3),
3532                                                   info);
3533                       }
3534                   }
3535                   break;
3536
3537                 case 'B':
3538                   {
3539                     int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3540                     int offset = (given >> 1) & 0x3f;
3541
3542                     if (offset == 1)
3543                       func (stream, "{d%d}", regno);
3544                     else if (regno + offset > 32)
3545                       func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3546                     else
3547                       func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3548                   }
3549                   break;
3550
3551                 case 'u':
3552                   if (cond != COND_UNCOND)
3553                     is_unpredictable = TRUE;
3554
3555                   /* Fall through.  */
3556                 case 'c':
3557                   if (cond != COND_UNCOND && cp_num == 9)
3558                     is_unpredictable = TRUE;
3559
3560                   func (stream, "%s", arm_conditional[cond]);
3561                   break;
3562
3563                 case 'I':
3564                   /* Print a Cirrus/DSP shift immediate.  */
3565                   /* Immediates are 7bit signed ints with bits 0..3 in
3566                      bits 0..3 of opcode and bits 4..6 in bits 5..7
3567                      of opcode.  */
3568                   {
3569                     int imm;
3570
3571                     imm = (given & 0xf) | ((given & 0xe0) >> 1);
3572
3573                     /* Is ``imm'' a negative number?  */
3574                     if (imm & 0x40)
3575                       imm -= 0x80;
3576
3577                     func (stream, "%d", imm);
3578                   }
3579
3580                   break;
3581
3582                 case 'F':
3583                   switch (given & 0x00408000)
3584                     {
3585                     case 0:
3586                       func (stream, "4");
3587                       break;
3588                     case 0x8000:
3589                       func (stream, "1");
3590                       break;
3591                     case 0x00400000:
3592                       func (stream, "2");
3593                       break;
3594                     default:
3595                       func (stream, "3");
3596                     }
3597                   break;
3598
3599                 case 'P':
3600                   switch (given & 0x00080080)
3601                     {
3602                     case 0:
3603                       func (stream, "s");
3604                       break;
3605                     case 0x80:
3606                       func (stream, "d");
3607                       break;
3608                     case 0x00080000:
3609                       func (stream, "e");
3610                       break;
3611                     default:
3612                       func (stream, _("<illegal precision>"));
3613                       break;
3614                     }
3615                   break;
3616
3617                 case 'Q':
3618                   switch (given & 0x00408000)
3619                     {
3620                     case 0:
3621                       func (stream, "s");
3622                       break;
3623                     case 0x8000:
3624                       func (stream, "d");
3625                       break;
3626                     case 0x00400000:
3627                       func (stream, "e");
3628                       break;
3629                     default:
3630                       func (stream, "p");
3631                       break;
3632                     }
3633                   break;
3634
3635                 case 'R':
3636                   switch (given & 0x60)
3637                     {
3638                     case 0:
3639                       break;
3640                     case 0x20:
3641                       func (stream, "p");
3642                       break;
3643                     case 0x40:
3644                       func (stream, "m");
3645                       break;
3646                     default:
3647                       func (stream, "z");
3648                       break;
3649                     }
3650                   break;
3651
3652                 case '0': case '1': case '2': case '3': case '4':
3653                 case '5': case '6': case '7': case '8': case '9':
3654                   {
3655                     int width;
3656
3657                     c = arm_decode_bitfield (c, given, &value, &width);
3658
3659                     switch (*c)
3660                       {
3661                       case 'R':
3662                         if (value == 15)
3663                           is_unpredictable = TRUE;
3664                         /* Fall through.  */
3665                       case 'r':
3666                         if (c[1] == 'u')
3667                           {
3668                             /* Eat the 'u' character.  */
3669                             ++ c;
3670
3671                             if (u_reg == value)
3672                               is_unpredictable = TRUE;
3673                             u_reg = value;
3674                           }
3675                         func (stream, "%s", arm_regnames[value]);
3676                         break;
3677                       case 'V':
3678                         if (given & (1 << 6))
3679                           goto Q;
3680                         /* FALLTHROUGH */
3681                       case 'D':
3682                         func (stream, "d%ld", value);
3683                         break;
3684                       case 'Q':
3685                       Q:
3686                         if (value & 1)
3687                           func (stream, "<illegal reg q%ld.5>", value >> 1);
3688                         else
3689                           func (stream, "q%ld", value >> 1);
3690                         break;
3691                       case 'd':
3692                         func (stream, "%ld", value);
3693                         value_in_comment = value;
3694                         break;
3695                       case 'E':
3696                         {
3697                           /* Converts immediate 8 bit back to float value.  */
3698                           unsigned floatVal = (value & 0x80) << 24
3699                             | (value & 0x3F) << 19
3700                             | ((value & 0x40) ? (0xF8 << 22) : (1 << 30));
3701
3702                           /* Quarter float have a maximum value of 31.0.
3703                              Get floating point value multiplied by 1e7.
3704                              The maximum value stays in limit of a 32-bit int.  */
3705                           unsigned decVal =
3706                             (78125 << (((floatVal >> 23) & 0xFF) - 124)) *
3707                             (16 + (value & 0xF));
3708
3709                           if (!(decVal % 1000000))
3710                             func (stream, "%ld\t; 0x%08x %c%u.%01u", value,
3711                                   floatVal, value & 0x80 ? '-' : ' ',
3712                                   decVal / 10000000,
3713                                   decVal % 10000000 / 1000000);
3714                           else if (!(decVal % 10000))
3715                             func (stream, "%ld\t; 0x%08x %c%u.%03u", value,
3716                                   floatVal, value & 0x80 ? '-' : ' ',
3717                                   decVal / 10000000,
3718                                   decVal % 10000000 / 10000);
3719                           else
3720                             func (stream, "%ld\t; 0x%08x %c%u.%07u", value,
3721                                   floatVal, value & 0x80 ? '-' : ' ',
3722                                   decVal / 10000000, decVal % 10000000);
3723                           break;
3724                         }
3725                       case 'k':
3726                         {
3727                           int from = (given & (1 << 7)) ? 32 : 16;
3728                           func (stream, "%ld", from - value);
3729                         }
3730                         break;
3731
3732                       case 'f':
3733                         if (value > 7)
3734                           func (stream, "#%s", arm_fp_const[value & 7]);
3735                         else
3736                           func (stream, "f%ld", value);
3737                         break;
3738
3739                       case 'w':
3740                         if (width == 2)
3741                           func (stream, "%s", iwmmxt_wwnames[value]);
3742                         else
3743                           func (stream, "%s", iwmmxt_wwssnames[value]);
3744                         break;
3745
3746                       case 'g':
3747                         func (stream, "%s", iwmmxt_regnames[value]);
3748                         break;
3749                       case 'G':
3750                         func (stream, "%s", iwmmxt_cregnames[value]);
3751                         break;
3752
3753                       case 'x':
3754                         func (stream, "0x%lx", (value & 0xffffffffUL));
3755                         break;
3756
3757                       case 'c':
3758                         switch (value)
3759                           {
3760                           case 0:
3761                             func (stream, "eq");
3762                             break;
3763
3764                           case 1:
3765                             func (stream, "vs");
3766                             break;
3767
3768                           case 2:
3769                             func (stream, "ge");
3770                             break;
3771
3772                           case 3:
3773                             func (stream, "gt");
3774                             break;
3775
3776                           default:
3777                             func (stream, "??");
3778                             break;
3779                           }
3780                         break;
3781
3782                       case '`':
3783                         c++;
3784                         if (value == 0)
3785                           func (stream, "%c", *c);
3786                         break;
3787                       case '\'':
3788                         c++;
3789                         if (value == ((1ul << width) - 1))
3790                           func (stream, "%c", *c);
3791                         break;
3792                       case '?':
3793                         func (stream, "%c", c[(1 << width) - (int) value]);
3794                         c += 1 << width;
3795                         break;
3796                       default:
3797                         abort ();
3798                       }
3799                     break;
3800
3801                   case 'y':
3802                   case 'z':
3803                     {
3804                       int single = *c++ == 'y';
3805                       int regno;
3806
3807                       switch (*c)
3808                         {
3809                         case '4': /* Sm pair */
3810                         case '0': /* Sm, Dm */
3811                           regno = given & 0x0000000f;
3812                           if (single)
3813                             {
3814                               regno <<= 1;
3815                               regno += (given >> 5) & 1;
3816                             }
3817                           else
3818                             regno += ((given >> 5) & 1) << 4;
3819                           break;
3820
3821                         case '1': /* Sd, Dd */
3822                           regno = (given >> 12) & 0x0000000f;
3823                           if (single)
3824                             {
3825                               regno <<= 1;
3826                               regno += (given >> 22) & 1;
3827                             }
3828                           else
3829                             regno += ((given >> 22) & 1) << 4;
3830                           break;
3831
3832                         case '2': /* Sn, Dn */
3833                           regno = (given >> 16) & 0x0000000f;
3834                           if (single)
3835                             {
3836                               regno <<= 1;
3837                               regno += (given >> 7) & 1;
3838                             }
3839                           else
3840                             regno += ((given >> 7) & 1) << 4;
3841                           break;
3842
3843                         case '3': /* List */
3844                           func (stream, "{");
3845                           regno = (given >> 12) & 0x0000000f;
3846                           if (single)
3847                             {
3848                               regno <<= 1;
3849                               regno += (given >> 22) & 1;
3850                             }
3851                           else
3852                             regno += ((given >> 22) & 1) << 4;
3853                           break;
3854
3855                         default:
3856                           abort ();
3857                         }
3858
3859                       func (stream, "%c%d", single ? 's' : 'd', regno);
3860
3861                       if (*c == '3')
3862                         {
3863                           int count = given & 0xff;
3864
3865                           if (single == 0)
3866                             count >>= 1;
3867
3868                           if (--count)
3869                             {
3870                               func (stream, "-%c%d",
3871                                     single ? 's' : 'd',
3872                                     regno + count);
3873                             }
3874
3875                           func (stream, "}");
3876                         }
3877                       else if (*c == '4')
3878                         func (stream, ", %c%d", single ? 's' : 'd',
3879                               regno + 1);
3880                     }
3881                     break;
3882
3883                   case 'L':
3884                     switch (given & 0x00400100)
3885                       {
3886                       case 0x00000000: func (stream, "b"); break;
3887                       case 0x00400000: func (stream, "h"); break;
3888                       case 0x00000100: func (stream, "w"); break;
3889                       case 0x00400100: func (stream, "d"); break;
3890                       default:
3891                         break;
3892                       }
3893                     break;
3894
3895                   case 'Z':
3896                     {
3897                       /* given (20, 23) | given (0, 3) */
3898                       value = ((given >> 16) & 0xf0) | (given & 0xf);
3899                       func (stream, "%d", (int) value);
3900                     }
3901                     break;
3902
3903                   case 'l':
3904                     /* This is like the 'A' operator, except that if
3905                        the width field "M" is zero, then the offset is
3906                        *not* multiplied by four.  */
3907                     {
3908                       int offset = given & 0xff;
3909                       int multiplier = (given & 0x00000100) ? 4 : 1;
3910
3911                       func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3912
3913                       if (multiplier > 1)
3914                         {
3915                           value_in_comment = offset * multiplier;
3916                           if (NEGATIVE_BIT_SET)
3917                             value_in_comment = - value_in_comment;
3918                         }
3919
3920                       if (offset)
3921                         {
3922                           if (PRE_BIT_SET)
3923                             func (stream, ", #%s%d]%s",
3924                                   NEGATIVE_BIT_SET ? "-" : "",
3925                                   offset * multiplier,
3926                                   WRITEBACK_BIT_SET ? "!" : "");
3927                           else
3928                             func (stream, "], #%s%d",
3929                                   NEGATIVE_BIT_SET ? "-" : "",
3930                                   offset * multiplier);
3931                         }
3932                       else
3933                         func (stream, "]");
3934                     }
3935                     break;
3936
3937                   case 'r':
3938                     {
3939                       int imm4 = (given >> 4) & 0xf;
3940                       int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3941                       int ubit = ! NEGATIVE_BIT_SET;
3942                       const char *rm = arm_regnames [given & 0xf];
3943                       const char *rn = arm_regnames [(given >> 16) & 0xf];
3944
3945                       switch (puw_bits)
3946                         {
3947                         case 1:
3948                         case 3:
3949                           func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3950                           if (imm4)
3951                             func (stream, ", lsl #%d", imm4);
3952                           break;
3953
3954                         case 4:
3955                         case 5:
3956                         case 6:
3957                         case 7:
3958                           func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3959                           if (imm4 > 0)
3960                             func (stream, ", lsl #%d", imm4);
3961                           func (stream, "]");
3962                           if (puw_bits == 5 || puw_bits == 7)
3963                             func (stream, "!");
3964                           break;
3965
3966                         default:
3967                           func (stream, "INVALID");
3968                         }
3969                     }
3970                     break;
3971
3972                   case 'i':
3973                     {
3974                       long imm5;
3975                       imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3976                       func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3977                     }
3978                     break;
3979
3980                   default:
3981                     abort ();
3982                   }
3983                 }
3984             }
3985           else
3986             func (stream, "%c", *c);
3987         }
3988
3989       if (value_in_comment > 32 || value_in_comment < -16)
3990         func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3991
3992       if (is_unpredictable)
3993         func (stream, UNPREDICTABLE_INSTRUCTION);
3994
3995       return TRUE;
3996     }
3997   return FALSE;
3998 }
3999
4000 /* Decodes and prints ARM addressing modes.  Returns the offset
4001    used in the address, if any, if it is worthwhile printing the
4002    offset as a hexadecimal value in a comment at the end of the
4003    line of disassembly.  */
4004
4005 static signed long
4006 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
4007 {
4008   void *stream = info->stream;
4009   fprintf_ftype func = info->fprintf_func;
4010   bfd_vma offset = 0;
4011
4012   if (((given & 0x000f0000) == 0x000f0000)
4013       && ((given & 0x02000000) == 0))
4014     {
4015       offset = given & 0xfff;
4016
4017       func (stream, "[pc");
4018
4019       if (PRE_BIT_SET)
4020         {
4021           /* Pre-indexed.  Elide offset of positive zero when
4022              non-writeback.  */
4023           if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4024             func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4025
4026           if (NEGATIVE_BIT_SET)
4027             offset = -offset;
4028
4029           offset += pc + 8;
4030
4031           /* Cope with the possibility of write-back
4032              being used.  Probably a very dangerous thing
4033              for the programmer to do, but who are we to
4034              argue ?  */
4035           func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
4036         }
4037       else  /* Post indexed.  */
4038         {
4039           func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4040
4041           /* Ie ignore the offset.  */
4042           offset = pc + 8;
4043         }
4044
4045       func (stream, "\t; ");
4046       info->print_address_func (offset, info);
4047       offset = 0;
4048     }
4049   else
4050     {
4051       func (stream, "[%s",
4052             arm_regnames[(given >> 16) & 0xf]);
4053
4054       if (PRE_BIT_SET)
4055         {
4056           if ((given & 0x02000000) == 0)
4057             {
4058               /* Elide offset of positive zero when non-writeback.  */
4059               offset = given & 0xfff;
4060               if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
4061                 func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4062             }
4063           else
4064             {
4065               func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
4066               arm_decode_shift (given, func, stream, TRUE);
4067             }
4068
4069           func (stream, "]%s",
4070                 WRITEBACK_BIT_SET ? "!" : "");
4071         }
4072       else
4073         {
4074           if ((given & 0x02000000) == 0)
4075             {
4076               /* Always show offset.  */
4077               offset = given & 0xfff;
4078               func (stream, "], #%s%d",
4079                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4080             }
4081           else
4082             {
4083               func (stream, "], %s",
4084                     NEGATIVE_BIT_SET ? "-" : "");
4085               arm_decode_shift (given, func, stream, TRUE);
4086             }
4087         }
4088       if (NEGATIVE_BIT_SET)
4089         offset = -offset;
4090     }
4091
4092   return (signed long) offset;
4093 }
4094
4095 /* Print one neon instruction on INFO->STREAM.
4096    Return TRUE if the instuction matched, FALSE if this is not a
4097    recognised neon instruction.  */
4098
4099 static bfd_boolean
4100 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
4101 {
4102   const struct opcode32 *insn;
4103   void *stream = info->stream;
4104   fprintf_ftype func = info->fprintf_func;
4105
4106   if (thumb)
4107     {
4108       if ((given & 0xef000000) == 0xef000000)
4109         {
4110           /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
4111           unsigned long bit28 = given & (1 << 28);
4112
4113           given &= 0x00ffffff;
4114           if (bit28)
4115             given |= 0xf3000000;
4116           else
4117             given |= 0xf2000000;
4118         }
4119       else if ((given & 0xff000000) == 0xf9000000)
4120         given ^= 0xf9000000 ^ 0xf4000000;
4121       else
4122         return FALSE;
4123     }
4124
4125   for (insn = neon_opcodes; insn->assembler; insn++)
4126     {
4127       if ((given & insn->mask) == insn->value)
4128         {
4129           signed long value_in_comment = 0;
4130           bfd_boolean is_unpredictable = FALSE;
4131           const char *c;
4132
4133           for (c = insn->assembler; *c; c++)
4134             {
4135               if (*c == '%')
4136                 {
4137                   switch (*++c)
4138                     {
4139                     case '%':
4140                       func (stream, "%%");
4141                       break;
4142
4143                     case 'u':
4144                       if (thumb && ifthen_state)
4145                         is_unpredictable = TRUE;
4146
4147                       /* Fall through.  */
4148                     case 'c':
4149                       if (thumb && ifthen_state)
4150                         func (stream, "%s", arm_conditional[IFTHEN_COND]);
4151                       break;
4152
4153                     case 'A':
4154                       {
4155                         static const unsigned char enc[16] =
4156                         {
4157                           0x4, 0x14, /* st4 0,1 */
4158                           0x4, /* st1 2 */
4159                           0x4, /* st2 3 */
4160                           0x3, /* st3 4 */
4161                           0x13, /* st3 5 */
4162                           0x3, /* st1 6 */
4163                           0x1, /* st1 7 */
4164                           0x2, /* st2 8 */
4165                           0x12, /* st2 9 */
4166                           0x2, /* st1 10 */
4167                           0, 0, 0, 0, 0
4168                         };
4169                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4170                         int rn = ((given >> 16) & 0xf);
4171                         int rm = ((given >> 0) & 0xf);
4172                         int align = ((given >> 4) & 0x3);
4173                         int type = ((given >> 8) & 0xf);
4174                         int n = enc[type] & 0xf;
4175                         int stride = (enc[type] >> 4) + 1;
4176                         int ix;
4177
4178                         func (stream, "{");
4179                         if (stride > 1)
4180                           for (ix = 0; ix != n; ix++)
4181                             func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
4182                         else if (n == 1)
4183                           func (stream, "d%d", rd);
4184                         else
4185                           func (stream, "d%d-d%d", rd, rd + n - 1);
4186                         func (stream, "}, [%s", arm_regnames[rn]);
4187                         if (align)
4188                           func (stream, " :%d", 32 << align);
4189                         func (stream, "]");
4190                         if (rm == 0xd)
4191                           func (stream, "!");
4192                         else if (rm != 0xf)
4193                           func (stream, ", %s", arm_regnames[rm]);
4194                       }
4195                       break;
4196
4197                     case 'B':
4198                       {
4199                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4200                         int rn = ((given >> 16) & 0xf);
4201                         int rm = ((given >> 0) & 0xf);
4202                         int idx_align = ((given >> 4) & 0xf);
4203                         int align = 0;
4204                         int size = ((given >> 10) & 0x3);
4205                         int idx = idx_align >> (size + 1);
4206                         int length = ((given >> 8) & 3) + 1;
4207                         int stride = 1;
4208                         int i;
4209
4210                         if (length > 1 && size > 0)
4211                           stride = (idx_align & (1 << size)) ? 2 : 1;
4212
4213                         switch (length)
4214                           {
4215                           case 1:
4216                             {
4217                               int amask = (1 << size) - 1;
4218                               if ((idx_align & (1 << size)) != 0)
4219                                 return FALSE;
4220                               if (size > 0)
4221                                 {
4222                                   if ((idx_align & amask) == amask)
4223                                     align = 8 << size;
4224                                   else if ((idx_align & amask) != 0)
4225                                     return FALSE;
4226                                 }
4227                               }
4228                             break;
4229
4230                           case 2:
4231                             if (size == 2 && (idx_align & 2) != 0)
4232                               return FALSE;
4233                             align = (idx_align & 1) ? 16 << size : 0;
4234                             break;
4235
4236                           case 3:
4237                             if ((size == 2 && (idx_align & 3) != 0)
4238                                 || (idx_align & 1) != 0)
4239                               return FALSE;
4240                             break;
4241
4242                           case 4:
4243                             if (size == 2)
4244                               {
4245                                 if ((idx_align & 3) == 3)
4246                                   return FALSE;
4247                                 align = (idx_align & 3) * 64;
4248                               }
4249                             else
4250                               align = (idx_align & 1) ? 32 << size : 0;
4251                             break;
4252
4253                           default:
4254                             abort ();
4255                           }
4256
4257                         func (stream, "{");
4258                         for (i = 0; i < length; i++)
4259                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
4260                             rd + i * stride, idx);
4261                         func (stream, "}, [%s", arm_regnames[rn]);
4262                         if (align)
4263                           func (stream, " :%d", align);
4264                         func (stream, "]");
4265                         if (rm == 0xd)
4266                           func (stream, "!");
4267                         else if (rm != 0xf)
4268                           func (stream, ", %s", arm_regnames[rm]);
4269                       }
4270                       break;
4271
4272                     case 'C':
4273                       {
4274                         int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
4275                         int rn = ((given >> 16) & 0xf);
4276                         int rm = ((given >> 0) & 0xf);
4277                         int align = ((given >> 4) & 0x1);
4278                         int size = ((given >> 6) & 0x3);
4279                         int type = ((given >> 8) & 0x3);
4280                         int n = type + 1;
4281                         int stride = ((given >> 5) & 0x1);
4282                         int ix;
4283
4284                         if (stride && (n == 1))
4285                           n++;
4286                         else
4287                           stride++;
4288
4289                         func (stream, "{");
4290                         if (stride > 1)
4291                           for (ix = 0; ix != n; ix++)
4292                             func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
4293                         else if (n == 1)
4294                           func (stream, "d%d[]", rd);
4295                         else
4296                           func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
4297                         func (stream, "}, [%s", arm_regnames[rn]);
4298                         if (align)
4299                           {
4300                             align = (8 * (type + 1)) << size;
4301                             if (type == 3)
4302                               align = (size > 1) ? align >> 1 : align;
4303                             if (type == 2 || (type == 0 && !size))
4304                               func (stream, " :<bad align %d>", align);
4305                             else
4306                               func (stream, " :%d", align);
4307                           }
4308                         func (stream, "]");
4309                         if (rm == 0xd)
4310                           func (stream, "!");
4311                         else if (rm != 0xf)
4312                           func (stream, ", %s", arm_regnames[rm]);
4313                       }
4314                       break;
4315
4316                     case 'D':
4317                       {
4318                         int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
4319                         int size = (given >> 20) & 3;
4320                         int reg = raw_reg & ((4 << size) - 1);
4321                         int ix = raw_reg >> size >> 2;
4322
4323                         func (stream, "d%d[%d]", reg, ix);
4324                       }
4325                       break;
4326
4327                     case 'E':
4328                       /* Neon encoded constant for mov, mvn, vorr, vbic.  */
4329                       {
4330                         int bits = 0;
4331                         int cmode = (given >> 8) & 0xf;
4332                         int op = (given >> 5) & 0x1;
4333                         unsigned long value = 0, hival = 0;
4334                         unsigned shift;
4335                         int size = 0;
4336                         int isfloat = 0;
4337
4338                         bits |= ((given >> 24) & 1) << 7;
4339                         bits |= ((given >> 16) & 7) << 4;
4340                         bits |= ((given >> 0) & 15) << 0;
4341
4342                         if (cmode < 8)
4343                           {
4344                             shift = (cmode >> 1) & 3;
4345                             value = (unsigned long) bits << (8 * shift);
4346                             size = 32;
4347                           }
4348                         else if (cmode < 12)
4349                           {
4350                             shift = (cmode >> 1) & 1;
4351                             value = (unsigned long) bits << (8 * shift);
4352                             size = 16;
4353                           }
4354                         else if (cmode < 14)
4355                           {
4356                             shift = (cmode & 1) + 1;
4357                             value = (unsigned long) bits << (8 * shift);
4358                             value |= (1ul << (8 * shift)) - 1;
4359                             size = 32;
4360                           }
4361                         else if (cmode == 14)
4362                           {
4363                             if (op)
4364                               {
4365                                 /* Bit replication into bytes.  */
4366                                 int ix;
4367                                 unsigned long mask;
4368
4369                                 value = 0;
4370                                 hival = 0;
4371                                 for (ix = 7; ix >= 0; ix--)
4372                                   {
4373                                     mask = ((bits >> ix) & 1) ? 0xff : 0;
4374                                     if (ix <= 3)
4375                                       value = (value << 8) | mask;
4376                                     else
4377                                       hival = (hival << 8) | mask;
4378                                   }
4379                                 size = 64;
4380                               }
4381                             else
4382                               {
4383                                 /* Byte replication.  */
4384                                 value = (unsigned long) bits;
4385                                 size = 8;
4386                               }
4387                           }
4388                         else if (!op)
4389                           {
4390                             /* Floating point encoding.  */
4391                             int tmp;
4392
4393                             value = (unsigned long)  (bits & 0x7f) << 19;
4394                             value |= (unsigned long) (bits & 0x80) << 24;
4395                             tmp = bits & 0x40 ? 0x3c : 0x40;
4396                             value |= (unsigned long) tmp << 24;
4397                             size = 32;
4398                             isfloat = 1;
4399                           }
4400                         else
4401                           {
4402                             func (stream, "<illegal constant %.8x:%x:%x>",
4403                                   bits, cmode, op);
4404                             size = 32;
4405                             break;
4406                           }
4407                         switch (size)
4408                           {
4409                           case 8:
4410                             func (stream, "#%ld\t; 0x%.2lx", value, value);
4411                             break;
4412
4413                           case 16:
4414                             func (stream, "#%ld\t; 0x%.4lx", value, value);
4415                             break;
4416
4417                           case 32:
4418                             if (isfloat)
4419                               {
4420                                 unsigned char valbytes[4];
4421                                 double fvalue;
4422
4423                                 /* Do this a byte at a time so we don't have to
4424                                    worry about the host's endianness.  */
4425                                 valbytes[0] = value & 0xff;
4426                                 valbytes[1] = (value >> 8) & 0xff;
4427                                 valbytes[2] = (value >> 16) & 0xff;
4428                                 valbytes[3] = (value >> 24) & 0xff;
4429
4430                                 floatformat_to_double
4431                                   (& floatformat_ieee_single_little, valbytes,
4432                                   & fvalue);
4433
4434                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
4435                                       value);
4436                               }
4437                             else
4438                               func (stream, "#%ld\t; 0x%.8lx",
4439                                     (long) (((value & 0x80000000L) != 0)
4440                                             ? value | ~0xffffffffL : value),
4441                                     value);
4442                             break;
4443
4444                           case 64:
4445                             func (stream, "#0x%.8lx%.8lx", hival, value);
4446                             break;
4447
4448                           default:
4449                             abort ();
4450                           }
4451                       }
4452                       break;
4453
4454                     case 'F':
4455                       {
4456                         int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
4457                         int num = (given >> 8) & 0x3;
4458
4459                         if (!num)
4460                           func (stream, "{d%d}", regno);
4461                         else if (num + regno >= 32)
4462                           func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
4463                         else
4464                           func (stream, "{d%d-d%d}", regno, regno + num);
4465                       }
4466                       break;
4467
4468
4469                     case '0': case '1': case '2': case '3': case '4':
4470                     case '5': case '6': case '7': case '8': case '9':
4471                       {
4472                         int width;
4473                         unsigned long value;
4474
4475                         c = arm_decode_bitfield (c, given, &value, &width);
4476
4477                         switch (*c)
4478                           {
4479                           case 'r':
4480                             func (stream, "%s", arm_regnames[value]);
4481                             break;
4482                           case 'd':
4483                             func (stream, "%ld", value);
4484                             value_in_comment = value;
4485                             break;
4486                           case 'e':
4487                             func (stream, "%ld", (1ul << width) - value);
4488                             break;
4489
4490                           case 'S':
4491                           case 'T':
4492                           case 'U':
4493                             /* Various width encodings.  */
4494                             {
4495                               int base = 8 << (*c - 'S'); /* 8,16 or 32 */
4496                               int limit;
4497                               unsigned low, high;
4498
4499                               c++;
4500                               if (*c >= '0' && *c <= '9')
4501                                 limit = *c - '0';
4502                               else if (*c >= 'a' && *c <= 'f')
4503                                 limit = *c - 'a' + 10;
4504                               else
4505                                 abort ();
4506                               low = limit >> 2;
4507                               high = limit & 3;
4508
4509                               if (value < low || value > high)
4510                                 func (stream, "<illegal width %d>", base << value);
4511                               else
4512                                 func (stream, "%d", base << value);
4513                             }
4514                             break;
4515                           case 'R':
4516                             if (given & (1 << 6))
4517                               goto Q;
4518                             /* FALLTHROUGH */
4519                           case 'D':
4520                             func (stream, "d%ld", value);
4521                             break;
4522                           case 'Q':
4523                           Q:
4524                             if (value & 1)
4525                               func (stream, "<illegal reg q%ld.5>", value >> 1);
4526                             else
4527                               func (stream, "q%ld", value >> 1);
4528                             break;
4529
4530                           case '`':
4531                             c++;
4532                             if (value == 0)
4533                               func (stream, "%c", *c);
4534                             break;
4535                           case '\'':
4536                             c++;
4537                             if (value == ((1ul << width) - 1))
4538                               func (stream, "%c", *c);
4539                             break;
4540                           case '?':
4541                             func (stream, "%c", c[(1 << width) - (int) value]);
4542                             c += 1 << width;
4543                             break;
4544                           default:
4545                             abort ();
4546                           }
4547                         break;
4548
4549                       default:
4550                         abort ();
4551                       }
4552                     }
4553                 }
4554               else
4555                 func (stream, "%c", *c);
4556             }
4557
4558           if (value_in_comment > 32 || value_in_comment < -16)
4559             func (stream, "\t; 0x%lx", value_in_comment);
4560
4561           if (is_unpredictable)
4562             func (stream, UNPREDICTABLE_INSTRUCTION);
4563
4564           return TRUE;
4565         }
4566     }
4567   return FALSE;
4568 }
4569
4570 /* Return the name of a v7A special register.  */
4571
4572 static const char *
4573 banked_regname (unsigned reg)
4574 {
4575   switch (reg)
4576     {
4577       case 15: return "CPSR";
4578       case 32: return "R8_usr";
4579       case 33: return "R9_usr";
4580       case 34: return "R10_usr";
4581       case 35: return "R11_usr";
4582       case 36: return "R12_usr";
4583       case 37: return "SP_usr";
4584       case 38: return "LR_usr";
4585       case 40: return "R8_fiq";
4586       case 41: return "R9_fiq";
4587       case 42: return "R10_fiq";
4588       case 43: return "R11_fiq";
4589       case 44: return "R12_fiq";
4590       case 45: return "SP_fiq";
4591       case 46: return "LR_fiq";
4592       case 48: return "LR_irq";
4593       case 49: return "SP_irq";
4594       case 50: return "LR_svc";
4595       case 51: return "SP_svc";
4596       case 52: return "LR_abt";
4597       case 53: return "SP_abt";
4598       case 54: return "LR_und";
4599       case 55: return "SP_und";
4600       case 60: return "LR_mon";
4601       case 61: return "SP_mon";
4602       case 62: return "ELR_hyp";
4603       case 63: return "SP_hyp";
4604       case 79: return "SPSR";
4605       case 110: return "SPSR_fiq";
4606       case 112: return "SPSR_irq";
4607       case 114: return "SPSR_svc";
4608       case 116: return "SPSR_abt";
4609       case 118: return "SPSR_und";
4610       case 124: return "SPSR_mon";
4611       case 126: return "SPSR_hyp";
4612       default: return NULL;
4613     }
4614 }
4615
4616 /* Return the name of the DMB/DSB option.  */
4617 static const char *
4618 data_barrier_option (unsigned option)
4619 {
4620   switch (option & 0xf)
4621     {
4622     case 0xf: return "sy";
4623     case 0xe: return "st";
4624     case 0xd: return "ld";
4625     case 0xb: return "ish";
4626     case 0xa: return "ishst";
4627     case 0x9: return "ishld";
4628     case 0x7: return "un";
4629     case 0x6: return "unst";
4630     case 0x5: return "nshld";
4631     case 0x3: return "osh";
4632     case 0x2: return "oshst";
4633     case 0x1: return "oshld";
4634     default:  return NULL;
4635     }
4636 }
4637
4638 /* Print one ARM instruction from PC on INFO->STREAM.  */
4639
4640 static void
4641 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
4642 {
4643   const struct opcode32 *insn;
4644   void *stream = info->stream;
4645   fprintf_ftype func = info->fprintf_func;
4646   struct arm_private_data *private_data = info->private_data;
4647
4648   if (print_insn_coprocessor (pc, info, given, FALSE))
4649     return;
4650
4651   if (print_insn_neon (info, given, FALSE))
4652     return;
4653
4654   for (insn = arm_opcodes; insn->assembler; insn++)
4655     {
4656       if ((given & insn->mask) != insn->value)
4657         continue;
4658
4659       if (! ARM_CPU_HAS_FEATURE (insn->arch, private_data->features))
4660         continue;
4661
4662       /* Special case: an instruction with all bits set in the condition field
4663          (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
4664          or by the catchall at the end of the table.  */
4665       if ((given & 0xF0000000) != 0xF0000000
4666           || (insn->mask & 0xF0000000) == 0xF0000000
4667           || (insn->mask == 0 && insn->value == 0))
4668         {
4669           unsigned long u_reg = 16;
4670           unsigned long U_reg = 16;
4671           bfd_boolean is_unpredictable = FALSE;
4672           signed long value_in_comment = 0;
4673           const char *c;
4674
4675           for (c = insn->assembler; *c; c++)
4676             {
4677               if (*c == '%')
4678                 {
4679                   bfd_boolean allow_unpredictable = FALSE;
4680
4681                   switch (*++c)
4682                     {
4683                     case '%':
4684                       func (stream, "%%");
4685                       break;
4686
4687                     case 'a':
4688                       value_in_comment = print_arm_address (pc, info, given);
4689                       break;
4690
4691                     case 'P':
4692                       /* Set P address bit and use normal address
4693                          printing routine.  */
4694                       value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
4695                       break;
4696
4697                     case 'S':
4698                       allow_unpredictable = TRUE;
4699                       /* Fall through.  */
4700                     case 's':
4701                       if ((given & 0x004f0000) == 0x004f0000)
4702                         {
4703                           /* PC relative with immediate offset.  */
4704                           bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
4705
4706                           if (PRE_BIT_SET)
4707                             {
4708                               /* Elide positive zero offset.  */
4709                               if (offset || NEGATIVE_BIT_SET)
4710                                 func (stream, "[pc, #%s%d]\t; ",
4711                                       NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4712                               else
4713                                 func (stream, "[pc]\t; ");
4714                               if (NEGATIVE_BIT_SET)
4715                                 offset = -offset;
4716                               info->print_address_func (offset + pc + 8, info);
4717                             }
4718                           else
4719                             {
4720                               /* Always show the offset.  */
4721                               func (stream, "[pc], #%s%d",
4722                                     NEGATIVE_BIT_SET ? "-" : "", (int) offset);
4723                               if (! allow_unpredictable)
4724                                 is_unpredictable = TRUE;
4725                             }
4726                         }
4727                       else
4728                         {
4729                           int offset = ((given & 0xf00) >> 4) | (given & 0xf);
4730
4731                           func (stream, "[%s",
4732                                 arm_regnames[(given >> 16) & 0xf]);
4733
4734                           if (PRE_BIT_SET)
4735                             {
4736                               if (IMMEDIATE_BIT_SET)
4737                                 {
4738                                   /* Elide offset for non-writeback
4739                                      positive zero.  */
4740                                   if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
4741                                       || offset)
4742                                     func (stream, ", #%s%d",
4743                                           NEGATIVE_BIT_SET ? "-" : "", offset);
4744
4745                                   if (NEGATIVE_BIT_SET)
4746                                     offset = -offset;
4747
4748                                   value_in_comment = offset;
4749                                 }
4750                               else
4751                                 {
4752                                   /* Register Offset or Register Pre-Indexed.  */
4753                                   func (stream, ", %s%s",
4754                                         NEGATIVE_BIT_SET ? "-" : "",
4755                                         arm_regnames[given & 0xf]);
4756
4757                                   /* Writing back to the register that is the source/
4758                                      destination of the load/store is unpredictable.  */
4759                                   if (! allow_unpredictable
4760                                       && WRITEBACK_BIT_SET
4761                                       && ((given & 0xf) == ((given >> 12) & 0xf)))
4762                                     is_unpredictable = TRUE;
4763                                 }
4764
4765                               func (stream, "]%s",
4766                                     WRITEBACK_BIT_SET ? "!" : "");
4767                             }
4768                           else
4769                             {
4770                               if (IMMEDIATE_BIT_SET)
4771                                 {
4772                                   /* Immediate Post-indexed.  */
4773                                   /* PR 10924: Offset must be printed, even if it is zero.  */
4774                                   func (stream, "], #%s%d",
4775                                         NEGATIVE_BIT_SET ? "-" : "", offset);
4776                                   if (NEGATIVE_BIT_SET)
4777                                     offset = -offset;
4778                                   value_in_comment = offset;
4779                                 }
4780                               else
4781                                 {
4782                                   /* Register Post-indexed.  */
4783                                   func (stream, "], %s%s",
4784                                         NEGATIVE_BIT_SET ? "-" : "",
4785                                         arm_regnames[given & 0xf]);
4786
4787                                   /* Writing back to the register that is the source/
4788                                      destination of the load/store is unpredictable.  */
4789                                   if (! allow_unpredictable
4790                                       && (given & 0xf) == ((given >> 12) & 0xf))
4791                                     is_unpredictable = TRUE;
4792                                 }
4793
4794                               if (! allow_unpredictable)
4795                                 {
4796                                   /* Writeback is automatically implied by post- addressing.
4797                                      Setting the W bit is unnecessary and ARM specify it as
4798                                      being unpredictable.  */
4799                                   if (WRITEBACK_BIT_SET
4800                                       /* Specifying the PC register as the post-indexed
4801                                          registers is also unpredictable.  */
4802                                       || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
4803                                     is_unpredictable = TRUE;
4804                                 }
4805                             }
4806                         }
4807                       break;
4808
4809                     case 'b':
4810                       {
4811                         bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
4812                         info->print_address_func (disp * 4 + pc + 8, info);
4813                       }
4814                       break;
4815
4816                     case 'c':
4817                       if (((given >> 28) & 0xf) != 0xe)
4818                         func (stream, "%s",
4819                               arm_conditional [(given >> 28) & 0xf]);
4820                       break;
4821
4822                     case 'm':
4823                       {
4824                         int started = 0;
4825                         int reg;
4826
4827                         func (stream, "{");
4828                         for (reg = 0; reg < 16; reg++)
4829                           if ((given & (1 << reg)) != 0)
4830                             {
4831                               if (started)
4832                                 func (stream, ", ");
4833                               started = 1;
4834                               func (stream, "%s", arm_regnames[reg]);
4835                             }
4836                         func (stream, "}");
4837                         if (! started)
4838                           is_unpredictable = TRUE;
4839                       }
4840                       break;
4841
4842                     case 'q':
4843                       arm_decode_shift (given, func, stream, FALSE);
4844                       break;
4845
4846                     case 'o':
4847                       if ((given & 0x02000000) != 0)
4848                         {
4849                           unsigned int rotate = (given & 0xf00) >> 7;
4850                           unsigned int immed = (given & 0xff);
4851                           unsigned int a, i;
4852
4853                           a = (((immed << (32 - rotate))
4854                                 | (immed >> rotate)) & 0xffffffff);
4855                           /* If there is another encoding with smaller rotate,
4856                              the rotate should be specified directly.  */
4857                           for (i = 0; i < 32; i += 2)
4858                             if ((a << i | a >> (32 - i)) <= 0xff)
4859                               break;
4860
4861                           if (i != rotate)
4862                             func (stream, "#%d, %d", immed, rotate);
4863                           else
4864                             func (stream, "#%d", a);
4865                           value_in_comment = a;
4866                         }
4867                       else
4868                         arm_decode_shift (given, func, stream, TRUE);
4869                       break;
4870
4871                     case 'p':
4872                       if ((given & 0x0000f000) == 0x0000f000)
4873                         {
4874                           arm_feature_set arm_ext_v6 =
4875                             ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
4876
4877                           /* The p-variants of tst/cmp/cmn/teq are the pre-V6
4878                              mechanism for setting PSR flag bits.  They are
4879                              obsolete in V6 onwards.  */
4880                           if (! ARM_CPU_HAS_FEATURE (private_data->features, \
4881                                                      arm_ext_v6))
4882                             func (stream, "p");
4883                           else
4884                             is_unpredictable = TRUE;
4885                         }
4886                       break;
4887
4888                     case 't':
4889                       if ((given & 0x01200000) == 0x00200000)
4890                         func (stream, "t");
4891                       break;
4892
4893                     case 'A':
4894                       {
4895                         int offset = given & 0xff;
4896
4897                         value_in_comment = offset * 4;
4898                         if (NEGATIVE_BIT_SET)
4899                           value_in_comment = - value_in_comment;
4900
4901                         func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
4902
4903                         if (PRE_BIT_SET)
4904                           {
4905                             if (offset)
4906                               func (stream, ", #%d]%s",
4907                                     (int) value_in_comment,
4908                                     WRITEBACK_BIT_SET ? "!" : "");
4909                             else
4910                               func (stream, "]");
4911                           }
4912                         else
4913                           {
4914                             func (stream, "]");
4915
4916                             if (WRITEBACK_BIT_SET)
4917                               {
4918                                 if (offset)
4919                                   func (stream, ", #%d", (int) value_in_comment);
4920                               }
4921                             else
4922                               {
4923                                 func (stream, ", {%d}", (int) offset);
4924                                 value_in_comment = offset;
4925                               }
4926                           }
4927                       }
4928                       break;
4929
4930                     case 'B':
4931                       /* Print ARM V5 BLX(1) address: pc+25 bits.  */
4932                       {
4933                         bfd_vma address;
4934                         bfd_vma offset = 0;
4935
4936                         if (! NEGATIVE_BIT_SET)
4937                           /* Is signed, hi bits should be ones.  */
4938                           offset = (-1) ^ 0x00ffffff;
4939
4940                         /* Offset is (SignExtend(offset field)<<2).  */
4941                         offset += given & 0x00ffffff;
4942                         offset <<= 2;
4943                         address = offset + pc + 8;
4944
4945                         if (given & 0x01000000)
4946                           /* H bit allows addressing to 2-byte boundaries.  */
4947                           address += 2;
4948
4949                         info->print_address_func (address, info);
4950                       }
4951                       break;
4952
4953                     case 'C':
4954                       if ((given & 0x02000200) == 0x200)
4955                         {
4956                           const char * name;
4957                           unsigned sysm = (given & 0x004f0000) >> 16;
4958
4959                           sysm |= (given & 0x300) >> 4;
4960                           name = banked_regname (sysm);
4961
4962                           if (name != NULL)
4963                             func (stream, "%s", name);
4964                           else
4965                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
4966                         }
4967                       else
4968                         {
4969                           func (stream, "%cPSR_",
4970                                 (given & 0x00400000) ? 'S' : 'C');
4971                           if (given & 0x80000)
4972                             func (stream, "f");
4973                           if (given & 0x40000)
4974                             func (stream, "s");
4975                           if (given & 0x20000)
4976                             func (stream, "x");
4977                           if (given & 0x10000)
4978                             func (stream, "c");
4979                         }
4980                       break;
4981
4982                     case 'U':
4983                       if ((given & 0xf0) == 0x60)
4984                         {
4985                           switch (given & 0xf)
4986                             {
4987                             case 0xf: func (stream, "sy"); break;
4988                             default:
4989                               func (stream, "#%d", (int) given & 0xf);
4990                               break;
4991                             }
4992                         }
4993                       else
4994                         {
4995                           const char * opt = data_barrier_option (given & 0xf);
4996                           if (opt != NULL)
4997                             func (stream, "%s", opt);
4998                           else
4999                               func (stream, "#%d", (int) given & 0xf);
5000                         }
5001                       break;
5002
5003                     case '0': case '1': case '2': case '3': case '4':
5004                     case '5': case '6': case '7': case '8': case '9':
5005                       {
5006                         int width;
5007                         unsigned long value;
5008
5009                         c = arm_decode_bitfield (c, given, &value, &width);
5010
5011                         switch (*c)
5012                           {
5013                           case 'R':
5014                             if (value == 15)
5015                               is_unpredictable = TRUE;
5016                             /* Fall through.  */
5017                           case 'r':
5018                           case 'T':
5019                             /* We want register + 1 when decoding T.  */
5020                             if (*c == 'T')
5021                               ++value;
5022
5023                             if (c[1] == 'u')
5024                               {
5025                                 /* Eat the 'u' character.  */
5026                                 ++ c;
5027
5028                                 if (u_reg == value)
5029                                   is_unpredictable = TRUE;
5030                                 u_reg = value;
5031                               }
5032                             if (c[1] == 'U')
5033                               {
5034                                 /* Eat the 'U' character.  */
5035                                 ++ c;
5036
5037                                 if (U_reg == value)
5038                                   is_unpredictable = TRUE;
5039                                 U_reg = value;
5040                               }
5041                             func (stream, "%s", arm_regnames[value]);
5042                             break;
5043                           case 'd':
5044                             func (stream, "%ld", value);
5045                             value_in_comment = value;
5046                             break;
5047                           case 'b':
5048                             func (stream, "%ld", value * 8);
5049                             value_in_comment = value * 8;
5050                             break;
5051                           case 'W':
5052                             func (stream, "%ld", value + 1);
5053                             value_in_comment = value + 1;
5054                             break;
5055                           case 'x':
5056                             func (stream, "0x%08lx", value);
5057
5058                             /* Some SWI instructions have special
5059                                meanings.  */
5060                             if ((given & 0x0fffffff) == 0x0FF00000)
5061                               func (stream, "\t; IMB");
5062                             else if ((given & 0x0fffffff) == 0x0FF00001)
5063                               func (stream, "\t; IMBRange");
5064                             break;
5065                           case 'X':
5066                             func (stream, "%01lx", value & 0xf);
5067                             value_in_comment = value;
5068                             break;
5069                           case '`':
5070                             c++;
5071                             if (value == 0)
5072                               func (stream, "%c", *c);
5073                             break;
5074                           case '\'':
5075                             c++;
5076                             if (value == ((1ul << width) - 1))
5077                               func (stream, "%c", *c);
5078                             break;
5079                           case '?':
5080                             func (stream, "%c", c[(1 << width) - (int) value]);
5081                             c += 1 << width;
5082                             break;
5083                           default:
5084                             abort ();
5085                           }
5086                         break;
5087
5088                       case 'e':
5089                         {
5090                           int imm;
5091
5092                           imm = (given & 0xf) | ((given & 0xfff00) >> 4);
5093                           func (stream, "%d", imm);
5094                           value_in_comment = imm;
5095                         }
5096                         break;
5097
5098                       case 'E':
5099                         /* LSB and WIDTH fields of BFI or BFC.  The machine-
5100                            language instruction encodes LSB and MSB.  */
5101                         {
5102                           long msb = (given & 0x001f0000) >> 16;
5103                           long lsb = (given & 0x00000f80) >> 7;
5104                           long w = msb - lsb + 1;
5105
5106                           if (w > 0)
5107                             func (stream, "#%lu, #%lu", lsb, w);
5108                           else
5109                             func (stream, "(invalid: %lu:%lu)", lsb, msb);
5110                         }
5111                         break;
5112
5113                       case 'R':
5114                         /* Get the PSR/banked register name.  */
5115                         {
5116                           const char * name;
5117                           unsigned sysm = (given & 0x004f0000) >> 16;
5118
5119                           sysm |= (given & 0x300) >> 4;
5120                           name = banked_regname (sysm);
5121
5122                           if (name != NULL)
5123                             func (stream, "%s", name);
5124                           else
5125                             func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5126                         }
5127                         break;
5128
5129                       case 'V':
5130                         /* 16-bit unsigned immediate from a MOVT or MOVW
5131                            instruction, encoded in bits 0:11 and 15:19.  */
5132                         {
5133                           long hi = (given & 0x000f0000) >> 4;
5134                           long lo = (given & 0x00000fff);
5135                           long imm16 = hi | lo;
5136
5137                           func (stream, "#%lu", imm16);
5138                           value_in_comment = imm16;
5139                         }
5140                         break;
5141
5142                       default:
5143                         abort ();
5144                       }
5145                     }
5146                 }
5147               else
5148                 func (stream, "%c", *c);
5149             }
5150
5151           if (value_in_comment > 32 || value_in_comment < -16)
5152             func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
5153
5154           if (is_unpredictable)
5155             func (stream, UNPREDICTABLE_INSTRUCTION);
5156
5157           return;
5158         }
5159     }
5160   abort ();
5161 }
5162
5163 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
5164
5165 static void
5166 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
5167 {
5168   const struct opcode16 *insn;
5169   void *stream = info->stream;
5170   fprintf_ftype func = info->fprintf_func;
5171
5172   for (insn = thumb_opcodes; insn->assembler; insn++)
5173     if ((given & insn->mask) == insn->value)
5174       {
5175         signed long value_in_comment = 0;
5176         const char *c = insn->assembler;
5177
5178         for (; *c; c++)
5179           {
5180             int domaskpc = 0;
5181             int domasklr = 0;
5182
5183             if (*c != '%')
5184               {
5185                 func (stream, "%c", *c);
5186                 continue;
5187               }
5188
5189             switch (*++c)
5190               {
5191               case '%':
5192                 func (stream, "%%");
5193                 break;
5194
5195               case 'c':
5196                 if (ifthen_state)
5197                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5198                 break;
5199
5200               case 'C':
5201                 if (ifthen_state)
5202                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5203                 else
5204                   func (stream, "s");
5205                 break;
5206
5207               case 'I':
5208                 {
5209                   unsigned int tmp;
5210
5211                   ifthen_next_state = given & 0xff;
5212                   for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
5213                     func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
5214                   func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
5215                 }
5216                 break;
5217
5218               case 'x':
5219                 if (ifthen_next_state)
5220                   func (stream, "\t; unpredictable branch in IT block\n");
5221                 break;
5222
5223               case 'X':
5224                 if (ifthen_state)
5225                   func (stream, "\t; unpredictable <IT:%s>",
5226                         arm_conditional[IFTHEN_COND]);
5227                 break;
5228
5229               case 'S':
5230                 {
5231                   long reg;
5232
5233                   reg = (given >> 3) & 0x7;
5234                   if (given & (1 << 6))
5235                     reg += 8;
5236
5237                   func (stream, "%s", arm_regnames[reg]);
5238                 }
5239                 break;
5240
5241               case 'D':
5242                 {
5243                   long reg;
5244
5245                   reg = given & 0x7;
5246                   if (given & (1 << 7))
5247                     reg += 8;
5248
5249                   func (stream, "%s", arm_regnames[reg]);
5250                 }
5251                 break;
5252
5253               case 'N':
5254                 if (given & (1 << 8))
5255                   domasklr = 1;
5256                 /* Fall through.  */
5257               case 'O':
5258                 if (*c == 'O' && (given & (1 << 8)))
5259                   domaskpc = 1;
5260                 /* Fall through.  */
5261               case 'M':
5262                 {
5263                   int started = 0;
5264                   int reg;
5265
5266                   func (stream, "{");
5267
5268                   /* It would be nice if we could spot
5269                      ranges, and generate the rS-rE format: */
5270                   for (reg = 0; (reg < 8); reg++)
5271                     if ((given & (1 << reg)) != 0)
5272                       {
5273                         if (started)
5274                           func (stream, ", ");
5275                         started = 1;
5276                         func (stream, "%s", arm_regnames[reg]);
5277                       }
5278
5279                   if (domasklr)
5280                     {
5281                       if (started)
5282                         func (stream, ", ");
5283                       started = 1;
5284                       func (stream, "%s", arm_regnames[14] /* "lr" */);
5285                     }
5286
5287                   if (domaskpc)
5288                     {
5289                       if (started)
5290                         func (stream, ", ");
5291                       func (stream, "%s", arm_regnames[15] /* "pc" */);
5292                     }
5293
5294                   func (stream, "}");
5295                 }
5296                 break;
5297
5298               case 'W':
5299                 /* Print writeback indicator for a LDMIA.  We are doing a
5300                    writeback if the base register is not in the register
5301                    mask.  */
5302                 if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
5303                   func (stream, "!");
5304                 break;
5305
5306               case 'b':
5307                 /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
5308                 {
5309                   bfd_vma address = (pc + 4
5310                                      + ((given & 0x00f8) >> 2)
5311                                      + ((given & 0x0200) >> 3));
5312                   info->print_address_func (address, info);
5313                 }
5314                 break;
5315
5316               case 's':
5317                 /* Right shift immediate -- bits 6..10; 1-31 print
5318                    as themselves, 0 prints as 32.  */
5319                 {
5320                   long imm = (given & 0x07c0) >> 6;
5321                   if (imm == 0)
5322                     imm = 32;
5323                   func (stream, "#%ld", imm);
5324                 }
5325                 break;
5326
5327               case '0': case '1': case '2': case '3': case '4':
5328               case '5': case '6': case '7': case '8': case '9':
5329                 {
5330                   int bitstart = *c++ - '0';
5331                   int bitend = 0;
5332
5333                   while (*c >= '0' && *c <= '9')
5334                     bitstart = (bitstart * 10) + *c++ - '0';
5335
5336                   switch (*c)
5337                     {
5338                     case '-':
5339                       {
5340                         bfd_vma reg;
5341
5342                         c++;
5343                         while (*c >= '0' && *c <= '9')
5344                           bitend = (bitend * 10) + *c++ - '0';
5345                         if (!bitend)
5346                           abort ();
5347                         reg = given >> bitstart;
5348                         reg &= (2 << (bitend - bitstart)) - 1;
5349
5350                         switch (*c)
5351                           {
5352                           case 'r':
5353                             func (stream, "%s", arm_regnames[reg]);
5354                             break;
5355
5356                           case 'd':
5357                             func (stream, "%ld", (long) reg);
5358                             value_in_comment = reg;
5359                             break;
5360
5361                           case 'H':
5362                             func (stream, "%ld", (long) (reg << 1));
5363                             value_in_comment = reg << 1;
5364                             break;
5365
5366                           case 'W':
5367                             func (stream, "%ld", (long) (reg << 2));
5368                             value_in_comment = reg << 2;
5369                             break;
5370
5371                           case 'a':
5372                             /* PC-relative address -- the bottom two
5373                                bits of the address are dropped
5374                                before the calculation.  */
5375                             info->print_address_func
5376                               (((pc + 4) & ~3) + (reg << 2), info);
5377                             value_in_comment = 0;
5378                             break;
5379
5380                           case 'x':
5381                             func (stream, "0x%04lx", (long) reg);
5382                             break;
5383
5384                           case 'B':
5385                             reg = ((reg ^ (1 << bitend)) - (1 << bitend));
5386                             info->print_address_func (reg * 2 + pc + 4, info);
5387                             value_in_comment = 0;
5388                             break;
5389
5390                           case 'c':
5391                             func (stream, "%s", arm_conditional [reg]);
5392                             break;
5393
5394                           default:
5395                             abort ();
5396                           }
5397                       }
5398                       break;
5399
5400                     case '\'':
5401                       c++;
5402                       if ((given & (1 << bitstart)) != 0)
5403                         func (stream, "%c", *c);
5404                       break;
5405
5406                     case '?':
5407                       ++c;
5408                       if ((given & (1 << bitstart)) != 0)
5409                         func (stream, "%c", *c++);
5410                       else
5411                         func (stream, "%c", *++c);
5412                       break;
5413
5414                     default:
5415                       abort ();
5416                     }
5417                 }
5418                 break;
5419
5420               default:
5421                 abort ();
5422               }
5423           }
5424
5425         if (value_in_comment > 32 || value_in_comment < -16)
5426           func (stream, "\t; 0x%lx", value_in_comment);
5427         return;
5428       }
5429
5430   /* No match.  */
5431   abort ();
5432 }
5433
5434 /* Return the name of an V7M special register.  */
5435
5436 static const char *
5437 psr_name (int regno)
5438 {
5439   switch (regno)
5440     {
5441     case 0x0: return "APSR";
5442     case 0x1: return "IAPSR";
5443     case 0x2: return "EAPSR";
5444     case 0x3: return "PSR";
5445     case 0x5: return "IPSR";
5446     case 0x6: return "EPSR";
5447     case 0x7: return "IEPSR";
5448     case 0x8: return "MSP";
5449     case 0x9: return "PSP";
5450     case 0xa: return "MSPLIM";
5451     case 0xb: return "PSPLIM";
5452     case 0x10: return "PRIMASK";
5453     case 0x11: return "BASEPRI";
5454     case 0x12: return "BASEPRI_MAX";
5455     case 0x13: return "FAULTMASK";
5456     case 0x14: return "CONTROL";
5457     case 0x88: return "MSP_NS";
5458     case 0x89: return "PSP_NS";
5459     case 0x8a: return "MSPLIM_NS";
5460     case 0x8b: return "PSPLIM_NS";
5461     case 0x90: return "PRIMASK_NS";
5462     case 0x91: return "BASEPRI_NS";
5463     case 0x93: return "FAULTMASK_NS";
5464     case 0x94: return "CONTROL_NS";
5465     case 0x98: return "SP_NS";
5466     default: return "<unknown>";
5467     }
5468 }
5469
5470 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
5471
5472 static void
5473 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
5474 {
5475   const struct opcode32 *insn;
5476   void *stream = info->stream;
5477   fprintf_ftype func = info->fprintf_func;
5478
5479   if (print_insn_coprocessor (pc, info, given, TRUE))
5480     return;
5481
5482   if (print_insn_neon (info, given, TRUE))
5483     return;
5484
5485   for (insn = thumb32_opcodes; insn->assembler; insn++)
5486     if ((given & insn->mask) == insn->value)
5487       {
5488         bfd_boolean is_unpredictable = FALSE;
5489         signed long value_in_comment = 0;
5490         const char *c = insn->assembler;
5491
5492         for (; *c; c++)
5493           {
5494             if (*c != '%')
5495               {
5496                 func (stream, "%c", *c);
5497                 continue;
5498               }
5499
5500             switch (*++c)
5501               {
5502               case '%':
5503                 func (stream, "%%");
5504                 break;
5505
5506               case 'c':
5507                 if (ifthen_state)
5508                   func (stream, "%s", arm_conditional[IFTHEN_COND]);
5509                 break;
5510
5511               case 'x':
5512                 if (ifthen_next_state)
5513                   func (stream, "\t; unpredictable branch in IT block\n");
5514                 break;
5515
5516               case 'X':
5517                 if (ifthen_state)
5518                   func (stream, "\t; unpredictable <IT:%s>",
5519                         arm_conditional[IFTHEN_COND]);
5520                 break;
5521
5522               case 'I':
5523                 {
5524                   unsigned int imm12 = 0;
5525
5526                   imm12 |= (given & 0x000000ffu);
5527                   imm12 |= (given & 0x00007000u) >> 4;
5528                   imm12 |= (given & 0x04000000u) >> 15;
5529                   func (stream, "#%u", imm12);
5530                   value_in_comment = imm12;
5531                 }
5532                 break;
5533
5534               case 'M':
5535                 {
5536                   unsigned int bits = 0, imm, imm8, mod;
5537
5538                   bits |= (given & 0x000000ffu);
5539                   bits |= (given & 0x00007000u) >> 4;
5540                   bits |= (given & 0x04000000u) >> 15;
5541                   imm8 = (bits & 0x0ff);
5542                   mod = (bits & 0xf00) >> 8;
5543                   switch (mod)
5544                     {
5545                     case 0: imm = imm8; break;
5546                     case 1: imm = ((imm8 << 16) | imm8); break;
5547                     case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
5548                     case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
5549                     default:
5550                       mod  = (bits & 0xf80) >> 7;
5551                       imm8 = (bits & 0x07f) | 0x80;
5552                       imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
5553                     }
5554                   func (stream, "#%u", imm);
5555                   value_in_comment = imm;
5556                 }
5557                 break;
5558
5559               case 'J':
5560                 {
5561                   unsigned int imm = 0;
5562
5563                   imm |= (given & 0x000000ffu);
5564                   imm |= (given & 0x00007000u) >> 4;
5565                   imm |= (given & 0x04000000u) >> 15;
5566                   imm |= (given & 0x000f0000u) >> 4;
5567                   func (stream, "#%u", imm);
5568                   value_in_comment = imm;
5569                 }
5570                 break;
5571
5572               case 'K':
5573                 {
5574                   unsigned int imm = 0;
5575
5576                   imm |= (given & 0x000f0000u) >> 16;
5577                   imm |= (given & 0x00000ff0u) >> 0;
5578                   imm |= (given & 0x0000000fu) << 12;
5579                   func (stream, "#%u", imm);
5580                   value_in_comment = imm;
5581                 }
5582                 break;
5583
5584               case 'H':
5585                 {
5586                   unsigned int imm = 0;
5587
5588                   imm |= (given & 0x000f0000u) >> 4;
5589                   imm |= (given & 0x00000fffu) >> 0;
5590                   func (stream, "#%u", imm);
5591                   value_in_comment = imm;
5592                 }
5593                 break;
5594
5595               case 'V':
5596                 {
5597                   unsigned int imm = 0;
5598
5599                   imm |= (given & 0x00000fffu);
5600                   imm |= (given & 0x000f0000u) >> 4;
5601                   func (stream, "#%u", imm);
5602                   value_in_comment = imm;
5603                 }
5604                 break;
5605
5606               case 'S':
5607                 {
5608                   unsigned int reg = (given & 0x0000000fu);
5609                   unsigned int stp = (given & 0x00000030u) >> 4;
5610                   unsigned int imm = 0;
5611                   imm |= (given & 0x000000c0u) >> 6;
5612                   imm |= (given & 0x00007000u) >> 10;
5613
5614                   func (stream, "%s", arm_regnames[reg]);
5615                   switch (stp)
5616                     {
5617                     case 0:
5618                       if (imm > 0)
5619                         func (stream, ", lsl #%u", imm);
5620                       break;
5621
5622                     case 1:
5623                       if (imm == 0)
5624                         imm = 32;
5625                       func (stream, ", lsr #%u", imm);
5626                       break;
5627
5628                     case 2:
5629                       if (imm == 0)
5630                         imm = 32;
5631                       func (stream, ", asr #%u", imm);
5632                       break;
5633
5634                     case 3:
5635                       if (imm == 0)
5636                         func (stream, ", rrx");
5637                       else
5638                         func (stream, ", ror #%u", imm);
5639                     }
5640                 }
5641                 break;
5642
5643               case 'a':
5644                 {
5645                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5646                   unsigned int U   = ! NEGATIVE_BIT_SET;
5647                   unsigned int op  = (given & 0x00000f00) >> 8;
5648                   unsigned int i12 = (given & 0x00000fff);
5649                   unsigned int i8  = (given & 0x000000ff);
5650                   bfd_boolean writeback = FALSE, postind = FALSE;
5651                   bfd_vma offset = 0;
5652
5653                   func (stream, "[%s", arm_regnames[Rn]);
5654                   if (U) /* 12-bit positive immediate offset.  */
5655                     {
5656                       offset = i12;
5657                       if (Rn != 15)
5658                         value_in_comment = offset;
5659                     }
5660                   else if (Rn == 15) /* 12-bit negative immediate offset.  */
5661                     offset = - (int) i12;
5662                   else if (op == 0x0) /* Shifted register offset.  */
5663                     {
5664                       unsigned int Rm = (i8 & 0x0f);
5665                       unsigned int sh = (i8 & 0x30) >> 4;
5666
5667                       func (stream, ", %s", arm_regnames[Rm]);
5668                       if (sh)
5669                         func (stream, ", lsl #%u", sh);
5670                       func (stream, "]");
5671                       break;
5672                     }
5673                   else switch (op)
5674                     {
5675                     case 0xE:  /* 8-bit positive immediate offset.  */
5676                       offset = i8;
5677                       break;
5678
5679                     case 0xC:  /* 8-bit negative immediate offset.  */
5680                       offset = -i8;
5681                       break;
5682
5683                     case 0xF:  /* 8-bit + preindex with wb.  */
5684                       offset = i8;
5685                       writeback = TRUE;
5686                       break;
5687
5688                     case 0xD:  /* 8-bit - preindex with wb.  */
5689                       offset = -i8;
5690                       writeback = TRUE;
5691                       break;
5692
5693                     case 0xB:  /* 8-bit + postindex.  */
5694                       offset = i8;
5695                       postind = TRUE;
5696                       break;
5697
5698                     case 0x9:  /* 8-bit - postindex.  */
5699                       offset = -i8;
5700                       postind = TRUE;
5701                       break;
5702
5703                     default:
5704                       func (stream, ", <undefined>]");
5705                       goto skip;
5706                     }
5707
5708                   if (postind)
5709                     func (stream, "], #%d", (int) offset);
5710                   else
5711                     {
5712                       if (offset)
5713                         func (stream, ", #%d", (int) offset);
5714                       func (stream, writeback ? "]!" : "]");
5715                     }
5716
5717                   if (Rn == 15)
5718                     {
5719                       func (stream, "\t; ");
5720                       info->print_address_func (((pc + 4) & ~3) + offset, info);
5721                     }
5722                 }
5723               skip:
5724                 break;
5725
5726               case 'A':
5727                 {
5728                   unsigned int U   = ! NEGATIVE_BIT_SET;
5729                   unsigned int W   = WRITEBACK_BIT_SET;
5730                   unsigned int Rn  = (given & 0x000f0000) >> 16;
5731                   unsigned int off = (given & 0x000000ff);
5732
5733                   func (stream, "[%s", arm_regnames[Rn]);
5734
5735                   if (PRE_BIT_SET)
5736                     {
5737                       if (off || !U)
5738                         {
5739                           func (stream, ", #%c%u", U ? '+' : '-', off * 4);
5740                           value_in_comment = off * 4 * (U ? 1 : -1);
5741                         }
5742                       func (stream, "]");
5743                       if (W)
5744                         func (stream, "!");
5745                     }
5746                   else
5747                     {
5748                       func (stream, "], ");
5749                       if (W)
5750                         {
5751                           func (stream, "#%c%u", U ? '+' : '-', off * 4);
5752                           value_in_comment = off * 4 * (U ? 1 : -1);
5753                         }
5754                       else
5755                         {
5756                           func (stream, "{%u}", off);
5757                           value_in_comment = off;
5758                         }
5759                     }
5760                 }
5761                 break;
5762
5763               case 'w':
5764                 {
5765                   unsigned int Sbit = (given & 0x01000000) >> 24;
5766                   unsigned int type = (given & 0x00600000) >> 21;
5767
5768                   switch (type)
5769                     {
5770                     case 0: func (stream, Sbit ? "sb" : "b"); break;
5771                     case 1: func (stream, Sbit ? "sh" : "h"); break;
5772                     case 2:
5773                       if (Sbit)
5774                         func (stream, "??");
5775                       break;
5776                     case 3:
5777                       func (stream, "??");
5778                       break;
5779                     }
5780                 }
5781                 break;
5782
5783               case 'm':
5784                 {
5785                   int started = 0;
5786                   int reg;
5787
5788                   func (stream, "{");
5789                   for (reg = 0; reg < 16; reg++)
5790                     if ((given & (1 << reg)) != 0)
5791                       {
5792                         if (started)
5793                           func (stream, ", ");
5794                         started = 1;
5795                         func (stream, "%s", arm_regnames[reg]);
5796                       }
5797                   func (stream, "}");
5798                 }
5799                 break;
5800
5801               case 'E':
5802                 {
5803                   unsigned int msb = (given & 0x0000001f);
5804                   unsigned int lsb = 0;
5805
5806                   lsb |= (given & 0x000000c0u) >> 6;
5807                   lsb |= (given & 0x00007000u) >> 10;
5808                   func (stream, "#%u, #%u", lsb, msb - lsb + 1);
5809                 }
5810                 break;
5811
5812               case 'F':
5813                 {
5814                   unsigned int width = (given & 0x0000001f) + 1;
5815                   unsigned int lsb = 0;
5816
5817                   lsb |= (given & 0x000000c0u) >> 6;
5818                   lsb |= (given & 0x00007000u) >> 10;
5819                   func (stream, "#%u, #%u", lsb, width);
5820                 }
5821                 break;
5822
5823               case 'b':
5824                 {
5825                   unsigned int S = (given & 0x04000000u) >> 26;
5826                   unsigned int J1 = (given & 0x00002000u) >> 13;
5827                   unsigned int J2 = (given & 0x00000800u) >> 11;
5828                   bfd_vma offset = 0;
5829
5830                   offset |= !S << 20;
5831                   offset |= J2 << 19;
5832                   offset |= J1 << 18;
5833                   offset |= (given & 0x003f0000) >> 4;
5834                   offset |= (given & 0x000007ff) << 1;
5835                   offset -= (1 << 20);
5836
5837                   info->print_address_func (pc + 4 + offset, info);
5838                 }
5839                 break;
5840
5841               case 'B':
5842                 {
5843                   unsigned int S = (given & 0x04000000u) >> 26;
5844                   unsigned int I1 = (given & 0x00002000u) >> 13;
5845                   unsigned int I2 = (given & 0x00000800u) >> 11;
5846                   bfd_vma offset = 0;
5847
5848                   offset |= !S << 24;
5849                   offset |= !(I1 ^ S) << 23;
5850                   offset |= !(I2 ^ S) << 22;
5851                   offset |= (given & 0x03ff0000u) >> 4;
5852                   offset |= (given & 0x000007ffu) << 1;
5853                   offset -= (1 << 24);
5854                   offset += pc + 4;
5855
5856                   /* BLX target addresses are always word aligned.  */
5857                   if ((given & 0x00001000u) == 0)
5858                       offset &= ~2u;
5859
5860                   info->print_address_func (offset, info);
5861                 }
5862                 break;
5863
5864               case 's':
5865                 {
5866                   unsigned int shift = 0;
5867
5868                   shift |= (given & 0x000000c0u) >> 6;
5869                   shift |= (given & 0x00007000u) >> 10;
5870                   if (WRITEBACK_BIT_SET)
5871                     func (stream, ", asr #%u", shift);
5872                   else if (shift)
5873                     func (stream, ", lsl #%u", shift);
5874                   /* else print nothing - lsl #0 */
5875                 }
5876                 break;
5877
5878               case 'R':
5879                 {
5880                   unsigned int rot = (given & 0x00000030) >> 4;
5881
5882                   if (rot)
5883                     func (stream, ", ror #%u", rot * 8);
5884                 }
5885                 break;
5886
5887               case 'U':
5888                 if ((given & 0xf0) == 0x60)
5889                   {
5890                     switch (given & 0xf)
5891                       {
5892                         case 0xf: func (stream, "sy"); break;
5893                         default:
5894                           func (stream, "#%d", (int) given & 0xf);
5895                               break;
5896                       }
5897                   }
5898                 else
5899                   {
5900                     const char * opt = data_barrier_option (given & 0xf);
5901                     if (opt != NULL)
5902                       func (stream, "%s", opt);
5903                     else
5904                       func (stream, "#%d", (int) given & 0xf);
5905                    }
5906                 break;
5907
5908               case 'C':
5909                 if ((given & 0xff) == 0)
5910                   {
5911                     func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
5912                     if (given & 0x800)
5913                       func (stream, "f");
5914                     if (given & 0x400)
5915                       func (stream, "s");
5916                     if (given & 0x200)
5917                       func (stream, "x");
5918                     if (given & 0x100)
5919                       func (stream, "c");
5920                   }
5921                 else if ((given & 0x20) == 0x20)
5922                   {
5923                     char const* name;
5924                     unsigned sysm = (given & 0xf00) >> 8;
5925
5926                     sysm |= (given & 0x30);
5927                     sysm |= (given & 0x00100000) >> 14;
5928                     name = banked_regname (sysm);
5929
5930                     if (name != NULL)
5931                       func (stream, "%s", name);
5932                     else
5933                       func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
5934                   }
5935                 else
5936                   {
5937                     func (stream, "%s", psr_name (given & 0xff));
5938                   }
5939                 break;
5940
5941               case 'D':
5942                 if (((given & 0xff) == 0)
5943                     || ((given & 0x20) == 0x20))
5944                   {
5945                     char const* name;
5946                     unsigned sm = (given & 0xf0000) >> 16;
5947
5948                     sm |= (given & 0x30);
5949                     sm |= (given & 0x00100000) >> 14;
5950                     name = banked_regname (sm);
5951
5952                     if (name != NULL)
5953                       func (stream, "%s", name);
5954                     else
5955                       func (stream, "(UNDEF: %lu)", (unsigned long) sm);
5956                   }
5957                 else
5958                   func (stream, "%s", psr_name (given & 0xff));
5959                 break;
5960
5961               case '0': case '1': case '2': case '3': case '4':
5962               case '5': case '6': case '7': case '8': case '9':
5963                 {
5964                   int width;
5965                   unsigned long val;
5966
5967                   c = arm_decode_bitfield (c, given, &val, &width);
5968
5969                   switch (*c)
5970                     {
5971                     case 'd':
5972                       func (stream, "%lu", val);
5973                       value_in_comment = val;
5974                       break;
5975
5976                     case 'D':
5977                       func (stream, "%lu", val + 1);
5978                       value_in_comment = val + 1;
5979                       break;
5980
5981                     case 'W':
5982                       func (stream, "%lu", val * 4);
5983                       value_in_comment = val * 4;
5984                       break;
5985
5986                     case 'S':
5987                       if (val == 13)
5988                         is_unpredictable = TRUE;
5989                       /* Fall through.  */
5990                     case 'R':
5991                       if (val == 15)
5992                         is_unpredictable = TRUE;
5993                       /* Fall through.  */
5994                     case 'r':
5995                       func (stream, "%s", arm_regnames[val]);
5996                       break;
5997
5998                     case 'c':
5999                       func (stream, "%s", arm_conditional[val]);
6000                       break;
6001
6002                     case '\'':
6003                       c++;
6004                       if (val == ((1ul << width) - 1))
6005                         func (stream, "%c", *c);
6006                       break;
6007
6008                     case '`':
6009                       c++;
6010                       if (val == 0)
6011                         func (stream, "%c", *c);
6012                       break;
6013
6014                     case '?':
6015                       func (stream, "%c", c[(1 << width) - (int) val]);
6016                       c += 1 << width;
6017                       break;
6018
6019                     case 'x':
6020                       func (stream, "0x%lx", val & 0xffffffffUL);
6021                       break;
6022
6023                     default:
6024                       abort ();
6025                     }
6026                 }
6027                 break;
6028
6029               case 'L':
6030                 /* PR binutils/12534
6031                    If we have a PC relative offset in an LDRD or STRD
6032                    instructions then display the decoded address.  */
6033                 if (((given >> 16) & 0xf) == 0xf)
6034                   {
6035                     bfd_vma offset = (given & 0xff) * 4;
6036
6037                     if ((given & (1 << 23)) == 0)
6038                       offset = - offset;
6039                     func (stream, "\t; ");
6040                     info->print_address_func ((pc & ~3) + 4 + offset, info);
6041                   }
6042                 break;
6043
6044               default:
6045                 abort ();
6046               }
6047           }
6048
6049         if (value_in_comment > 32 || value_in_comment < -16)
6050           func (stream, "\t; 0x%lx", value_in_comment);
6051
6052         if (is_unpredictable)
6053           func (stream, UNPREDICTABLE_INSTRUCTION);
6054
6055         return;
6056       }
6057
6058   /* No match.  */
6059   abort ();
6060 }
6061
6062 /* Print data bytes on INFO->STREAM.  */
6063
6064 static void
6065 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
6066                  struct disassemble_info *info,
6067                  long given)
6068 {
6069   switch (info->bytes_per_chunk)
6070     {
6071     case 1:
6072       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
6073       break;
6074     case 2:
6075       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
6076       break;
6077     case 4:
6078       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
6079       break;
6080     default:
6081       abort ();
6082     }
6083 }
6084
6085 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
6086    being displayed in symbol relative addresses.
6087
6088    Also disallow private symbol, with __tagsym$$ prefix,
6089    from ARM RVCT toolchain being displayed.  */
6090
6091 bfd_boolean
6092 arm_symbol_is_valid (asymbol * sym,
6093                      struct disassemble_info * info ATTRIBUTE_UNUSED)
6094 {
6095   const char * name;
6096
6097   if (sym == NULL)
6098     return FALSE;
6099
6100   name = bfd_asymbol_name (sym);
6101
6102   return (name && *name != '$' && strncmp (name, "__tagsym$$", 10));
6103 }
6104
6105 /* Parse the string of disassembler options.  */
6106
6107 static void
6108 parse_arm_disassembler_options (const char *options)
6109 {
6110   const char *opt;
6111
6112   FOR_EACH_DISASSEMBLER_OPTION (opt, options)
6113     {
6114       if (CONST_STRNEQ (opt, "reg-names-"))
6115         {
6116           unsigned int i;
6117           for (i = 0; i < NUM_ARM_OPTIONS; i++)
6118             if (disassembler_options_cmp (opt, regnames[i].name) == 0)
6119               {
6120                 regname_selected = i;
6121                 break;
6122               }
6123
6124           if (i >= NUM_ARM_OPTIONS)
6125             fprintf (stderr, _("Unrecognised register name set: %s\n"), opt);
6126         }
6127       else if (CONST_STRNEQ (opt, "force-thumb"))
6128         force_thumb = 1;
6129       else if (CONST_STRNEQ (opt, "no-force-thumb"))
6130         force_thumb = 0;
6131       else
6132         fprintf (stderr, _("Unrecognised disassembler option: %s\n"), opt);
6133     }
6134
6135   return;
6136 }
6137
6138 static bfd_boolean
6139 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6140                          enum map_type *map_symbol);
6141
6142 /* Search back through the insn stream to determine if this instruction is
6143    conditionally executed.  */
6144
6145 static void
6146 find_ifthen_state (bfd_vma pc,
6147                    struct disassemble_info *info,
6148                    bfd_boolean little)
6149 {
6150   unsigned char b[2];
6151   unsigned int insn;
6152   int status;
6153   /* COUNT is twice the number of instructions seen.  It will be odd if we
6154      just crossed an instruction boundary.  */
6155   int count;
6156   int it_count;
6157   unsigned int seen_it;
6158   bfd_vma addr;
6159
6160   ifthen_address = pc;
6161   ifthen_state = 0;
6162
6163   addr = pc;
6164   count = 1;
6165   it_count = 0;
6166   seen_it = 0;
6167   /* Scan backwards looking for IT instructions, keeping track of where
6168      instruction boundaries are.  We don't know if something is actually an
6169      IT instruction until we find a definite instruction boundary.  */
6170   for (;;)
6171     {
6172       if (addr == 0 || info->symbol_at_address_func (addr, info))
6173         {
6174           /* A symbol must be on an instruction boundary, and will not
6175              be within an IT block.  */
6176           if (seen_it && (count & 1))
6177             break;
6178
6179           return;
6180         }
6181       addr -= 2;
6182       status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
6183       if (status)
6184         return;
6185
6186       if (little)
6187         insn = (b[0]) | (b[1] << 8);
6188       else
6189         insn = (b[1]) | (b[0] << 8);
6190       if (seen_it)
6191         {
6192           if ((insn & 0xf800) < 0xe800)
6193             {
6194               /* Addr + 2 is an instruction boundary.  See if this matches
6195                  the expected boundary based on the position of the last
6196                  IT candidate.  */
6197               if (count & 1)
6198                 break;
6199               seen_it = 0;
6200             }
6201         }
6202       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
6203         {
6204           enum map_type type = MAP_ARM;
6205           bfd_boolean found = mapping_symbol_for_insn (addr, info, &type);
6206
6207           if (!found || (found && type == MAP_THUMB))
6208             {
6209               /* This could be an IT instruction.  */
6210               seen_it = insn;
6211               it_count = count >> 1;
6212             }
6213         }
6214       if ((insn & 0xf800) >= 0xe800)
6215         count++;
6216       else
6217         count = (count + 2) | 1;
6218       /* IT blocks contain at most 4 instructions.  */
6219       if (count >= 8 && !seen_it)
6220         return;
6221     }
6222   /* We found an IT instruction.  */
6223   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
6224   if ((ifthen_state & 0xf) == 0)
6225     ifthen_state = 0;
6226 }
6227
6228 /* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
6229    mapping symbol.  */
6230
6231 static int
6232 is_mapping_symbol (struct disassemble_info *info, int n,
6233                    enum map_type *map_type)
6234 {
6235   const char *name;
6236
6237   name = bfd_asymbol_name (info->symtab[n]);
6238   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
6239       && (name[2] == 0 || name[2] == '.'))
6240     {
6241       *map_type = ((name[1] == 'a') ? MAP_ARM
6242                    : (name[1] == 't') ? MAP_THUMB
6243                    : MAP_DATA);
6244       return TRUE;
6245     }
6246
6247   return FALSE;
6248 }
6249
6250 /* Try to infer the code type (ARM or Thumb) from a mapping symbol.
6251    Returns nonzero if *MAP_TYPE was set.  */
6252
6253 static int
6254 get_map_sym_type (struct disassemble_info *info,
6255                   int n,
6256                   enum map_type *map_type)
6257 {
6258   /* If the symbol is in a different section, ignore it.  */
6259   if (info->section != NULL && info->section != info->symtab[n]->section)
6260     return FALSE;
6261
6262   return is_mapping_symbol (info, n, map_type);
6263 }
6264
6265 /* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
6266    Returns nonzero if *MAP_TYPE was set.  */
6267
6268 static int
6269 get_sym_code_type (struct disassemble_info *info,
6270                    int n,
6271                    enum map_type *map_type)
6272 {
6273   elf_symbol_type *es;
6274   unsigned int type;
6275
6276   /* If the symbol is in a different section, ignore it.  */
6277   if (info->section != NULL && info->section != info->symtab[n]->section)
6278     return FALSE;
6279
6280   es = *(elf_symbol_type **)(info->symtab + n);
6281   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6282
6283   /* If the symbol has function type then use that.  */
6284   if (type == STT_FUNC || type == STT_GNU_IFUNC)
6285     {
6286       if (ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6287           == ST_BRANCH_TO_THUMB)
6288         *map_type = MAP_THUMB;
6289       else
6290         *map_type = MAP_ARM;
6291       return TRUE;
6292     }
6293
6294   return FALSE;
6295 }
6296
6297 /* Search the mapping symbol state for instruction at pc.  This is only
6298    applicable for elf target.
6299
6300    There is an assumption Here, info->private_data contains the correct AND
6301    up-to-date information about current scan process.  The information will be
6302    used to speed this search process.
6303
6304    Return TRUE if the mapping state can be determined, and map_symbol
6305    will be updated accordingly.  Otherwise, return FALSE.  */
6306
6307 static bfd_boolean
6308 mapping_symbol_for_insn (bfd_vma pc, struct disassemble_info *info,
6309                          enum map_type *map_symbol)
6310 {
6311   bfd_vma addr;
6312   int n, start = 0;
6313   bfd_boolean found = FALSE;
6314   enum map_type type = MAP_ARM;
6315   struct arm_private_data *private_data;
6316
6317   if (info->private_data == NULL || info->symtab_size == 0
6318       || bfd_asymbol_flavour (*info->symtab) != bfd_target_elf_flavour)
6319     return FALSE;
6320
6321   private_data = info->private_data;
6322   if (pc == 0)
6323     start = 0;
6324   else
6325     start = private_data->last_mapping_sym;
6326
6327   start = (start == -1)? 0 : start;
6328   addr = bfd_asymbol_value (info->symtab[start]);
6329
6330   if (pc >= addr)
6331     {
6332       if (get_map_sym_type (info, start, &type))
6333       found = TRUE;
6334     }
6335   else
6336     {
6337       for (n = start - 1; n >= 0; n--)
6338         {
6339           if (get_map_sym_type (info, n, &type))
6340             {
6341               found = TRUE;
6342               break;
6343             }
6344         }
6345     }
6346
6347   /* No mapping symbols were found.  A leading $d may be
6348      omitted for sections which start with data; but for
6349      compatibility with legacy and stripped binaries, only
6350      assume the leading $d if there is at least one mapping
6351      symbol in the file.  */
6352   if (!found && private_data->has_mapping_symbols == 1)
6353     {
6354       type = MAP_DATA;
6355       found = TRUE;
6356     }
6357
6358   *map_symbol = type;
6359   return found;
6360 }
6361
6362 /* Given a bfd_mach_arm_XXX value, this function fills in the fields
6363    of the supplied arm_feature_set structure with bitmasks indicating
6364    the support base architectures and coprocessor extensions.
6365
6366    FIXME: This could more efficiently implemented as a constant array,
6367    although it would also be less robust.  */
6368
6369 static void
6370 select_arm_features (unsigned long mach,
6371                      arm_feature_set * features)
6372 {
6373 #undef ARM_SET_FEATURES
6374 #define ARM_SET_FEATURES(FSET) \
6375   {                                                     \
6376     const arm_feature_set fset = FSET;                  \
6377     arm_feature_set tmp = ARM_FEATURE (0, 0, FPU_FPA) ; \
6378     ARM_MERGE_FEATURE_SETS (*features, tmp, fset);      \
6379   }
6380
6381   switch (mach)
6382     {
6383     case bfd_mach_arm_2:       ARM_SET_FEATURES (ARM_ARCH_V2); break;
6384     case bfd_mach_arm_2a:      ARM_SET_FEATURES (ARM_ARCH_V2S); break;
6385     case bfd_mach_arm_3:       ARM_SET_FEATURES (ARM_ARCH_V3); break;
6386     case bfd_mach_arm_3M:      ARM_SET_FEATURES (ARM_ARCH_V3M); break;
6387     case bfd_mach_arm_4:       ARM_SET_FEATURES (ARM_ARCH_V4); break;
6388     case bfd_mach_arm_4T:      ARM_SET_FEATURES (ARM_ARCH_V4T); break;
6389     case bfd_mach_arm_5:       ARM_SET_FEATURES (ARM_ARCH_V5); break;
6390     case bfd_mach_arm_5T:      ARM_SET_FEATURES (ARM_ARCH_V5T); break;
6391     case bfd_mach_arm_5TE:     ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
6392     case bfd_mach_arm_XScale:  ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
6393     case bfd_mach_arm_ep9312:
6394       ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
6395                                          ARM_CEXT_MAVERICK | FPU_MAVERICK));
6396        break;
6397     case bfd_mach_arm_iWMMXt:  ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
6398     case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
6399       /* If the machine type is unknown allow all
6400          architecture types and all extensions.  */
6401     case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
6402     default:
6403       abort ();
6404     }
6405
6406 #undef ARM_SET_FEATURES
6407 }
6408
6409
6410 /* NOTE: There are no checks in these routines that
6411    the relevant number of data bytes exist.  */
6412
6413 static int
6414 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
6415 {
6416   unsigned char b[4];
6417   long          given;
6418   int           status;
6419   int           is_thumb = FALSE;
6420   int           is_data = FALSE;
6421   int           little_code;
6422   unsigned int  size = 4;
6423   void          (*printer) (bfd_vma, struct disassemble_info *, long);
6424   bfd_boolean   found = FALSE;
6425   struct arm_private_data *private_data;
6426
6427   if (info->disassembler_options)
6428     {
6429       parse_arm_disassembler_options (info->disassembler_options);
6430
6431       /* To avoid repeated parsing of these options, we remove them here.  */
6432       info->disassembler_options = NULL;
6433     }
6434
6435   /* PR 10288: Control which instructions will be disassembled.  */
6436   if (info->private_data == NULL)
6437     {
6438       static struct arm_private_data private;
6439
6440       if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
6441         /* If the user did not use the -m command line switch then default to
6442            disassembling all types of ARM instruction.
6443
6444            The info->mach value has to be ignored as this will be based on
6445            the default archictecture for the target and/or hints in the notes
6446            section, but it will never be greater than the current largest arm
6447            machine value (iWMMXt2), which is only equivalent to the V5TE
6448            architecture.  ARM architectures have advanced beyond the machine
6449            value encoding, and these newer architectures would be ignored if
6450            the machine value was used.
6451
6452            Ie the -m switch is used to restrict which instructions will be
6453            disassembled.  If it is necessary to use the -m switch to tell
6454            objdump that an ARM binary is being disassembled, eg because the
6455            input is a raw binary file, but it is also desired to disassemble
6456            all ARM instructions then use "-marm".  This will select the
6457            "unknown" arm architecture which is compatible with any ARM
6458            instruction.  */
6459           info->mach = bfd_mach_arm_unknown;
6460
6461       /* Compute the architecture bitmask from the machine number.
6462          Note: This assumes that the machine number will not change
6463          during disassembly....  */
6464       select_arm_features (info->mach, & private.features);
6465
6466       private.has_mapping_symbols = -1;
6467       private.last_mapping_sym = -1;
6468       private.last_mapping_addr = 0;
6469
6470       info->private_data = & private;
6471     }
6472
6473   private_data = info->private_data;
6474
6475   /* Decide if our code is going to be little-endian, despite what the
6476      function argument might say.  */
6477   little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
6478
6479   /* For ELF, consult the symbol table to determine what kind of code
6480      or data we have.  */
6481   if (info->symtab_size != 0
6482       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
6483     {
6484       bfd_vma addr;
6485       int n, start;
6486       int last_sym = -1;
6487       enum map_type type = MAP_ARM;
6488
6489       /* Start scanning at the start of the function, or wherever
6490          we finished last time.  */
6491       /* PR 14006.  When the address is 0 we are either at the start of the
6492          very first function, or else the first function in a new, unlinked
6493          executable section (eg because of -ffunction-sections).  Either way
6494          start scanning from the beginning of the symbol table, not where we
6495          left off last time.  */
6496       if (pc == 0)
6497         start = 0;
6498       else
6499         {
6500           start = info->symtab_pos + 1;
6501           if (start < private_data->last_mapping_sym)
6502             start = private_data->last_mapping_sym;
6503         }
6504       found = FALSE;
6505
6506       /* First, look for mapping symbols.  */
6507       if (private_data->has_mapping_symbols != 0)
6508         {
6509           /* Scan up to the location being disassembled.  */
6510           for (n = start; n < info->symtab_size; n++)
6511             {
6512               addr = bfd_asymbol_value (info->symtab[n]);
6513               if (addr > pc)
6514                 break;
6515               if (get_map_sym_type (info, n, &type))
6516                 {
6517                   last_sym = n;
6518                   found = TRUE;
6519                 }
6520             }
6521
6522           if (!found)
6523             {
6524               /* No mapping symbol found at this address.  Look backwards
6525                  for a preceding one.  */
6526               for (n = start - 1; n >= 0; n--)
6527                 {
6528                   if (get_map_sym_type (info, n, &type))
6529                     {
6530                       last_sym = n;
6531                       found = TRUE;
6532                       break;
6533                     }
6534                 }
6535             }
6536
6537           if (found)
6538             private_data->has_mapping_symbols = 1;
6539
6540           /* No mapping symbols were found.  A leading $d may be
6541              omitted for sections which start with data; but for
6542              compatibility with legacy and stripped binaries, only
6543              assume the leading $d if there is at least one mapping
6544              symbol in the file.  */
6545           if (!found && private_data->has_mapping_symbols == -1)
6546             {
6547               /* Look for mapping symbols, in any section.  */
6548               for (n = 0; n < info->symtab_size; n++)
6549                 if (is_mapping_symbol (info, n, &type))
6550                   {
6551                     private_data->has_mapping_symbols = 1;
6552                     break;
6553                   }
6554               if (private_data->has_mapping_symbols == -1)
6555                 private_data->has_mapping_symbols = 0;
6556             }
6557
6558           if (!found && private_data->has_mapping_symbols == 1)
6559             {
6560               type = MAP_DATA;
6561               found = TRUE;
6562             }
6563         }
6564
6565       /* Next search for function symbols to separate ARM from Thumb
6566          in binaries without mapping symbols.  */
6567       if (!found)
6568         {
6569           /* Scan up to the location being disassembled.  */
6570           for (n = start; n < info->symtab_size; n++)
6571             {
6572               addr = bfd_asymbol_value (info->symtab[n]);
6573               if (addr > pc)
6574                 break;
6575               if (get_sym_code_type (info, n, &type))
6576                 {
6577                   last_sym = n;
6578                   found = TRUE;
6579                 }
6580             }
6581
6582           if (!found)
6583             {
6584               /* No mapping symbol found at this address.  Look backwards
6585                  for a preceding one.  */
6586               for (n = start - 1; n >= 0; n--)
6587                 {
6588                   if (get_sym_code_type (info, n, &type))
6589                     {
6590                       last_sym = n;
6591                       found = TRUE;
6592                       break;
6593                     }
6594                 }
6595             }
6596         }
6597
6598       private_data->last_mapping_sym = last_sym;
6599       private_data->last_type = type;
6600       is_thumb = (private_data->last_type == MAP_THUMB);
6601       is_data = (private_data->last_type == MAP_DATA);
6602
6603       /* Look a little bit ahead to see if we should print out
6604          two or four bytes of data.  If there's a symbol,
6605          mapping or otherwise, after two bytes then don't
6606          print more.  */
6607       if (is_data)
6608         {
6609           size = 4 - (pc & 3);
6610           for (n = last_sym + 1; n < info->symtab_size; n++)
6611             {
6612               addr = bfd_asymbol_value (info->symtab[n]);
6613               if (addr > pc
6614                   && (info->section == NULL
6615                       || info->section == info->symtab[n]->section))
6616                 {
6617                   if (addr - pc < size)
6618                     size = addr - pc;
6619                   break;
6620                 }
6621             }
6622           /* If the next symbol is after three bytes, we need to
6623              print only part of the data, so that we can use either
6624              .byte or .short.  */
6625           if (size == 3)
6626             size = (pc & 1) ? 1 : 2;
6627         }
6628     }
6629
6630   if (info->symbols != NULL)
6631     {
6632       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
6633         {
6634           coff_symbol_type * cs;
6635
6636           cs = coffsymbol (*info->symbols);
6637           is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
6638                       || cs->native->u.syment.n_sclass == C_THUMBSTAT
6639                       || cs->native->u.syment.n_sclass == C_THUMBLABEL
6640                       || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
6641                       || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
6642         }
6643       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
6644                && !found)
6645         {
6646           /* If no mapping symbol has been found then fall back to the type
6647              of the function symbol.  */
6648           elf_symbol_type *  es;
6649           unsigned int       type;
6650
6651           es = *(elf_symbol_type **)(info->symbols);
6652           type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
6653
6654           is_thumb =
6655             ((ARM_GET_SYM_BRANCH_TYPE (es->internal_elf_sym.st_target_internal)
6656               == ST_BRANCH_TO_THUMB) || type == STT_ARM_16BIT);
6657         }
6658       else if (bfd_asymbol_flavour (*info->symbols)
6659                == bfd_target_mach_o_flavour)
6660         {
6661           bfd_mach_o_asymbol *asym = (bfd_mach_o_asymbol *)*info->symbols;
6662
6663           is_thumb = (asym->n_desc & BFD_MACH_O_N_ARM_THUMB_DEF);
6664         }
6665     }
6666
6667   if (force_thumb)
6668     is_thumb = TRUE;
6669
6670   if (is_data)
6671     info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6672   else
6673     info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
6674
6675   info->bytes_per_line = 4;
6676
6677   /* PR 10263: Disassemble data if requested to do so by the user.  */
6678   if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
6679     {
6680       int i;
6681
6682       /* Size was already set above.  */
6683       info->bytes_per_chunk = size;
6684       printer = print_insn_data;
6685
6686       status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
6687       given = 0;
6688       if (little)
6689         for (i = size - 1; i >= 0; i--)
6690           given = b[i] | (given << 8);
6691       else
6692         for (i = 0; i < (int) size; i++)
6693           given = b[i] | (given << 8);
6694     }
6695   else if (!is_thumb)
6696     {
6697       /* In ARM mode endianness is a straightforward issue: the instruction
6698          is four bytes long and is either ordered 0123 or 3210.  */
6699       printer = print_insn_arm;
6700       info->bytes_per_chunk = 4;
6701       size = 4;
6702
6703       status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
6704       if (little_code)
6705         given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
6706       else
6707         given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
6708     }
6709   else
6710     {
6711       /* In Thumb mode we have the additional wrinkle of two
6712          instruction lengths.  Fortunately, the bits that determine
6713          the length of the current instruction are always to be found
6714          in the first two bytes.  */
6715       printer = print_insn_thumb16;
6716       info->bytes_per_chunk = 2;
6717       size = 2;
6718
6719       status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
6720       if (little_code)
6721         given = (b[0]) | (b[1] << 8);
6722       else
6723         given = (b[1]) | (b[0] << 8);
6724
6725       if (!status)
6726         {
6727           /* These bit patterns signal a four-byte Thumb
6728              instruction.  */
6729           if ((given & 0xF800) == 0xF800
6730               || (given & 0xF800) == 0xF000
6731               || (given & 0xF800) == 0xE800)
6732             {
6733               status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
6734               if (little_code)
6735                 given = (b[0]) | (b[1] << 8) | (given << 16);
6736               else
6737                 given = (b[1]) | (b[0] << 8) | (given << 16);
6738
6739               printer = print_insn_thumb32;
6740               size = 4;
6741             }
6742         }
6743
6744       if (ifthen_address != pc)
6745         find_ifthen_state (pc, info, little_code);
6746
6747       if (ifthen_state)
6748         {
6749           if ((ifthen_state & 0xf) == 0x8)
6750             ifthen_next_state = 0;
6751           else
6752             ifthen_next_state = (ifthen_state & 0xe0)
6753                                 | ((ifthen_state & 0xf) << 1);
6754         }
6755     }
6756
6757   if (status)
6758     {
6759       info->memory_error_func (status, pc, info);
6760       return -1;
6761     }
6762   if (info->flags & INSN_HAS_RELOC)
6763     /* If the instruction has a reloc associated with it, then
6764        the offset field in the instruction will actually be the
6765        addend for the reloc.  (We are using REL type relocs).
6766        In such cases, we can ignore the pc when computing
6767        addresses, since the addend is not currently pc-relative.  */
6768     pc = 0;
6769
6770   printer (pc, info, given);
6771
6772   if (is_thumb)
6773     {
6774       ifthen_state = ifthen_next_state;
6775       ifthen_address += size;
6776     }
6777   return size;
6778 }
6779
6780 int
6781 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
6782 {
6783   /* Detect BE8-ness and record it in the disassembler info.  */
6784   if (info->flavour == bfd_target_elf_flavour
6785       && info->section != NULL
6786       && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
6787     info->endian_code = BFD_ENDIAN_LITTLE;
6788
6789   return print_insn (pc, info, FALSE);
6790 }
6791
6792 int
6793 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
6794 {
6795   return print_insn (pc, info, TRUE);
6796 }
6797
6798 const disasm_options_t *
6799 disassembler_options_arm (void)
6800 {
6801   static disasm_options_t *opts = NULL;
6802
6803   if (opts == NULL)
6804     {
6805       unsigned int i;
6806       opts = XNEW (disasm_options_t);
6807       opts->name = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6808       opts->description = XNEWVEC (const char *, NUM_ARM_OPTIONS + 1);
6809       for (i = 0; i < NUM_ARM_OPTIONS; i++)
6810         {
6811           opts->name[i] = regnames[i].name;
6812           if (regnames[i].description != NULL)
6813             opts->description[i] = _(regnames[i].description);
6814           else
6815             opts->description[i] = NULL;
6816         }
6817       /* The array we return must be NULL terminated.  */
6818       opts->name[i] = NULL;
6819       opts->description[i] = NULL;
6820     }
6821
6822   return opts;
6823 }
6824
6825 void
6826 print_arm_disassembler_options (FILE *stream)
6827 {
6828   unsigned int i, max_len = 0;
6829   fprintf (stream, _("\n\
6830 The following ARM specific disassembler options are supported for use with\n\
6831 the -M switch:\n"));
6832
6833   for (i = 0; i < NUM_ARM_OPTIONS; i++)
6834     {
6835       unsigned int len = strlen (regnames[i].name);
6836       if (max_len < len)
6837         max_len = len;
6838     }
6839
6840   for (i = 0, max_len++; i < NUM_ARM_OPTIONS; i++)
6841     fprintf (stream, "  %s%*c %s\n",
6842              regnames[i].name,
6843              (int)(max_len - strlen (regnames[i].name)), ' ',
6844              _(regnames[i].description));
6845 }