sim/testsuite/bfin/c_interr_disable_enable.S

   1 //Original:/proj/frio/dv/testcases/core/c_interr_disable_enable/c_interr_disable_enable.dsp
   2 // Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 //
  11 // Include Files
  12 //
  13
  14 include(std.inc)
  15 include(selfcheck.inc)
  16
  17 // Defines
  18
  19 #ifndef TCNTL
  20 #define TCNTL            0xFFE03000
  21 #endif
  22 #ifndef TPERIOD
  23 #define TPERIOD          0xFFE03004
  24 #endif
  25 #ifndef TSCALE
  26 #define TSCALE           0xFFE03008
  27 #endif
  28 #ifndef TCOUNT
  29 #define TCOUNT           0xFFE0300c
  30 #endif
  31 #ifndef EVT
  32 #define EVT              0xFFE02000
  33 #endif
  34 #ifndef EVT15
  35 #define EVT15            0xFFE0203c
  36 #endif
  37 #ifndef EVT_OVERRIDE
  38 #define EVT_OVERRIDE     0xFFE02100
  39 #endif
  40 #ifndef ITABLE
  41 #define ITABLE           0x000FF000
  42 #endif
  43 #ifndef PROGRAM_STACK
  44 #define PROGRAM_STACK    0x000FF100
  45 #endif
  46 #ifndef STACKSIZE
  47 #define STACKSIZE        0x00000300
  48 #endif
  49
  50 // Boot code
  51
  52  BOOT :
  53 INIT_R_REGS(0);                             // Initialize Dregs
  54 INIT_P_REGS(0);                             // Initialize Pregs
  55
  56      // CHECK_INIT(p5,   0x00BFFFFC);
  57      // CHECK_INIT(p5,   0xE0000000);
  58 include(symtable.inc)
  59 CHECK_INIT_DEF(p5);
  60
  61      // LD32(sp, 0x000FF200);
  62 LD32_LABEL(sp, KSTACK);   // setup the stack pointer
  63 FP = SP;                  // and frame pointer
  64
  65 LD32(p0, EVT);              // Setup Event Vectors and Handlers
  66 LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
  67         [ P0 ++ ] = R0;
  68
  69 LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
  70         [ P0 ++ ] = R0;
  71
  72 LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
  73         [ P0 ++ ] = R0;
  74
  75 LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
  76         [ P0 ++ ] = R0;
  77
  78         [ P0 ++ ] = R0;                // IVT4 not used
  79
  80 LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
  81         [ P0 ++ ] = R0;
  82
  83 LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
  84         [ P0 ++ ] = R0;
  85
  86 LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
  87         [ P0 ++ ] = R0;
  88
  89 LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
  90         [ P0 ++ ] = R0;
  91
  92 LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
  93         [ P0 ++ ] = R0;
  94
  95 LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
  96         [ P0 ++ ] = R0;
  97
  98 LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
  99         [ P0 ++ ] = R0;
 100
 101 LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
 102         [ P0 ++ ] = R0;
 103
 104 LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
 105         [ P0 ++ ] = R0;
 106
 107 LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
 108         [ P0 ++ ] = R0;
 109
 110 LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
 111         [ P0 ++ ] = R0;
 112
 113 LD32(p0, EVT_OVERRIDE);
 114         R0 = 0;
 115         [ P0 ++ ] = R0;
 116         R0 = -1;     // Change this to mask interrupts (*)
 117         [ P0 ] = R0;   // IMASK
 118
 119 LD32_LABEL(p1, START);
 120
 121 LD32(p0, EVT15);
 122         [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 123 CSYNC;
 124 RAISE 15;    // after we RTI, INT 15 should be taken
 125
 126 LD32_LABEL(r7, START);
 127 RETI = r7;
 128 NOP;        // Workaround for Bug 217
 129 RTI;
 130 NOP;
 131 NOP;
 132 NOP;
 133 NOP;
 134 NOP;
 135 NOP;
 136 NOP;
 137 NOP;
 138 DUMMY:
 139           NOP;
 140 NOP;
 141 NOP;
 142 NOP;
 143 NOP;
 144 NOP;
 145 NOP;
 146 NOP;
 147 NOP;
 148 NOP;
 149
 150 //.code 0x200
 151  START :
 152         P1 = 0;
 153         R7 = 0x0;
 154         R6 = 0x1;
 155         [ -- SP ] = RETI;        // Enable Nested Interrupts
 156
 157 CLI R1;                                           // stop interrupt
 158 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR (active state)
 159 WR_MMR(TPERIOD, 0x00000050, p0, r0);
 160 WR_MMR(TCOUNT,  0x00000013, p0, r0);
 161 WR_MMR(TSCALE,  0x00000000, p0, r0);
 162 CSYNC;
 163         // Read the contents of the Timer
 164
 165 RD_MMR(TPERIOD, p0, r2);
 166 CHECKREG(r2,    0x00000050);
 167
 168 //      RD_MMR(TCOUNT, p0, r3);
 169 //      CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
 170
 171
 172 WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
 173 CSYNC;
 174
 175 RD_MMR(TPERIOD, p0, r4);
 176 CHECKREG(r4,    0x00000050);
 177
 178 //      RD_MMR(TCNTL, p0, r5);
 179 //      CHECKREG(r5,    0x0000000B);                // INTERRUPT did happen
 180
 181 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 182 CSYNC;
 183 NOP;
 184 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
 185 WR_MMR(TPERIOD, 0x00000015, p0, r0);
 186 WR_MMR(TCOUNT,  0x00000013, p0, r0);
 187 WR_MMR(TSCALE,  0x00000002, p0, r0);
 188 WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer (TAUTORLD=1)
 189 CSYNC;
 190 NOP;
 191 NOP;
 192 NOP;
 193 NOP;
 194 NOP;
 195 NOP;
 196 NOP;
 197 NOP;
 198 NOP;
 199 NOP;
 200 NOP;
 201 NOP;
 202 NOP;
 203 NOP;
 204 NOP;
 205 JUMP.S label4;
 206         R4.L = 0x1111;                             // Will be killed
 207         R4.H = 0x1111;                             // Will be killed
 208 NOP;
 209 NOP;
 210 NOP;
 211 label5: R5.H = 0x7777;
 212         R5.L = 0x7888;
 213 JUMP.S label6;
 214         R5.L = 0x1111;                             // Will be killed
 215         R5.H = 0x1111;                             // Will be killed
 216 NOP;
 217 NOP;
 218 NOP;
 219 NOP;
 220 NOP;
 221 NOP;
 222 label4: R4.H = 0x5555;
 223         R4.L = 0x6666;
 224 NOP;
 225 JUMP.S label5;
 226         R5.L = 0x2222;     // Will be killed
 227         R5.H = 0x2222;     // Will be killed
 228 NOP;
 229 NOP;
 230 NOP;
 231 NOP;
 232 label6: R3.H = 0x7999;
 233         R3.L = 0x7aaa;
 234 NOP;
 235 NOP;
 236 NOP;
 237 NOP;
 238 NOP;
 239 NOP;
 240 NOP;
 241                                                     // With auto reload
 242         // Read the contents of the Timer
 243
 244 RD_MMR(TPERIOD, p0, r2);
 245 CHECKREG(r2,    0x00000015);
 246
 247 //      RD_MMR(TCNTL , p0, r3);
 248 //      CHECKREG(r3,    0x0000000F);
 249 CHECKREG(r7,    0x00000000);    // no interrupt being serviced
 250 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 251 CSYNC;
 252 STI R1;
 253 NOP;
 254 CHECKREG(r7,    0x00000001);    // interrupt being serviced
 255 WR_MMR(TCOUNT,  0x00000005, p0, r0);
 256 WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
 257 CSYNC;
 258 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 259 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 260 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 261 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 262 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 263 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 264 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 265 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 266 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 267 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 268 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 269 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 270 NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP; NOP;
 271 CHECKREG(r7,    0x00000002);    // interrupt being serviced
 272 RAISE 7;
 273 NOP; NOP;
 274 CHECKREG(p1,    0x00000001);    // interrupt being serviced
 275
 276
 277
 278
 279
 280 dbg_pass;        // Call Endtest Macro
 281
 282
 283
 284 //*********************************************************************
 285 //
 286 // Handlers for Events
 287 //
 288 //.code ITABLE
 289
 290 EHANDLE:            // Emulation Handler 0
 291 RTE;
 292
 293 RHANDLE:            // Reset Handler 1
 294 RTI;
 295
 296 NHANDLE:            // NMI Handler 2
 297 RTN;
 298
 299 XHANDLE:            // Exception Handler 3
 300 RTX;
 301
 302 HWHANDLE:           // HW Error Handler 5
 303 RTI;
 304
 305 THANDLE:            // Timer Handler 6
 306         R7 = R7 + R6;
 307 RTI;
 308
 309 I7HANDLE:           // IVG 7 Handler
 310         P1 += 1;
 311 RTI;
 312
 313 I8HANDLE:           // IVG 8 Handler
 314 RTI;
 315
 316 I9HANDLE:           // IVG 9 Handler
 317 RTI;
 318
 319 I10HANDLE:          // IVG 10 Handler
 320 RTI;
 321
 322 I11HANDLE:          // IVG 11 Handler
 323 RTI;
 324
 325 I12HANDLE:          // IVG 12 Handler
 326 RTI;
 327
 328 I13HANDLE:          // IVG 13 Handler
 329 RTI;
 330
 331 I14HANDLE:          // IVG 14 Handler
 332 RTI;
 333
 334 I15HANDLE:          // IVG 15 Handler
 335         R5 = RETI;
 336         P0 = R5;
 337 JUMP ( P0 );
 338 RTI;
 339
 340 .data
 341
 342 .space (STACKSIZE);
 343 KSTACK:
 344 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug